mediatek,mt8196-resets.h

 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 2/*
 3 * Copyright (c) 2025 Collabora Ltd.
 4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 5 */
 6
 7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196
 8#define _DT_BINDINGS_RESET_CONTROLLER_MT8196
 9
10/* PEXTP0 resets */
11#define MT8196_PEXTP0_RST0_PCIE0_MAC		0
12#define MT8196_PEXTP0_RST0_PCIE0_PHY		1
13
14/* PEXTP1 resets */
15#define MT8196_PEXTP1_RST0_PCIE1_MAC		0
16#define MT8196_PEXTP1_RST0_PCIE1_PHY		1
17#define MT8196_PEXTP1_RST0_PCIE2_MAC		2
18#define MT8196_PEXTP1_RST0_PCIE2_PHY		3
19
20/* UFS resets */
21#define MT8196_UFSAO_RST0_UFS_MPHY		0
22#define MT8196_UFSAO_RST1_UFS_UNIPRO		1
23#define MT8196_UFSAO_RST1_UFS_CRYPTO		2
24#define MT8196_UFSAO_RST1_UFSHCI		3
25
26#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */