spacemit,k1-syscon.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2/*
  3 * Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>
  4 */
  5
  6#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
  7#define _DT_BINDINGS_SPACEMIT_CCU_H_
  8
  9/* APBS (PLL) clocks */
 10#define CLK_PLL1		0
 11#define CLK_PLL2		1
 12#define CLK_PLL3		2
 13#define CLK_PLL1_D2		3
 14#define CLK_PLL1_D3		4
 15#define CLK_PLL1_D4		5
 16#define CLK_PLL1_D5		6
 17#define CLK_PLL1_D6		7
 18#define CLK_PLL1_D7		8
 19#define CLK_PLL1_D8		9
 20#define CLK_PLL1_D11		10
 21#define CLK_PLL1_D13		11
 22#define CLK_PLL1_D23		12
 23#define CLK_PLL1_D64		13
 24#define CLK_PLL1_D10_AUD	14
 25#define CLK_PLL1_D100_AUD	15
 26#define CLK_PLL2_D1		16
 27#define CLK_PLL2_D2		17
 28#define CLK_PLL2_D3		18
 29#define CLK_PLL2_D4		19
 30#define CLK_PLL2_D5		20
 31#define CLK_PLL2_D6		21
 32#define CLK_PLL2_D7		22
 33#define CLK_PLL2_D8		23
 34#define CLK_PLL3_D1		24
 35#define CLK_PLL3_D2		25
 36#define CLK_PLL3_D3		26
 37#define CLK_PLL3_D4		27
 38#define CLK_PLL3_D5		28
 39#define CLK_PLL3_D6		29
 40#define CLK_PLL3_D7		30
 41#define CLK_PLL3_D8		31
 42#define CLK_PLL3_80		32
 43#define CLK_PLL3_40		33
 44#define CLK_PLL3_20		34
 45
 46/* MPMU clocks */
 47#define CLK_PLL1_307P2		0
 48#define CLK_PLL1_76P8		1
 49#define CLK_PLL1_61P44		2
 50#define CLK_PLL1_153P6		3
 51#define CLK_PLL1_102P4		4
 52#define CLK_PLL1_51P2		5
 53#define CLK_PLL1_51P2_AP	6
 54#define CLK_PLL1_57P6		7
 55#define CLK_PLL1_25P6		8
 56#define CLK_PLL1_12P8		9
 57#define CLK_PLL1_12P8_WDT	10
 58#define CLK_PLL1_6P4		11
 59#define CLK_PLL1_3P2		12
 60#define CLK_PLL1_1P6		13
 61#define CLK_PLL1_0P8		14
 62#define CLK_PLL1_409P6		15
 63#define CLK_PLL1_204P8		16
 64#define CLK_PLL1_491		17
 65#define CLK_PLL1_245P76		18
 66#define CLK_PLL1_614		19
 67#define CLK_PLL1_47P26		20
 68#define CLK_PLL1_31P5		21
 69#define CLK_PLL1_819		22
 70#define CLK_PLL1_1228		23
 71#define CLK_SLOW_UART		24
 72#define CLK_SLOW_UART1		25
 73#define CLK_SLOW_UART2		26
 74#define CLK_WDT			27
 75#define CLK_RIPC		28
 76#define CLK_I2S_SYSCLK		29
 77#define CLK_I2S_BCLK		30
 78#define CLK_APB			31
 79#define CLK_WDT_BUS		32
 80#define CLK_I2S_153P6		33
 81#define CLK_I2S_153P6_BASE	34
 82#define CLK_I2S_SYSCLK_SRC	35
 83#define CLK_I2S_BCLK_FACTOR	36
 84
 85/* MPMU resets */
 86#define RESET_WDT		0
 87
 88/* APBC clocks */
 89#define CLK_UART0		0
 90#define CLK_UART2		1
 91#define CLK_UART3		2
 92#define CLK_UART4		3
 93#define CLK_UART5		4
 94#define CLK_UART6		5
 95#define CLK_UART7		6
 96#define CLK_UART8		7
 97#define CLK_UART9		8
 98#define CLK_GPIO		9
 99#define CLK_PWM0		10
100#define CLK_PWM1		11
101#define CLK_PWM2		12
102#define CLK_PWM3		13
103#define CLK_PWM4		14
104#define CLK_PWM5		15
105#define CLK_PWM6		16
106#define CLK_PWM7		17
107#define CLK_PWM8		18
108#define CLK_PWM9		19
109#define CLK_PWM10		20
110#define CLK_PWM11		21
111#define CLK_PWM12		22
112#define CLK_PWM13		23
113#define CLK_PWM14		24
114#define CLK_PWM15		25
115#define CLK_PWM16		26
116#define CLK_PWM17		27
117#define CLK_PWM18		28
118#define CLK_PWM19		29
119#define CLK_SSP3		30
120#define CLK_RTC			31
121#define CLK_TWSI0		32
122#define CLK_TWSI1		33
123#define CLK_TWSI2		34
124#define CLK_TWSI4		35
125#define CLK_TWSI5		36
126#define CLK_TWSI6		37
127#define CLK_TWSI7		38
128#define CLK_TWSI8		39
129#define CLK_TIMERS1		40
130#define CLK_TIMERS2		41
131#define CLK_AIB			42
132#define CLK_ONEWIRE		43
133#define CLK_SSPA0		44
134#define CLK_SSPA1		45
135#define CLK_DRO			46
136#define CLK_IR			47
137#define CLK_TSEN		48
138#define CLK_IPC_AP2AUD		49
139#define CLK_CAN0		50
140#define CLK_CAN0_BUS		51
141#define CLK_UART0_BUS		52
142#define CLK_UART2_BUS		53
143#define CLK_UART3_BUS		54
144#define CLK_UART4_BUS		55
145#define CLK_UART5_BUS		56
146#define CLK_UART6_BUS		57
147#define CLK_UART7_BUS		58
148#define CLK_UART8_BUS		59
149#define CLK_UART9_BUS		60
150#define CLK_GPIO_BUS		61
151#define CLK_PWM0_BUS		62
152#define CLK_PWM1_BUS		63
153#define CLK_PWM2_BUS		64
154#define CLK_PWM3_BUS		65
155#define CLK_PWM4_BUS		66
156#define CLK_PWM5_BUS		67
157#define CLK_PWM6_BUS		68
158#define CLK_PWM7_BUS		69
159#define CLK_PWM8_BUS		70
160#define CLK_PWM9_BUS		71
161#define CLK_PWM10_BUS		72
162#define CLK_PWM11_BUS		73
163#define CLK_PWM12_BUS		74
164#define CLK_PWM13_BUS		75
165#define CLK_PWM14_BUS		76
166#define CLK_PWM15_BUS		77
167#define CLK_PWM16_BUS		78
168#define CLK_PWM17_BUS		79
169#define CLK_PWM18_BUS		80
170#define CLK_PWM19_BUS		81
171#define CLK_SSP3_BUS		82
172#define CLK_RTC_BUS		83
173#define CLK_TWSI0_BUS		84
174#define CLK_TWSI1_BUS		85
175#define CLK_TWSI2_BUS		86
176#define CLK_TWSI4_BUS		87
177#define CLK_TWSI5_BUS		88
178#define CLK_TWSI6_BUS		89
179#define CLK_TWSI7_BUS		90
180#define CLK_TWSI8_BUS		91
181#define CLK_TIMERS1_BUS		92
182#define CLK_TIMERS2_BUS		93
183#define CLK_AIB_BUS		94
184#define CLK_ONEWIRE_BUS		95
185#define CLK_SSPA0_BUS		96
186#define CLK_SSPA1_BUS		97
187#define CLK_TSEN_BUS		98
188#define CLK_IPC_AP2AUD_BUS	99
189#define CLK_SSPA0_I2S_BCLK	100
190#define CLK_SSPA1_I2S_BCLK	101
191
192/* APBC resets */
193#define RESET_UART0		0
194#define RESET_UART2		1
195#define RESET_UART3		2
196#define RESET_UART4		3
197#define RESET_UART5		4
198#define RESET_UART6		5
199#define RESET_UART7		6
200#define RESET_UART8		7
201#define RESET_UART9		8
202#define RESET_GPIO		9
203#define RESET_PWM0		10
204#define RESET_PWM1		11
205#define RESET_PWM2		12
206#define RESET_PWM3		13
207#define RESET_PWM4		14
208#define RESET_PWM5		15
209#define RESET_PWM6		16
210#define RESET_PWM7		17
211#define RESET_PWM8		18
212#define RESET_PWM9		19
213#define RESET_PWM10		20
214#define RESET_PWM11		21
215#define RESET_PWM12		22
216#define RESET_PWM13		23
217#define RESET_PWM14		24
218#define RESET_PWM15		25
219#define RESET_PWM16		26
220#define RESET_PWM17		27
221#define RESET_PWM18		28
222#define RESET_PWM19		29
223#define RESET_SSP3		30
224#define RESET_RTC		31
225#define RESET_TWSI0		32
226#define RESET_TWSI1		33
227#define RESET_TWSI2		34
228#define RESET_TWSI4		35
229#define RESET_TWSI5		36
230#define RESET_TWSI6		37
231#define RESET_TWSI7		38
232#define RESET_TWSI8		39
233#define RESET_TIMERS1		40
234#define RESET_TIMERS2		41
235#define RESET_AIB		42
236#define RESET_ONEWIRE		43
237#define RESET_SSPA0		44
238#define RESET_SSPA1		45
239#define RESET_DRO		46
240#define RESET_IR		47
241#define RESET_TSEN		48
242#define RESET_IPC_AP2AUD	49
243#define RESET_CAN0		50
244
245/* APMU clocks */
246#define CLK_CCI550		0
247#define CLK_CPU_C0_HI		1
248#define CLK_CPU_C0_CORE		2
249#define CLK_CPU_C0_ACE		3
250#define CLK_CPU_C0_TCM		4
251#define CLK_CPU_C1_HI		5
252#define CLK_CPU_C1_CORE		6
253#define CLK_CPU_C1_ACE		7
254#define CLK_CCIC_4X		8
255#define CLK_CCIC1PHY		9
256#define CLK_SDH_AXI		10
257#define CLK_SDH0		11
258#define CLK_SDH1		12
259#define CLK_SDH2		13
260#define CLK_USB_P1		14
261#define CLK_USB_AXI		15
262#define CLK_USB30		16
263#define CLK_QSPI		17
264#define CLK_QSPI_BUS		18
265#define CLK_DMA			19
266#define CLK_AES			20
267#define CLK_VPU			21
268#define CLK_GPU			22
269#define CLK_EMMC		23
270#define CLK_EMMC_X		24
271#define CLK_AUDIO		25
272#define CLK_HDMI		26
273#define CLK_PMUA_ACLK		27
274#define CLK_PCIE0_MASTER	28
275#define CLK_PCIE0_SLAVE		29
276#define CLK_PCIE0_DBI		30
277#define CLK_PCIE1_MASTER	31
278#define CLK_PCIE1_SLAVE		32
279#define CLK_PCIE1_DBI		33
280#define CLK_PCIE2_MASTER	34
281#define CLK_PCIE2_SLAVE		35
282#define CLK_PCIE2_DBI		36
283#define CLK_EMAC0_BUS		37
284#define CLK_EMAC0_PTP		38
285#define CLK_EMAC1_BUS		39
286#define CLK_EMAC1_PTP		40
287#define CLK_JPG			41
288#define CLK_CCIC2PHY		42
289#define CLK_CCIC3PHY		43
290#define CLK_CSI			44
291#define CLK_CAMM0		45
292#define CLK_CAMM1		46
293#define CLK_CAMM2		47
294#define CLK_ISP_CPP		48
295#define CLK_ISP_BUS		49
296#define CLK_ISP			50
297#define CLK_DPU_MCLK		51
298#define CLK_DPU_ESC		52
299#define CLK_DPU_BIT		53
300#define CLK_DPU_PXCLK		54
301#define CLK_DPU_HCLK		55
302#define CLK_DPU_SPI		56
303#define CLK_DPU_SPI_HBUS	57
304#define CLK_DPU_SPIBUS		58
305#define CLK_DPU_SPI_ACLK	59
306#define CLK_V2D			60
307#define CLK_EMMC_BUS		61
308
309/* APMU resets */
310#define RESET_CCIC_4X		0
311#define RESET_CCIC1_PHY		1
312#define RESET_SDH_AXI		2
313#define RESET_SDH0		3
314#define RESET_SDH1		4
315#define RESET_SDH2		5
316#define RESET_USBP1_AXI		6
317#define RESET_USB_AXI		7
318#define RESET_USB30_AHB		8
319#define RESET_USB30_VCC		9
320#define RESET_USB30_PHY		10
321#define RESET_QSPI		11
322#define RESET_QSPI_BUS		12
323#define RESET_DMA		13
324#define RESET_AES		14
325#define RESET_VPU		15
326#define RESET_GPU		16
327#define RESET_EMMC		17
328#define RESET_EMMC_X		18
329#define RESET_AUDIO_SYS		19
330#define RESET_AUDIO_MCU		20
331#define RESET_AUDIO_APMU	21
332#define RESET_HDMI		22
333#define RESET_PCIE0_MASTER	23
334#define RESET_PCIE0_SLAVE	24
335#define RESET_PCIE0_DBI		25
336#define RESET_PCIE0_GLOBAL	26
337#define RESET_PCIE1_MASTER	27
338#define RESET_PCIE1_SLAVE	28
339#define RESET_PCIE1_DBI		29
340#define RESET_PCIE1_GLOBAL	30
341#define RESET_PCIE2_MASTER	31
342#define RESET_PCIE2_SLAVE	32
343#define RESET_PCIE2_DBI		33
344#define RESET_PCIE2_GLOBAL	34
345#define RESET_EMAC0		35
346#define RESET_EMAC1		36
347#define RESET_JPG		37
348#define RESET_CCIC2PHY		38
349#define RESET_CCIC3PHY		39
350#define RESET_CSI		40
351#define RESET_ISP_CPP		41
352#define RESET_ISP_BUS		42
353#define RESET_ISP		43
354#define RESET_ISP_CI		44
355#define RESET_DPU_MCLK		45
356#define RESET_DPU_ESC		46
357#define RESET_DPU_HCLK		47
358#define RESET_DPU_SPIBUS	48
359#define RESET_DPU_SPI_HBUS	49
360#define RESET_V2D		50
361#define RESET_MIPI		51
362#define RESET_MC		52
363
364/*	RCPU resets	*/
365#define RESET_RCPU_SSP0		0
366#define RESET_RCPU_I2C0		1
367#define RESET_RCPU_UART1	2
368#define RESET_RCPU_IR		3
369#define RESET_RCPU_CAN		4
370#define RESET_RCPU_UART0	5
371#define RESET_RCPU_HDMI_AUDIO	6
372
373/*	RCPU2 resets	*/
374#define RESET_RCPU2_PWM0	0
375#define RESET_RCPU2_PWM1	1
376#define RESET_RCPU2_PWM2	2
377#define RESET_RCPU2_PWM3	3
378#define RESET_RCPU2_PWM4	4
379#define RESET_RCPU2_PWM5	5
380#define RESET_RCPU2_PWM6	6
381#define RESET_RCPU2_PWM7	7
382#define RESET_RCPU2_PWM8	8
383#define RESET_RCPU2_PWM9	9
384
385/*	APBC2 resets	*/
386#define RESET_APBC2_UART1	0
387#define RESET_APBC2_SSP2	1
388#define RESET_APBC2_TWSI3	2
389#define RESET_APBC2_RTC		3
390#define RESET_APBC2_TIMERS0	4
391#define RESET_APBC2_KPC		5
392#define RESET_APBC2_GPIO	6
393
394#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */