sophgo,sg2044-clk.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
  2/*
  3 * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com>
  4 */
  5
  6#ifndef __DT_BINDINGS_SOPHGO_SG2044_CLK_H__
  7#define __DT_BINDINGS_SOPHGO_SG2044_CLK_H__
  8
  9#define CLK_DIV_AP_SYS_FIXED		0
 10#define CLK_DIV_AP_SYS_MAIN		1
 11#define CLK_DIV_RP_SYS_FIXED		2
 12#define CLK_DIV_RP_SYS_MAIN		3
 13#define CLK_DIV_TPU_SYS_FIXED		4
 14#define CLK_DIV_TPU_SYS_MAIN		5
 15#define CLK_DIV_NOC_SYS_FIXED		6
 16#define CLK_DIV_NOC_SYS_MAIN		7
 17#define CLK_DIV_VC_SRC0_FIXED		8
 18#define CLK_DIV_VC_SRC0_MAIN		9
 19#define CLK_DIV_VC_SRC1_FIXED		10
 20#define CLK_DIV_VC_SRC1_MAIN		11
 21#define CLK_DIV_CXP_MAC_FIXED		12
 22#define CLK_DIV_CXP_MAC_MAIN		13
 23#define CLK_DIV_DDR0_FIXED		14
 24#define CLK_DIV_DDR0_MAIN		15
 25#define CLK_DIV_DDR1_FIXED		16
 26#define CLK_DIV_DDR1_MAIN		17
 27#define CLK_DIV_DDR2_FIXED		18
 28#define CLK_DIV_DDR2_MAIN		19
 29#define CLK_DIV_DDR3_FIXED		20
 30#define CLK_DIV_DDR3_MAIN		21
 31#define CLK_DIV_DDR4_FIXED		22
 32#define CLK_DIV_DDR4_MAIN		23
 33#define CLK_DIV_DDR5_FIXED		24
 34#define CLK_DIV_DDR5_MAIN		25
 35#define CLK_DIV_DDR6_FIXED		26
 36#define CLK_DIV_DDR6_MAIN		27
 37#define CLK_DIV_DDR7_FIXED		28
 38#define CLK_DIV_DDR7_MAIN		29
 39#define CLK_DIV_TOP_50M			30
 40#define CLK_DIV_TOP_AXI0		31
 41#define CLK_DIV_TOP_AXI_HSPERI		32
 42#define CLK_DIV_TIMER0			33
 43#define CLK_DIV_TIMER1			34
 44#define CLK_DIV_TIMER2			35
 45#define CLK_DIV_TIMER3			36
 46#define CLK_DIV_TIMER4			37
 47#define CLK_DIV_TIMER5			38
 48#define CLK_DIV_TIMER6			39
 49#define CLK_DIV_TIMER7			40
 50#define CLK_DIV_CXP_TEST_PHY		41
 51#define CLK_DIV_CXP_TEST_ETH_PHY	42
 52#define CLK_DIV_C2C0_TEST_PHY		43
 53#define CLK_DIV_C2C1_TEST_PHY		44
 54#define CLK_DIV_PCIE_1G			45
 55#define CLK_DIV_UART_500M		46
 56#define CLK_DIV_GPIO_DB			47
 57#define CLK_DIV_SD			48
 58#define CLK_DIV_SD_100K			49
 59#define CLK_DIV_EMMC			50
 60#define CLK_DIV_EMMC_100K		51
 61#define CLK_DIV_EFUSE			52
 62#define CLK_DIV_TX_ETH0			53
 63#define CLK_DIV_PTP_REF_I_ETH0		54
 64#define CLK_DIV_REF_ETH0		55
 65#define CLK_DIV_PKA			56
 66#define CLK_MUX_DDR0			57
 67#define CLK_MUX_DDR1			58
 68#define CLK_MUX_DDR2			59
 69#define CLK_MUX_DDR3			60
 70#define CLK_MUX_DDR4			61
 71#define CLK_MUX_DDR5			62
 72#define CLK_MUX_DDR6			63
 73#define CLK_MUX_DDR7			64
 74#define CLK_MUX_NOC_SYS			65
 75#define CLK_MUX_TPU_SYS			66
 76#define CLK_MUX_RP_SYS			67
 77#define CLK_MUX_AP_SYS			68
 78#define CLK_MUX_VC_SRC0			69
 79#define CLK_MUX_VC_SRC1			70
 80#define CLK_MUX_CXP_MAC			71
 81#define CLK_GATE_AP_SYS			72
 82#define CLK_GATE_RP_SYS			73
 83#define CLK_GATE_TPU_SYS		74
 84#define CLK_GATE_NOC_SYS		75
 85#define CLK_GATE_VC_SRC0		76
 86#define CLK_GATE_VC_SRC1		77
 87#define CLK_GATE_DDR0			78
 88#define CLK_GATE_DDR1			79
 89#define CLK_GATE_DDR2			80
 90#define CLK_GATE_DDR3			81
 91#define CLK_GATE_DDR4			82
 92#define CLK_GATE_DDR5			83
 93#define CLK_GATE_DDR6			84
 94#define CLK_GATE_DDR7			85
 95#define CLK_GATE_TOP_50M		86
 96#define CLK_GATE_SC_RX			87
 97#define CLK_GATE_SC_RX_X0Y1		88
 98#define CLK_GATE_TOP_AXI0		89
 99#define CLK_GATE_INTC0			90
100#define CLK_GATE_INTC1			91
101#define CLK_GATE_INTC2			92
102#define CLK_GATE_INTC3			93
103#define CLK_GATE_MAILBOX0		94
104#define CLK_GATE_MAILBOX1		95
105#define CLK_GATE_MAILBOX2		96
106#define CLK_GATE_MAILBOX3		97
107#define CLK_GATE_TOP_AXI_HSPERI		98
108#define CLK_GATE_APB_TIMER		99
109#define CLK_GATE_TIMER0			100
110#define CLK_GATE_TIMER1			101
111#define CLK_GATE_TIMER2			102
112#define CLK_GATE_TIMER3			103
113#define CLK_GATE_TIMER4			104
114#define CLK_GATE_TIMER5			105
115#define CLK_GATE_TIMER6			106
116#define CLK_GATE_TIMER7			107
117#define CLK_GATE_CXP_CFG		108
118#define CLK_GATE_CXP_MAC		109
119#define CLK_GATE_CXP_TEST_PHY		110
120#define CLK_GATE_CXP_TEST_ETH_PHY	111
121#define CLK_GATE_PCIE_1G		112
122#define CLK_GATE_C2C0_TEST_PHY		113
123#define CLK_GATE_C2C1_TEST_PHY		114
124#define CLK_GATE_UART_500M		115
125#define CLK_GATE_APB_UART		116
126#define CLK_GATE_APB_SPI		117
127#define CLK_GATE_AHB_SPIFMC		118
128#define CLK_GATE_APB_I2C		119
129#define CLK_GATE_AXI_DBG_I2C		120
130#define CLK_GATE_GPIO_DB		121
131#define CLK_GATE_APB_GPIO_INTR		122
132#define CLK_GATE_APB_GPIO		123
133#define CLK_GATE_SD			124
134#define CLK_GATE_AXI_SD			125
135#define CLK_GATE_SD_100K		126
136#define CLK_GATE_EMMC			127
137#define CLK_GATE_AXI_EMMC		128
138#define CLK_GATE_EMMC_100K		129
139#define CLK_GATE_EFUSE			130
140#define CLK_GATE_APB_EFUSE		131
141#define CLK_GATE_SYSDMA_AXI		132
142#define CLK_GATE_TX_ETH0		133
143#define CLK_GATE_AXI_ETH0		134
144#define CLK_GATE_PTP_REF_I_ETH0		135
145#define CLK_GATE_REF_ETH0		136
146#define CLK_GATE_APB_RTC		137
147#define CLK_GATE_APB_PWM		138
148#define CLK_GATE_APB_WDT		139
149#define CLK_GATE_AXI_SRAM		140
150#define CLK_GATE_AHB_ROM		141
151#define CLK_GATE_PKA			142
152
153#endif /* __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ */