rockchip,rv1126b-cru.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
  2/*
  3 * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
  4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
  5 */
  6
  7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
  8#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
  9
 10/* pll clocks */
 11#define PLL_GPLL				0
 12#define PLL_CPLL				1
 13#define PLL_AUPLL				2
 14#define ARMCLK					3
 15#define SCLK_DDR				4
 16
 17/* clk (clocks) */
 18#define CLK_CPLL_DIV20				5
 19#define CLK_CPLL_DIV10				6
 20#define CLK_CPLL_DIV8				7
 21#define CLK_GPLL_DIV8				8
 22#define CLK_GPLL_DIV6				9
 23#define CLK_GPLL_DIV4				10
 24#define CLK_CPLL_DIV3				11
 25#define CLK_GPLL_DIV3				12
 26#define CLK_CPLL_DIV2				13
 27#define CLK_GPLL_DIV2				14
 28#define CLK_CM_FRAC0				15
 29#define CLK_CM_FRAC1				16
 30#define CLK_CM_FRAC2				17
 31#define CLK_UART_FRAC0				18
 32#define CLK_UART_FRAC1				19
 33#define CLK_AUDIO_FRAC0				20
 34#define CLK_AUDIO_FRAC1				21
 35#define CLK_AUDIO_INT0				22
 36#define CLK_AUDIO_INT1				23
 37#define SCLK_UART0_SRC				24
 38#define SCLK_UART1				25
 39#define SCLK_UART2				26
 40#define SCLK_UART3				27
 41#define SCLK_UART4				28
 42#define SCLK_UART5				29
 43#define SCLK_UART6				30
 44#define SCLK_UART7				31
 45#define MCLK_SAI0				32
 46#define MCLK_SAI1				33
 47#define MCLK_SAI2				34
 48#define MCLK_PDM				35
 49#define CLKOUT_PDM				36
 50#define MCLK_ASRC0				37
 51#define MCLK_ASRC1				38
 52#define MCLK_ASRC2				39
 53#define MCLK_ASRC3				40
 54#define CLK_ASRC0				41
 55#define CLK_ASRC1				42
 56#define CLK_CORE_PLL				43
 57#define CLK_NPU_PLL				44
 58#define CLK_VEPU_PLL				45
 59#define CLK_ISP_PLL				46
 60#define CLK_AISP_PLL				47
 61#define CLK_SARADC0_SRC				48
 62#define CLK_SARADC1_SRC				49
 63#define CLK_SARADC2_SRC				50
 64#define HCLK_NPU_ROOT				51
 65#define PCLK_NPU_ROOT				52
 66#define ACLK_VEPU_ROOT				53
 67#define HCLK_VEPU_ROOT				54
 68#define PCLK_VEPU_ROOT				55
 69#define CLK_CORE_RGA_SRC			56
 70#define ACLK_GMAC_ROOT				57
 71#define ACLK_VI_ROOT				58
 72#define HCLK_VI_ROOT				59
 73#define PCLK_VI_ROOT				60
 74#define DCLK_VICAP_ROOT				61
 75#define CLK_SYS_DSMC_ROOT			62
 76#define ACLK_VDO_ROOT				63
 77#define ACLK_RKVDEC_ROOT			64
 78#define HCLK_VDO_ROOT				65
 79#define PCLK_VDO_ROOT				66
 80#define DCLK_OOC_SRC				67
 81#define DCLK_VOP				68
 82#define DCLK_DECOM_SRC				69
 83#define PCLK_DDR_ROOT				70
 84#define ACLK_SYSMEM_SRC				71
 85#define ACLK_TOP_ROOT				72
 86#define ACLK_BUS_ROOT				73
 87#define HCLK_BUS_ROOT				74
 88#define PCLK_BUS_ROOT				75
 89#define CCLK_SDMMC0				76
 90#define CCLK_SDMMC1				77
 91#define CCLK_EMMC				78
 92#define SCLK_2X_FSPI0				79
 93#define CLK_GMAC_PTP_REF_SRC			80
 94#define CLK_GMAC_125M				81
 95#define CLK_TIMER_ROOT				82
 96#define TCLK_WDT_NS_SRC				83
 97#define TCLK_WDT_S_SRC				84
 98#define TCLK_WDT_HPMCU				85
 99#define CLK_CAN0				86
100#define CLK_CAN1				87
101#define PCLK_PERI_ROOT				88
102#define ACLK_PERI_ROOT				89
103#define CLK_I2C_BUS_SRC				90
104#define CLK_SPI0				91
105#define CLK_SPI1				92
106#define BUSCLK_PMU_SRC				93
107#define CLK_PWM0				94
108#define CLK_PWM2				95
109#define CLK_PWM3				96
110#define CLK_PKA_RKCE_SRC			97
111#define ACLK_RKCE_SRC				98
112#define ACLK_VCP_ROOT				99
113#define HCLK_VCP_ROOT				100
114#define PCLK_VCP_ROOT				101
115#define CLK_CORE_FEC_SRC			102
116#define CLK_CORE_AVSP_SRC			103
117#define CLK_50M_GMAC_IOBUF_VI			104
118#define PCLK_TOP_ROOT				105
119#define CLK_MIPI0_OUT2IO			106
120#define CLK_MIPI1_OUT2IO			107
121#define CLK_MIPI2_OUT2IO			108
122#define CLK_MIPI3_OUT2IO			109
123#define CLK_CIF_OUT2IO				110
124#define CLK_MAC_OUT2IO				111
125#define MCLK_SAI0_OUT2IO			112
126#define MCLK_SAI1_OUT2IO			113
127#define MCLK_SAI2_OUT2IO			114
128#define CLK_CM_FRAC0_SRC			115
129#define CLK_CM_FRAC1_SRC			116
130#define CLK_CM_FRAC2_SRC			117
131#define CLK_UART_FRAC0_SRC			118
132#define CLK_UART_FRAC1_SRC			119
133#define CLK_AUDIO_FRAC0_SRC			120
134#define CLK_AUDIO_FRAC1_SRC			121
135#define ACLK_NPU_ROOT				122
136#define HCLK_RKNN				123
137#define ACLK_RKNN				124
138#define PCLK_GPIO3				125
139#define DBCLK_GPIO3				126
140#define PCLK_IOC_VCCIO3				127
141#define PCLK_SARADC0				128
142#define CLK_SARADC0				129
143#define HCLK_SDMMC1				130
144#define HCLK_VEPU				131
145#define ACLK_VEPU				132
146#define CLK_CORE_VEPU				133
147#define HCLK_FEC				134
148#define ACLK_FEC				135
149#define CLK_CORE_FEC				136
150#define HCLK_AVSP				137
151#define ACLK_AVSP				138
152#define BUSCLK_PMU1_ROOT			139
153#define HCLK_AISP				140
154#define ACLK_AISP				141
155#define CLK_CORE_AISP				142
156#define CLK_CORE_ISP_ROOT			143
157#define PCLK_DSMC				144
158#define ACLK_DSMC				145
159#define HCLK_CAN0				146
160#define HCLK_CAN1				147
161#define PCLK_GPIO2				148
162#define DBCLK_GPIO2				149
163#define PCLK_GPIO4				150
164#define DBCLK_GPIO4				151
165#define PCLK_GPIO5				152
166#define DBCLK_GPIO5				153
167#define PCLK_GPIO6				154
168#define DBCLK_GPIO6				155
169#define PCLK_GPIO7				156
170#define DBCLK_GPIO7				157
171#define PCLK_IOC_VCCIO2				158
172#define PCLK_IOC_VCCIO4				159
173#define PCLK_IOC_VCCIO5				160
174#define PCLK_IOC_VCCIO6				161
175#define PCLK_IOC_VCCIO7				162
176#define HCLK_ISP				163
177#define ACLK_ISP				164
178#define CLK_CORE_ISP				165
179#define HCLK_VICAP				166
180#define ACLK_VICAP				167
181#define DCLK_VICAP				168
182#define ISP0CLK_VICAP				169
183#define HCLK_VPSS				170
184#define ACLK_VPSS				171
185#define CLK_CORE_VPSS				172
186#define PCLK_CSI2HOST0				173
187#define DCLK_CSI2HOST0				174
188#define PCLK_CSI2HOST1				175
189#define DCLK_CSI2HOST1				176
190#define PCLK_CSI2HOST2				177
191#define DCLK_CSI2HOST2				178
192#define PCLK_CSI2HOST3				179
193#define DCLK_CSI2HOST3				180
194#define HCLK_SDMMC0				181
195#define ACLK_GMAC				182
196#define PCLK_GMAC				183
197#define CLK_GMAC_PTP_REF			184
198#define PCLK_CSIPHY0				185
199#define PCLK_CSIPHY1				186
200#define PCLK_MACPHY				187
201#define PCLK_SARADC1				188
202#define CLK_SARADC1				189
203#define PCLK_SARADC2				190
204#define CLK_SARADC2				191
205#define ACLK_RKVDEC				192
206#define HCLK_RKVDEC				193
207#define CLK_HEVC_CA_RKVDEC			194
208#define ACLK_VOP				195
209#define HCLK_VOP				196
210#define HCLK_RKJPEG				197
211#define ACLK_RKJPEG				198
212#define ACLK_RKMMU_DECOM			199
213#define HCLK_RKMMU_DECOM			200
214#define DCLK_DECOM				201
215#define ACLK_DECOM				202
216#define PCLK_DECOM				203
217#define PCLK_MIPI_DSI				204
218#define PCLK_DSIPHY				205
219#define ACLK_OOC				206
220#define ACLK_SYSMEM				207
221#define PCLK_DDRC				208
222#define PCLK_DDRMON				209
223#define CLK_TIMER_DDRMON			210
224#define PCLK_DFICTRL				211
225#define PCLK_DDRPHY				212
226#define PCLK_DMA2DDR				213
227#define CLK_RCOSC_SRC				214
228#define BUSCLK_PMU_MUX				215
229#define BUSCLK_PMU_ROOT				216
230#define PCLK_PMU				217
231#define CLK_XIN_RC_DIV				218
232#define CLK_32K					219
233#define PCLK_PMU_GPIO0				220
234#define DBCLK_PMU_GPIO0				221
235#define PCLK_PMU_HP_TIMER			222
236#define CLK_PMU_HP_TIMER			223
237#define CLK_PMU_32K_HP_TIMER			224
238#define PCLK_PWM1				225
239#define CLK_PWM1				226
240#define CLK_OSC_PWM1				227
241#define CLK_RC_PWM1				228
242#define CLK_FREQ_PWM1				229
243#define CLK_COUNTER_PWM1			230
244#define PCLK_I2C2				231
245#define CLK_I2C2				232
246#define PCLK_UART0				233
247#define SCLK_UART0				234
248#define PCLK_RCOSC_CTRL				235
249#define CLK_OSC_RCOSC_CTRL			236
250#define CLK_REF_RCOSC_CTRL			237
251#define PCLK_IOC_PMUIO0				238
252#define CLK_REFOUT				239
253#define CLK_PREROLL				240
254#define CLK_PREROLL_32K				241
255#define HCLK_PMU_SRAM				242
256#define PCLK_WDT_LPMCU				243
257#define TCLK_WDT_LPMCU				244
258#define CLK_LPMCU				245
259#define CLK_LPMCU_RTC				246
260#define PCLK_LPMCU_MAILBOX			247
261#define HCLK_OOC				248
262#define PCLK_SPI2AHB				249
263#define HCLK_SPI2AHB				250
264#define HCLK_FSPI1				251
265#define HCLK_XIP_FSPI1				252
266#define SCLK_1X_FSPI1				253
267#define PCLK_IOC_PMUIO1				254
268#define PCLK_AUDIO_ADC_PMU			255
269#define MCLK_AUDIO_ADC_PMU			256
270#define MCLK_AUDIO_ADC_DIV4_PMU			257
271#define MCLK_LPSAI				258
272#define ACLK_GIC400				259
273#define PCLK_WDT_NS				260
274#define TCLK_WDT_NS				261
275#define PCLK_WDT_HPMCU				262
276#define HCLK_CACHE				263
277#define PCLK_HPMCU_MAILBOX			264
278#define PCLK_HPMCU_INTMUX			265
279#define CLK_HPMCU				266
280#define CLK_HPMCU_RTC				267
281#define PCLK_RKDMA				268
282#define ACLK_RKDMA				269
283#define PCLK_DCF				270
284#define ACLK_DCF				271
285#define HCLK_RGA				272
286#define ACLK_RGA				273
287#define CLK_CORE_RGA				274
288#define PCLK_TIMER				275
289#define CLK_TIMER0				276
290#define CLK_TIMER1				277
291#define CLK_TIMER2				278
292#define CLK_TIMER3				279
293#define CLK_TIMER4				280
294#define CLK_TIMER5				281
295#define PCLK_I2C0				282
296#define CLK_I2C0				283
297#define PCLK_I2C1				284
298#define CLK_I2C1				285
299#define PCLK_I2C3				286
300#define CLK_I2C3				287
301#define PCLK_I2C4				288
302#define CLK_I2C4				289
303#define PCLK_I2C5				290
304#define CLK_I2C5				291
305#define PCLK_SPI0				292
306#define PCLK_SPI1				293
307#define PCLK_PWM0				294
308#define CLK_OSC_PWM0				295
309#define CLK_RC_PWM0				296
310#define PCLK_PWM2				297
311#define CLK_OSC_PWM2				298
312#define CLK_RC_PWM2				299
313#define PCLK_PWM3				300
314#define CLK_OSC_PWM3				301
315#define CLK_RC_PWM3				302
316#define PCLK_UART1				303
317#define PCLK_UART2				304
318#define PCLK_UART3				305
319#define PCLK_UART4				306
320#define PCLK_UART5				307
321#define PCLK_UART6				308
322#define PCLK_UART7				309
323#define PCLK_TSADC				310
324#define CLK_TSADC				311
325#define HCLK_SAI0				312
326#define HCLK_SAI1				313
327#define HCLK_SAI2				314
328#define HCLK_RKDSM				315
329#define MCLK_RKDSM				316
330#define HCLK_PDM				317
331#define HCLK_ASRC0				318
332#define HCLK_ASRC1				319
333#define PCLK_AUDIO_ADC_BUS			320
334#define MCLK_AUDIO_ADC_BUS			321
335#define MCLK_AUDIO_ADC_DIV4_BUS			322
336#define PCLK_RKCE				323
337#define HCLK_NS_RKCE				324
338#define PCLK_OTPC_NS				325
339#define CLK_SBPI_OTPC_NS			326
340#define CLK_USER_OTPC_NS			327
341#define CLK_OTPC_ARB				328
342#define PCLK_OTP_MASK				329
343#define CLK_TSADC_PHYCTRL			330
344#define LRCK_SRC_ASRC0				331
345#define LRCK_DST_ASRC0				332
346#define LRCK_SRC_ASRC1				333
347#define LRCK_DST_ASRC1				334
348#define PCLK_KEY_READER				335
349#define ACLK_NSRKCE				336
350#define CLK_PKA_NSRKCE				337
351#define PCLK_RTC_ROOT				338
352#define PCLK_GPIO1				339
353#define DBCLK_GPIO1				340
354#define PCLK_IOC_VCCIO1				341
355#define ACLK_USB3OTG				342
356#define CLK_REF_USB3OTG				343
357#define CLK_SUSPEND_USB3OTG			344
358#define HCLK_USB2HOST				345
359#define HCLK_ARB_USB2HOST			346
360#define PCLK_RTC_TEST				347
361#define HCLK_EMMC				348
362#define HCLK_FSPI0				349
363#define HCLK_XIP_FSPI0				350
364#define PCLK_PIPEPHY				351
365#define PCLK_USB2PHY				352
366#define CLK_REF_PIPEPHY_CPLL_SRC		353
367#define CLK_REF_PIPEPHY				354
368#define HCLK_VPSL				355
369#define ACLK_VPSL				356
370#define CLK_CORE_VPSL				357
371#define CLK_MACPHY				358
372#define HCLK_RKRNG_NS				359
373#define HCLK_RKRNG_S_NS				360
374#define CLK_AISP_PLL_SRC			361
375
376/* secure clks */
377#define CLK_USER_OTPC_S				362
378#define CLK_SBPI_OTPC_S				363
379#define PCLK_OTPC_S				364
380#define PCLK_KEY_READER_S			365
381#define HCLK_KL_RKCE_S				366
382#define HCLK_RKCE_S				367
383#define PCLK_WDT_S				368
384#define TCLK_WDT_S				369
385#define CLK_STIMER0				370
386#define CLK_STIMER1				371
387#define PLK_STIMER				372
388#define HCLK_RKRNG_S				373
389#define CLK_PKA_RKCE_S				374
390#define ACLK_RKCE_S				375
391
392#endif