rockchip,rk3562-cru.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2/*
  3 * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd.
  4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
  5 */
  6
  7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
  8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
  9
 10/* cru-clocks indices */
 11
 12/* cru plls */
 13#define PLL_DMPLL0			0
 14#define PLL_APLL			1
 15#define PLL_GPLL			2
 16#define PLL_VPLL			3
 17#define PLL_HPLL			4
 18#define PLL_CPLL			5
 19#define PLL_DPLL			6
 20#define PLL_DMPLL1			7
 21
 22/* cru clocks */
 23#define ARMCLK				8
 24#define CLK_GPU				9
 25#define ACLK_RKNN			10
 26#define CLK_DDR				11
 27#define CLK_MATRIX_50M_SRC		12
 28#define CLK_MATRIX_100M_SRC		13
 29#define CLK_MATRIX_125M_SRC		14
 30#define CLK_MATRIX_200M_SRC		15
 31#define CLK_MATRIX_300M_SRC		16
 32#define ACLK_TOP			17
 33#define ACLK_TOP_VIO			18
 34#define CLK_CAM0_OUT2IO			19
 35#define CLK_CAM1_OUT2IO			20
 36#define CLK_CAM2_OUT2IO			21
 37#define CLK_CAM3_OUT2IO			22
 38#define ACLK_BUS			23
 39#define HCLK_BUS			24
 40#define PCLK_BUS			25
 41#define PCLK_I2C1			26
 42#define PCLK_I2C2			27
 43#define PCLK_I2C3			28
 44#define PCLK_I2C4			29
 45#define PCLK_I2C5			30
 46#define CLK_I2C				31
 47#define CLK_I2C1			32
 48#define CLK_I2C2			33
 49#define CLK_I2C3			34
 50#define CLK_I2C4			35
 51#define CLK_I2C5			36
 52#define DCLK_BUS_GPIO			37
 53#define DCLK_BUS_GPIO3			38
 54#define DCLK_BUS_GPIO4			39
 55#define PCLK_TIMER			40
 56#define CLK_TIMER0			41
 57#define CLK_TIMER1			42
 58#define CLK_TIMER2			43
 59#define CLK_TIMER3			44
 60#define CLK_TIMER4			45
 61#define CLK_TIMER5			46
 62#define PCLK_STIMER			47
 63#define CLK_STIMER0			48
 64#define CLK_STIMER1			49
 65#define PCLK_WDTNS			50
 66#define CLK_WDTNS			51
 67#define PCLK_GRF			52
 68#define PCLK_SGRF			53
 69#define PCLK_MAILBOX			54
 70#define PCLK_INTC			55
 71#define ACLK_BUS_GIC400			56
 72#define ACLK_BUS_SPINLOCK		57
 73#define ACLK_DCF			58
 74#define PCLK_DCF			59
 75#define FCLK_BUS_CM0_CORE		60
 76#define CLK_BUS_CM0_RTC			61
 77#define HCLK_ICACHE			62
 78#define HCLK_DCACHE			63
 79#define PCLK_TSADC			64
 80#define CLK_TSADC			65
 81#define CLK_TSADC_TSEN			66
 82#define PCLK_DFT2APB			67
 83#define CLK_SARADC_VCCIO156		68
 84#define PCLK_GMAC			69
 85#define ACLK_GMAC			70
 86#define CLK_GMAC_125M_CRU_I		71
 87#define CLK_GMAC_50M_CRU_I		72
 88#define CLK_GMAC_50M_O			73
 89#define CLK_GMAC_ETH_OUT2IO		74
 90#define PCLK_APB2ASB_VCCIO156		75
 91#define PCLK_TO_VCCIO156		76
 92#define PCLK_DSIPHY			77
 93#define PCLK_DSITX			78
 94#define PCLK_CPU_EMA_DET		79
 95#define PCLK_HASH			80
 96#define PCLK_TOPCRU			81
 97#define PCLK_ASB2APB_VCCIO156		82
 98#define PCLK_IOC_VCCIO156		83
 99#define PCLK_GPIO3_VCCIO156		84
100#define PCLK_GPIO4_VCCIO156		85
101#define PCLK_SARADC_VCCIO156		86
102#define PCLK_MAC100			87
103#define ACLK_MAC100			89
104#define CLK_MAC100_50M_MATRIX		90
105#define HCLK_CORE			91
106#define PCLK_DDR			92
107#define CLK_MSCH_BRG_BIU		93
108#define PCLK_DDR_HWLP			94
109#define PCLK_DDR_UPCTL			95
110#define PCLK_DDR_PHY			96
111#define PCLK_DDR_DFICTL			97
112#define PCLK_DDR_DMA2DDR		98
113#define PCLK_DDR_MON			99
114#define TMCLK_DDR_MON			100
115#define PCLK_DDR_GRF			101
116#define PCLK_DDR_CRU			102
117#define PCLK_SUBDDR_CRU			103
118#define CLK_GPU_PRE			104
119#define ACLK_GPU_PRE			105
120#define CLK_GPU_BRG			107
121#define CLK_NPU_PRE			108
122#define HCLK_NPU_PRE			109
123#define HCLK_RKNN			111
124#define ACLK_PERI			112
125#define HCLK_PERI			113
126#define PCLK_PERI			114
127#define PCLK_PERICRU			115
128#define HCLK_SAI0			116
129#define CLK_SAI0_SRC			117
130#define CLK_SAI0_FRAC			118
131#define CLK_SAI0			119
132#define MCLK_SAI0			120
133#define MCLK_SAI0_OUT2IO		121
134#define HCLK_SAI1			122
135#define CLK_SAI1_SRC			123
136#define CLK_SAI1_FRAC			124
137#define CLK_SAI1			125
138#define MCLK_SAI1			126
139#define MCLK_SAI1_OUT2IO		127
140#define HCLK_SAI2			128
141#define CLK_SAI2_SRC			129
142#define CLK_SAI2_FRAC			130
143#define CLK_SAI2			131
144#define MCLK_SAI2			132
145#define MCLK_SAI2_OUT2IO		133
146#define HCLK_DSM			134
147#define CLK_DSM				135
148#define HCLK_PDM			136
149#define MCLK_PDM			137
150#define HCLK_SPDIF			138
151#define CLK_SPDIF_SRC			139
152#define CLK_SPDIF_FRAC			140
153#define CLK_SPDIF			141
154#define MCLK_SPDIF			142
155#define HCLK_SDMMC0			143
156#define CCLK_SDMMC0			144
157#define HCLK_SDMMC1			145
158#define CCLK_SDMMC1			146
159#define SCLK_SDMMC0_DRV			147
160#define SCLK_SDMMC0_SAMPLE		148
161#define SCLK_SDMMC1_DRV			149
162#define SCLK_SDMMC1_SAMPLE		150
163#define HCLK_EMMC			151
164#define ACLK_EMMC			152
165#define CCLK_EMMC			153
166#define BCLK_EMMC			154
167#define TMCLK_EMMC			155
168#define SCLK_SFC			156
169#define HCLK_SFC			157
170#define HCLK_USB2HOST			158
171#define HCLK_USB2HOST_ARB		159
172#define PCLK_SPI1			160
173#define CLK_SPI1			161
174#define SCLK_IN_SPI1			162
175#define PCLK_SPI2			163
176#define CLK_SPI2			164
177#define SCLK_IN_SPI2			165
178#define PCLK_UART1			166
179#define PCLK_UART2			167
180#define PCLK_UART3			168
181#define PCLK_UART4			169
182#define PCLK_UART5			170
183#define PCLK_UART6			171
184#define PCLK_UART7			172
185#define PCLK_UART8			173
186#define PCLK_UART9			174
187#define CLK_UART1_SRC			175
188#define CLK_UART1_FRAC			176
189#define CLK_UART1			177
190#define SCLK_UART1			178
191#define CLK_UART2_SRC			179
192#define CLK_UART2_FRAC			180
193#define CLK_UART2			181
194#define SCLK_UART2			182
195#define CLK_UART3_SRC			183
196#define CLK_UART3_FRAC			184
197#define CLK_UART3			185
198#define SCLK_UART3			186
199#define CLK_UART4_SRC			187
200#define CLK_UART4_FRAC			188
201#define CLK_UART4			189
202#define SCLK_UART4			190
203#define CLK_UART5_SRC			191
204#define CLK_UART5_FRAC			192
205#define CLK_UART5			193
206#define SCLK_UART5			194
207#define CLK_UART6_SRC			195
208#define CLK_UART6_FRAC			196
209#define CLK_UART6			197
210#define SCLK_UART6			198
211#define CLK_UART7_SRC			199
212#define CLK_UART7_FRAC			200
213#define CLK_UART7			201
214#define SCLK_UART7			202
215#define CLK_UART8_SRC			203
216#define CLK_UART8_FRAC			204
217#define CLK_UART8			205
218#define SCLK_UART8			206
219#define CLK_UART9_SRC			207
220#define CLK_UART9_FRAC			208
221#define CLK_UART9			209
222#define SCLK_UART9			210
223#define PCLK_PWM1_PERI			211
224#define CLK_PWM1_PERI			212
225#define CLK_CAPTURE_PWM1_PERI		213
226#define PCLK_PWM2_PERI			214
227#define CLK_PWM2_PERI			215
228#define CLK_CAPTURE_PWM2_PERI		216
229#define PCLK_PWM3_PERI			217
230#define CLK_PWM3_PERI			218
231#define CLK_CAPTURE_PWM3_PERI		219
232#define PCLK_CAN0			220
233#define CLK_CAN0			221
234#define PCLK_CAN1			222
235#define CLK_CAN1			223
236#define ACLK_CRYPTO			224
237#define HCLK_CRYPTO			225
238#define PCLK_CRYPTO			226
239#define CLK_CORE_CRYPTO			227
240#define CLK_PKA_CRYPTO			228
241#define HCLK_KLAD			229
242#define PCLK_KEY_READER			230
243#define HCLK_RK_RNG_NS			231
244#define HCLK_RK_RNG_S			232
245#define HCLK_TRNG_NS			233
246#define HCLK_TRNG_S			234
247#define HCLK_CRYPTO_S			235
248#define PCLK_PERI_WDT			236
249#define TCLK_PERI_WDT			237
250#define ACLK_SYSMEM			238
251#define HCLK_BOOTROM			239
252#define PCLK_PERI_GRF			240
253#define ACLK_DMAC			241
254#define ACLK_RKDMAC			242
255#define PCLK_OTPC_NS			243
256#define CLK_SBPI_OTPC_NS		244
257#define CLK_USER_OTPC_NS		245
258#define PCLK_OTPC_S			246
259#define CLK_SBPI_OTPC_S			247
260#define CLK_USER_OTPC_S			248
261#define CLK_OTPC_ARB			249
262#define PCLK_OTPPHY			250
263#define PCLK_USB2PHY			251
264#define PCLK_PIPEPHY			252
265#define PCLK_SARADC			253
266#define CLK_SARADC			254
267#define PCLK_IOC_VCCIO234		255
268#define PCLK_PERI_GPIO1			256
269#define PCLK_PERI_GPIO2			257
270#define DCLK_PERI_GPIO			258
271#define DCLK_PERI_GPIO1			259
272#define DCLK_PERI_GPIO2			260
273#define ACLK_PHP			261
274#define PCLK_PHP			262
275#define ACLK_PCIE20_MST			263
276#define ACLK_PCIE20_SLV			264
277#define ACLK_PCIE20_DBI			265
278#define PCLK_PCIE20			266
279#define CLK_PCIE20_AUX			267
280#define ACLK_USB3OTG			268
281#define CLK_USB3OTG_SUSPEND		269
282#define CLK_USB3OTG_REF			270
283#define CLK_PIPEPHY_REF_FUNC		271
284#define CLK_200M_PMU			272
285#define CLK_RTC_32K			273
286#define CLK_RTC32K_FRAC			274
287#define BUSCLK_PDPMU0			275
288#define PCLK_PMU0_CRU			276
289#define PCLK_PMU0_PMU			277
290#define CLK_PMU0_PMU			278
291#define PCLK_PMU0_HP_TIMER		279
292#define CLK_PMU0_HP_TIMER		280
293#define CLK_PMU0_32K_HP_TIMER		281
294#define PCLK_PMU0_PVTM			282
295#define CLK_PMU0_PVTM			283
296#define PCLK_IOC_PMUIO			284
297#define PCLK_PMU0_GPIO0			285
298#define DBCLK_PMU0_GPIO0		286
299#define PCLK_PMU0_GRF			287
300#define PCLK_PMU0_SGRF			288
301#define CLK_DDR_FAIL_SAFE		289
302#define PCLK_PMU0_SCRKEYGEN		290
303#define PCLK_PMU1_CRU			291
304#define HCLK_PMU1_MEM			292
305#define PCLK_PMU0_I2C0			293
306#define CLK_PMU0_I2C0			294
307#define PCLK_PMU1_UART0			295
308#define CLK_PMU1_UART0_SRC		296
309#define CLK_PMU1_UART0_FRAC		297
310#define CLK_PMU1_UART0			298
311#define SCLK_PMU1_UART0			299
312#define PCLK_PMU1_SPI0			300
313#define CLK_PMU1_SPI0			301
314#define SCLK_IN_PMU1_SPI0		302
315#define PCLK_PMU1_PWM0			303
316#define CLK_PMU1_PWM0			304
317#define CLK_CAPTURE_PMU1_PWM0		305
318#define CLK_PMU1_WIFI			306
319#define FCLK_PMU1_CM0_CORE		307
320#define CLK_PMU1_CM0_RTC		308
321#define PCLK_PMU1_WDTNS			309
322#define CLK_PMU1_WDTNS			310
323#define PCLK_PMU1_MAILBOX		311
324#define CLK_PIPEPHY_DIV			312
325#define CLK_PIPEPHY_XIN24M		313
326#define CLK_PIPEPHY_REF			314
327#define CLK_24M_SSCSRC			315
328#define CLK_USB2PHY_XIN24M		316
329#define CLK_USB2PHY_REF			317
330#define CLK_MIPIDSIPHY_XIN24M		318
331#define CLK_MIPIDSIPHY_REF		319
332#define ACLK_RGA_PRE			320
333#define HCLK_RGA_PRE			321
334#define ACLK_RGA			322
335#define HCLK_RGA			323
336#define CLK_RGA_CORE			324
337#define ACLK_JDEC			325
338#define HCLK_JDEC			326
339#define ACLK_VDPU_PRE			327
340#define CLK_RKVDEC_HEVC_CA		328
341#define HCLK_VDPU_PRE			329
342#define ACLK_RKVDEC			330
343#define HCLK_RKVDEC			331
344#define CLK_RKVENC_CORE			332
345#define ACLK_VEPU_PRE			333
346#define HCLK_VEPU_PRE			334
347#define ACLK_RKVENC			335
348#define HCLK_RKVENC			336
349#define ACLK_VI				337
350#define HCLK_VI				338
351#define PCLK_VI				339
352#define ACLK_ISP			340
353#define HCLK_ISP			341
354#define CLK_ISP				342
355#define ACLK_VICAP			343
356#define HCLK_VICAP			344
357#define DCLK_VICAP			345
358#define CSIRX0_CLK_DATA			346
359#define CSIRX1_CLK_DATA			347
360#define CSIRX2_CLK_DATA			348
361#define CSIRX3_CLK_DATA			349
362#define PCLK_CSIHOST0			350
363#define PCLK_CSIHOST1			351
364#define PCLK_CSIHOST2			352
365#define PCLK_CSIHOST3			353
366#define PCLK_CSIPHY0			354
367#define PCLK_CSIPHY1			355
368#define ACLK_VO_PRE			356
369#define HCLK_VO_PRE			357
370#define ACLK_VOP			358
371#define HCLK_VOP			359
372#define DCLK_VOP			360
373#define DCLK_VOP1			361
374#define ACLK_CRYPTO_S			362
375#define PCLK_CRYPTO_S			363
376#define CLK_CORE_CRYPTO_S		364
377#define CLK_PKA_CRYPTO_S		365
378
379#endif