rk3368-cru.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
  4 */
  5
  6#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
  7#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
  8
  9/* core clocks */
 10#define PLL_APLLB		1
 11#define PLL_APLLL		2
 12#define PLL_DPLL		3
 13#define PLL_CPLL		4
 14#define PLL_GPLL		5
 15#define PLL_NPLL		6
 16#define ARMCLKB			7
 17#define ARMCLKL			8
 18
 19/* sclk gates (special clocks) */
 20#define SCLK_GPU_CORE		64
 21#define SCLK_SPI0		65
 22#define SCLK_SPI1		66
 23#define SCLK_SPI2		67
 24#define SCLK_SDMMC		68
 25#define SCLK_SDIO0		69
 26#define SCLK_EMMC		71
 27#define SCLK_TSADC		72
 28#define SCLK_SARADC		73
 29#define SCLK_NANDC0		75
 30#define SCLK_UART0		77
 31#define SCLK_UART1		78
 32#define SCLK_UART2		79
 33#define SCLK_UART3		80
 34#define SCLK_UART4		81
 35#define SCLK_I2S_8CH		82
 36#define SCLK_SPDIF_8CH		83
 37#define SCLK_I2S_2CH		84
 38#define SCLK_TIMER00		85
 39#define SCLK_TIMER01		86
 40#define SCLK_TIMER02		87
 41#define SCLK_TIMER03		88
 42#define SCLK_TIMER04		89
 43#define SCLK_TIMER05		90
 44#define SCLK_OTGPHY0		93
 45#define SCLK_OTG_ADP		96
 46#define SCLK_HSICPHY480M	97
 47#define SCLK_HSICPHY12M		98
 48#define SCLK_MACREF		99
 49#define SCLK_VOP0_PWM		100
 50#define SCLK_MAC_RX		102
 51#define SCLK_MAC_TX		103
 52#define SCLK_EDP_24M		104
 53#define SCLK_EDP		105
 54#define SCLK_RGA		106
 55#define SCLK_ISP		107
 56#define SCLK_HDCP		108
 57#define SCLK_HDMI_HDCP		109
 58#define SCLK_HDMI_CEC		110
 59#define SCLK_HEVC_CABAC		111
 60#define SCLK_HEVC_CORE		112
 61#define SCLK_I2S_8CH_OUT	113
 62#define SCLK_SDMMC_DRV		114
 63#define SCLK_SDIO0_DRV		115
 64#define SCLK_EMMC_DRV		117
 65#define SCLK_SDMMC_SAMPLE	118
 66#define SCLK_SDIO0_SAMPLE	119
 67#define SCLK_EMMC_SAMPLE	121
 68#define SCLK_USBPHY480M		122
 69#define SCLK_PVTM_CORE		123
 70#define SCLK_PVTM_GPU		124
 71#define SCLK_PVTM_PMU		125
 72#define SCLK_SFC		126
 73#define SCLK_MAC		127
 74#define SCLK_MACREF_OUT		128
 75#define SCLK_MIPIDSI_24M	129
 76#define SCLK_TIMER10		133
 77#define SCLK_TIMER11		134
 78#define SCLK_TIMER12		135
 79#define SCLK_TIMER13		136
 80#define SCLK_TIMER14		137
 81#define SCLK_TIMER15		138
 82#define SCLK_VIP_OUT		139
 83
 84#define DCLK_VOP		190
 85#define MCLK_CRYPTO		191
 86
 87/* aclk gates */
 88#define ACLK_GPU_MEM		192
 89#define ACLK_GPU_CFG		193
 90#define ACLK_DMAC_BUS		194
 91#define ACLK_DMAC_PERI		195
 92#define ACLK_PERI_MMU		196
 93#define ACLK_GMAC		197
 94#define ACLK_VOP		198
 95#define ACLK_VOP_IEP		199
 96#define ACLK_RGA		200
 97#define ACLK_HDCP		201
 98#define ACLK_IEP		202
 99#define ACLK_VIO0_NOC		203
100#define ACLK_VIP		204
101#define ACLK_ISP		205
102#define ACLK_VIO1_NOC		206
103#define ACLK_VIDEO		208
104#define ACLK_BUS		209
105#define ACLK_PERI		210
106
107/* pclk gates */
108#define PCLK_GPIO0		320
109#define PCLK_GPIO1		321
110#define PCLK_GPIO2		322
111#define PCLK_GPIO3		323
112#define PCLK_PMUGRF		324
113#define PCLK_MAILBOX		325
114#define PCLK_GRF		329
115#define PCLK_SGRF		330
116#define PCLK_PMU		331
117#define PCLK_I2C0		332
118#define PCLK_I2C1		333
119#define PCLK_I2C2		334
120#define PCLK_I2C3		335
121#define PCLK_I2C4		336
122#define PCLK_I2C5		337
123#define PCLK_SPI0		338
124#define PCLK_SPI1		339
125#define PCLK_SPI2		340
126#define PCLK_UART0		341
127#define PCLK_UART1		342
128#define PCLK_UART2		343
129#define PCLK_UART3		344
130#define PCLK_UART4		345
131#define PCLK_TSADC		346
132#define PCLK_SARADC		347
133#define PCLK_SIM		348
134#define PCLK_GMAC		349
135#define PCLK_PWM0		350
136#define PCLK_PWM1		351
137#define PCLK_TIMER0		353
138#define PCLK_TIMER1		354
139#define PCLK_EDP_CTRL		355
140#define PCLK_MIPI_DSI0		356
141#define PCLK_MIPI_CSI		358
142#define PCLK_HDCP		359
143#define PCLK_HDMI_CTRL		360
144#define PCLK_VIO_H2P		361
145#define PCLK_BUS		362
146#define PCLK_PERI		363
147#define PCLK_DDRUPCTL		364
148#define PCLK_DDRPHY		365
149#define PCLK_ISP		366
150#define PCLK_VIP		367
151#define PCLK_WDT		368
152#define PCLK_EFUSE256		369
153#define PCLK_DPHYRX		370
154#define PCLK_DPHYTX0		371
155
156/* hclk gates */
157#define HCLK_SFC		448
158#define HCLK_OTG0		449
159#define HCLK_HOST0		450
160#define HCLK_HOST1		451
161#define HCLK_HSIC		452
162#define HCLK_NANDC0		453
163#define HCLK_TSP		455
164#define HCLK_SDMMC		456
165#define HCLK_SDIO0		457
166#define HCLK_EMMC		459
167#define HCLK_HSADC		460
168#define HCLK_CRYPTO		461
169#define HCLK_I2S_2CH		462
170#define HCLK_I2S_8CH		463
171#define HCLK_SPDIF		464
172#define HCLK_VOP		465
173#define HCLK_ROM		467
174#define HCLK_IEP		468
175#define HCLK_ISP		469
176#define HCLK_RGA		470
177#define HCLK_VIO_AHB_ARBI	471
178#define HCLK_VIO_NOC		472
179#define HCLK_VIP		473
180#define HCLK_VIO_H2P		474
181#define HCLK_VIO_HDCPMMU	475
182#define HCLK_VIDEO		476
183#define HCLK_BUS		477
184#define HCLK_PERI		478
185
186/* soft-reset indices */
187#define SRST_CORE_B0		0
188#define SRST_CORE_B1		1
189#define SRST_CORE_B2		2
190#define SRST_CORE_B3		3
191#define SRST_CORE_B0_PO		4
192#define SRST_CORE_B1_PO		5
193#define SRST_CORE_B2_PO		6
194#define SRST_CORE_B3_PO		7
195#define SRST_L2_B		8
196#define SRST_ADB_B		9
197#define SRST_PD_CORE_B_NIU	10
198#define SRST_PDBUS_STRSYS	11
199#define SRST_SOCDBG_B		14
200#define SRST_CORE_B_DBG		15
201
202#define SRST_DMAC1		18
203#define SRST_INTMEM		19
204#define SRST_ROM		20
205#define SRST_SPDIF8CH		21
206#define SRST_I2S8CH		23
207#define SRST_MAILBOX		24
208#define SRST_I2S2CH		25
209#define SRST_EFUSE_256		26
210#define SRST_MCU_SYS		28
211#define SRST_MCU_PO		29
212#define SRST_MCU_NOC		30
213#define SRST_EFUSE		31
214
215#define SRST_GPIO0		32
216#define SRST_GPIO1		33
217#define SRST_GPIO2		34
218#define SRST_GPIO3		35
219#define SRST_GPIO4		36
220#define SRST_PMUGRF		41
221#define SRST_I2C0		42
222#define SRST_I2C1		43
223#define SRST_I2C2		44
224#define SRST_I2C3		45
225#define SRST_I2C4		46
226#define SRST_I2C5		47
227
228#define SRST_DWPWM		48
229#define SRST_MMC_PERI		49
230#define SRST_PERIPH_MMU		50
231#define SRST_GRF		55
232#define SRST_PMU		56
233#define SRST_PERIPH_AXI		57
234#define SRST_PERIPH_AHB		58
235#define SRST_PERIPH_APB		59
236#define SRST_PERIPH_NIU		60
237#define SRST_PDPERI_AHB_ARBI	61
238#define SRST_EMEM		62
239#define SRST_USB_PERI		63
240
241#define SRST_DMAC2		64
242#define SRST_MAC		66
243#define SRST_GPS		67
244#define SRST_RKPWM		69
245#define SRST_USBHOST0		72
246#define SRST_HSIC		73
247#define SRST_HSIC_AUX		74
248#define SRST_HSIC_PHY		75
249#define SRST_HSADC		76
250#define SRST_NANDC0		77
251#define SRST_SFC		79
252
253#define SRST_SPI0		83
254#define SRST_SPI1		84
255#define SRST_SPI2		85
256#define SRST_SARADC		87
257#define SRST_PDALIVE_NIU	88
258#define SRST_PDPMU_INTMEM	89
259#define SRST_PDPMU_NIU		90
260#define SRST_SGRF		91
261
262#define SRST_VIO_ARBI		96
263#define SRST_RGA_NIU		97
264#define SRST_VIO0_NIU_AXI	98
265#define SRST_VIO_NIU_AHB	99
266#define SRST_LCDC0_AXI		100
267#define SRST_LCDC0_AHB		101
268#define SRST_LCDC0_DCLK		102
269#define SRST_VIP		104
270#define SRST_RGA_CORE		105
271#define SRST_IEP_AXI		106
272#define SRST_IEP_AHB		107
273#define SRST_RGA_AXI		108
274#define SRST_RGA_AHB		109
275#define SRST_ISP		110
276#define SRST_EDP_24M		111
277
278#define SRST_VIDEO_AXI		112
279#define SRST_VIDEO_AHB		113
280#define SRST_MIPIDPHYTX		114
281#define SRST_MIPIDSI0		115
282#define SRST_MIPIDPHYRX		116
283#define SRST_MIPICSI		117
284#define SRST_GPU		120
285#define SRST_HDMI		121
286#define SRST_EDP		122
287#define SRST_PMU_PVTM		123
288#define SRST_CORE_PVTM		124
289#define SRST_GPU_PVTM		125
290#define SRST_GPU_SYS		126
291#define SRST_GPU_MEM_NIU	127
292
293#define SRST_MMC0		128
294#define SRST_SDIO0		129
295#define SRST_EMMC		131
296#define SRST_USBOTG_AHB		132
297#define SRST_USBOTG_PHY		133
298#define SRST_USBOTG_CON		134
299#define SRST_USBHOST0_AHB	135
300#define SRST_USBHOST0_PHY	136
301#define SRST_USBHOST0_CON	137
302#define SRST_USBOTG_UTMI	138
303#define SRST_USBHOST1_UTMI	139
304#define SRST_USB_ADP		141
305
306#define SRST_CORESIGHT		144
307#define SRST_PD_CORE_AHB_NOC	145
308#define SRST_PD_CORE_APB_NOC	146
309#define SRST_GIC		148
310#define SRST_LCDC_PWM0		149
311#define SRST_RGA_H2P_BRG	153
312#define SRST_VIDEO		154
313#define SRST_GPU_CFG_NIU	157
314#define SRST_TSADC		159
315
316#define SRST_DDRPHY0		160
317#define SRST_DDRPHY0_APB	161
318#define SRST_DDRCTRL0		162
319#define SRST_DDRCTRL0_APB	163
320#define SRST_VIDEO_NIU		165
321#define SRST_VIDEO_NIU_AHB	167
322#define SRST_DDRMSCH0		170
323#define SRST_PDBUS_AHB		173
324#define SRST_CRYPTO		174
325
326#define SRST_UART0		179
327#define SRST_UART1		180
328#define SRST_UART2		181
329#define SRST_UART3		182
330#define SRST_UART4		183
331#define SRST_SIMC		186
332#define SRST_TSP		188
333#define SRST_TSP_CLKIN0		189
334
335#define SRST_CORE_L0		192
336#define SRST_CORE_L1		193
337#define SRST_CORE_L2		194
338#define SRST_CORE_L3		195
339#define SRST_CORE_L0_PO		195
340#define SRST_CORE_L1_PO		197
341#define SRST_CORE_L2_PO		198
342#define SRST_CORE_L3_PO		199
343#define SRST_L2_L		200
344#define SRST_ADB_L		201
345#define SRST_PD_CORE_L_NIU	202
346#define SRST_CCI_SYS		203
347#define SRST_CCI_DDR		204
348#define SRST_CCI		205
349#define SRST_SOCDBG_L		206
350#define SRST_CORE_L_DBG		207
351
352#define SRST_CORE_B0_NC		208
353#define SRST_CORE_B0_PO_NC	209
354#define SRST_L2_B_NC		210
355#define SRST_ADB_B_NC		211
356#define SRST_PD_CORE_B_NIU_NC	212
357#define SRST_PDBUS_STRSYS_NC	213
358#define SRST_CORE_L0_NC		214
359#define SRST_CORE_L0_PO_NC	215
360#define SRST_L2_L_NC		216
361#define SRST_ADB_L_NC		217
362#define SRST_PD_CORE_L_NIU_NC	218
363#define SRST_CCI_SYS_NC		219
364#define SRST_CCI_DDR_NC		220
365#define SRST_CCI_NC		221
366#define SRST_TRACE_NC		222
367
368#define SRST_TIMER00		224
369#define SRST_TIMER01		225
370#define SRST_TIMER02		226
371#define SRST_TIMER03		227
372#define SRST_TIMER04		228
373#define SRST_TIMER05		229
374#define SRST_TIMER10		230
375#define SRST_TIMER11		231
376#define SRST_TIMER12		232
377#define SRST_TIMER13		233
378#define SRST_TIMER14		234
379#define SRST_TIMER15		235
380#define SRST_TIMER0_APB		236
381#define SRST_TIMER1_APB		237
382
383#endif