renesas,r9a09g047-cpg.h

 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2 *
 3 * Copyright (C) 2024 Renesas Electronics Corp.
 4 */
 5#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
 6#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
 7
 8#include <dt-bindings/clock/renesas-cpg-mssr.h>
 9
10/* Core Clock list */
11#define R9A09G047_SYS_0_PCLK			0
12#define R9A09G047_CA55_0_CORECLK0		1
13#define R9A09G047_CA55_0_CORECLK1		2
14#define R9A09G047_CA55_0_CORECLK2		3
15#define R9A09G047_CA55_0_CORECLK3		4
16#define R9A09G047_CA55_0_PERIPHCLK		5
17#define R9A09G047_CM33_CLK0			6
18#define R9A09G047_CST_0_SWCLKTCK		7
19#define R9A09G047_IOTOP_0_SHCLK			8
20#define R9A09G047_SPI_CLK_SPI			9
21#define R9A09G047_GBETH_0_CLK_PTP_REF_I		10
22#define R9A09G047_GBETH_1_CLK_PTP_REF_I		11
23#define R9A09G047_USB3_0_REF_ALT_CLK_P		12
24#define R9A09G047_USB3_0_CLKCORE		13
25#define R9A09G047_USB2_0_CLK_CORE0		14
26#define R9A09G047_USB2_0_CLK_CORE1		15
27
28#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */