qcom,sm8750-gcc.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2/*
  3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
  7#define _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
  8
  9/* GCC clocks */
 10#define GCC_AGGRE_NOC_PCIE_AXI_CLK				0
 11#define GCC_AGGRE_UFS_PHY_AXI_CLK				1
 12#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			2
 13#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
 14#define GCC_BOOT_ROM_AHB_CLK					4
 15#define GCC_CAM_BIST_MCLK_AHB_CLK				5
 16#define GCC_CAMERA_AHB_CLK					6
 17#define GCC_CAMERA_HF_AXI_CLK					7
 18#define GCC_CAMERA_SF_AXI_CLK					8
 19#define GCC_CAMERA_XO_CLK					9
 20#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				10
 21#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				11
 22#define GCC_CNOC_PCIE_SF_AXI_CLK				12
 23#define GCC_DDRSS_GPU_AXI_CLK					13
 24#define GCC_DDRSS_PCIE_SF_QTB_CLK				14
 25#define GCC_DISP_AHB_CLK					15
 26#define GCC_DISP_HF_AXI_CLK					16
 27#define GCC_EVA_AHB_CLK						17
 28#define GCC_EVA_AXI0_CLK					18
 29#define GCC_EVA_AXI0C_CLK					19
 30#define GCC_EVA_XO_CLK						20
 31#define GCC_GP1_CLK						21
 32#define GCC_GP1_CLK_SRC						22
 33#define GCC_GP2_CLK						23
 34#define GCC_GP2_CLK_SRC						24
 35#define GCC_GP3_CLK						25
 36#define GCC_GP3_CLK_SRC						26
 37#define GCC_GPLL0						27
 38#define GCC_GPLL0_OUT_EVEN					28
 39#define GCC_GPLL1						29
 40#define GCC_GPLL4						30
 41#define GCC_GPLL7						31
 42#define GCC_GPLL9						32
 43#define GCC_GPU_CFG_AHB_CLK					33
 44#define GCC_GPU_GEMNOC_GFX_CLK					34
 45#define GCC_GPU_GPLL0_CLK_SRC					35
 46#define GCC_GPU_GPLL0_DIV_CLK_SRC				36
 47#define GCC_PCIE_0_AUX_CLK					37
 48#define GCC_PCIE_0_AUX_CLK_SRC					38
 49#define GCC_PCIE_0_CFG_AHB_CLK					39
 50#define GCC_PCIE_0_MSTR_AXI_CLK					40
 51#define GCC_PCIE_0_PHY_RCHNG_CLK				41
 52#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				42
 53#define GCC_PCIE_0_PIPE_CLK					43
 54#define GCC_PCIE_0_PIPE_CLK_SRC					44
 55#define GCC_PCIE_0_SLV_AXI_CLK					45
 56#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				46
 57#define GCC_PCIE_RSCC_CFG_AHB_CLK				47
 58#define GCC_PCIE_RSCC_XO_CLK					48
 59#define GCC_PDM2_CLK						49
 60#define GCC_PDM2_CLK_SRC					50
 61#define GCC_PDM_AHB_CLK						51
 62#define GCC_PDM_XO4_CLK						52
 63#define GCC_QMIP_CAMERA_CMD_AHB_CLK				53
 64#define GCC_QMIP_CAMERA_NRT_AHB_CLK				54
 65#define GCC_QMIP_CAMERA_RT_AHB_CLK				55
 66#define GCC_QMIP_GPU_AHB_CLK					56
 67#define GCC_QMIP_PCIE_AHB_CLK					57
 68#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				58
 69#define GCC_QMIP_VIDEO_CVP_AHB_CLK				59
 70#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				60
 71#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				61
 72#define GCC_QUPV3_I2C_CORE_CLK					62
 73#define GCC_QUPV3_I2C_S0_CLK					63
 74#define GCC_QUPV3_I2C_S0_CLK_SRC				64
 75#define GCC_QUPV3_I2C_S1_CLK					65
 76#define GCC_QUPV3_I2C_S1_CLK_SRC				66
 77#define GCC_QUPV3_I2C_S2_CLK					67
 78#define GCC_QUPV3_I2C_S2_CLK_SRC				68
 79#define GCC_QUPV3_I2C_S3_CLK					69
 80#define GCC_QUPV3_I2C_S3_CLK_SRC				70
 81#define GCC_QUPV3_I2C_S4_CLK					71
 82#define GCC_QUPV3_I2C_S4_CLK_SRC				72
 83#define GCC_QUPV3_I2C_S5_CLK					73
 84#define GCC_QUPV3_I2C_S5_CLK_SRC				74
 85#define GCC_QUPV3_I2C_S6_CLK					75
 86#define GCC_QUPV3_I2C_S6_CLK_SRC				76
 87#define GCC_QUPV3_I2C_S7_CLK					77
 88#define GCC_QUPV3_I2C_S7_CLK_SRC				78
 89#define GCC_QUPV3_I2C_S8_CLK					79
 90#define GCC_QUPV3_I2C_S8_CLK_SRC				80
 91#define GCC_QUPV3_I2C_S9_CLK					81
 92#define GCC_QUPV3_I2C_S9_CLK_SRC				82
 93#define GCC_QUPV3_I2C_S_AHB_CLK					83
 94#define GCC_QUPV3_WRAP1_CORE_2X_CLK				84
 95#define GCC_QUPV3_WRAP1_CORE_CLK				85
 96#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				86
 97#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			87
 98#define GCC_QUPV3_WRAP1_S0_CLK					88
 99#define GCC_QUPV3_WRAP1_S0_CLK_SRC				89
100#define GCC_QUPV3_WRAP1_S1_CLK					90
101#define GCC_QUPV3_WRAP1_S1_CLK_SRC				91
102#define GCC_QUPV3_WRAP1_S2_CLK					92
103#define GCC_QUPV3_WRAP1_S2_CLK_SRC				93
104#define GCC_QUPV3_WRAP1_S3_CLK					94
105#define GCC_QUPV3_WRAP1_S3_CLK_SRC				95
106#define GCC_QUPV3_WRAP1_S4_CLK					96
107#define GCC_QUPV3_WRAP1_S4_CLK_SRC				97
108#define GCC_QUPV3_WRAP1_S5_CLK					98
109#define GCC_QUPV3_WRAP1_S5_CLK_SRC				99
110#define GCC_QUPV3_WRAP1_S6_CLK					100
111#define GCC_QUPV3_WRAP1_S6_CLK_SRC				101
112#define GCC_QUPV3_WRAP1_S7_CLK					102
113#define GCC_QUPV3_WRAP1_S7_CLK_SRC				103
114#define GCC_QUPV3_WRAP2_CORE_2X_CLK				104
115#define GCC_QUPV3_WRAP2_CORE_CLK				105
116#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC			106
117#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK				107
118#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK				108
119#define GCC_QUPV3_WRAP2_S0_CLK					109
120#define GCC_QUPV3_WRAP2_S0_CLK_SRC				110
121#define GCC_QUPV3_WRAP2_S1_CLK					111
122#define GCC_QUPV3_WRAP2_S1_CLK_SRC				112
123#define GCC_QUPV3_WRAP2_S2_CLK					113
124#define GCC_QUPV3_WRAP2_S2_CLK_SRC				114
125#define GCC_QUPV3_WRAP2_S3_CLK					115
126#define GCC_QUPV3_WRAP2_S3_CLK_SRC				116
127#define GCC_QUPV3_WRAP2_S4_CLK					117
128#define GCC_QUPV3_WRAP2_S4_CLK_SRC				118
129#define GCC_QUPV3_WRAP2_S5_CLK					119
130#define GCC_QUPV3_WRAP2_S5_CLK_SRC				120
131#define GCC_QUPV3_WRAP2_S6_CLK					121
132#define GCC_QUPV3_WRAP2_S6_CLK_SRC				122
133#define GCC_QUPV3_WRAP2_S7_CLK					123
134#define GCC_QUPV3_WRAP2_S7_CLK_SRC				124
135#define GCC_QUPV3_WRAP_1_M_AHB_CLK				125
136#define GCC_QUPV3_WRAP_1_S_AHB_CLK				126
137#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK				127
138#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK				128
139#define GCC_QUPV3_WRAP_2_M_AHB_CLK				129
140#define GCC_QUPV3_WRAP_2_S_AHB_CLK				130
141#define GCC_SDCC2_AHB_CLK					131
142#define GCC_SDCC2_APPS_CLK					132
143#define GCC_SDCC2_APPS_CLK_SRC					133
144#define GCC_SDCC4_AHB_CLK					134
145#define GCC_SDCC4_APPS_CLK					135
146#define GCC_SDCC4_APPS_CLK_SRC					136
147#define GCC_UFS_PHY_AHB_CLK					137
148#define GCC_UFS_PHY_AXI_CLK					138
149#define GCC_UFS_PHY_AXI_CLK_SRC					139
150#define GCC_UFS_PHY_AXI_HW_CTL_CLK				140
151#define GCC_UFS_PHY_ICE_CORE_CLK				141
152#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				142
153#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				143
154#define GCC_UFS_PHY_PHY_AUX_CLK					144
155#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				145
156#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				146
157#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				147
158#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				148
159#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				149
160#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				150
161#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				151
162#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				152
163#define GCC_UFS_PHY_UNIPRO_CORE_CLK				153
164#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				154
165#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			155
166#define GCC_USB30_PRIM_MASTER_CLK				156
167#define GCC_USB30_PRIM_MASTER_CLK_SRC				157
168#define GCC_USB30_PRIM_MOCK_UTMI_CLK				158
169#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			159
170#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		160
171#define GCC_USB30_PRIM_SLEEP_CLK				161
172#define GCC_USB3_PRIM_PHY_AUX_CLK				162
173#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				163
174#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				164
175#define GCC_USB3_PRIM_PHY_PIPE_CLK				165
176#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				166
177#define GCC_VIDEO_AHB_CLK					167
178#define GCC_VIDEO_AXI0_CLK					168
179#define GCC_VIDEO_AXI1_CLK					169
180#define GCC_VIDEO_XO_CLK					170
181
182/* GCC power domains */
183#define GCC_PCIE_0_GDSC						0
184#define GCC_PCIE_0_PHY_GDSC					1
185#define GCC_UFS_MEM_PHY_GDSC					2
186#define GCC_UFS_PHY_GDSC					3
187#define GCC_USB30_PRIM_GDSC					4
188#define GCC_USB3_PHY_GDSC					5
189
190/* GCC resets */
191#define GCC_CAMERA_BCR						0
192#define GCC_DISPLAY_BCR						1
193#define GCC_EVA_BCR						2
194#define GCC_GPU_BCR						3
195#define GCC_PCIE_0_BCR						4
196#define GCC_PCIE_0_LINK_DOWN_BCR				5
197#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				6
198#define GCC_PCIE_0_PHY_BCR					7
199#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			8
200#define GCC_PCIE_PHY_BCR					9
201#define GCC_PCIE_PHY_CFG_AHB_BCR				10
202#define GCC_PCIE_PHY_COM_BCR					11
203#define GCC_PCIE_RSCC_BCR					12
204#define GCC_PDM_BCR						13
205#define GCC_QUPV3_WRAPPER_1_BCR					14
206#define GCC_QUPV3_WRAPPER_2_BCR					15
207#define GCC_QUPV3_WRAPPER_I2C_BCR				16
208#define GCC_QUSB2PHY_PRIM_BCR					17
209#define GCC_QUSB2PHY_SEC_BCR					18
210#define GCC_SDCC2_BCR						19
211#define GCC_SDCC4_BCR						20
212#define GCC_UFS_PHY_BCR						21
213#define GCC_USB30_PRIM_BCR					22
214#define GCC_USB3_DP_PHY_PRIM_BCR				23
215#define GCC_USB3_DP_PHY_SEC_BCR					24
216#define GCC_USB3_PHY_PRIM_BCR					25
217#define GCC_USB3_PHY_SEC_BCR					26
218#define GCC_USB3PHY_PHY_PRIM_BCR				27
219#define GCC_USB3PHY_PHY_SEC_BCR					28
220#define GCC_VIDEO_AXI0_CLK_ARES					29
221#define GCC_VIDEO_AXI1_CLK_ARES					30
222#define GCC_VIDEO_BCR						31
223#define GCC_EVA_AXI0_CLK_ARES					32
224#define GCC_EVA_AXI0C_CLK_ARES					33
225
226#endif