qcom,milos-camcc.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2/*
  3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
  5 */
  6
  7#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_MILOS_H
  8#define _DT_BINDINGS_CLK_QCOM_CAM_CC_MILOS_H
  9
 10/* CAM_CC clocks */
 11#define CAM_CC_PLL0						0
 12#define CAM_CC_PLL0_OUT_EVEN					1
 13#define CAM_CC_PLL0_OUT_ODD					2
 14#define CAM_CC_PLL1						3
 15#define CAM_CC_PLL1_OUT_EVEN					4
 16#define CAM_CC_PLL2						5
 17#define CAM_CC_PLL2_OUT_EVEN					6
 18#define CAM_CC_PLL3						7
 19#define CAM_CC_PLL3_OUT_EVEN					8
 20#define CAM_CC_PLL4						9
 21#define CAM_CC_PLL4_OUT_EVEN					10
 22#define CAM_CC_PLL5						11
 23#define CAM_CC_PLL5_OUT_EVEN					12
 24#define CAM_CC_PLL6						13
 25#define CAM_CC_PLL6_OUT_EVEN					14
 26#define CAM_CC_BPS_AHB_CLK					15
 27#define CAM_CC_BPS_AREG_CLK					16
 28#define CAM_CC_BPS_CLK						17
 29#define CAM_CC_BPS_CLK_SRC					18
 30#define CAM_CC_CAMNOC_ATB_CLK					19
 31#define CAM_CC_CAMNOC_AXI_CLK_SRC				20
 32#define CAM_CC_CAMNOC_AXI_HF_CLK				21
 33#define CAM_CC_CAMNOC_AXI_SF_CLK				22
 34#define CAM_CC_CAMNOC_NRT_AXI_CLK				23
 35#define CAM_CC_CAMNOC_RT_AXI_CLK				24
 36#define CAM_CC_CCI_0_CLK					25
 37#define CAM_CC_CCI_0_CLK_SRC					26
 38#define CAM_CC_CCI_1_CLK					27
 39#define CAM_CC_CCI_1_CLK_SRC					28
 40#define CAM_CC_CORE_AHB_CLK					29
 41#define CAM_CC_CPAS_AHB_CLK					30
 42#define CAM_CC_CPHY_RX_CLK_SRC					31
 43#define CAM_CC_CRE_AHB_CLK					32
 44#define CAM_CC_CRE_CLK						33
 45#define CAM_CC_CRE_CLK_SRC					34
 46#define CAM_CC_CSI0PHYTIMER_CLK					35
 47#define CAM_CC_CSI0PHYTIMER_CLK_SRC				36
 48#define CAM_CC_CSI1PHYTIMER_CLK					37
 49#define CAM_CC_CSI1PHYTIMER_CLK_SRC				38
 50#define CAM_CC_CSI2PHYTIMER_CLK					39
 51#define CAM_CC_CSI2PHYTIMER_CLK_SRC				40
 52#define CAM_CC_CSI3PHYTIMER_CLK					41
 53#define CAM_CC_CSI3PHYTIMER_CLK_SRC				42
 54#define CAM_CC_CSIPHY0_CLK					43
 55#define CAM_CC_CSIPHY1_CLK					44
 56#define CAM_CC_CSIPHY2_CLK					45
 57#define CAM_CC_CSIPHY3_CLK					46
 58#define CAM_CC_FAST_AHB_CLK_SRC					47
 59#define CAM_CC_GDSC_CLK						48
 60#define CAM_CC_ICP_ATB_CLK					49
 61#define CAM_CC_ICP_CLK						50
 62#define CAM_CC_ICP_CLK_SRC					51
 63#define CAM_CC_ICP_CTI_CLK					52
 64#define CAM_CC_ICP_TS_CLK					53
 65#define CAM_CC_MCLK0_CLK					54
 66#define CAM_CC_MCLK0_CLK_SRC					55
 67#define CAM_CC_MCLK1_CLK					56
 68#define CAM_CC_MCLK1_CLK_SRC					57
 69#define CAM_CC_MCLK2_CLK					58
 70#define CAM_CC_MCLK2_CLK_SRC					59
 71#define CAM_CC_MCLK3_CLK					60
 72#define CAM_CC_MCLK3_CLK_SRC					61
 73#define CAM_CC_MCLK4_CLK					62
 74#define CAM_CC_MCLK4_CLK_SRC					63
 75#define CAM_CC_OPE_0_AHB_CLK					64
 76#define CAM_CC_OPE_0_AREG_CLK					65
 77#define CAM_CC_OPE_0_CLK					66
 78#define CAM_CC_OPE_0_CLK_SRC					67
 79#define CAM_CC_SLEEP_CLK					68
 80#define CAM_CC_SLEEP_CLK_SRC					69
 81#define CAM_CC_SLOW_AHB_CLK_SRC					70
 82#define CAM_CC_SOC_AHB_CLK					71
 83#define CAM_CC_SYS_TMR_CLK					72
 84#define CAM_CC_TFE_0_AHB_CLK					73
 85#define CAM_CC_TFE_0_CLK					74
 86#define CAM_CC_TFE_0_CLK_SRC					75
 87#define CAM_CC_TFE_0_CPHY_RX_CLK				76
 88#define CAM_CC_TFE_0_CSID_CLK					77
 89#define CAM_CC_TFE_0_CSID_CLK_SRC				78
 90#define CAM_CC_TFE_1_AHB_CLK					79
 91#define CAM_CC_TFE_1_CLK					80
 92#define CAM_CC_TFE_1_CLK_SRC					81
 93#define CAM_CC_TFE_1_CPHY_RX_CLK				82
 94#define CAM_CC_TFE_1_CSID_CLK					83
 95#define CAM_CC_TFE_1_CSID_CLK_SRC				84
 96#define CAM_CC_TFE_2_AHB_CLK					85
 97#define CAM_CC_TFE_2_CLK					86
 98#define CAM_CC_TFE_2_CLK_SRC					87
 99#define CAM_CC_TFE_2_CPHY_RX_CLK				88
100#define CAM_CC_TFE_2_CSID_CLK					89
101#define CAM_CC_TFE_2_CSID_CLK_SRC				90
102#define CAM_CC_TOP_SHIFT_CLK					91
103#define CAM_CC_XO_CLK_SRC					92
104
105/* CAM_CC resets */
106#define CAM_CC_BPS_BCR						0
107#define CAM_CC_CAMNOC_BCR					1
108#define CAM_CC_CAMSS_TOP_BCR					2
109#define CAM_CC_CCI_0_BCR					3
110#define CAM_CC_CCI_1_BCR					4
111#define CAM_CC_CPAS_BCR						5
112#define CAM_CC_CRE_BCR						6
113#define CAM_CC_CSI0PHY_BCR					7
114#define CAM_CC_CSI1PHY_BCR					8
115#define CAM_CC_CSI2PHY_BCR					9
116#define CAM_CC_CSI3PHY_BCR					10
117#define CAM_CC_ICP_BCR						11
118#define CAM_CC_MCLK0_BCR					12
119#define CAM_CC_MCLK1_BCR					13
120#define CAM_CC_MCLK2_BCR					14
121#define CAM_CC_MCLK3_BCR					15
122#define CAM_CC_MCLK4_BCR					16
123#define CAM_CC_OPE_0_BCR					17
124#define CAM_CC_TFE_0_BCR					18
125#define CAM_CC_TFE_1_BCR					19
126#define CAM_CC_TFE_2_BCR					20
127
128/* CAM_CC power domains */
129#define CAM_CC_CAMSS_TOP_GDSC					0
130
131#endif