mediatek,mtmips-sysc.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2/*
  3 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  4 */
  5
  6#ifndef _DT_BINDINGS_CLK_MTMIPS_H
  7#define _DT_BINDINGS_CLK_MTMIPS_H
  8
  9/* Ralink RT-2880 clocks */
 10
 11#define RT2880_CLK_XTAL		0
 12#define RT2880_CLK_CPU		1
 13#define RT2880_CLK_BUS		2
 14#define RT2880_CLK_TIMER	3
 15#define RT2880_CLK_WATCHDOG	4
 16#define RT2880_CLK_UART		5
 17#define RT2880_CLK_I2C		6
 18#define RT2880_CLK_UARTLITE	7
 19#define RT2880_CLK_ETHERNET	8
 20#define RT2880_CLK_WMAC		9
 21
 22/* Ralink RT-305X clocks */
 23
 24#define RT305X_CLK_XTAL		0
 25#define RT305X_CLK_CPU		1
 26#define RT305X_CLK_BUS		2
 27#define RT305X_CLK_TIMER	3
 28#define RT305X_CLK_WATCHDOG	4
 29#define RT305X_CLK_UART		5
 30#define RT305X_CLK_I2C		6
 31#define RT305X_CLK_I2S		7
 32#define RT305X_CLK_SPI1		8
 33#define RT305X_CLK_SPI2		9
 34#define RT305X_CLK_UARTLITE	10
 35#define RT305X_CLK_ETHERNET	11
 36#define RT305X_CLK_WMAC		12
 37
 38/* Ralink RT-3352 clocks */
 39
 40#define RT3352_CLK_XTAL		0
 41#define RT3352_CLK_CPU		1
 42#define RT3352_CLK_PERIPH	2
 43#define RT3352_CLK_BUS		3
 44#define RT3352_CLK_TIMER	4
 45#define RT3352_CLK_WATCHDOG	5
 46#define RT3352_CLK_UART		6
 47#define RT3352_CLK_I2C		7
 48#define RT3352_CLK_I2S		8
 49#define RT3352_CLK_SPI1		9
 50#define RT3352_CLK_SPI2		10
 51#define RT3352_CLK_UARTLITE	11
 52#define RT3352_CLK_ETHERNET	12
 53#define RT3352_CLK_WMAC		13
 54
 55/* Ralink RT-3883 clocks */
 56
 57#define RT3883_CLK_XTAL		0
 58#define RT3883_CLK_CPU		1
 59#define RT3883_CLK_BUS		2
 60#define RT3883_CLK_PERIPH	3
 61#define RT3883_CLK_TIMER	4
 62#define RT3883_CLK_WATCHDOG	5
 63#define RT3883_CLK_UART		6
 64#define RT3883_CLK_I2C		7
 65#define RT3883_CLK_I2S		8
 66#define RT3883_CLK_SPI1		9
 67#define RT3883_CLK_SPI2		10
 68#define RT3883_CLK_UARTLITE	11
 69#define RT3883_CLK_ETHERNET	12
 70#define RT3883_CLK_WMAC		13
 71
 72/* Ralink RT-5350 clocks */
 73
 74#define RT5350_CLK_XTAL		0
 75#define RT5350_CLK_CPU		1
 76#define RT5350_CLK_BUS		2
 77#define RT5350_CLK_PERIPH	3
 78#define RT5350_CLK_TIMER	4
 79#define RT5350_CLK_WATCHDOG	5
 80#define RT5350_CLK_UART		6
 81#define RT5350_CLK_I2C		7
 82#define RT5350_CLK_I2S		8
 83#define RT5350_CLK_SPI1		9
 84#define RT5350_CLK_SPI2		10
 85#define RT5350_CLK_UARTLITE	11
 86#define RT5350_CLK_ETHERNET	12
 87#define RT5350_CLK_WMAC		13
 88
 89/* Ralink MT-7620 clocks */
 90
 91#define MT7620_CLK_XTAL		0
 92#define MT7620_CLK_PLL		1
 93#define MT7620_CLK_CPU		2
 94#define MT7620_CLK_PERIPH	3
 95#define MT7620_CLK_BUS		4
 96#define MT7620_CLK_BBPPLL	5
 97#define MT7620_CLK_SDHC		6
 98#define MT7620_CLK_TIMER	7
 99#define MT7620_CLK_WATCHDOG	8
100#define MT7620_CLK_UART		9
101#define MT7620_CLK_I2C		10
102#define MT7620_CLK_I2S		11
103#define MT7620_CLK_SPI1		12
104#define MT7620_CLK_SPI2		13
105#define MT7620_CLK_UARTLITE	14
106#define MT7620_CLK_MMC		15
107#define MT7620_CLK_WMAC		16
108
109/* Ralink MT-76X8 clocks */
110
111#define MT76X8_CLK_XTAL		0
112#define MT76X8_CLK_CPU		1
113#define MT76X8_CLK_BBPPLL	2
114#define MT76X8_CLK_PCMI2S	3
115#define MT76X8_CLK_PERIPH	4
116#define MT76X8_CLK_BUS		5
117#define MT76X8_CLK_SDHC		6
118#define MT76X8_CLK_TIMER	7
119#define MT76X8_CLK_WATCHDOG	8
120#define MT76X8_CLK_I2C		9
121#define MT76X8_CLK_I2S		10
122#define MT76X8_CLK_SPI1		11
123#define MT76X8_CLK_SPI2		12
124#define MT76X8_CLK_UART0	13
125#define MT76X8_CLK_UART1	14
126#define MT76X8_CLK_UART2	15
127#define MT76X8_CLK_MMC		16
128#define MT76X8_CLK_WMAC		17
129
130#endif /* _DT_BINDINGS_CLK_MTMIPS_H */