mediatek,mt8196-clock.h

  1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
  2/*
  3 * Copyright (c) 2025 MediaTek Inc.
  4 *                    Guangjie Song <guangjie.song@mediatek.com>
  5 * Copyright (c) 2025 Collabora Ltd.
  6 *                    Laura Nao <laura.nao@collabora.com>
  7 */
  8
  9#ifndef _DT_BINDINGS_CLK_MT8196_H
 10#define _DT_BINDINGS_CLK_MT8196_H
 11
 12/* CKSYS */
 13#define CLK_TOP_AXI					0
 14#define CLK_TOP_MEM_SUB					1
 15#define CLK_TOP_IO_NOC					2
 16#define CLK_TOP_P_AXI					3
 17#define CLK_TOP_UFS_PEXTP0_AXI				4
 18#define CLK_TOP_PEXTP1_USB_AXI				5
 19#define CLK_TOP_P_FMEM_SUB				6
 20#define CLK_TOP_PEXPT0_MEM_SUB				7
 21#define CLK_TOP_PEXTP1_USB_MEM_SUB			8
 22#define CLK_TOP_P_NOC					9
 23#define CLK_TOP_EMI_N					10
 24#define CLK_TOP_EMI_S					11
 25#define CLK_TOP_AP2CONN_HOST				12
 26#define CLK_TOP_ATB					13
 27#define CLK_TOP_CIRQ					14
 28#define CLK_TOP_PBUS_156M				15
 29#define CLK_TOP_EFUSE					16
 30#define CLK_TOP_MCL3GIC					17
 31#define CLK_TOP_MCINFRA					18
 32#define CLK_TOP_DSP					19
 33#define CLK_TOP_MFG_REF					20
 34#define CLK_TOP_MFG_EB					21
 35#define CLK_TOP_UART					22
 36#define CLK_TOP_SPI0_BCLK				23
 37#define CLK_TOP_SPI1_BCLK				24
 38#define CLK_TOP_SPI2_BCLK				25
 39#define CLK_TOP_SPI3_BCLK				26
 40#define CLK_TOP_SPI4_BCLK				27
 41#define CLK_TOP_SPI5_BCLK				28
 42#define CLK_TOP_SPI6_BCLK				29
 43#define CLK_TOP_SPI7_BCLK				30
 44#define CLK_TOP_MSDC30_1				31
 45#define CLK_TOP_MSDC30_2				32
 46#define CLK_TOP_DISP_PWM				33
 47#define CLK_TOP_USB_TOP_1P				34
 48#define CLK_TOP_USB_XHCI_1P				35
 49#define CLK_TOP_USB_FMCNT_P1				36
 50#define CLK_TOP_I2C_P					37
 51#define CLK_TOP_I2C_EAST				38
 52#define CLK_TOP_I2C_WEST				39
 53#define CLK_TOP_I2C_NORTH				40
 54#define CLK_TOP_AES_UFSFDE				41
 55#define CLK_TOP_UFS					42
 56#define CLK_TOP_AUD_1					43
 57#define CLK_TOP_AUD_2					44
 58#define CLK_TOP_ADSP					45
 59#define CLK_TOP_ADSP_UARTHUB_B				46
 60#define CLK_TOP_DPMAIF_MAIN				47
 61#define CLK_TOP_PWM					48
 62#define CLK_TOP_MCUPM					49
 63#define CLK_TOP_IPSEAST					50
 64#define CLK_TOP_TL					51
 65#define CLK_TOP_TL_P1					52
 66#define CLK_TOP_TL_P2					53
 67#define CLK_TOP_EMI_INTERFACE_546			54
 68#define CLK_TOP_SDF					55
 69#define CLK_TOP_UARTHUB_BCLK				56
 70#define CLK_TOP_DPSW_CMP_26M				57
 71#define CLK_TOP_SMAP					58
 72#define CLK_TOP_SSR_PKA					59
 73#define CLK_TOP_SSR_DMA					60
 74#define CLK_TOP_SSR_KDF					61
 75#define CLK_TOP_SSR_RNG					62
 76#define CLK_TOP_SPU0					63
 77#define CLK_TOP_SPU1					64
 78#define CLK_TOP_DXCC					65
 79#define CLK_TOP_APLL_I2SIN0				66
 80#define CLK_TOP_APLL_I2SIN1				67
 81#define CLK_TOP_APLL_I2SIN2				68
 82#define CLK_TOP_APLL_I2SIN3				69
 83#define CLK_TOP_APLL_I2SIN4				70
 84#define CLK_TOP_APLL_I2SIN6				71
 85#define CLK_TOP_APLL_I2SOUT0				72
 86#define CLK_TOP_APLL_I2SOUT1				73
 87#define CLK_TOP_APLL_I2SOUT2				74
 88#define CLK_TOP_APLL_I2SOUT3				75
 89#define CLK_TOP_APLL_I2SOUT4				76
 90#define CLK_TOP_APLL_I2SOUT6				77
 91#define CLK_TOP_APLL_FMI2S				78
 92#define CLK_TOP_APLL_TDMOUT				79
 93#define CLK_TOP_APLL12_DIV_TDMOUT_M			80
 94#define CLK_TOP_APLL12_DIV_TDMOUT_B			81
 95#define CLK_TOP_MAINPLL_D3				82
 96#define CLK_TOP_MAINPLL_D4				83
 97#define CLK_TOP_MAINPLL_D4_D2				84
 98#define CLK_TOP_MAINPLL_D4_D4				85
 99#define CLK_TOP_MAINPLL_D4_D8				86
100#define CLK_TOP_MAINPLL_D5				87
101#define CLK_TOP_MAINPLL_D5_D2				88
102#define CLK_TOP_MAINPLL_D5_D4				89
103#define CLK_TOP_MAINPLL_D5_D8				90
104#define CLK_TOP_MAINPLL_D6				91
105#define CLK_TOP_MAINPLL_D6_D2				92
106#define CLK_TOP_MAINPLL_D7				93
107#define CLK_TOP_MAINPLL_D7_D2				94
108#define CLK_TOP_MAINPLL_D7_D4				95
109#define CLK_TOP_MAINPLL_D7_D8				96
110#define CLK_TOP_MAINPLL_D9				97
111#define CLK_TOP_UNIVPLL_D4				98
112#define CLK_TOP_UNIVPLL_D4_D2				99
113#define CLK_TOP_UNIVPLL_D4_D4				100
114#define CLK_TOP_UNIVPLL_D4_D8				101
115#define CLK_TOP_UNIVPLL_D5				102
116#define CLK_TOP_UNIVPLL_D5_D2				103
117#define CLK_TOP_UNIVPLL_D5_D4				104
118#define CLK_TOP_UNIVPLL_D6				105
119#define CLK_TOP_UNIVPLL_D6_D2				106
120#define CLK_TOP_UNIVPLL_D6_D4				107
121#define CLK_TOP_UNIVPLL_D6_D8				108
122#define CLK_TOP_UNIVPLL_D6_D16				109
123#define CLK_TOP_UNIVPLL_192M				110
124#define CLK_TOP_UNIVPLL_192M_D4				111
125#define CLK_TOP_UNIVPLL_192M_D8				112
126#define CLK_TOP_UNIVPLL_192M_D16			113
127#define CLK_TOP_UNIVPLL_192M_D32			114
128#define CLK_TOP_UNIVPLL_192M_D10			115
129#define CLK_TOP_TVDPLL1_D2				116
130#define CLK_TOP_MSDCPLL_D2				117
131#define CLK_TOP_OSC_D2					118
132#define CLK_TOP_OSC_D3					119
133#define CLK_TOP_OSC_D4					120
134#define CLK_TOP_OSC_D5					121
135#define CLK_TOP_OSC_D7					122
136#define CLK_TOP_OSC_D8					123
137#define CLK_TOP_OSC_D10					124
138#define CLK_TOP_OSC_D14					125
139#define CLK_TOP_OSC_D20					126
140#define CLK_TOP_OSC_D32					127
141#define CLK_TOP_OSC_D40					128
142#define CLK_TOP_SFLASH					129
143
144/* APMIXEDSYS */
145#define CLK_APMIXED_MAINPLL				0
146#define CLK_APMIXED_UNIVPLL				1
147#define CLK_APMIXED_MSDCPLL				2
148#define CLK_APMIXED_ADSPPLL				3
149#define CLK_APMIXED_EMIPLL				4
150#define CLK_APMIXED_EMIPLL2				5
151#define CLK_APMIXED_NET1PLL				6
152#define CLK_APMIXED_SGMIIPLL				7
153
154/* CKSYS_GP2 */
155#define CLK_TOP2_SENINF0				0
156#define CLK_TOP2_SENINF1				1
157#define CLK_TOP2_SENINF2				2
158#define CLK_TOP2_SENINF3				3
159#define CLK_TOP2_SENINF4				4
160#define CLK_TOP2_SENINF5				5
161#define CLK_TOP2_IMG1					6
162#define CLK_TOP2_IPE					7
163#define CLK_TOP2_CAM					8
164#define CLK_TOP2_CAMTM					9
165#define CLK_TOP2_DPE					10
166#define CLK_TOP2_VDEC					11
167#define CLK_TOP2_CCUSYS					12
168#define CLK_TOP2_CCUTM					13
169#define CLK_TOP2_VENC					14
170#define CLK_TOP2_DP1					15
171#define CLK_TOP2_DP0					16
172#define CLK_TOP2_DISP					17
173#define CLK_TOP2_MDP					18
174#define CLK_TOP2_MMINFRA				19
175#define CLK_TOP2_MMINFRA_SNOC				20
176#define CLK_TOP2_MMUP					21
177#define CLK_TOP2_MMINFRA_AO				22
178#define CLK_TOP2_MAINPLL2_D2				23
179#define CLK_TOP2_MAINPLL2_D3				24
180#define CLK_TOP2_MAINPLL2_D4				25
181#define CLK_TOP2_MAINPLL2_D4_D2				26
182#define CLK_TOP2_MAINPLL2_D4_D4				27
183#define CLK_TOP2_MAINPLL2_D5				28
184#define CLK_TOP2_MAINPLL2_D5_D2				29
185#define CLK_TOP2_MAINPLL2_D6				30
186#define CLK_TOP2_MAINPLL2_D6_D2				31
187#define CLK_TOP2_MAINPLL2_D7				32
188#define CLK_TOP2_MAINPLL2_D7_D2				33
189#define CLK_TOP2_MAINPLL2_D9				34
190#define CLK_TOP2_UNIVPLL2_D3				35
191#define CLK_TOP2_UNIVPLL2_D4				36
192#define CLK_TOP2_UNIVPLL2_D4_D2				37
193#define CLK_TOP2_UNIVPLL2_D5				38
194#define CLK_TOP2_UNIVPLL2_D5_D2				39
195#define CLK_TOP2_UNIVPLL2_D6				40
196#define CLK_TOP2_UNIVPLL2_D6_D2				41
197#define CLK_TOP2_UNIVPLL2_D6_D4				42
198#define CLK_TOP2_UNIVPLL2_D7				43
199#define CLK_TOP2_IMGPLL_D2				44
200#define CLK_TOP2_IMGPLL_D4				45
201#define CLK_TOP2_IMGPLL_D5				46
202#define CLK_TOP2_IMGPLL_D5_D2				47
203#define CLK_TOP2_MMPLL2_D3				48
204#define CLK_TOP2_MMPLL2_D4				49
205#define CLK_TOP2_MMPLL2_D4_D2				50
206#define CLK_TOP2_MMPLL2_D5				51
207#define CLK_TOP2_MMPLL2_D5_D2				52
208#define CLK_TOP2_MMPLL2_D6				53
209#define CLK_TOP2_MMPLL2_D6_D2				54
210#define CLK_TOP2_MMPLL2_D7				55
211#define CLK_TOP2_MMPLL2_D9				56
212#define CLK_TOP2_TVDPLL1_D4				57
213#define CLK_TOP2_TVDPLL1_D8				58
214#define CLK_TOP2_TVDPLL1_D16				59
215#define CLK_TOP2_TVDPLL2_D2				60
216#define CLK_TOP2_TVDPLL2_D4				61
217#define CLK_TOP2_TVDPLL2_D8				62
218#define CLK_TOP2_TVDPLL2_D16				63
219#define CLK_TOP2_DVO					64
220#define CLK_TOP2_DVO_FAVT				65
221#define CLK_TOP2_TVDPLL3_D2				66
222#define CLK_TOP2_TVDPLL3_D4				67
223#define CLK_TOP2_TVDPLL3_D8				68
224#define CLK_TOP2_TVDPLL3_D16				69
225
226/* APMIXEDSYS_GP2 */
227#define CLK_APMIXED2_MAINPLL2				0
228#define CLK_APMIXED2_UNIVPLL2				1
229#define CLK_APMIXED2_MMPLL2				2
230#define CLK_APMIXED2_IMGPLL				3
231#define CLK_APMIXED2_TVDPLL1				4
232#define CLK_APMIXED2_TVDPLL2				5
233#define CLK_APMIXED2_TVDPLL3				6
234
235/* IMP_IIC_WRAP_E */
236#define CLK_IMPE_I2C5					0
237
238/* IMP_IIC_WRAP_W */
239#define CLK_IMPW_I2C0					0
240#define CLK_IMPW_I2C3					1
241#define CLK_IMPW_I2C6					2
242#define CLK_IMPW_I2C10					3
243
244/* IMP_IIC_WRAP_N */
245#define CLK_IMPN_I2C1					0
246#define CLK_IMPN_I2C2					1
247#define CLK_IMPN_I2C4					2
248#define CLK_IMPN_I2C7					3
249#define CLK_IMPN_I2C8					4
250#define CLK_IMPN_I2C9					5
251
252/* IMP_IIC_WRAP_C */
253#define CLK_IMPC_I2C11					0
254#define CLK_IMPC_I2C12					1
255#define CLK_IMPC_I2C13					2
256#define CLK_IMPC_I2C14					3
257
258/* PERICFG_AO */
259#define CLK_PERI_AO_UART0_BCLK				0
260#define CLK_PERI_AO_UART1_BCLK				1
261#define CLK_PERI_AO_UART2_BCLK				2
262#define CLK_PERI_AO_UART3_BCLK				3
263#define CLK_PERI_AO_UART4_BCLK				4
264#define CLK_PERI_AO_UART5_BCLK				5
265#define CLK_PERI_AO_PWM_X16W_HCLK			6
266#define CLK_PERI_AO_PWM_X16W_BCLK			7
267#define CLK_PERI_AO_PWM_PWM_BCLK0			8
268#define CLK_PERI_AO_PWM_PWM_BCLK1			9
269#define CLK_PERI_AO_PWM_PWM_BCLK2			10
270#define CLK_PERI_AO_PWM_PWM_BCLK3			11
271#define CLK_PERI_AO_SPI0_BCLK				12
272#define CLK_PERI_AO_SPI1_BCLK				13
273#define CLK_PERI_AO_SPI2_BCLK				14
274#define CLK_PERI_AO_SPI3_BCLK				15
275#define CLK_PERI_AO_SPI4_BCLK				16
276#define CLK_PERI_AO_SPI5_BCLK				17
277#define CLK_PERI_AO_SPI6_BCLK				18
278#define CLK_PERI_AO_SPI7_BCLK				19
279#define CLK_PERI_AO_AP_DMA_X32W_BCLK			20
280#define CLK_PERI_AO_MSDC1_MSDC_SRC			21
281#define CLK_PERI_AO_MSDC1_HCLK				22
282#define CLK_PERI_AO_MSDC1_AXI				23
283#define CLK_PERI_AO_MSDC1_HCLK_WRAP			24
284#define CLK_PERI_AO_MSDC2_MSDC_SRC			25
285#define CLK_PERI_AO_MSDC2_HCLK				26
286#define CLK_PERI_AO_MSDC2_AXI				27
287#define CLK_PERI_AO_MSDC2_HCLK_WRAP			28
288#define CLK_PERI_AO_FLASHIF_FLASH			29
289#define CLK_PERI_AO_FLASHIF_27M				30
290#define CLK_PERI_AO_FLASHIF_DRAM			31
291#define CLK_PERI_AO_FLASHIF_AXI				32
292#define CLK_PERI_AO_FLASHIF_BCLK			33
293
294/* UFSCFG_AO */
295#define CLK_UFSAO_UNIPRO_TX_SYM				0
296#define CLK_UFSAO_UNIPRO_RX_SYM0			1
297#define CLK_UFSAO_UNIPRO_RX_SYM1			2
298#define CLK_UFSAO_UNIPRO_SYS				3
299#define CLK_UFSAO_UNIPRO_SAP				4
300#define CLK_UFSAO_PHY_SAP				5
301#define CLK_UFSAO_UFSHCI_UFS				6
302#define CLK_UFSAO_UFSHCI_AES				7
303
304/* PEXTP0CFG_AO */
305#define CLK_PEXT_PEXTP_MAC_P0_TL			0
306#define CLK_PEXT_PEXTP_MAC_P0_REF			1
307#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS			2
308#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF			3
309#define CLK_PEXT_PEXTP_MAC_P0_AXI_250			4
310#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB			5
311#define CLK_PEXT_PEXTP_MAC_P0_PL_P			6
312#define CLK_PEXT_PEXTP_VLP_AO_P0_LP			7
313
314/* PEXTP1CFG_AO */
315#define CLK_PEXT1_PEXTP_MAC_P1_TL			0
316#define CLK_PEXT1_PEXTP_MAC_P1_REF			1
317#define CLK_PEXT1_PEXTP_MAC_P2_TL			2
318#define CLK_PEXT1_PEXTP_MAC_P2_REF			3
319#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS			4
320#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF		5
321#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS			6
322#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF		7
323#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250			8
324#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB			9
325#define CLK_PEXT1_PEXTP_MAC_P1_PL_P			10
326#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250			11
327#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB			12
328#define CLK_PEXT1_PEXTP_MAC_P2_PL_P			13
329#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP			14
330#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP			15
331
332/* VLP_CKSYS */
333#define CLK_VLP_APLL1					0
334#define CLK_VLP_APLL2					1
335#define CLK_VLP_SCP					2
336#define CLK_VLP_SCP_SPI					3
337#define CLK_VLP_SCP_IIC					4
338#define CLK_VLP_SCP_IIC_HS				5
339#define CLK_VLP_PWRAP_ULPOSC				6
340#define CLK_VLP_SPMI_M_TIA_32K				7
341#define CLK_VLP_APXGPT_26M_B				8
342#define CLK_VLP_DPSW					9
343#define CLK_VLP_DPSW_CENTRAL				10
344#define CLK_VLP_SPMI_M_MST				11
345#define CLK_VLP_DVFSRC					12
346#define CLK_VLP_PWM_VLP					13
347#define CLK_VLP_AXI_VLP					14
348#define CLK_VLP_SYSTIMER_26M				15
349#define CLK_VLP_SSPM					16
350#define CLK_VLP_SRCK					17
351#define CLK_VLP_CAMTG0					18
352#define CLK_VLP_CAMTG1					19
353#define CLK_VLP_CAMTG2					20
354#define CLK_VLP_CAMTG3					21
355#define CLK_VLP_CAMTG4					22
356#define CLK_VLP_CAMTG5					23
357#define CLK_VLP_CAMTG6					24
358#define CLK_VLP_CAMTG7					25
359#define CLK_VLP_SSPM_26M				26
360#define CLK_VLP_ULPOSC_SSPM				27
361#define CLK_VLP_VLP_PBUS_26M				28
362#define CLK_VLP_DEBUG_ERR_FLAG				29
363#define CLK_VLP_DPMSRDMA				30
364#define CLK_VLP_VLP_PBUS_156M				31
365#define CLK_VLP_SPM					32
366#define CLK_VLP_MMINFRA					33
367#define CLK_VLP_USB_TOP					34
368#define CLK_VLP_USB_XHCI				35
369#define CLK_VLP_NOC_VLP					36
370#define CLK_VLP_AUDIO_H					37
371#define CLK_VLP_AUD_ENGEN1				38
372#define CLK_VLP_AUD_ENGEN2				39
373#define CLK_VLP_AUD_INTBUS				40
374#define CLK_VLP_SPVLP_26M				41
375#define CLK_VLP_SPU0_VLP				42
376#define CLK_VLP_SPU1_VLP				43
377#define CLK_VLP_CLK26M                                  44
378#define CLK_VLP_APLL1_D4				45
379#define CLK_VLP_APLL1_D8				46
380#define CLK_VLP_APLL2_D4				47
381#define CLK_VLP_APLL2_D8				48
382
383/* DISPSYS_CONFIG */
384#define CLK_MM_CONFIG					0
385#define CLK_MM_DISP_MUTEX0				1
386#define CLK_MM_DISP_AAL0				2
387#define CLK_MM_DISP_AAL1				3
388#define CLK_MM_DISP_C3D0				4
389#define CLK_MM_DISP_C3D1				5
390#define CLK_MM_DISP_C3D2				6
391#define CLK_MM_DISP_C3D3				7
392#define CLK_MM_DISP_CCORR0				8
393#define CLK_MM_DISP_CCORR1				9
394#define CLK_MM_DISP_CCORR2				10
395#define CLK_MM_DISP_CCORR3				11
396#define CLK_MM_DISP_CHIST0				12
397#define CLK_MM_DISP_CHIST1				13
398#define CLK_MM_DISP_COLOR0				14
399#define CLK_MM_DISP_COLOR1				15
400#define CLK_MM_DISP_DITHER0				16
401#define CLK_MM_DISP_DITHER1				17
402#define CLK_MM_DISP_DLI_ASYNC0				18
403#define CLK_MM_DISP_DLI_ASYNC1				19
404#define CLK_MM_DISP_DLI_ASYNC2				20
405#define CLK_MM_DISP_DLI_ASYNC3				21
406#define CLK_MM_DISP_DLI_ASYNC4				22
407#define CLK_MM_DISP_DLI_ASYNC5				23
408#define CLK_MM_DISP_DLI_ASYNC6				24
409#define CLK_MM_DISP_DLI_ASYNC7				25
410#define CLK_MM_DISP_DLI_ASYNC8				26
411#define CLK_MM_DISP_DLI_ASYNC9				27
412#define CLK_MM_DISP_DLI_ASYNC10				28
413#define CLK_MM_DISP_DLI_ASYNC11				29
414#define CLK_MM_DISP_DLI_ASYNC12				30
415#define CLK_MM_DISP_DLI_ASYNC13				31
416#define CLK_MM_DISP_DLI_ASYNC14				32
417#define CLK_MM_DISP_DLI_ASYNC15				33
418#define CLK_MM_DISP_DLO_ASYNC0				34
419#define CLK_MM_DISP_DLO_ASYNC1				35
420#define CLK_MM_DISP_DLO_ASYNC2				36
421#define CLK_MM_DISP_DLO_ASYNC3				37
422#define CLK_MM_DISP_DLO_ASYNC4				38
423#define CLK_MM_DISP_DLO_ASYNC5				39
424#define CLK_MM_DISP_DLO_ASYNC6				40
425#define CLK_MM_DISP_DLO_ASYNC7				41
426#define CLK_MM_DISP_DLO_ASYNC8				42
427#define CLK_MM_DISP_GAMMA0				43
428#define CLK_MM_DISP_GAMMA1				44
429#define CLK_MM_MDP_AAL0					45
430#define CLK_MM_MDP_AAL1					46
431#define CLK_MM_MDP_RDMA0				47
432#define CLK_MM_DISP_POSTMASK0				48
433#define CLK_MM_DISP_POSTMASK1				49
434#define CLK_MM_MDP_RSZ0					50
435#define CLK_MM_MDP_RSZ1					51
436#define CLK_MM_DISP_SPR0				52
437#define CLK_MM_DISP_TDSHP0				53
438#define CLK_MM_DISP_TDSHP1				54
439#define CLK_MM_DISP_WDMA0				55
440#define CLK_MM_DISP_Y2R0				56
441#define CLK_MM_SMI_SUB_COMM0				57
442#define CLK_MM_DISP_FAKE_ENG0				58
443
444/* DISPSYS1_CONFIG */
445#define CLK_MM1_DISPSYS1_CONFIG				0
446#define CLK_MM1_DISPSYS1_S_CONFIG			1
447#define CLK_MM1_DISP_MUTEX0				2
448#define CLK_MM1_DISP_DLI_ASYNC20			3
449#define CLK_MM1_DISP_DLI_ASYNC21			4
450#define CLK_MM1_DISP_DLI_ASYNC22			5
451#define CLK_MM1_DISP_DLI_ASYNC23			6
452#define CLK_MM1_DISP_DLI_ASYNC24			7
453#define CLK_MM1_DISP_DLI_ASYNC25			8
454#define CLK_MM1_DISP_DLI_ASYNC26			9
455#define CLK_MM1_DISP_DLI_ASYNC27			10
456#define CLK_MM1_DISP_DLI_ASYNC28			11
457#define CLK_MM1_DISP_RELAY0				12
458#define CLK_MM1_DISP_RELAY1				13
459#define CLK_MM1_DISP_RELAY2				14
460#define CLK_MM1_DISP_RELAY3				15
461#define CLK_MM1_DISP_DP_INTF0				16
462#define CLK_MM1_DISP_DP_INTF1				17
463#define CLK_MM1_DISP_DSC_WRAP0				18
464#define CLK_MM1_DISP_DSC_WRAP1				19
465#define CLK_MM1_DISP_DSC_WRAP2				20
466#define CLK_MM1_DISP_DSC_WRAP3				21
467#define CLK_MM1_DISP_DSI0				22
468#define CLK_MM1_DISP_DSI1				23
469#define CLK_MM1_DISP_DSI2				24
470#define CLK_MM1_DISP_DVO0				25
471#define CLK_MM1_DISP_GDMA0				26
472#define CLK_MM1_DISP_MERGE0				27
473#define CLK_MM1_DISP_MERGE1				28
474#define CLK_MM1_DISP_MERGE2				29
475#define CLK_MM1_DISP_ODDMR0				30
476#define CLK_MM1_DISP_POSTALIGN0				31
477#define CLK_MM1_DISP_DITHER2				32
478#define CLK_MM1_DISP_R2Y0				33
479#define CLK_MM1_DISP_SPLITTER0				34
480#define CLK_MM1_DISP_SPLITTER1				35
481#define CLK_MM1_DISP_SPLITTER2				36
482#define CLK_MM1_DISP_SPLITTER3				37
483#define CLK_MM1_DISP_VDCM0				38
484#define CLK_MM1_DISP_WDMA1				39
485#define CLK_MM1_DISP_WDMA2				40
486#define CLK_MM1_DISP_WDMA3				41
487#define CLK_MM1_DISP_WDMA4				42
488#define CLK_MM1_MDP_RDMA1				43
489#define CLK_MM1_SMI_LARB0				44
490#define CLK_MM1_MOD1					45
491#define CLK_MM1_MOD2					46
492#define CLK_MM1_MOD3					47
493#define CLK_MM1_MOD4					48
494#define CLK_MM1_MOD5					49
495#define CLK_MM1_MOD6					50
496#define CLK_MM1_CG0					51
497#define CLK_MM1_CG1					52
498#define CLK_MM1_CG2					53
499#define CLK_MM1_CG3					54
500#define CLK_MM1_CG4					55
501#define CLK_MM1_CG5					56
502#define CLK_MM1_CG6					57
503#define CLK_MM1_CG7					58
504#define CLK_MM1_F26M					59
505
506/* OVLSYS_CONFIG */
507#define CLK_OVLSYS_CONFIG				0
508#define CLK_OVL_FAKE_ENG0				1
509#define CLK_OVL_FAKE_ENG1				2
510#define CLK_OVL_MUTEX0					3
511#define CLK_OVL_EXDMA0					4
512#define CLK_OVL_EXDMA1					5
513#define CLK_OVL_EXDMA2					6
514#define CLK_OVL_EXDMA3					7
515#define CLK_OVL_EXDMA4					8
516#define CLK_OVL_EXDMA5					9
517#define CLK_OVL_EXDMA6					10
518#define CLK_OVL_EXDMA7					11
519#define CLK_OVL_EXDMA8					12
520#define CLK_OVL_EXDMA9					13
521#define CLK_OVL_BLENDER0				14
522#define CLK_OVL_BLENDER1				15
523#define CLK_OVL_BLENDER2				16
524#define CLK_OVL_BLENDER3				17
525#define CLK_OVL_BLENDER4				18
526#define CLK_OVL_BLENDER5				19
527#define CLK_OVL_BLENDER6				20
528#define CLK_OVL_BLENDER7				21
529#define CLK_OVL_BLENDER8				22
530#define CLK_OVL_BLENDER9				23
531#define CLK_OVL_OUTPROC0				24
532#define CLK_OVL_OUTPROC1				25
533#define CLK_OVL_OUTPROC2				26
534#define CLK_OVL_OUTPROC3				27
535#define CLK_OVL_OUTPROC4				28
536#define CLK_OVL_OUTPROC5				29
537#define CLK_OVL_MDP_RSZ0				30
538#define CLK_OVL_MDP_RSZ1				31
539#define CLK_OVL_DISP_WDMA0				32
540#define CLK_OVL_DISP_WDMA1				33
541#define CLK_OVL_UFBC_WDMA0				34
542#define CLK_OVL_MDP_RDMA0				35
543#define CLK_OVL_MDP_RDMA1				36
544#define CLK_OVL_BWM0					37
545#define CLK_OVL_DLI0					38
546#define CLK_OVL_DLI1					39
547#define CLK_OVL_DLI2					40
548#define CLK_OVL_DLI3					41
549#define CLK_OVL_DLI4					42
550#define CLK_OVL_DLI5					43
551#define CLK_OVL_DLI6					44
552#define CLK_OVL_DLI7					45
553#define CLK_OVL_DLI8					46
554#define CLK_OVL_DLO0					47
555#define CLK_OVL_DLO1					48
556#define CLK_OVL_DLO2					49
557#define CLK_OVL_DLO3					50
558#define CLK_OVL_DLO4					51
559#define CLK_OVL_DLO5					52
560#define CLK_OVL_DLO6					53
561#define CLK_OVL_DLO7					54
562#define CLK_OVL_DLO8					55
563#define CLK_OVL_DLO9					56
564#define CLK_OVL_DLO10					57
565#define CLK_OVL_DLO11					58
566#define CLK_OVL_DLO12					59
567#define CLK_OVLSYS_RELAY0				60
568#define CLK_OVL_INLINEROT0				61
569#define CLK_OVL_SMI					62
570#define CLK_OVL_SMI_SMI					63
571
572
573/* OVLSYS1_CONFIG */
574#define CLK_OVL1_OVLSYS_CONFIG				0
575#define CLK_OVL1_OVL_FAKE_ENG0				1
576#define CLK_OVL1_OVL_FAKE_ENG1				2
577#define CLK_OVL1_OVL_MUTEX0				3
578#define CLK_OVL1_OVL_EXDMA0				4
579#define CLK_OVL1_OVL_EXDMA1				5
580#define CLK_OVL1_OVL_EXDMA2				6
581#define CLK_OVL1_OVL_EXDMA3				7
582#define CLK_OVL1_OVL_EXDMA4				8
583#define CLK_OVL1_OVL_EXDMA5				9
584#define CLK_OVL1_OVL_EXDMA6				10
585#define CLK_OVL1_OVL_EXDMA7				11
586#define CLK_OVL1_OVL_EXDMA8				12
587#define CLK_OVL1_OVL_EXDMA9				13
588#define CLK_OVL1_OVL_BLENDER0				14
589#define CLK_OVL1_OVL_BLENDER1				15
590#define CLK_OVL1_OVL_BLENDER2				16
591#define CLK_OVL1_OVL_BLENDER3				17
592#define CLK_OVL1_OVL_BLENDER4				18
593#define CLK_OVL1_OVL_BLENDER5				19
594#define CLK_OVL1_OVL_BLENDER6				20
595#define CLK_OVL1_OVL_BLENDER7				21
596#define CLK_OVL1_OVL_BLENDER8				22
597#define CLK_OVL1_OVL_BLENDER9				23
598#define CLK_OVL1_OVL_OUTPROC0				24
599#define CLK_OVL1_OVL_OUTPROC1				25
600#define CLK_OVL1_OVL_OUTPROC2				26
601#define CLK_OVL1_OVL_OUTPROC3				27
602#define CLK_OVL1_OVL_OUTPROC4				28
603#define CLK_OVL1_OVL_OUTPROC5				29
604#define CLK_OVL1_OVL_MDP_RSZ0				30
605#define CLK_OVL1_OVL_MDP_RSZ1				31
606#define CLK_OVL1_OVL_DISP_WDMA0				32
607#define CLK_OVL1_OVL_DISP_WDMA1				33
608#define CLK_OVL1_OVL_UFBC_WDMA0				34
609#define CLK_OVL1_OVL_MDP_RDMA0				35
610#define CLK_OVL1_OVL_MDP_RDMA1				36
611#define CLK_OVL1_OVL_BWM0				37
612#define CLK_OVL1_DLI0					38
613#define CLK_OVL1_DLI1					39
614#define CLK_OVL1_DLI2					40
615#define CLK_OVL1_DLI3					41
616#define CLK_OVL1_DLI4					42
617#define CLK_OVL1_DLI5					43
618#define CLK_OVL1_DLI6					44
619#define CLK_OVL1_DLI7					45
620#define CLK_OVL1_DLI8					46
621#define CLK_OVL1_DLO0					47
622#define CLK_OVL1_DLO1					48
623#define CLK_OVL1_DLO2					49
624#define CLK_OVL1_DLO3					50
625#define CLK_OVL1_DLO4					51
626#define CLK_OVL1_DLO5					52
627#define CLK_OVL1_DLO6					53
628#define CLK_OVL1_DLO7					54
629#define CLK_OVL1_DLO8					55
630#define CLK_OVL1_DLO9					56
631#define CLK_OVL1_DLO10					57
632#define CLK_OVL1_DLO11					58
633#define CLK_OVL1_DLO12					59
634#define CLK_OVL1_OVLSYS_RELAY0				60
635#define CLK_OVL1_OVL_INLINEROT0				61
636#define CLK_OVL1_SMI					62
637
638
639/* VDEC_SOC_GCON_BASE */
640#define CLK_VDE1_LARB1_CKEN				0
641#define CLK_VDE1_LAT_CKEN				1
642#define CLK_VDE1_LAT_ACTIVE				2
643#define CLK_VDE1_LAT_CKEN_ENG				3
644#define CLK_VDE1_VDEC_CKEN				4
645#define CLK_VDE1_VDEC_ACTIVE				5
646#define CLK_VDE1_VDEC_CKEN_ENG				6
647#define CLK_VDE1_VDEC_SOC_APTV_EN			7
648#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN			8
649#define CLK_VDE1_VDEC_SOC_IPS_EN			9
650
651/* VDEC_GCON_BASE */
652#define CLK_VDE2_LARB1_CKEN				0
653#define CLK_VDE2_LAT_CKEN				1
654#define CLK_VDE2_LAT_ACTIVE				2
655#define CLK_VDE2_LAT_CKEN_ENG				3
656#define CLK_VDE2_VDEC_CKEN				4
657#define CLK_VDE2_VDEC_ACTIVE				5
658#define CLK_VDE2_VDEC_CKEN_ENG				6
659
660/* VENC_GCON */
661#define CLK_VEN1_CKE0_LARB				0
662#define CLK_VEN1_CKE1_VENC				1
663#define CLK_VEN1_CKE2_JPGENC				2
664#define CLK_VEN1_CKE3_JPGDEC				3
665#define CLK_VEN1_CKE4_JPGDEC_C1				4
666#define CLK_VEN1_CKE5_GALS				5
667#define CLK_VEN1_CKE29_VENC_ADAB_CTRL			6
668#define CLK_VEN1_CKE29_VENC_XPC_CTRL			7
669#define CLK_VEN1_CKE6_GALS_SRAM				8
670#define CLK_VEN1_RES_FLAT				9
671
672/* VENC_GCON_CORE1 */
673#define CLK_VEN2_CKE0_LARB				0
674#define CLK_VEN2_CKE1_VENC				1
675#define CLK_VEN2_CKE2_JPGENC				2
676#define CLK_VEN2_CKE3_JPGDEC				3
677#define CLK_VEN2_CKE5_GALS				4
678#define CLK_VEN2_CKE29_VENC_XPC_CTRL			5
679#define CLK_VEN2_CKE6_GALS_SRAM				6
680#define CLK_VEN2_RES_FLAT				7
681
682/* VENC_GCON_CORE2 */
683#define CLK_VEN_C2_CKE0_LARB				0
684#define CLK_VEN_C2_CKE1_VENC				1
685#define CLK_VEN_C2_CKE5_GALS				2
686#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL			3
687#define CLK_VEN_C2_CKE6_GALS_SRAM			4
688#define CLK_VEN_C2_RES_FLAT				5
689
690/* MDPSYS_CONFIG */
691#define CLK_MDP_MDP_MUTEX0				0
692#define CLK_MDP_SMI0					1
693#define CLK_MDP_SMI0_SMI				2
694#define CLK_MDP_APB_BUS					3
695#define CLK_MDP_MDP_RDMA0				4
696#define CLK_MDP_MDP_RDMA1				5
697#define CLK_MDP_MDP_RDMA2				6
698#define CLK_MDP_MDP_BIRSZ0				7
699#define CLK_MDP_MDP_HDR0				8
700#define CLK_MDP_MDP_AAL0				9
701#define CLK_MDP_MDP_RSZ0				10
702#define CLK_MDP_MDP_RSZ2				11
703#define CLK_MDP_MDP_TDSHP0				12
704#define CLK_MDP_MDP_COLOR0				13
705#define CLK_MDP_MDP_WROT0				14
706#define CLK_MDP_MDP_WROT1				15
707#define CLK_MDP_MDP_WROT2				16
708#define CLK_MDP_MDP_FAKE_ENG0				17
709#define CLK_MDP_APB_DB					18
710#define CLK_MDP_MDP_DLI_ASYNC0				19
711#define CLK_MDP_MDP_DLI_ASYNC1				20
712#define CLK_MDP_MDP_DLO_ASYNC0				21
713#define CLK_MDP_MDP_DLO_ASYNC1				22
714#define CLK_MDP_MDP_DLI_ASYNC2				23
715#define CLK_MDP_MDP_DLO_ASYNC2				24
716#define CLK_MDP_MDP_DLO_ASYNC3				25
717#define CLK_MDP_IMG_DL_ASYNC0				26
718#define CLK_MDP_MDP_RROT0				27
719#define CLK_MDP_MDP_MERGE0				28
720#define CLK_MDP_MDP_C3D0				29
721#define CLK_MDP_MDP_FG0					30
722#define CLK_MDP_MDP_CLA2				31
723#define CLK_MDP_MDP_DLO_ASYNC4				32
724#define CLK_MDP_VPP_RSZ0				33
725#define CLK_MDP_VPP_RSZ1				34
726#define CLK_MDP_MDP_DLO_ASYNC5				35
727#define CLK_MDP_IMG0					36
728#define CLK_MDP_F26M					37
729#define CLK_MDP_IMG_DL_RELAY0				38
730#define CLK_MDP_IMG_DL_RELAY1				39
731
732/* MDPSYS1_CONFIG */
733#define CLK_MDP1_MDP_MUTEX0				0
734#define CLK_MDP1_SMI0					1
735#define CLK_MDP1_SMI0_SMI				2
736#define CLK_MDP1_APB_BUS				3
737#define CLK_MDP1_MDP_RDMA0				4
738#define CLK_MDP1_MDP_RDMA1				5
739#define CLK_MDP1_MDP_RDMA2				6
740#define CLK_MDP1_MDP_BIRSZ0				7
741#define CLK_MDP1_MDP_HDR0				8
742#define CLK_MDP1_MDP_AAL0				9
743#define CLK_MDP1_MDP_RSZ0				10
744#define CLK_MDP1_MDP_RSZ2				11
745#define CLK_MDP1_MDP_TDSHP0				12
746#define CLK_MDP1_MDP_COLOR0				13
747#define CLK_MDP1_MDP_WROT0				14
748#define CLK_MDP1_MDP_WROT1				15
749#define CLK_MDP1_MDP_WROT2				16
750#define CLK_MDP1_MDP_FAKE_ENG0				17
751#define CLK_MDP1_APB_DB					18
752#define CLK_MDP1_MDP_DLI_ASYNC0				19
753#define CLK_MDP1_MDP_DLI_ASYNC1				20
754#define CLK_MDP1_MDP_DLO_ASYNC0				21
755#define CLK_MDP1_MDP_DLO_ASYNC1				22
756#define CLK_MDP1_MDP_DLI_ASYNC2				23
757#define CLK_MDP1_MDP_DLO_ASYNC2				24
758#define CLK_MDP1_MDP_DLO_ASYNC3				25
759#define CLK_MDP1_IMG_DL_ASYNC0				26
760#define CLK_MDP1_MDP_RROT0				27
761#define CLK_MDP1_MDP_MERGE0				28
762#define CLK_MDP1_MDP_C3D0				29
763#define CLK_MDP1_MDP_FG0				30
764#define CLK_MDP1_MDP_CLA2				31
765#define CLK_MDP1_MDP_DLO_ASYNC4				32
766#define CLK_MDP1_VPP_RSZ0				33
767#define CLK_MDP1_VPP_RSZ1				34
768#define CLK_MDP1_MDP_DLO_ASYNC5				35
769#define CLK_MDP1_IMG0					36
770#define CLK_MDP1_F26M					37
771#define CLK_MDP1_IMG_DL_RELAY0				38
772#define CLK_MDP1_IMG_DL_RELAY1				39
773
774/* DISP_VDISP_AO_CONFIG */
775#define CLK_MM_V_DISP_VDISP_AO_CONFIG			0
776#define CLK_MM_V_DISP_DPC				1
777#define CLK_MM_V_SMI_SUB_SOMM0				2
778
779/* MFGPLL_PLL_CTRL */
780#define CLK_MFG_AO_MFGPLL				0
781
782/* MFGPLL_SC0_PLL_CTRL */
783#define CLK_MFGSC0_AO_MFGPLL_SC0			0
784
785/* MFGPLL_SC1_PLL_CTRL */
786#define CLK_MFGSC1_AO_MFGPLL_SC1			0
787
788/* CCIPLL_PLL_CTRL */
789#define CLK_CCIPLL					0
790
791/* ARMPLL_LL_PLL_CTRL */
792#define CLK_CPLL_ARMPLL_LL				0
793
794/* ARMPLL_BL_PLL_CTRL */
795#define CLK_CPBL_ARMPLL_BL				0
796
797/* ARMPLL_B_PLL_CTRL */
798#define CLK_CPB_ARMPLL_B				0
799
800/* PTPPLL_PLL_CTRL */
801#define CLK_PTPPLL					0
802
803#endif /* _DT_BINDINGS_CLK_MT8196_H */