drm_dp_helper.h

   1/*
   2 * Copyright © 2008 Keith Packard
   3 *
   4 * Permission to use, copy, modify, distribute, and sell this software and its
   5 * documentation for any purpose is hereby granted without fee, provided that
   6 * the above copyright notice appear in all copies and that both that copyright
   7 * notice and this permission notice appear in supporting documentation, and
   8 * that the name of the copyright holders not be used in advertising or
   9 * publicity pertaining to distribution of the software without specific,
  10 * written prior permission.  The copyright holders make no representations
  11 * about the suitability of this software for any purpose.  It is provided "as
  12 * is" without express or implied warranty.
  13 *
  14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20 * OF THIS SOFTWARE.
  21 */
  22
  23#ifndef _DRM_DP_HELPER_H_
  24#define _DRM_DP_HELPER_H_
  25
  26#include <linux/delay.h>
  27#include <linux/i2c.h>
  28
  29#include <drm/display/drm_dp.h>
  30#include <drm/drm_connector.h>
  31
  32struct drm_device;
  33struct drm_dp_aux;
  34struct drm_panel;
  35
  36bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  37			  int lane_count);
  38bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  39			      int lane_count);
  40bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]);
  41u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
  42				     int lane);
  43u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
  44					  int lane);
  45u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
  46				   int lane);
  47
  48int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  49				     enum drm_dp_phy dp_phy, bool uhbr);
  50int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  51				 enum drm_dp_phy dp_phy, bool uhbr);
  52
  53void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
  54					    const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
  55void drm_dp_lttpr_link_train_clock_recovery_delay(void);
  56void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
  57					const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
  58void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
  59					      const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
  60
  61int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
  62bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
  63					  int lane_count);
  64bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
  65					int lane_count);
  66bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
  67bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
  68bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
  69
  70u8 drm_dp_link_rate_to_bw_code(int link_rate);
  71int drm_dp_bw_code_to_link_rate(u8 link_bw);
  72
  73const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
  74
  75/**
  76 * struct drm_dp_vsc_sdp - drm DP VSC SDP
  77 *
  78 * This structure represents a DP VSC SDP of drm
  79 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
  80 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
  81 *
  82 * @sdp_type: secondary-data packet type
  83 * @revision: revision number
  84 * @length: number of valid data bytes
  85 * @pixelformat: pixel encoding format
  86 * @colorimetry: colorimetry format
  87 * @bpc: bit per color
  88 * @dynamic_range: dynamic range information
  89 * @content_type: CTA-861-G defines content types and expected processing by a sink device
  90 */
  91struct drm_dp_vsc_sdp {
  92	unsigned char sdp_type;
  93	unsigned char revision;
  94	unsigned char length;
  95	enum dp_pixelformat pixelformat;
  96	enum dp_colorimetry colorimetry;
  97	int bpc;
  98	enum dp_dynamic_range dynamic_range;
  99	enum dp_content_type content_type;
 100};
 101
 102/**
 103 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
 104 *
 105 * This structure represents a DP AS SDP of drm
 106 * It is based on DP 2.1 spec [Table 2-126:  Adaptive-Sync SDP Header Bytes] and
 107 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
 108 *
 109 * @sdp_type: Secondary-data packet type
 110 * @revision: Revision Number
 111 * @length: Number of valid data bytes
 112 * @vtotal: Minimum Vertical Vtotal
 113 * @target_rr: Target Refresh
 114 * @duration_incr_ms: Successive frame duration increase
 115 * @duration_decr_ms: Successive frame duration decrease
 116 * @target_rr_divider: Target refresh rate divider
 117 * @mode: Adaptive Sync Operation Mode
 118 */
 119struct drm_dp_as_sdp {
 120	unsigned char sdp_type;
 121	unsigned char revision;
 122	unsigned char length;
 123	int vtotal;
 124	int target_rr;
 125	int duration_incr_ms;
 126	int duration_decr_ms;
 127	bool target_rr_divider;
 128	enum operation_mode mode;
 129};
 130
 131void drm_dp_as_sdp_log(struct drm_printer *p,
 132		       const struct drm_dp_as_sdp *as_sdp);
 133void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
 134
 135bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 136bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 137
 138int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 139
 140static inline int
 141drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 142{
 143	return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
 144}
 145
 146static inline u8
 147drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 148{
 149	return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
 150}
 151
 152static inline bool
 153drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 154{
 155	return dpcd[DP_DPCD_REV] >= 0x11 &&
 156		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
 157}
 158
 159static inline bool
 160drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 161{
 162	return dpcd[DP_DPCD_REV] >= 0x13 &&
 163		(dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED);
 164}
 165
 166static inline bool
 167drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 168{
 169	return dpcd[DP_DPCD_REV] >= 0x11 &&
 170		(dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
 171}
 172
 173static inline bool
 174drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 175{
 176	return dpcd[DP_DPCD_REV] >= 0x12 &&
 177		dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
 178}
 179
 180static inline bool
 181drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 182{
 183	return dpcd[DP_DPCD_REV] >= 0x11 ||
 184		dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
 185}
 186
 187static inline bool
 188drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 189{
 190	return dpcd[DP_DPCD_REV] >= 0x14 &&
 191		dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
 192}
 193
 194static inline u8
 195drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 196{
 197	return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
 198		DP_TRAINING_PATTERN_MASK;
 199}
 200
 201static inline bool
 202drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 203{
 204	return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
 205}
 206
 207/* DP/eDP DSC support */
 208u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 209u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 210				   bool is_edp);
 211u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 212int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
 213					 u8 dsc_bpc[3]);
 214int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 215					 int peak_pixel_rate, bool is_rgb_yuv444);
 216int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
 217					     bool is_rgb_yuv444);
 218int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]);
 219
 220static inline bool
 221drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 222{
 223	return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
 224		DP_DSC_DECOMPRESSION_IS_SUPPORTED;
 225}
 226
 227static inline u16
 228drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 229{
 230	return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
 231		((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
 232		  DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8);
 233}
 234
 235static inline u32
 236drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 237{
 238	/* Max Slicewidth = Number of Pixels * 320 */
 239	return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
 240		DP_DSC_SLICE_WIDTH_MULTIPLIER;
 241}
 242
 243/**
 244 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
 245 * @dsc_dpcd : DSC-capability DPCDs of the sink
 246 * @output_format: output_format which is to be checked
 247 *
 248 * Returns true if the sink supports DSC with the given output_format, false otherwise.
 249 */
 250static inline bool
 251drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
 252{
 253	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
 254}
 255
 256/* Forward Error Correction Support on DP 1.4 */
 257static inline bool
 258drm_dp_sink_supports_fec(const u8 fec_capable)
 259{
 260	return fec_capable & DP_FEC_CAPABLE;
 261}
 262
 263static inline bool
 264drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 265{
 266	return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
 267}
 268
 269static inline bool
 270drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 271{
 272	return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
 273}
 274
 275static inline bool
 276drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 277{
 278	return dpcd[DP_EDP_CONFIGURATION_CAP] &
 279			DP_ALTERNATE_SCRAMBLER_RESET_CAP;
 280}
 281
 282/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
 283static inline bool
 284drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 285{
 286	return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
 287		DP_MSA_TIMING_PAR_IGNORED;
 288}
 289
 290/**
 291 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
 292 * @edp_dpcd: The DPCD to check
 293 *
 294 * Note that currently this function will return %false for panels which support various DPCD
 295 * backlight features but which require the brightness be set through PWM, and don't support setting
 296 * the brightness level via the DPCD.
 297 *
 298 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
 299 * otherwise
 300 */
 301static inline bool
 302drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
 303{
 304	return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
 305}
 306
 307/**
 308 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
 309 * @link_rate: link rate in 10kbits/s units
 310 *
 311 * Determine if the provided link rate is an UHBR rate.
 312 *
 313 * Returns: %True if @link_rate is an UHBR rate.
 314 */
 315static inline bool drm_dp_is_uhbr_rate(int link_rate)
 316{
 317	return link_rate >= 1000000;
 318}
 319
 320/*
 321 * DisplayPort AUX channel
 322 */
 323
 324/**
 325 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
 326 * @address: address of the (first) register to access
 327 * @request: contains the type of transaction (see DP_AUX_* macros)
 328 * @reply: upon completion, contains the reply type of the transaction
 329 * @buffer: pointer to a transmission or reception buffer
 330 * @size: size of @buffer
 331 */
 332struct drm_dp_aux_msg {
 333	unsigned int address;
 334	u8 request;
 335	u8 reply;
 336	void *buffer;
 337	size_t size;
 338};
 339
 340struct cec_adapter;
 341struct drm_connector;
 342struct drm_edid;
 343
 344/**
 345 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
 346 * @lock: mutex protecting this struct
 347 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
 348 * @connector: the connector this CEC adapter is associated with
 349 * @unregister_work: unregister the CEC adapter
 350 */
 351struct drm_dp_aux_cec {
 352	struct mutex lock;
 353	struct cec_adapter *adap;
 354	struct drm_connector *connector;
 355	struct delayed_work unregister_work;
 356};
 357
 358/**
 359 * struct drm_dp_aux - DisplayPort AUX channel
 360 *
 361 * An AUX channel can also be used to transport I2C messages to a sink. A
 362 * typical application of that is to access an EDID that's present in the sink
 363 * device. The @transfer() function can also be used to execute such
 364 * transactions. The drm_dp_aux_register() function registers an I2C adapter
 365 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
 366 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
 367 * transfers by default; if a partial response is received, the adapter will
 368 * drop down to the size given by the partial response for this transaction
 369 * only.
 370 */
 371struct drm_dp_aux {
 372	/**
 373	 * @name: user-visible name of this AUX channel and the
 374	 * I2C-over-AUX adapter.
 375	 *
 376	 * It's also used to specify the name of the I2C adapter. If set
 377	 * to %NULL, dev_name() of @dev will be used.
 378	 */
 379	const char *name;
 380
 381	/**
 382	 * @ddc: I2C adapter that can be used for I2C-over-AUX
 383	 * communication
 384	 */
 385	struct i2c_adapter ddc;
 386
 387	/**
 388	 * @dev: pointer to struct device that is the parent for this
 389	 * AUX channel.
 390	 */
 391	struct device *dev;
 392
 393	/**
 394	 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
 395	 * Beware, this may be %NULL before drm_dp_aux_register() has been
 396	 * called.
 397	 *
 398	 * It should be set to the &drm_device that will be using this AUX
 399	 * channel as early as possible. For many graphics drivers this should
 400	 * happen before drm_dp_aux_init(), however it's perfectly fine to set
 401	 * this field later so long as it's assigned before calling
 402	 * drm_dp_aux_register().
 403	 */
 404	struct drm_device *drm_dev;
 405
 406	/**
 407	 * @crtc: backpointer to the crtc that is currently using this
 408	 * AUX channel
 409	 */
 410	struct drm_crtc *crtc;
 411
 412	/**
 413	 * @hw_mutex: internal mutex used for locking transfers.
 414	 *
 415	 * Note that if the underlying hardware is shared among multiple
 416	 * channels, the driver needs to do additional locking to
 417	 * prevent concurrent access.
 418	 */
 419	struct mutex hw_mutex;
 420
 421	/**
 422	 * @crc_work: worker that captures CRCs for each frame
 423	 */
 424	struct work_struct crc_work;
 425
 426	/**
 427	 * @crc_count: counter of captured frame CRCs
 428	 */
 429	u8 crc_count;
 430
 431	/**
 432	 * @transfer: transfers a message representing a single AUX
 433	 * transaction.
 434	 *
 435	 * This is a hardware-specific implementation of how
 436	 * transactions are executed that the drivers must provide.
 437	 *
 438	 * A pointer to a &drm_dp_aux_msg structure describing the
 439	 * transaction is passed into this function. Upon success, the
 440	 * implementation should return the number of payload bytes that
 441	 * were transferred, or a negative error-code on failure.
 442	 *
 443	 * Helpers will propagate these errors, with the exception of
 444	 * the %-EBUSY error, which causes a transaction to be retried.
 445	 * On a short, helpers will return %-EPROTO to make it simpler
 446	 * to check for failure.
 447	 *
 448	 * The @transfer() function must only modify the reply field of
 449	 * the &drm_dp_aux_msg structure. The retry logic and i2c
 450	 * helpers assume this is the case.
 451	 *
 452	 * Also note that this callback can be called no matter the
 453	 * state @dev is in and also no matter what state the panel is
 454	 * in. It's expected:
 455	 *
 456	 * - If the @dev providing the AUX bus is currently unpowered then
 457	 *   it will power itself up for the transfer.
 458	 *
 459	 * - If we're on eDP (using a drm_panel) and the panel is not in a
 460	 *   state where it can respond (it's not powered or it's in a
 461	 *   low power state) then this function may return an error, but
 462	 *   not crash. It's up to the caller of this code to make sure that
 463	 *   the panel is powered on if getting an error back is not OK. If a
 464	 *   drm_panel driver is initiating a DP AUX transfer it may power
 465	 *   itself up however it wants. All other code should ensure that
 466	 *   the pre_enable() bridge chain (which eventually calls the
 467	 *   drm_panel prepare function) has powered the panel.
 468	 */
 469	ssize_t (*transfer)(struct drm_dp_aux *aux,
 470			    struct drm_dp_aux_msg *msg);
 471
 472	/**
 473	 * @wait_hpd_asserted: wait for HPD to be asserted
 474	 *
 475	 * This is mainly useful for eDP panels drivers to wait for an eDP
 476	 * panel to finish powering on. It is optional for DP AUX controllers
 477	 * to implement this function. It is required for DP AUX endpoints
 478	 * (panel drivers) to call this function after powering up but before
 479	 * doing AUX transfers unless the DP AUX endpoint driver knows that
 480	 * we're not using the AUX controller's HPD. One example of the panel
 481	 * driver not needing to call this is if HPD is hooked up to a GPIO
 482	 * that the panel driver can read directly.
 483	 *
 484	 * If a DP AUX controller does not implement this function then it
 485	 * may still support eDP panels that use the AUX controller's built-in
 486	 * HPD signal by implementing a long wait for HPD in the transfer()
 487	 * callback, though this is deprecated.
 488	 *
 489	 * This function will efficiently wait for the HPD signal to be
 490	 * asserted. The `wait_us` parameter that is passed in says that we
 491	 * know that the HPD signal is expected to be asserted within `wait_us`
 492	 * microseconds. This function could wait for longer than `wait_us` if
 493	 * the logic in the DP controller has a long debouncing time. The
 494	 * important thing is that if this function returns success that the
 495	 * DP controller is ready to send AUX transactions.
 496	 *
 497	 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
 498	 * expired and HPD wasn't asserted. This function should not print
 499	 * timeout errors to the log.
 500	 *
 501	 * The semantics of this function are designed to match the
 502	 * readx_poll_timeout() function. That means a `wait_us` of 0 means
 503	 * to wait forever. Like readx_poll_timeout(), this function may sleep.
 504	 *
 505	 * NOTE: this function specifically reports the state of the HPD pin
 506	 * that's associated with the DP AUX channel. This is different from
 507	 * the HPD concept in much of the rest of DRM which is more about
 508	 * physical presence of a display. For eDP, for instance, a display is
 509	 * assumed always present even if the HPD pin is deasserted.
 510	 */
 511	int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
 512
 513	/**
 514	 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
 515	 */
 516	unsigned i2c_nack_count;
 517	/**
 518	 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
 519	 */
 520	unsigned i2c_defer_count;
 521	/**
 522	 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
 523	 */
 524	struct drm_dp_aux_cec cec;
 525	/**
 526	 * @is_remote: Is this AUX CH actually using sideband messaging.
 527	 */
 528	bool is_remote;
 529
 530	/**
 531	 * @powered_down: If true then the remote endpoint is powered down.
 532	 */
 533	bool powered_down;
 534
 535	/**
 536	 * @no_zero_sized: If the hw can't use zero sized transfers (NVIDIA)
 537	 */
 538	bool no_zero_sized;
 539
 540	/**
 541	 * @dpcd_probe_disabled: If probing before a DPCD access is disabled.
 542	 */
 543	bool dpcd_probe_disabled;
 544};
 545
 546int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
 547void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered);
 548void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable);
 549ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
 550			 void *buffer, size_t size);
 551ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
 552			  void *buffer, size_t size);
 553
 554/**
 555 * drm_dp_dpcd_readb() - read a single byte from the DPCD
 556 * @aux: DisplayPort AUX channel
 557 * @offset: address of the register to read
 558 * @valuep: location where the value of the register will be stored
 559 *
 560 * Returns the number of bytes transferred (1) on success, or a negative
 561 * error code on failure. In most of the cases you should be using
 562 * drm_dp_dpcd_read_byte() instead.
 563 */
 564static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
 565					unsigned int offset, u8 *valuep)
 566{
 567	return drm_dp_dpcd_read(aux, offset, valuep, 1);
 568}
 569
 570/**
 571 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD
 572 * @aux: DisplayPort AUX channel (SST or MST)
 573 * @offset: address of the (first) register to read
 574 * @buffer: buffer to store the register values
 575 * @size: number of bytes in @buffer
 576 *
 577 * Returns zero (0) on success, or a negative error
 578 * code on failure. -EIO is returned if the request was NAKed by the sink or
 579 * if the retry count was exceeded. If not all bytes were transferred, this
 580 * function returns -EPROTO. Errors from the underlying AUX channel transfer
 581 * function, with the exception of -EBUSY (which causes the transaction to
 582 * be retried), are propagated to the caller.
 583 */
 584static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux,
 585					unsigned int offset,
 586					void *buffer, size_t size)
 587{
 588	int ret;
 589	size_t i;
 590	u8 *buf = buffer;
 591
 592	ret = drm_dp_dpcd_read(aux, offset, buffer, size);
 593	if (ret >= 0) {
 594		if (ret < size)
 595			return -EPROTO;
 596		return 0;
 597	}
 598
 599	/*
 600	 * Workaround for USB-C hubs/adapters with buggy firmware that fail
 601	 * multi-byte AUX reads but work with single-byte reads.
 602	 * Known affected devices:
 603	 * - Lenovo USB-C to VGA adapter (VIA VL817, idVendor=17ef, idProduct=7217)
 604	 * - Dell DA310 USB-C hub (idVendor=413c, idProduct=c010)
 605	 * Attempt byte-by-byte reading as a fallback.
 606	 */
 607	for (i = 0; i < size; i++) {
 608		ret = drm_dp_dpcd_readb(aux, offset + i, &buf[i]);
 609		if (ret < 0)
 610			return ret;
 611	}
 612
 613	return 0;
 614}
 615
 616/**
 617 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD
 618 * @aux: DisplayPort AUX channel (SST or MST)
 619 * @offset: address of the (first) register to write
 620 * @buffer: buffer containing the values to write
 621 * @size: number of bytes in @buffer
 622 *
 623 * Returns zero (0) on success, or a negative error
 624 * code on failure. -EIO is returned if the request was NAKed by the sink or
 625 * if the retry count was exceeded. If not all bytes were transferred, this
 626 * function returns -EPROTO. Errors from the underlying AUX channel transfer
 627 * function, with the exception of -EBUSY (which causes the transaction to
 628 * be retried), are propagated to the caller.
 629 */
 630static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux,
 631					 unsigned int offset,
 632					 void *buffer, size_t size)
 633{
 634	int ret;
 635
 636	ret = drm_dp_dpcd_write(aux, offset, buffer, size);
 637	if (ret < 0)
 638		return ret;
 639	if (ret < size)
 640		return -EPROTO;
 641
 642	return 0;
 643}
 644
 645/**
 646 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
 647 * @aux: DisplayPort AUX channel
 648 * @offset: address of the register to write
 649 * @value: value to write to the register
 650 *
 651 * Returns the number of bytes transferred (1) on success, or a negative
 652 * error code on failure. In most of the cases you should be using
 653 * drm_dp_dpcd_write_byte() instead.
 654 */
 655static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
 656					 unsigned int offset, u8 value)
 657{
 658	return drm_dp_dpcd_write(aux, offset, &value, 1);
 659}
 660
 661/**
 662 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD
 663 * @aux: DisplayPort AUX channel
 664 * @offset: address of the register to read
 665 * @valuep: location where the value of the register will be stored
 666 *
 667 * Returns zero (0) on success, or a negative error code on failure.
 668 */
 669static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux,
 670					unsigned int offset, u8 *valuep)
 671{
 672	return drm_dp_dpcd_read_data(aux, offset, valuep, 1);
 673}
 674
 675/**
 676 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD
 677 * @aux: DisplayPort AUX channel
 678 * @offset: address of the register to write
 679 * @value: value to write to the register
 680 *
 681 * Returns zero (0) on success, or a negative error code on failure.
 682 */
 683static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux,
 684					 unsigned int offset, u8 value)
 685{
 686	return drm_dp_dpcd_write_data(aux, offset, &value, 1);
 687}
 688
 689int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
 690			  u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 691
 692int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 693				 u8 status[DP_LINK_STATUS_SIZE]);
 694
 695int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
 696				     enum drm_dp_phy dp_phy,
 697				     u8 link_status[DP_LINK_STATUS_SIZE]);
 698int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision);
 699int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision);
 700
 701int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux,
 702			      int vcpid, u8 start_time_slot, u8 time_slot_count);
 703int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux);
 704int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms);
 705
 706bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
 707				    u8 real_edid_checksum);
 708
 709int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
 710				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 711				u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
 712bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 713			       const u8 port_cap[4], u8 type);
 714bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 715			       const u8 port_cap[4],
 716			       const struct drm_edid *drm_edid);
 717int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 718				   const u8 port_cap[4]);
 719int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 720				     const u8 port_cap[4],
 721				     const struct drm_edid *drm_edid);
 722int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 723				     const u8 port_cap[4],
 724				     const struct drm_edid *drm_edid);
 725int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 726			      const u8 port_cap[4],
 727			      const struct drm_edid *drm_edid);
 728bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 729				       const u8 port_cap[4]);
 730bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 731					     const u8 port_cap[4]);
 732struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
 733						const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 734						const u8 port_cap[4]);
 735int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
 736void drm_dp_downstream_debug(struct seq_file *m,
 737			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 738			     const u8 port_cap[4],
 739			     const struct drm_edid *drm_edid,
 740			     struct drm_dp_aux *aux);
 741enum drm_mode_subconnector
 742drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 743			 const u8 port_cap[4]);
 744void drm_dp_set_subconnector_property(struct drm_connector *connector,
 745				      enum drm_connector_status status,
 746				      const u8 *dpcd,
 747				      const u8 port_cap[4]);
 748
 749struct drm_dp_desc;
 750bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
 751				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 752				const struct drm_dp_desc *desc);
 753int drm_dp_read_sink_count(struct drm_dp_aux *aux);
 754
 755int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
 756				  const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 757				  u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
 758int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
 759			       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 760			       enum drm_dp_phy dp_phy,
 761			       u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
 762int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
 763int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
 764int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable);
 765int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count);
 766int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
 767bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
 768bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
 769void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode);
 770
 771void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
 772void drm_dp_aux_init(struct drm_dp_aux *aux);
 773int drm_dp_aux_register(struct drm_dp_aux *aux);
 774void drm_dp_aux_unregister(struct drm_dp_aux *aux);
 775
 776int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
 777int drm_dp_stop_crc(struct drm_dp_aux *aux);
 778
 779struct drm_dp_dpcd_ident {
 780	u8 oui[3];
 781	u8 device_id[6];
 782	u8 hw_rev;
 783	u8 sw_major_rev;
 784	u8 sw_minor_rev;
 785} __packed;
 786
 787/**
 788 * struct drm_dp_desc - DP branch/sink device descriptor
 789 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
 790 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
 791 */
 792struct drm_dp_desc {
 793	struct drm_dp_dpcd_ident ident;
 794	u32 quirks;
 795};
 796
 797int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
 798		     bool is_branch);
 799
 800int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy);
 801
 802/**
 803 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
 804 *
 805 * Display Port sink and branch devices in the wild have a variety of bugs, try
 806 * to collect them here. The quirks are shared, but it's up to the drivers to
 807 * implement workarounds for them.
 808 */
 809enum drm_dp_quirk {
 810	/**
 811	 * @DP_DPCD_QUIRK_CONSTANT_N:
 812	 *
 813	 * The device requires main link attributes Mvid and Nvid to be limited
 814	 * to 16 bits. So will give a constant value (0x8000) for compatability.
 815	 */
 816	DP_DPCD_QUIRK_CONSTANT_N,
 817	/**
 818	 * @DP_DPCD_QUIRK_NO_PSR:
 819	 *
 820	 * The device does not support PSR even if reports that it supports or
 821	 * driver still need to implement proper handling for such device.
 822	 */
 823	DP_DPCD_QUIRK_NO_PSR,
 824	/**
 825	 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
 826	 *
 827	 * The device does not set SINK_COUNT to a non-zero value.
 828	 * The driver should ignore SINK_COUNT during detection. Note that
 829	 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
 830	 */
 831	DP_DPCD_QUIRK_NO_SINK_COUNT,
 832	/**
 833	 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
 834	 *
 835	 * The device supports MST DSC despite not supporting Virtual DPCD.
 836	 * The DSC caps can be read from the physical aux instead.
 837	 */
 838	DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
 839	/**
 840	 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
 841	 *
 842	 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
 843	 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
 844	 */
 845	DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
 846	/**
 847	 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
 848	 *
 849	 * The device applies HBLANK expansion for some modes, but this
 850	 * requires enabling DSC.
 851	 */
 852	DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
 853	/**
 854	 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT:
 855	 *
 856	 * The device doesn't support DSC decompression at the maximum DSC
 857	 * pixel throughput and compressed bpp it indicates via its DPCD DSC
 858	 * capabilities. The compressed bpp must be limited above a device
 859	 * specific DSC pixel throughput.
 860	 */
 861	DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT,
 862};
 863
 864/**
 865 * drm_dp_has_quirk() - does the DP device have a specific quirk
 866 * @desc: Device descriptor filled by drm_dp_read_desc()
 867 * @quirk: Quirk to query for
 868 *
 869 * Return true if DP device identified by @desc has @quirk.
 870 */
 871static inline bool
 872drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
 873{
 874	return desc->quirks & BIT(quirk);
 875}
 876
 877/**
 878 * struct drm_edp_backlight_info - Probed eDP backlight info struct
 879 * @pwmgen_bit_count: The pwmgen bit count
 880 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
 881 * @max: The maximum backlight level that may be set
 882 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
 883 * @aux_enable: Does the panel support the AUX enable cap?
 884 * @aux_set: Does the panel support setting the brightness through AUX?
 885 * @luminance_set: Does the panel support setting the brightness through AUX using luminance values?
 886 *
 887 * This structure contains various data about an eDP backlight, which can be populated by using
 888 * drm_edp_backlight_init().
 889 */
 890struct drm_edp_backlight_info {
 891	u8 pwmgen_bit_count;
 892	u8 pwm_freq_pre_divider;
 893	u32 max;
 894
 895	bool lsb_reg_used : 1;
 896	bool aux_enable : 1;
 897	bool aux_set : 1;
 898	bool luminance_set : 1;
 899};
 900
 901int
 902drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
 903		       u32 max_luminance,
 904		       u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
 905		       u32 *current_level, u8 *current_mode, bool need_luminance);
 906int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
 907				u32 level);
 908int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
 909			     u32 level);
 910int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
 911
 912#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
 913	(IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
 914
 915int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
 916
 917#else
 918
 919static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
 920					     struct drm_dp_aux *aux)
 921{
 922	return 0;
 923}
 924
 925#endif
 926
 927#ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC
 928void drm_dp_cec_irq(struct drm_dp_aux *aux);
 929void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
 930				   struct drm_connector *connector);
 931void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
 932void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address);
 933void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
 934void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
 935#else
 936static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
 937{
 938}
 939
 940static inline void
 941drm_dp_cec_register_connector(struct drm_dp_aux *aux,
 942			      struct drm_connector *connector)
 943{
 944}
 945
 946static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
 947{
 948}
 949
 950static inline void drm_dp_cec_attach(struct drm_dp_aux *aux,
 951				     u16 source_physical_address)
 952{
 953}
 954
 955static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
 956				       const struct edid *edid)
 957{
 958}
 959
 960static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
 961{
 962}
 963
 964#endif
 965
 966/**
 967 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
 968 * @link_rate: Requested Link rate from DPCD 0x219
 969 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
 970 * @phy_pattern: DP Phy test pattern from DPCD 0x248
 971 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
 972 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
 973 * @enhanced_frame_cap: flag for enhanced frame capability.
 974 */
 975struct drm_dp_phy_test_params {
 976	int link_rate;
 977	u8 num_lanes;
 978	u8 phy_pattern;
 979	u8 hbr2_reset[2];
 980	u8 custom80[10];
 981	bool enhanced_frame_cap;
 982};
 983
 984int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
 985				struct drm_dp_phy_test_params *data);
 986int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
 987				struct drm_dp_phy_test_params *data, u8 dp_rev);
 988int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 989			       const u8 port_cap[4]);
 990int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
 991bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
 992int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
 993				u8 frl_mode);
 994int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
 995				u8 frl_type);
 996int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
 997int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
 998
 999bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
1000int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
1001void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
1002					   struct drm_connector *connector);
1003bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1004int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1005int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1006int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1007int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
1008int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
1009int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
1010bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1011					       const u8 port_cap[4], u8 color_spc);
1012int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
1013
1014#define DRM_DP_BW_OVERHEAD_MST		BIT(0)
1015#define DRM_DP_BW_OVERHEAD_UHBR		BIT(1)
1016#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK	BIT(2)
1017#define DRM_DP_BW_OVERHEAD_FEC		BIT(3)
1018#define DRM_DP_BW_OVERHEAD_DSC		BIT(4)
1019
1020int drm_dp_bw_overhead(int lane_count, int hactive,
1021		       int dsc_slice_count,
1022		       int bpp_x16, unsigned long flags);
1023int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
1024int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
1025
1026ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
1027int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
1028			      int bpp_x16, int symbol_size, bool is_mst);
1029
1030#endif /* _DRM_DP_HELPER_H_ */