lpc18xx_wdt.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * NXP LPC18xx Watchdog Timer (WDT)
  4 *
  5 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
  6 *
  7 * Notes
  8 * -----
  9 * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
 10 * counter which decrements on every clock cycle.
 11 */
 12
 13#include <linux/clk.h>
 14#include <linux/io.h>
 15#include <linux/module.h>
 16#include <linux/of.h>
 17#include <linux/platform_device.h>
 18#include <linux/watchdog.h>
 19
 20/* Registers */
 21#define LPC18XX_WDT_MOD			0x00
 22#define LPC18XX_WDT_MOD_WDEN		BIT(0)
 23#define LPC18XX_WDT_MOD_WDRESET		BIT(1)
 24
 25#define LPC18XX_WDT_TC			0x04
 26#define LPC18XX_WDT_TC_MIN		0xff
 27#define LPC18XX_WDT_TC_MAX		0xffffff
 28
 29#define LPC18XX_WDT_FEED		0x08
 30#define LPC18XX_WDT_FEED_MAGIC1		0xaa
 31#define LPC18XX_WDT_FEED_MAGIC2		0x55
 32
 33#define LPC18XX_WDT_TV			0x0c
 34
 35/* Clock pre-scaler */
 36#define LPC18XX_WDT_CLK_DIV		4
 37
 38/* Timeout values in seconds */
 39#define LPC18XX_WDT_DEF_TIMEOUT		30U
 40
 41static int heartbeat;
 42module_param(heartbeat, int, 0);
 43MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds (default="
 44		 __MODULE_STRING(LPC18XX_WDT_DEF_TIMEOUT) ")");
 45
 46static bool nowayout = WATCHDOG_NOWAYOUT;
 47module_param(nowayout, bool, 0);
 48MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
 49		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 50
 51struct lpc18xx_wdt_dev {
 52	struct watchdog_device	wdt_dev;
 53	struct clk		*reg_clk;
 54	struct clk		*wdt_clk;
 55	unsigned long		clk_rate;
 56	void __iomem		*base;
 57	struct timer_list	timer;
 58	spinlock_t		lock;
 59};
 60
 61static int lpc18xx_wdt_feed(struct watchdog_device *wdt_dev)
 62{
 63	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
 64	unsigned long flags;
 65
 66	/*
 67	 * An abort condition will occur if an interrupt happens during the feed
 68	 * sequence.
 69	 */
 70	spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
 71	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
 72	writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
 73	spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
 74
 75	return 0;
 76}
 77
 78static void lpc18xx_wdt_timer_feed(struct timer_list *t)
 79{
 80	struct lpc18xx_wdt_dev *lpc18xx_wdt = timer_container_of(lpc18xx_wdt,
 81								 t, timer);
 82	struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev;
 83
 84	lpc18xx_wdt_feed(wdt_dev);
 85
 86	/* Use safe value (1/2 of real timeout) */
 87	mod_timer(&lpc18xx_wdt->timer, jiffies +
 88		  msecs_to_jiffies((wdt_dev->timeout * MSEC_PER_SEC) / 2));
 89}
 90
 91/*
 92 * Since LPC18xx Watchdog cannot be disabled in hardware, we must keep feeding
 93 * it with a timer until userspace watchdog software takes over.
 94 */
 95static int lpc18xx_wdt_stop(struct watchdog_device *wdt_dev)
 96{
 97	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
 98
 99	lpc18xx_wdt_timer_feed(&lpc18xx_wdt->timer);
100
101	return 0;
102}
103
104static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev *lpc18xx_wdt)
105{
106	unsigned int val;
107
108	val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate,
109			   LPC18XX_WDT_CLK_DIV);
110	writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC);
111}
112
113static int lpc18xx_wdt_set_timeout(struct watchdog_device *wdt_dev,
114				   unsigned int new_timeout)
115{
116	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
117
118	lpc18xx_wdt->wdt_dev.timeout = new_timeout;
119	__lpc18xx_wdt_set_timeout(lpc18xx_wdt);
120
121	return 0;
122}
123
124static unsigned int lpc18xx_wdt_get_timeleft(struct watchdog_device *wdt_dev)
125{
126	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
127	unsigned int val;
128
129	val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV);
130	return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
131}
132
133static int lpc18xx_wdt_start(struct watchdog_device *wdt_dev)
134{
135	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
136	unsigned int val;
137
138	if (timer_pending(&lpc18xx_wdt->timer))
139		timer_delete(&lpc18xx_wdt->timer);
140
141	val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
142	val |= LPC18XX_WDT_MOD_WDEN;
143	val |= LPC18XX_WDT_MOD_WDRESET;
144	writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
145
146	/*
147	 * Setting the WDEN bit in the WDMOD register is not sufficient to
148	 * enable the Watchdog. A valid feed sequence must be completed after
149	 * setting WDEN before the Watchdog is capable of generating a reset.
150	 */
151	lpc18xx_wdt_feed(wdt_dev);
152
153	return 0;
154}
155
156static int lpc18xx_wdt_restart(struct watchdog_device *wdt_dev,
157			       unsigned long action, void *data)
158{
159	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
160	unsigned long flags;
161	int val;
162
163	/*
164	 * Incorrect feed sequence causes immediate watchdog reset if enabled.
165	 */
166	spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
167
168	val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
169	val |= LPC18XX_WDT_MOD_WDEN;
170	val |= LPC18XX_WDT_MOD_WDRESET;
171	writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
172
173	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
174	writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
175
176	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
177	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
178
179	spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
180
181	return 0;
182}
183
184static const struct watchdog_info lpc18xx_wdt_info = {
185	.identity	= "NXP LPC18xx Watchdog",
186	.options	= WDIOF_SETTIMEOUT |
187			  WDIOF_KEEPALIVEPING |
188			  WDIOF_MAGICCLOSE,
189};
190
191static const struct watchdog_ops lpc18xx_wdt_ops = {
192	.owner		= THIS_MODULE,
193	.start		= lpc18xx_wdt_start,
194	.stop		= lpc18xx_wdt_stop,
195	.ping		= lpc18xx_wdt_feed,
196	.set_timeout	= lpc18xx_wdt_set_timeout,
197	.get_timeleft	= lpc18xx_wdt_get_timeleft,
198	.restart        = lpc18xx_wdt_restart,
199};
200
201static int lpc18xx_wdt_probe(struct platform_device *pdev)
202{
203	struct lpc18xx_wdt_dev *lpc18xx_wdt;
204	struct device *dev = &pdev->dev;
205
206	lpc18xx_wdt = devm_kzalloc(dev, sizeof(*lpc18xx_wdt), GFP_KERNEL);
207	if (!lpc18xx_wdt)
208		return -ENOMEM;
209
210	lpc18xx_wdt->base = devm_platform_ioremap_resource(pdev, 0);
211	if (IS_ERR(lpc18xx_wdt->base))
212		return PTR_ERR(lpc18xx_wdt->base);
213
214	lpc18xx_wdt->reg_clk = devm_clk_get_enabled(dev, "reg");
215	if (IS_ERR(lpc18xx_wdt->reg_clk)) {
216		dev_err(dev, "failed to get the reg clock\n");
217		return PTR_ERR(lpc18xx_wdt->reg_clk);
218	}
219
220	lpc18xx_wdt->wdt_clk = devm_clk_get_enabled(dev, "wdtclk");
221	if (IS_ERR(lpc18xx_wdt->wdt_clk)) {
222		dev_err(dev, "failed to get the wdt clock\n");
223		return PTR_ERR(lpc18xx_wdt->wdt_clk);
224	}
225
226	/* We use the clock rate to calculate timeouts */
227	lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk);
228	if (lpc18xx_wdt->clk_rate == 0) {
229		dev_err(dev, "failed to get clock rate\n");
230		return -EINVAL;
231	}
232
233	lpc18xx_wdt->wdt_dev.info = &lpc18xx_wdt_info;
234	lpc18xx_wdt->wdt_dev.ops = &lpc18xx_wdt_ops;
235
236	lpc18xx_wdt->wdt_dev.min_timeout = DIV_ROUND_UP(LPC18XX_WDT_TC_MIN *
237				LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate);
238
239	lpc18xx_wdt->wdt_dev.max_timeout = (LPC18XX_WDT_TC_MAX *
240				LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
241
242	lpc18xx_wdt->wdt_dev.timeout = min(lpc18xx_wdt->wdt_dev.max_timeout,
243					   LPC18XX_WDT_DEF_TIMEOUT);
244
245	spin_lock_init(&lpc18xx_wdt->lock);
246
247	lpc18xx_wdt->wdt_dev.parent = dev;
248	watchdog_set_drvdata(&lpc18xx_wdt->wdt_dev, lpc18xx_wdt);
249
250	watchdog_init_timeout(&lpc18xx_wdt->wdt_dev, heartbeat, dev);
251
252	__lpc18xx_wdt_set_timeout(lpc18xx_wdt);
253
254	timer_setup(&lpc18xx_wdt->timer, lpc18xx_wdt_timer_feed, 0);
255
256	watchdog_set_nowayout(&lpc18xx_wdt->wdt_dev, nowayout);
257	watchdog_set_restart_priority(&lpc18xx_wdt->wdt_dev, 128);
258
259	platform_set_drvdata(pdev, lpc18xx_wdt);
260
261	watchdog_stop_on_reboot(&lpc18xx_wdt->wdt_dev);
262	return devm_watchdog_register_device(dev, &lpc18xx_wdt->wdt_dev);
263}
264
265static void lpc18xx_wdt_remove(struct platform_device *pdev)
266{
267	struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev);
268
269	dev_warn(&pdev->dev, "I quit now, hardware will probably reboot!\n");
270	timer_delete_sync(&lpc18xx_wdt->timer);
271}
272
273static const struct of_device_id lpc18xx_wdt_match[] = {
274	{ .compatible = "nxp,lpc1850-wwdt" },
275	{}
276};
277MODULE_DEVICE_TABLE(of, lpc18xx_wdt_match);
278
279static struct platform_driver lpc18xx_wdt_driver = {
280	.driver = {
281		.name = "lpc18xx-wdt",
282		.of_match_table	= lpc18xx_wdt_match,
283	},
284	.probe = lpc18xx_wdt_probe,
285	.remove = lpc18xx_wdt_remove,
286};
287module_platform_driver(lpc18xx_wdt_driver);
288
289MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
290MODULE_DESCRIPTION("NXP LPC18xx Watchdog Timer Driver");
291MODULE_LICENSE("GPL v2");