iTCO_wdt.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 *	intel TCO Watchdog Driver
  4 *
  5 *	(c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
  6 *
  7 *	Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  8 *	provide warranty for any of this software. This material is
  9 *	provided "AS-IS" and at no charge.
 10 *
 11 *	The TCO watchdog is implemented in the following I/O controller hubs:
 12 *	(See the intel documentation on http://developer.intel.com.)
 13 *	document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
 14 *	document number 290687-002, 298242-027: 82801BA (ICH2)
 15 *	document number 290733-003, 290739-013: 82801CA (ICH3-S)
 16 *	document number 290716-001, 290718-007: 82801CAM (ICH3-M)
 17 *	document number 290744-001, 290745-025: 82801DB (ICH4)
 18 *	document number 252337-001, 252663-008: 82801DBM (ICH4-M)
 19 *	document number 273599-001, 273645-002: 82801E (C-ICH)
 20 *	document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
 21 *	document number 300641-004, 300884-013: 6300ESB
 22 *	document number 301473-002, 301474-026: 82801F (ICH6)
 23 *	document number 313082-001, 313075-006: 631xESB, 632xESB
 24 *	document number 307013-003, 307014-024: 82801G (ICH7)
 25 *	document number 322896-001, 322897-001: NM10
 26 *	document number 313056-003, 313057-017: 82801H (ICH8)
 27 *	document number 316972-004, 316973-012: 82801I (ICH9)
 28 *	document number 319973-002, 319974-002: 82801J (ICH10)
 29 *	document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
 30 *	document number 320066-003, 320257-008: EP80597 (IICH)
 31 *	document number 324645-001, 324646-001: Cougar Point (CPT)
 32 *	document number TBD                   : Patsburg (PBG)
 33 *	document number TBD                   : DH89xxCC
 34 *	document number TBD                   : Panther Point
 35 *	document number TBD                   : Lynx Point
 36 *	document number TBD                   : Lynx Point-LP
 37 */
 38
 39/*
 40 *	Includes, defines, variables, module parameters, ...
 41 */
 42
 43/* Module and version information */
 44#define DRV_NAME	"iTCO_wdt"
 45#define DRV_VERSION	"1.11"
 46
 47/* Includes */
 48#include <linux/acpi.h>			/* For ACPI support */
 49#include <linux/bits.h>			/* For BIT() */
 50#include <linux/module.h>		/* For module specific items */
 51#include <linux/moduleparam.h>		/* For new moduleparam's */
 52#include <linux/types.h>		/* For standard types (like size_t) */
 53#include <linux/errno.h>		/* For the -ENODEV/... values */
 54#include <linux/kernel.h>		/* For printk/panic/... */
 55#include <linux/watchdog.h>		/* For the watchdog specific items */
 56#include <linux/init.h>			/* For __init/__exit/... */
 57#include <linux/fs.h>			/* For file operations */
 58#include <linux/platform_device.h>	/* For platform_driver framework */
 59#include <linux/pci.h>			/* For pci functions */
 60#include <linux/ioport.h>		/* For io-port access */
 61#include <linux/uaccess.h>		/* For copy_to_user/put_user/... */
 62#include <linux/io.h>			/* For inb/outb/... */
 63#include <linux/platform_data/itco_wdt.h>
 64#include <linux/mfd/intel_pmc_bxt.h>
 65
 66#include "iTCO_vendor.h"
 67
 68/* Address definitions for the TCO */
 69/* TCO base address */
 70#define TCOBASE(p)	((p)->tco_res->start)
 71/* SMI Control and Enable Register */
 72#define SMI_EN(p)	((p)->smi_res->start)
 73
 74#define TCO_RLD(p)	(TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
 75#define TCOv1_TMR(p)	(TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
 76#define TCO_DAT_IN(p)	(TCOBASE(p) + 0x02) /* TCO Data In Register	*/
 77#define TCO_DAT_OUT(p)	(TCOBASE(p) + 0x03) /* TCO Data Out Register	*/
 78#define TCO1_STS(p)	(TCOBASE(p) + 0x04) /* TCO1 Status Register	*/
 79#define TCO2_STS(p)	(TCOBASE(p) + 0x06) /* TCO2 Status Register	*/
 80#define TCO1_CNT(p)	(TCOBASE(p) + 0x08) /* TCO1 Control Register	*/
 81#define TCO2_CNT(p)	(TCOBASE(p) + 0x0a) /* TCO2 Control Register	*/
 82#define TCOv2_TMR(p)	(TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
 83
 84/*
 85 * NMI_NOW is bit 8 of TCO1_CNT register
 86 * Read/Write
 87 * This bit is implemented as RW but has no effect on HW.
 88 */
 89#define NMI_NOW		BIT(8)
 90
 91/* internal variables */
 92struct iTCO_wdt_private {
 93	struct watchdog_device wddev;
 94
 95	/* TCO version/generation */
 96	unsigned int iTCO_version;
 97	struct resource *tco_res;
 98	struct resource *smi_res;
 99	/*
100	 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
101	 * or memory-mapped PMC register bit 4 (TCO version 3).
102	 */
103	unsigned long __iomem *gcs_pmc;
104	/* the PCI-device */
105	struct pci_dev *pci_dev;
106	/* whether or not the watchdog has been suspended */
107	bool suspended;
108	/* no reboot API private data */
109	void *no_reboot_priv;
110	/* no reboot update function pointer */
111	int (*update_no_reboot_bit)(void *p, bool set);
112};
113
114/* module parameters */
115#define WATCHDOG_TIMEOUT 30	/* 30 sec default heartbeat */
116static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
117module_param(heartbeat, int, 0);
118MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
119	"5..76 (TCO v1) or 3..614 (TCO v2), default="
120				__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
121
122static bool nowayout = WATCHDOG_NOWAYOUT;
123module_param(nowayout, bool, 0);
124MODULE_PARM_DESC(nowayout,
125	"Watchdog cannot be stopped once started (default="
126				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
127
128static int turn_SMI_watchdog_clear_off = 1;
129module_param(turn_SMI_watchdog_clear_off, int, 0);
130MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
131	"Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
132
133/*
134 * Some TCO specific functions
135 */
136
137/*
138 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
139 * every 0.6 seconds.  v3's internal timer is stored as seconds (some
140 * datasheets incorrectly state 0.6 seconds).
141 */
142static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
143					    int secs)
144{
145	return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
146}
147
148static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
149					    int ticks)
150{
151	return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
152}
153
154static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
155{
156	u32 enable_bit;
157
158	switch (p->iTCO_version) {
159	case 5:
160	case 3:
161		enable_bit = 0x00000010;
162		break;
163	case 2:
164		enable_bit = 0x00000020;
165		break;
166	case 4:
167	case 1:
168	default:
169		enable_bit = 0x00000002;
170		break;
171	}
172
173	return enable_bit;
174}
175
176static int update_no_reboot_bit_def(void *priv, bool set)
177{
178	return 0;
179}
180
181static int update_no_reboot_bit_pci(void *priv, bool set)
182{
183	struct iTCO_wdt_private *p = priv;
184	u32 val32 = 0, newval32 = 0;
185
186	pci_read_config_dword(p->pci_dev, 0xd4, &val32);
187	if (set)
188		val32 |= no_reboot_bit(p);
189	else
190		val32 &= ~no_reboot_bit(p);
191	pci_write_config_dword(p->pci_dev, 0xd4, val32);
192	pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
193
194	/* make sure the update is successful */
195	if (val32 != newval32)
196		return -EIO;
197
198	return 0;
199}
200
201static int update_no_reboot_bit_mem(void *priv, bool set)
202{
203	struct iTCO_wdt_private *p = priv;
204	u32 val32 = 0, newval32 = 0;
205
206	val32 = readl(p->gcs_pmc);
207	if (set)
208		val32 |= no_reboot_bit(p);
209	else
210		val32 &= ~no_reboot_bit(p);
211	writel(val32, p->gcs_pmc);
212	newval32 = readl(p->gcs_pmc);
213
214	/* make sure the update is successful */
215	if (val32 != newval32)
216		return -EIO;
217
218	return 0;
219}
220
221static int update_no_reboot_bit_cnt(void *priv, bool set)
222{
223	struct iTCO_wdt_private *p = priv;
224	u16 val, newval;
225
226	/*
227	 * writing back 1b1 to NMI_NOW of TCO1_CNT register
228	 * causes NMI_NOW bit inversion what consequently does
229	 * not allow to perform the register's value comparison
230	 * properly.
231	 *
232	 * NMI_NOW bit masking for TCO1_CNT register values
233	 * helps to avoid possible NMI_NOW bit inversions on
234	 * following write operation.
235	 */
236	val = inw(TCO1_CNT(p)) & ~NMI_NOW;
237	if (set)
238		val |= BIT(0);
239	else
240		val &= ~BIT(0);
241	outw(val, TCO1_CNT(p));
242	newval = inw(TCO1_CNT(p)) & ~NMI_NOW;
243
244	/* make sure the update is successful */
245	return val != newval ? -EIO : 0;
246}
247
248static int update_no_reboot_bit_pmc(void *priv, bool set)
249{
250	struct intel_pmc_dev *pmc = priv;
251	u32 bits = PMC_CFG_NO_REBOOT_EN;
252	u32 value = set ? bits : 0;
253
254	return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
255}
256
257static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
258					 struct platform_device *pdev,
259					 struct itco_wdt_platform_data *pdata)
260{
261	if (pdata->no_reboot_use_pmc) {
262		struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
263
264		p->update_no_reboot_bit = update_no_reboot_bit_pmc;
265		p->no_reboot_priv = pmc;
266		return;
267	}
268
269	if (p->iTCO_version >= 6)
270		p->update_no_reboot_bit = update_no_reboot_bit_cnt;
271	else if (p->iTCO_version >= 2)
272		p->update_no_reboot_bit = update_no_reboot_bit_mem;
273	else if (p->iTCO_version == 1)
274		p->update_no_reboot_bit = update_no_reboot_bit_pci;
275	else
276		p->update_no_reboot_bit = update_no_reboot_bit_def;
277
278	p->no_reboot_priv = p;
279}
280
281static int iTCO_wdt_start(struct watchdog_device *wd_dev)
282{
283	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
284	unsigned int val;
285
286	iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
287
288	/* disable chipset's NO_REBOOT bit */
289	if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
290		dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
291		return -EIO;
292	}
293
294	/* Force the timer to its reload value by writing to the TCO_RLD
295	   register */
296	if (p->iTCO_version >= 2)
297		outw(0x01, TCO_RLD(p));
298	else if (p->iTCO_version == 1)
299		outb(0x01, TCO_RLD(p));
300
301	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
302	val = inw(TCO1_CNT(p));
303	val &= 0xf7ff;
304	outw(val, TCO1_CNT(p));
305	val = inw(TCO1_CNT(p));
306
307	if (val & 0x0800)
308		return -1;
309	return 0;
310}
311
312static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
313{
314	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
315	unsigned int val;
316
317	iTCO_vendor_pre_stop(p->smi_res);
318
319	/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
320	val = inw(TCO1_CNT(p));
321	val |= 0x0800;
322	outw(val, TCO1_CNT(p));
323	val = inw(TCO1_CNT(p));
324
325	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
326	p->update_no_reboot_bit(p->no_reboot_priv, true);
327
328	if ((val & 0x0800) == 0)
329		return -1;
330	return 0;
331}
332
333static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
334{
335	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
336
337	/* Reload the timer by writing to the TCO Timer Counter register */
338	if (p->iTCO_version >= 2) {
339		outw(0x01, TCO_RLD(p));
340	} else if (p->iTCO_version == 1) {
341		/* Reset the timeout status bit so that the timer
342		 * needs to count down twice again before rebooting */
343		outw(0x0008, TCO1_STS(p));	/* write 1 to clear bit */
344
345		outb(0x01, TCO_RLD(p));
346	}
347
348	return 0;
349}
350
351static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
352{
353	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
354	unsigned int val16;
355	unsigned char val8;
356	unsigned int tmrval;
357
358	tmrval = seconds_to_ticks(p, t);
359
360	/* For TCO v1 the timer counts down twice before rebooting */
361	if (p->iTCO_version == 1)
362		tmrval /= 2;
363
364	/* from the specs: */
365	/* "Values of 0h-3h are ignored and should not be attempted" */
366	if (tmrval < 0x04)
367		return -EINVAL;
368	if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
369	    (p->iTCO_version == 1 && tmrval > 0x03f))
370		return -EINVAL;
371
372	/* Write new heartbeat to watchdog */
373	if (p->iTCO_version >= 2) {
374		val16 = inw(TCOv2_TMR(p));
375		val16 &= 0xfc00;
376		val16 |= tmrval;
377		outw(val16, TCOv2_TMR(p));
378		val16 = inw(TCOv2_TMR(p));
379
380		if ((val16 & 0x3ff) != tmrval)
381			return -EINVAL;
382	} else if (p->iTCO_version == 1) {
383		val8 = inb(TCOv1_TMR(p));
384		val8 &= 0xc0;
385		val8 |= (tmrval & 0xff);
386		outb(val8, TCOv1_TMR(p));
387		val8 = inb(TCOv1_TMR(p));
388
389		if ((val8 & 0x3f) != tmrval)
390			return -EINVAL;
391	}
392
393	wd_dev->timeout = t;
394	return 0;
395}
396
397static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
398{
399	struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
400	unsigned int val16;
401	unsigned char val8;
402	unsigned int time_left = 0;
403
404	/* read the TCO Timer */
405	if (p->iTCO_version >= 2) {
406		val16 = inw(TCO_RLD(p));
407		val16 &= 0x3ff;
408
409		time_left = ticks_to_seconds(p, val16);
410	} else if (p->iTCO_version == 1) {
411		val8 = inb(TCO_RLD(p));
412		val8 &= 0x3f;
413		if (!(inw(TCO1_STS(p)) & 0x0008))
414			val8 += (inb(TCOv1_TMR(p)) & 0x3f);
415
416		time_left = ticks_to_seconds(p, val8);
417	}
418	return time_left;
419}
420
421/* Returns true if the watchdog was running */
422static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
423{
424	u16 val;
425
426	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
427	val = inw(TCO1_CNT(p));
428	if (!(val & BIT(11))) {
429		set_bit(WDOG_HW_RUNNING, &p->wddev.status);
430		return true;
431	}
432	return false;
433}
434
435/*
436 *	Kernel Interfaces
437 */
438
439static struct watchdog_info ident = {
440	.options =		WDIOF_SETTIMEOUT |
441				WDIOF_KEEPALIVEPING |
442				WDIOF_MAGICCLOSE,
443	.identity =		DRV_NAME,
444};
445
446static const struct watchdog_ops iTCO_wdt_ops = {
447	.owner =		THIS_MODULE,
448	.start =		iTCO_wdt_start,
449	.stop =			iTCO_wdt_stop,
450	.ping =			iTCO_wdt_ping,
451	.set_timeout =		iTCO_wdt_set_timeout,
452	.get_timeleft =		iTCO_wdt_get_timeleft,
453};
454
455/*
456 *	Init & exit routines
457 */
458
459static int iTCO_wdt_probe(struct platform_device *pdev)
460{
461	struct device *dev = &pdev->dev;
462	struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
463	struct iTCO_wdt_private *p;
464	unsigned long val32;
465	int ret;
466
467	if (!pdata)
468		return -ENODEV;
469
470	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
471	if (!p)
472		return -ENOMEM;
473
474	p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
475	if (!p->tco_res)
476		return -ENODEV;
477
478	p->iTCO_version = pdata->version;
479	p->pci_dev = to_pci_dev(dev->parent);
480
481	p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
482	if (p->smi_res) {
483		/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
484		if (!devm_request_region(dev, p->smi_res->start,
485					 resource_size(p->smi_res),
486					 pdev->name)) {
487			dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
488			       (u64)SMI_EN(p));
489			return -EBUSY;
490		}
491	} else if (iTCO_vendorsupport ||
492		   turn_SMI_watchdog_clear_off >= p->iTCO_version) {
493		dev_err(dev, "SMI I/O resource is missing\n");
494		return -ENODEV;
495	}
496
497	iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
498
499	/*
500	 * Get the Memory-Mapped GCS or PMC register, we need it for the
501	 * NO_REBOOT flag (TCO v2 and v3).
502	 */
503	if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
504	    !pdata->no_reboot_use_pmc) {
505		p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC);
506		if (IS_ERR(p->gcs_pmc))
507			return PTR_ERR(p->gcs_pmc);
508	}
509
510	/* Check chipset's NO_REBOOT bit */
511	if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
512	    iTCO_vendor_check_noreboot_on()) {
513		dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
514		return -ENODEV;	/* Cannot reset NO_REBOOT bit */
515	}
516
517	if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
518		/*
519		 * Bit 13: TCO_EN -> 0
520		 * Disables TCO logic generating an SMI#
521		 */
522		val32 = inl(SMI_EN(p));
523		val32 &= 0xffffdfff;	/* Turn off SMI clearing watchdog */
524		outl(val32, SMI_EN(p));
525	}
526
527	if (!devm_request_region(dev, p->tco_res->start,
528				 resource_size(p->tco_res),
529				 pdev->name)) {
530		dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
531		       (u64)TCOBASE(p));
532		return -EBUSY;
533	}
534
535	dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
536		pdata->name, pdata->version, (u64)TCOBASE(p));
537
538	/* Clear out the (probably old) status */
539	switch (p->iTCO_version) {
540	case 6:
541	case 5:
542	case 4:
543		outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
544		outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
545		break;
546	case 3:
547		outl(0x20008, TCO1_STS(p));
548		break;
549	case 2:
550	case 1:
551	default:
552		outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
553		outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
554		outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
555		break;
556	}
557
558	ident.firmware_version = p->iTCO_version;
559	p->wddev.info = &ident;
560	p->wddev.ops = &iTCO_wdt_ops;
561	p->wddev.bootstatus = 0;
562	p->wddev.timeout = WATCHDOG_TIMEOUT;
563	watchdog_set_nowayout(&p->wddev, nowayout);
564	p->wddev.parent = dev;
565
566	watchdog_set_drvdata(&p->wddev, p);
567	platform_set_drvdata(pdev, p);
568
569	if (!iTCO_wdt_set_running(p)) {
570		/*
571		 * If the watchdog was not running set NO_REBOOT now to
572		 * prevent later reboots.
573		 */
574		p->update_no_reboot_bit(p->no_reboot_priv, true);
575	}
576
577	/* Check that the heartbeat value is within it's range;
578	   if not reset to the default */
579	if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
580		ret = iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
581		if (ret != 0) {
582			dev_err(dev, "Failed to set watchdog timeout (%d)\n", WATCHDOG_TIMEOUT);
583			return ret;
584		}
585		dev_info(dev, "timeout value out of range, using %d\n",
586			WATCHDOG_TIMEOUT);
587		heartbeat = WATCHDOG_TIMEOUT;
588	}
589
590	watchdog_stop_on_reboot(&p->wddev);
591	watchdog_stop_on_unregister(&p->wddev);
592	ret = devm_watchdog_register_device(dev, &p->wddev);
593	if (ret != 0)
594		return ret;
595
596	dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
597		heartbeat, nowayout);
598
599	return 0;
600}
601
602/*
603 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
604 * the watchdog cannot be pinged while in that state.  In ACPI sleep states the
605 * watchdog is stopped by the platform firmware.
606 */
607
608#ifdef CONFIG_ACPI
609static inline bool __maybe_unused need_suspend(void)
610{
611	return acpi_target_system_state() == ACPI_STATE_S0;
612}
613#else
614static inline bool __maybe_unused need_suspend(void) { return true; }
615#endif
616
617static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev)
618{
619	struct iTCO_wdt_private *p = dev_get_drvdata(dev);
620	int ret = 0;
621
622	p->suspended = false;
623	if (watchdog_active(&p->wddev) && need_suspend()) {
624		ret = iTCO_wdt_stop(&p->wddev);
625		if (!ret)
626			p->suspended = true;
627	}
628	return ret;
629}
630
631static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev)
632{
633	struct iTCO_wdt_private *p = dev_get_drvdata(dev);
634
635	if (p->suspended)
636		iTCO_wdt_start(&p->wddev);
637
638	return 0;
639}
640
641static const struct dev_pm_ops iTCO_wdt_pm = {
642	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq,
643				      iTCO_wdt_resume_noirq)
644};
645
646static struct platform_driver iTCO_wdt_driver = {
647	.probe          = iTCO_wdt_probe,
648	.driver         = {
649		.name   = DRV_NAME,
650		.pm     = &iTCO_wdt_pm,
651	},
652};
653
654module_platform_driver(iTCO_wdt_driver);
655
656MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
657MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
658MODULE_VERSION(DRV_VERSION);
659MODULE_LICENSE("GPL");
660MODULE_ALIAS("platform:" DRV_NAME);