chip.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  5
  6 */
  7#ifndef __CHIP_H__
  8#define __CHIP_H__
  9
 10#include "global.h"
 11
 12/***************************************/
 13/* Definition Graphic Chip Information */
 14/***************************************/
 15
 16#define     PCI_VIA_VENDOR_ID       0x1106
 17
 18/* Define VIA Graphic Chip Name */
 19#define     UNICHROME_CLE266        1
 20#define     UNICHROME_CLE266_DID    0x3122
 21#define     CLE266_REVISION_AX      0x0A
 22#define     CLE266_REVISION_CX      0x0C
 23
 24#define     UNICHROME_K400          2
 25#define     UNICHROME_K400_DID      0x7205
 26
 27#define     UNICHROME_K800          3
 28#define     UNICHROME_K800_DID      0x3108
 29
 30#define     UNICHROME_PM800         4
 31#define     UNICHROME_PM800_DID     0x3118
 32
 33#define     UNICHROME_CN700         5
 34#define     UNICHROME_CN700_DID     0x3344
 35
 36#define     UNICHROME_CX700         6
 37#define     UNICHROME_CX700_DID     0x3157
 38#define     CX700_REVISION_700      0x0
 39#define     CX700_REVISION_700M     0x1
 40#define     CX700_REVISION_700M2    0x2
 41
 42#define     UNICHROME_CN750         7
 43#define     UNICHROME_CN750_DID     0x3225
 44
 45#define     UNICHROME_K8M890        8
 46#define     UNICHROME_K8M890_DID    0x3230
 47
 48#define     UNICHROME_P4M890        9
 49#define     UNICHROME_P4M890_DID    0x3343
 50
 51#define     UNICHROME_P4M900        10
 52#define     UNICHROME_P4M900_DID    0x3371
 53
 54#define     UNICHROME_VX800         11
 55#define     UNICHROME_VX800_DID     0x1122
 56
 57#define     UNICHROME_VX855         12
 58#define     UNICHROME_VX855_DID     0x5122
 59
 60#define     UNICHROME_VX900         13
 61#define     UNICHROME_VX900_DID     0x7122
 62
 63/**************************************************/
 64/* Definition TMDS Trasmitter Information         */
 65/**************************************************/
 66
 67/* Definition TMDS Trasmitter Index */
 68#define     NON_TMDS_TRANSMITTER    0x00
 69#define     VT1632_TMDS             0x01
 70#define     INTEGRATED_TMDS         0x42
 71
 72/* Definition TMDS Trasmitter I2C Target Address */
 73#define     VT1632_TMDS_I2C_ADDR    0x10
 74
 75/**************************************************/
 76/* Definition LVDS Trasmitter Information         */
 77/**************************************************/
 78
 79/* Definition LVDS Trasmitter Index */
 80#define     NON_LVDS_TRANSMITTER    0x00
 81#define     VT1631_LVDS             0x01
 82#define     VT1636_LVDS             0x0E
 83#define     INTEGRATED_LVDS         0x41
 84
 85/* Definition Digital Transmitter Mode */
 86#define     TX_DATA_12_BITS         0x01
 87#define     TX_DATA_24_BITS         0x02
 88#define     TX_DATA_DDR_MODE        0x04
 89#define     TX_DATA_SDR_MODE        0x08
 90
 91/* Definition LVDS Trasmitter I2C Target Address */
 92#define     VT1631_LVDS_I2C_ADDR    0x70
 93#define     VT3271_LVDS_I2C_ADDR    0x80
 94#define     VT1636_LVDS_I2C_ADDR    0x80
 95
 96struct tmds_chip_information {
 97	int tmds_chip_name;
 98	int tmds_chip_target_addr;
 99	int output_interface;
100	int i2c_port;
101};
102
103struct lvds_chip_information {
104	int lvds_chip_name;
105	int lvds_chip_target_addr;
106	int output_interface;
107	int i2c_port;
108};
109
110/* The type of 2D engine */
111enum via_2d_engine {
112	VIA_2D_ENG_H2,
113	VIA_2D_ENG_H5,
114	VIA_2D_ENG_M1,
115};
116
117struct chip_information {
118	int gfx_chip_name;
119	int gfx_chip_revision;
120	enum via_2d_engine twod_engine;
121	struct tmds_chip_information tmds_chip_info;
122	struct lvds_chip_information lvds_chip_info;
123	struct lvds_chip_information lvds_chip_info2;
124};
125
126struct tmds_setting_information {
127	int iga_path;
128	int h_active;
129	int v_active;
130	int max_pixel_clock;
131};
132
133struct lvds_setting_information {
134	int iga_path;
135	int lcd_panel_hres;
136	int lcd_panel_vres;
137	int display_method;
138	int device_lcd_dualedge;
139	int LCDDithering;
140	int lcd_mode;
141	u32 vclk;		/*panel mode clock value */
142};
143
144struct GFX_DPA_SETTING {
145	int ClkRangeIndex;
146	u8 DVP0;		/* CR96[3:0] */
147	u8 DVP0DataDri_S1;	/* SR2A[5]   */
148	u8 DVP0DataDri_S;	/* SR1B[1]   */
149	u8 DVP0ClockDri_S1;	/* SR2A[4]   */
150	u8 DVP0ClockDri_S;	/* SR1E[2]   */
151	u8 DVP1;		/* CR9B[3:0] */
152	u8 DVP1Driving;		/* SR65[3:0], Data and Clock driving */
153	u8 DFPHigh;		/* CR97[3:0] */
154	u8 DFPLow;		/* CR99[3:0] */
155
156};
157
158struct VT1636_DPA_SETTING {
159	u8 CLK_SEL_ST1;
160	u8 CLK_SEL_ST2;
161};
162#endif /* __CHIP_H__ */