tdfxfb.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *
   4 * tdfxfb.c
   5 *
   6 * Author: Hannu Mallat <hmallat@cc.hut.fi>
   7 *
   8 * Copyright © 1999 Hannu Mallat
   9 * All rights reserved
  10 *
  11 * Created      : Thu Sep 23 18:17:43 1999, hmallat
  12 * Last modified: Tue Nov  2 21:19:47 1999, hmallat
  13 *
  14 * I2C part copied from the i2c-voodoo3.c driver by:
  15 * Frodo Looijaard <frodol@dds.nl>,
  16 * Philip Edelbrock <phil@netroedge.com>,
  17 * Ralph Metzler <rjkm@thp.uni-koeln.de>, and
  18 * Mark D. Studebaker <mdsxyz123@yahoo.com>
  19 *
  20 * Lots of the information here comes from the Daryll Strauss' Banshee
  21 * patches to the XF86 server, and the rest comes from the 3dfx
  22 * Banshee specification. I'm very much indebted to Daryll for his
  23 * work on the X server.
  24 *
  25 * Voodoo3 support was contributed Harold Oga. Lots of additions
  26 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
  27 * Kesmarki. Thanks guys!
  28 *
  29 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
  30 * behave very differently from the Voodoo3/4/5. For anyone wanting to
  31 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
  32 * located at http://www.sourceforge.net/projects/sstfb).
  33 *
  34 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
  35 * I do wish the next version is a bit more complete. Without the XF86
  36 * patches I couldn't have gotten even this far... for instance, the
  37 * extensions to the VGA register set go completely unmentioned in the
  38 * spec! Also, lots of references are made to the 'SST core', but no
  39 * spec is publicly available, AFAIK.
  40 *
  41 * The structure of this driver comes pretty much from the Permedia
  42 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
  43 *
  44 * TODO:
  45 * - multihead support (basically need to support an array of fb_infos)
  46 * - support other architectures (PPC, Alpha); does the fact that the VGA
  47 *   core can be accessed only thru I/O (not memory mapped) complicate
  48 *   things?
  49 *
  50 * Version history:
  51 *
  52 * 0.1.4 (released 2002-05-28)	ported over to new fbdev api by James Simmons
  53 *
  54 * 0.1.3 (released 1999-11-02)	added Attila's panning support, code
  55 *				reorg, hwcursor address page size alignment
  56 *				(for mmapping both frame buffer and regs),
  57 *				and my changes to get rid of hardcoded
  58 *				VGA i/o register locations (uses PCI
  59 *				configuration info now)
  60 * 0.1.2 (released 1999-10-19)	added Attila Kesmarki's bug fixes and
  61 *				improvements
  62 * 0.1.1 (released 1999-10-07)	added Voodoo3 support by Harold Oga.
  63 * 0.1.0 (released 1999-10-06)	initial version
  64 *
  65 */
  66
  67#include <linux/aperture.h>
  68#include <linux/module.h>
  69#include <linux/kernel.h>
  70#include <linux/errno.h>
  71#include <linux/string.h>
  72#include <linux/mm.h>
  73#include <linux/slab.h>
  74#include <linux/fb.h>
  75#include <linux/init.h>
  76#include <linux/pci.h>
  77#include <asm/io.h>
  78
  79#include <video/tdfx.h>
  80
  81#define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b)
  82
  83#define BANSHEE_MAX_PIXCLOCK 270000
  84#define VOODOO3_MAX_PIXCLOCK 300000
  85#define VOODOO5_MAX_PIXCLOCK 350000
  86
  87static const struct fb_fix_screeninfo tdfx_fix = {
  88	.type =		FB_TYPE_PACKED_PIXELS,
  89	.visual =	FB_VISUAL_PSEUDOCOLOR,
  90	.ypanstep =	1,
  91	.ywrapstep =	1,
  92	.accel =	FB_ACCEL_3DFX_BANSHEE
  93};
  94
  95static const struct fb_var_screeninfo tdfx_var = {
  96	/* "640x480, 8 bpp @ 60 Hz */
  97	.xres =		640,
  98	.yres =		480,
  99	.xres_virtual =	640,
 100	.yres_virtual =	1024,
 101	.bits_per_pixel = 8,
 102	.red =		{0, 8, 0},
 103	.blue =		{0, 8, 0},
 104	.green =	{0, 8, 0},
 105	.activate =	FB_ACTIVATE_NOW,
 106	.height =	-1,
 107	.width =	-1,
 108	.accel_flags =	FB_ACCELF_TEXT,
 109	.pixclock =	39722,
 110	.left_margin =	40,
 111	.right_margin =	24,
 112	.upper_margin =	32,
 113	.lower_margin =	11,
 114	.hsync_len =	96,
 115	.vsync_len =	2,
 116	.vmode =	FB_VMODE_NONINTERLACED
 117};
 118
 119/*
 120 * PCI driver prototypes
 121 */
 122static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id);
 123static void tdfxfb_remove(struct pci_dev *pdev);
 124
 125static const struct pci_device_id tdfxfb_id_table[] = {
 126	{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
 127	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 128	  0xff0000, 0 },
 129	{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
 130	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 131	  0xff0000, 0 },
 132	{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
 133	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 134	  0xff0000, 0 },
 135	{ 0, }
 136};
 137
 138static struct pci_driver tdfxfb_driver = {
 139	.name		= "tdfxfb",
 140	.id_table	= tdfxfb_id_table,
 141	.probe		= tdfxfb_probe,
 142	.remove		= tdfxfb_remove,
 143};
 144
 145MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
 146
 147/*
 148 * Driver data
 149 */
 150static int nopan;
 151static int nowrap = 1;      /* not implemented (yet) */
 152static int hwcursor = 1;
 153static char *mode_option;
 154static bool nomtrr;
 155
 156/* -------------------------------------------------------------------------
 157 *			Hardware-specific funcions
 158 * ------------------------------------------------------------------------- */
 159
 160static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
 161{
 162	return inb(par->iobase + reg - 0x300);
 163}
 164
 165static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
 166{
 167	outb(val, par->iobase + reg - 0x300);
 168}
 169
 170static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
 171{
 172	vga_outb(par, GRA_I, idx);
 173	wmb();
 174	vga_outb(par, GRA_D, val);
 175	wmb();
 176}
 177
 178static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
 179{
 180	vga_outb(par, SEQ_I, idx);
 181	wmb();
 182	vga_outb(par, SEQ_D, val);
 183	wmb();
 184}
 185
 186static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
 187{
 188	vga_outb(par, SEQ_I, idx);
 189	mb();
 190	return vga_inb(par, SEQ_D);
 191}
 192
 193static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
 194{
 195	vga_outb(par, CRT_I, idx);
 196	wmb();
 197	vga_outb(par, CRT_D, val);
 198	wmb();
 199}
 200
 201static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
 202{
 203	vga_outb(par, CRT_I, idx);
 204	mb();
 205	return vga_inb(par, CRT_D);
 206}
 207
 208static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
 209{
 210	vga_inb(par, IS1_R);
 211	vga_outb(par, ATT_IW, idx);
 212	vga_outb(par, ATT_IW, val);
 213}
 214
 215static inline void vga_disable_video(struct tdfx_par *par)
 216{
 217	unsigned char s;
 218
 219	s = seq_inb(par, 0x01) | 0x20;
 220	seq_outb(par, 0x00, 0x01);
 221	seq_outb(par, 0x01, s);
 222	seq_outb(par, 0x00, 0x03);
 223}
 224
 225static inline void vga_enable_video(struct tdfx_par *par)
 226{
 227	unsigned char s;
 228
 229	s = seq_inb(par, 0x01) & 0xdf;
 230	seq_outb(par, 0x00, 0x01);
 231	seq_outb(par, 0x01, s);
 232	seq_outb(par, 0x00, 0x03);
 233}
 234
 235static inline void vga_enable_palette(struct tdfx_par *par)
 236{
 237	vga_inb(par, IS1_R);
 238	mb();
 239	vga_outb(par, ATT_IW, 0x20);
 240}
 241
 242static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
 243{
 244	return readl(par->regbase_virt + reg);
 245}
 246
 247static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
 248{
 249	writel(val, par->regbase_virt + reg);
 250}
 251
 252static inline void banshee_make_room(struct tdfx_par *par, int size)
 253{
 254	/* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
 255	 * won't quit if you ask for more. */
 256	while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
 257		cpu_relax();
 258}
 259
 260static int banshee_wait_idle(struct fb_info *info)
 261{
 262	struct tdfx_par *par = info->par;
 263	int i = 0;
 264
 265	banshee_make_room(par, 1);
 266	tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
 267
 268	do {
 269		if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
 270			i++;
 271	} while (i < 3);
 272
 273	return 0;
 274}
 275
 276/*
 277 * Set the color of a palette entry in 8bpp mode
 278 */
 279static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
 280{
 281	banshee_make_room(par, 2);
 282	tdfx_outl(par, DACADDR, regno);
 283	/* read after write makes it working */
 284	tdfx_inl(par, DACADDR);
 285	tdfx_outl(par, DACDATA, c);
 286}
 287
 288static u32 do_calc_pll(int freq, int *freq_out)
 289{
 290	int m, n, k, best_m, best_n, best_k, best_error;
 291	int fref = 14318;
 292
 293	best_error = freq;
 294	best_n = best_m = best_k = 0;
 295
 296	for (k = 3; k >= 0; k--) {
 297		for (m = 63; m >= 0; m--) {
 298			/*
 299			 * Estimate value of n that produces target frequency
 300			 * with current m and k
 301			 */
 302			int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
 303
 304			/* Search neighborhood of estimated n */
 305			for (n = max(0, n_estimated);
 306				n <= min(255, n_estimated + 1);
 307				n++) {
 308				/*
 309				 * Calculate PLL freqency with current m, k and
 310				 * estimated n
 311				 */
 312				int f = (fref * (n + 2) / (m + 2)) >> k;
 313				int error = abs(f - freq);
 314
 315				/*
 316				 * If this is the closest we've come to the
 317				 * target frequency then remember n, m and k
 318				 */
 319				if (error < best_error) {
 320					best_error = error;
 321					best_n = n;
 322					best_m = m;
 323					best_k = k;
 324				}
 325			}
 326		}
 327	}
 328
 329	n = best_n;
 330	m = best_m;
 331	k = best_k;
 332	*freq_out = (fref * (n + 2) / (m + 2)) >> k;
 333
 334	return (n << 8) | (m << 2) | k;
 335}
 336
 337static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
 338{
 339	struct tdfx_par *par = info->par;
 340	int i;
 341
 342	banshee_wait_idle(info);
 343
 344	tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
 345
 346	crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
 347
 348	banshee_make_room(par, 3);
 349	tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
 350	tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
 351#if 0
 352	tdfx_outl(par, PLLCTRL1, reg->mempll);
 353	tdfx_outl(par, PLLCTRL2, reg->gfxpll);
 354#endif
 355	tdfx_outl(par, PLLCTRL0, reg->vidpll);
 356
 357	vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
 358
 359	for (i = 0; i < 5; i++)
 360		seq_outb(par, i, reg->seq[i]);
 361
 362	for (i = 0; i < 25; i++)
 363		crt_outb(par, i, reg->crt[i]);
 364
 365	for (i = 0; i < 9; i++)
 366		gra_outb(par, i, reg->gra[i]);
 367
 368	for (i = 0; i < 21; i++)
 369		att_outb(par, i, reg->att[i]);
 370
 371	crt_outb(par, 0x1a, reg->ext[0]);
 372	crt_outb(par, 0x1b, reg->ext[1]);
 373
 374	vga_enable_palette(par);
 375	vga_enable_video(par);
 376
 377	banshee_make_room(par, 9);
 378	tdfx_outl(par, VGAINIT0, reg->vgainit0);
 379	tdfx_outl(par, DACMODE, reg->dacmode);
 380	tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
 381	tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
 382
 383	tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
 384	tdfx_outl(par, VIDDESKSTART, reg->startaddr);
 385	tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
 386	tdfx_outl(par, VGAINIT1, reg->vgainit1);
 387	tdfx_outl(par, MISCINIT0, reg->miscinit0);
 388
 389	banshee_make_room(par, 8);
 390	tdfx_outl(par, SRCBASE, reg->startaddr);
 391	tdfx_outl(par, DSTBASE, reg->startaddr);
 392	tdfx_outl(par, COMMANDEXTRA_2D, 0);
 393	tdfx_outl(par, CLIP0MIN, 0);
 394	tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
 395	tdfx_outl(par, CLIP1MIN, 0);
 396	tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
 397	tdfx_outl(par, SRCXY, 0);
 398
 399	banshee_wait_idle(info);
 400}
 401
 402static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
 403{
 404	u32 draminit0 = tdfx_inl(par, DRAMINIT0);
 405	u32 draminit1 = tdfx_inl(par, DRAMINIT1);
 406	u32 miscinit1;
 407	int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
 408	int chip_size; /* in MB */
 409	int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
 410
 411	if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
 412		/* Banshee/Voodoo3 */
 413		chip_size = 2;
 414		if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE))
 415			chip_size = 1;
 416	} else {
 417		/* Voodoo4/5 */
 418		has_sgram = 0;
 419		chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
 420		chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
 421	}
 422
 423	/* disable block writes for SDRAM */
 424	miscinit1 = tdfx_inl(par, MISCINIT1);
 425	miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
 426	miscinit1 |= MISCINIT1_CLUT_INV;
 427
 428	banshee_make_room(par, 1);
 429	tdfx_outl(par, MISCINIT1, miscinit1);
 430	return num_chips * chip_size * 1024l * 1024;
 431}
 432
 433/* ------------------------------------------------------------------------- */
 434
 435static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 436{
 437	struct tdfx_par *par = info->par;
 438	u32 lpitch;
 439
 440	if (var->bits_per_pixel != 8  && var->bits_per_pixel != 16 &&
 441	    var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
 442		DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 443		return -EINVAL;
 444	}
 445
 446	if (var->xres != var->xres_virtual)
 447		var->xres_virtual = var->xres;
 448
 449	if (var->yres > var->yres_virtual)
 450		var->yres_virtual = var->yres;
 451
 452	if (var->xoffset) {
 453		DPRINTK("xoffset not supported\n");
 454		return -EINVAL;
 455	}
 456	var->yoffset = 0;
 457
 458	/*
 459	 * Banshee doesn't support interlace, but Voodoo4/5 and probably
 460	 * Voodoo3 do.
 461	 * no direct information about device id now?
 462	 *  use max_pixclock for this...
 463	 */
 464	if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
 465	    (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
 466		DPRINTK("interlace not supported\n");
 467		return -EINVAL;
 468	}
 469
 470	if (info->monspecs.hfmax && info->monspecs.vfmax &&
 471	    info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) {
 472		DPRINTK("mode outside monitor's specs\n");
 473		return -EINVAL;
 474	}
 475
 476	var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
 477	lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
 478
 479	if (var->xres < 320 || var->xres > 2048) {
 480		DPRINTK("width not supported: %u\n", var->xres);
 481		return -EINVAL;
 482	}
 483
 484	if (var->yres < 200 || var->yres > 2048) {
 485		DPRINTK("height not supported: %u\n", var->yres);
 486		return -EINVAL;
 487	}
 488
 489	if (lpitch * var->yres_virtual > info->fix.smem_len) {
 490		var->yres_virtual = info->fix.smem_len / lpitch;
 491		if (var->yres_virtual < var->yres) {
 492			DPRINTK("no memory for screen (%ux%ux%u)\n",
 493				var->xres, var->yres_virtual,
 494				var->bits_per_pixel);
 495			return -EINVAL;
 496		}
 497	}
 498
 499	if (!var->pixclock)
 500		return -EINVAL;
 501
 502	if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
 503		DPRINTK("pixclock too high (%ldKHz)\n",
 504			PICOS2KHZ(var->pixclock));
 505		return -EINVAL;
 506	}
 507
 508	var->transp.offset = 0;
 509	var->transp.length = 0;
 510	switch (var->bits_per_pixel) {
 511	case 8:
 512		var->red.length = 8;
 513		var->red.offset = 0;
 514		var->green = var->red;
 515		var->blue = var->red;
 516		break;
 517	case 16:
 518		var->red.offset   = 11;
 519		var->red.length   = 5;
 520		var->green.offset = 5;
 521		var->green.length = 6;
 522		var->blue.offset  = 0;
 523		var->blue.length  = 5;
 524		break;
 525	case 32:
 526		var->transp.offset = 24;
 527		var->transp.length = 8;
 528		fallthrough;
 529	case 24:
 530		var->red.offset = 16;
 531		var->green.offset = 8;
 532		var->blue.offset = 0;
 533		var->red.length = var->green.length = var->blue.length = 8;
 534		break;
 535	}
 536	var->width = -1;
 537	var->height = -1;
 538
 539	var->accel_flags = FB_ACCELF_TEXT;
 540
 541	DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 542		var->xres, var->yres, var->bits_per_pixel);
 543	return 0;
 544}
 545
 546static int tdfxfb_set_par(struct fb_info *info)
 547{
 548	struct tdfx_par *par = info->par;
 549	u32 hdispend = info->var.xres;
 550	u32 hsyncsta = hdispend + info->var.right_margin;
 551	u32 hsyncend = hsyncsta + info->var.hsync_len;
 552	u32 htotal   = hsyncend + info->var.left_margin;
 553	u32 hd, hs, he, ht, hbs, hbe;
 554	u32 vd, vs, ve, vt, vbs, vbe;
 555	struct banshee_reg reg;
 556	int fout, freq;
 557	u32 wd;
 558	u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
 559
 560	memset(&reg, 0, sizeof(reg));
 561
 562	reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
 563		     VIDCFG_CURS_X11 |
 564		     ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) |
 565		     (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
 566
 567	/* PLL settings */
 568	freq = PICOS2KHZ(info->var.pixclock);
 569
 570	reg.vidcfg &= ~VIDCFG_2X;
 571
 572	if (freq > par->max_pixclock / 2) {
 573		freq = freq > par->max_pixclock ? par->max_pixclock : freq;
 574		reg.dacmode |= DACMODE_2X;
 575		reg.vidcfg  |= VIDCFG_2X;
 576		hdispend >>= 1;
 577		hsyncsta >>= 1;
 578		hsyncend >>= 1;
 579		htotal   >>= 1;
 580	}
 581
 582	wd = (hdispend >> 3) - 1;
 583	hd  = wd;
 584	hs  = (hsyncsta >> 3) - 1;
 585	he  = (hsyncend >> 3) - 1;
 586	ht  = (htotal >> 3) - 1;
 587	hbs = hd;
 588	hbe = ht;
 589
 590	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
 591		vd = (info->var.yres << 1) - 1;
 592		vs  = vd + (info->var.lower_margin << 1);
 593		ve  = vs + (info->var.vsync_len << 1);
 594		vt = ve + (info->var.upper_margin << 1) - 1;
 595		reg.screensize = info->var.xres | (info->var.yres << 13);
 596		reg.vidcfg |= VIDCFG_HALF_MODE;
 597		reg.crt[0x09] = 0x80;
 598	} else {
 599		vd = info->var.yres - 1;
 600		vs  = vd + info->var.lower_margin;
 601		ve  = vs + info->var.vsync_len;
 602		vt = ve + info->var.upper_margin - 1;
 603		reg.screensize = info->var.xres | (info->var.yres << 12);
 604		reg.vidcfg &= ~VIDCFG_HALF_MODE;
 605	}
 606	vbs = vd;
 607	vbe = vt;
 608
 609	/* this is all pretty standard VGA register stuffing */
 610	reg.misc[0x00] = 0x0f |
 611			(info->var.xres < 400 ? 0xa0 :
 612			 info->var.xres < 480 ? 0x60 :
 613			 info->var.xres < 768 ? 0xe0 : 0x20);
 614
 615	reg.gra[0x05] = 0x40;
 616	reg.gra[0x06] = 0x05;
 617	reg.gra[0x07] = 0x0f;
 618	reg.gra[0x08] = 0xff;
 619
 620	reg.att[0x00] = 0x00;
 621	reg.att[0x01] = 0x01;
 622	reg.att[0x02] = 0x02;
 623	reg.att[0x03] = 0x03;
 624	reg.att[0x04] = 0x04;
 625	reg.att[0x05] = 0x05;
 626	reg.att[0x06] = 0x06;
 627	reg.att[0x07] = 0x07;
 628	reg.att[0x08] = 0x08;
 629	reg.att[0x09] = 0x09;
 630	reg.att[0x0a] = 0x0a;
 631	reg.att[0x0b] = 0x0b;
 632	reg.att[0x0c] = 0x0c;
 633	reg.att[0x0d] = 0x0d;
 634	reg.att[0x0e] = 0x0e;
 635	reg.att[0x0f] = 0x0f;
 636	reg.att[0x10] = 0x41;
 637	reg.att[0x12] = 0x0f;
 638
 639	reg.seq[0x00] = 0x03;
 640	reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
 641	reg.seq[0x02] = 0x0f;
 642	reg.seq[0x03] = 0x00;
 643	reg.seq[0x04] = 0x0e;
 644
 645	reg.crt[0x00] = ht - 4;
 646	reg.crt[0x01] = hd;
 647	reg.crt[0x02] = hbs;
 648	reg.crt[0x03] = 0x80 | (hbe & 0x1f);
 649	reg.crt[0x04] = hs;
 650	reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
 651	reg.crt[0x06] = vt;
 652	reg.crt[0x07] = ((vs & 0x200) >> 2) |
 653			((vd & 0x200) >> 3) |
 654			((vt & 0x200) >> 4) | 0x10 |
 655			((vbs & 0x100) >> 5) |
 656			((vs & 0x100) >> 6) |
 657			((vd & 0x100) >> 7) |
 658			((vt & 0x100) >> 8);
 659	reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
 660	reg.crt[0x10] = vs;
 661	reg.crt[0x11] = (ve & 0x0f) | 0x20;
 662	reg.crt[0x12] = vd;
 663	reg.crt[0x13] = wd;
 664	reg.crt[0x15] = vbs;
 665	reg.crt[0x16] = vbe + 1;
 666	reg.crt[0x17] = 0xc3;
 667	reg.crt[0x18] = 0xff;
 668
 669	/* Banshee's nonvga stuff */
 670	reg.ext[0x00] = (((ht & 0x100) >> 8) |
 671			((hd & 0x100) >> 6) |
 672			((hbs & 0x100) >> 4) |
 673			((hbe & 0x40) >> 1) |
 674			((hs & 0x100) >> 2) |
 675			((he & 0x20) << 2));
 676	reg.ext[0x01] = (((vt & 0x400) >> 10) |
 677			((vd & 0x400) >> 8) |
 678			((vbs & 0x400) >> 6) |
 679			((vbe & 0x400) >> 4));
 680
 681	reg.vgainit0 =	VGAINIT0_8BIT_DAC     |
 682			VGAINIT0_EXT_ENABLE   |
 683			VGAINIT0_WAKEUP_3C3   |
 684			VGAINIT0_ALT_READBACK |
 685			VGAINIT0_EXTSHIFTOUT;
 686	reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
 687
 688	if (hwcursor)
 689		reg.curspataddr = info->fix.smem_len;
 690
 691	reg.cursloc   = 0;
 692
 693	reg.cursc0    = 0;
 694	reg.cursc1    = 0xffffff;
 695
 696	reg.stride    = info->var.xres * cpp;
 697	reg.startaddr = info->var.yoffset * reg.stride
 698			+ info->var.xoffset * cpp;
 699
 700	reg.vidpll = do_calc_pll(freq, &fout);
 701#if 0
 702	reg.mempll = do_calc_pll(..., &fout);
 703	reg.gfxpll = do_calc_pll(..., &fout);
 704#endif
 705
 706	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
 707		reg.vidcfg |= VIDCFG_INTERLACE;
 708	reg.miscinit0 = tdfx_inl(par, MISCINIT0);
 709
 710#if defined(__BIG_ENDIAN)
 711	switch (info->var.bits_per_pixel) {
 712	case 8:
 713	case 24:
 714		reg.miscinit0 &= ~(1 << 30);
 715		reg.miscinit0 &= ~(1 << 31);
 716		break;
 717	case 16:
 718		reg.miscinit0 |= (1 << 30);
 719		reg.miscinit0 |= (1 << 31);
 720		break;
 721	case 32:
 722		reg.miscinit0 |= (1 << 30);
 723		reg.miscinit0 &= ~(1 << 31);
 724		break;
 725	}
 726#endif
 727	do_write_regs(info, &reg);
 728
 729	/* Now change fb_fix_screeninfo according to changes in par */
 730	info->fix.line_length = reg.stride;
 731	info->fix.visual = (info->var.bits_per_pixel == 8)
 732				? FB_VISUAL_PSEUDOCOLOR
 733				: FB_VISUAL_TRUECOLOR;
 734	DPRINTK("Graphics mode is now set at %dx%d depth %d\n",
 735		info->var.xres, info->var.yres, info->var.bits_per_pixel);
 736	return 0;
 737}
 738
 739/* A handy macro shamelessly pinched from matroxfb */
 740#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
 741
 742static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 743			    unsigned blue, unsigned transp,
 744			    struct fb_info *info)
 745{
 746	struct tdfx_par *par = info->par;
 747	u32 rgbcol;
 748
 749	if (regno >= info->cmap.len || regno > 255)
 750		return 1;
 751
 752	/* grayscale works only partially under directcolor */
 753	if (info->var.grayscale) {
 754		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
 755		blue = (red * 77 + green * 151 + blue * 28) >> 8;
 756		green = blue;
 757		red = blue;
 758	}
 759
 760	switch (info->fix.visual) {
 761	case FB_VISUAL_PSEUDOCOLOR:
 762		rgbcol = (((u32)red   & 0xff00) << 8) |
 763			 (((u32)green & 0xff00) << 0) |
 764			 (((u32)blue  & 0xff00) >> 8);
 765		do_setpalentry(par, regno, rgbcol);
 766		break;
 767	/* Truecolor has no hardware color palettes. */
 768	case FB_VISUAL_TRUECOLOR:
 769		if (regno < 16) {
 770			rgbcol = (CNVT_TOHW(red, info->var.red.length) <<
 771				  info->var.red.offset) |
 772				(CNVT_TOHW(green, info->var.green.length) <<
 773				 info->var.green.offset) |
 774				(CNVT_TOHW(blue, info->var.blue.length) <<
 775				 info->var.blue.offset) |
 776				(CNVT_TOHW(transp, info->var.transp.length) <<
 777				 info->var.transp.offset);
 778			par->palette[regno] = rgbcol;
 779		}
 780
 781		break;
 782	default:
 783		DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
 784		break;
 785	}
 786
 787	return 0;
 788}
 789
 790/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
 791static int tdfxfb_blank(int blank, struct fb_info *info)
 792{
 793	struct tdfx_par *par = info->par;
 794	int vgablank = 1;
 795	u32 dacmode = tdfx_inl(par, DACMODE);
 796
 797	dacmode &= ~(BIT(1) | BIT(3));
 798
 799	switch (blank) {
 800	case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
 801		vgablank = 0;
 802		break;
 803	case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
 804		break;
 805	case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
 806		dacmode |= BIT(3);
 807		break;
 808	case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
 809		dacmode |= BIT(1);
 810		break;
 811	case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
 812		dacmode |= BIT(1) | BIT(3);
 813		break;
 814	}
 815
 816	banshee_make_room(par, 1);
 817	tdfx_outl(par, DACMODE, dacmode);
 818	if (vgablank)
 819		vga_disable_video(par);
 820	else
 821		vga_enable_video(par);
 822	return 0;
 823}
 824
 825/*
 826 * Set the starting position of the visible screen to var->yoffset
 827 */
 828static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
 829			      struct fb_info *info)
 830{
 831	struct tdfx_par *par = info->par;
 832	u32 addr = var->yoffset * info->fix.line_length;
 833
 834	if (nopan || var->xoffset)
 835		return -EINVAL;
 836
 837	banshee_make_room(par, 1);
 838	tdfx_outl(par, VIDDESKSTART, addr);
 839
 840	return 0;
 841}
 842
 843#ifdef CONFIG_FB_3DFX_ACCEL
 844/*
 845 * FillRect 2D command (solidfill or invert (via ROP_XOR))
 846 */
 847static void tdfxfb_fillrect(struct fb_info *info,
 848			    const struct fb_fillrect *rect)
 849{
 850	struct tdfx_par *par = info->par;
 851	u32 bpp = info->var.bits_per_pixel;
 852	u32 stride = info->fix.line_length;
 853	u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 854	int tdfx_rop;
 855	u32 dx = rect->dx;
 856	u32 dy = rect->dy;
 857	u32 dstbase = 0;
 858
 859	if (rect->rop == ROP_COPY)
 860		tdfx_rop = TDFX_ROP_COPY;
 861	else
 862		tdfx_rop = TDFX_ROP_XOR;
 863
 864	/* assume always rect->height < 4096 */
 865	if (dy + rect->height > 4095) {
 866		dstbase = stride * dy;
 867		dy = 0;
 868	}
 869	/* assume always rect->width < 4096 */
 870	if (dx + rect->width > 4095) {
 871		dstbase += dx * bpp >> 3;
 872		dx = 0;
 873	}
 874	banshee_make_room(par, 6);
 875	tdfx_outl(par, DSTFORMAT, fmt);
 876	if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
 877		tdfx_outl(par, COLORFORE, rect->color);
 878	} else { /* FB_VISUAL_TRUECOLOR */
 879		tdfx_outl(par, COLORFORE, par->palette[rect->color]);
 880	}
 881	tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
 882	tdfx_outl(par, DSTBASE, dstbase);
 883	tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
 884	tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
 885}
 886
 887/*
 888 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
 889 */
 890static void tdfxfb_copyarea(struct fb_info *info,
 891			    const struct fb_copyarea *area)
 892{
 893	struct tdfx_par *par = info->par;
 894	u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
 895	u32 bpp = info->var.bits_per_pixel;
 896	u32 stride = info->fix.line_length;
 897	u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
 898	u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 899	u32 dstbase = 0;
 900	u32 srcbase = 0;
 901
 902	/* assume always area->height < 4096 */
 903	if (sy + area->height > 4095) {
 904		srcbase = stride * sy;
 905		sy = 0;
 906	}
 907	/* assume always area->width < 4096 */
 908	if (sx + area->width > 4095) {
 909		srcbase += sx * bpp >> 3;
 910		sx = 0;
 911	}
 912	/* assume always area->height < 4096 */
 913	if (dy + area->height > 4095) {
 914		dstbase = stride * dy;
 915		dy = 0;
 916	}
 917	/* assume always area->width < 4096 */
 918	if (dx + area->width > 4095) {
 919		dstbase += dx * bpp >> 3;
 920		dx = 0;
 921	}
 922
 923	if (area->sx <= area->dx) {
 924		/* -X */
 925		blitcmd |= BIT(14);
 926		sx += area->width - 1;
 927		dx += area->width - 1;
 928	}
 929	if (area->sy <= area->dy) {
 930		/* -Y */
 931		blitcmd |= BIT(15);
 932		sy += area->height - 1;
 933		dy += area->height - 1;
 934	}
 935
 936	banshee_make_room(par, 8);
 937
 938	tdfx_outl(par, SRCFORMAT, fmt);
 939	tdfx_outl(par, DSTFORMAT, fmt);
 940	tdfx_outl(par, COMMAND_2D, blitcmd);
 941	tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
 942	tdfx_outl(par, DSTXY, dx | (dy << 16));
 943	tdfx_outl(par, SRCBASE, srcbase);
 944	tdfx_outl(par, DSTBASE, dstbase);
 945	tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
 946}
 947
 948static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
 949{
 950	struct tdfx_par *par = info->par;
 951	int size = image->height * ((image->width * image->depth + 7) >> 3);
 952	int fifo_free;
 953	int i, stride = info->fix.line_length;
 954	u32 bpp = info->var.bits_per_pixel;
 955	u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 956	u8 *chardata = (u8 *) image->data;
 957	u32 srcfmt;
 958	u32 dx = image->dx;
 959	u32 dy = image->dy;
 960	u32 dstbase = 0;
 961
 962	if (image->depth != 1) {
 963#ifdef BROKEN_CODE
 964		banshee_make_room(par, 6 + ((size + 3) >> 2));
 965		srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) |
 966			0x400000;
 967#else
 968		cfb_imageblit(info, image);
 969#endif
 970		return;
 971	}
 972	banshee_make_room(par, 9);
 973	switch (info->fix.visual) {
 974	case FB_VISUAL_PSEUDOCOLOR:
 975		tdfx_outl(par, COLORFORE, image->fg_color);
 976		tdfx_outl(par, COLORBACK, image->bg_color);
 977		break;
 978	case FB_VISUAL_TRUECOLOR:
 979	default:
 980		tdfx_outl(par, COLORFORE,
 981			  par->palette[image->fg_color]);
 982		tdfx_outl(par, COLORBACK,
 983			  par->palette[image->bg_color]);
 984	}
 985#ifdef __BIG_ENDIAN
 986	srcfmt = 0x400000 | BIT(20);
 987#else
 988	srcfmt = 0x400000;
 989#endif
 990	/* assume always image->height < 4096 */
 991	if (dy + image->height > 4095) {
 992		dstbase = stride * dy;
 993		dy = 0;
 994	}
 995	/* assume always image->width < 4096 */
 996	if (dx + image->width > 4095) {
 997		dstbase += dx * bpp >> 3;
 998		dx = 0;
 999	}
1000
1001	tdfx_outl(par, DSTBASE, dstbase);
1002	tdfx_outl(par, SRCXY, 0);
1003	tdfx_outl(par, DSTXY, dx | (dy << 16));
1004	tdfx_outl(par, COMMAND_2D,
1005		  COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
1006	tdfx_outl(par, SRCFORMAT, srcfmt);
1007	tdfx_outl(par, DSTFORMAT, dstfmt);
1008	tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1009
1010	/* A count of how many free FIFO entries we've requested.
1011	 * When this goes negative, we need to request more. */
1012	fifo_free = 0;
1013
1014	/* Send four bytes at a time of data */
1015	for (i = (size >> 2); i > 0; i--) {
1016		if (--fifo_free < 0) {
1017			fifo_free = 31;
1018			banshee_make_room(par, fifo_free);
1019		}
1020		tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
1021		chardata += 4;
1022	}
1023
1024	/* Send the leftovers now */
1025	banshee_make_room(par, 3);
1026	switch (size % 4) {
1027	case 0:
1028		break;
1029	case 1:
1030		tdfx_outl(par, LAUNCH_2D, *chardata);
1031		break;
1032	case 2:
1033		tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
1034		break;
1035	case 3:
1036		tdfx_outl(par, LAUNCH_2D,
1037			*(u16 *)chardata | (chardata[3] << 24));
1038		break;
1039	}
1040}
1041#endif /* CONFIG_FB_3DFX_ACCEL */
1042
1043static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1044{
1045	struct tdfx_par *par = info->par;
1046	u32 vidcfg;
1047
1048	if (!hwcursor)
1049		return -EINVAL;	/* just to force soft_cursor() call */
1050
1051	/* Too large of a cursor or wrong bpp :-( */
1052	if (cursor->image.width > 64 ||
1053	    cursor->image.height > 64 ||
1054	    cursor->image.depth > 1)
1055		return -EINVAL;
1056
1057	vidcfg = tdfx_inl(par, VIDPROCCFG);
1058	if (cursor->enable)
1059		tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
1060	else
1061		tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
1062
1063	/*
1064	 * If the cursor is not be changed this means either we want the
1065	 * current cursor state (if enable is set) or we want to query what
1066	 * we can do with the cursor (if enable is not set)
1067	 */
1068	if (!cursor->set)
1069		return 0;
1070
1071	/* fix cursor color - XFree86 forgets to restore it properly */
1072	if (cursor->set & FB_CUR_SETCMAP) {
1073		struct fb_cmap cmap = info->cmap;
1074		u32 bg_idx = cursor->image.bg_color;
1075		u32 fg_idx = cursor->image.fg_color;
1076		unsigned long bg_color, fg_color;
1077
1078		fg_color = (((u32)cmap.red[fg_idx]   & 0xff00) << 8) |
1079			   (((u32)cmap.green[fg_idx] & 0xff00) << 0) |
1080			   (((u32)cmap.blue[fg_idx]  & 0xff00) >> 8);
1081		bg_color = (((u32)cmap.red[bg_idx]   & 0xff00) << 8) |
1082			   (((u32)cmap.green[bg_idx] & 0xff00) << 0) |
1083			   (((u32)cmap.blue[bg_idx]  & 0xff00) >> 8);
1084		banshee_make_room(par, 2);
1085		tdfx_outl(par, HWCURC0, bg_color);
1086		tdfx_outl(par, HWCURC1, fg_color);
1087	}
1088
1089	if (cursor->set & FB_CUR_SETPOS) {
1090		int x = cursor->image.dx;
1091		int y = cursor->image.dy - info->var.yoffset;
1092
1093		x += 63;
1094		y += 63;
1095		banshee_make_room(par, 1);
1096		tdfx_outl(par, HWCURLOC, (y << 16) + x);
1097	}
1098	if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
1099		/*
1100		 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1101		 *    The reason is so the card can fetch 8 words at a time
1102		 * and are stored on chip for use for the next 8 scanlines.
1103		 * This reduces the number of times for access to draw the
1104		 * cursor for each screen refresh.
1105		 *    Each pattern is a bitmap of 64 bit wide and 64 bit high
1106		 * (total of 8192 bits or 1024 bytes). The two patterns are
1107		 * stored in such a way that pattern 0 always resides in the
1108		 * lower half (least significant 64 bits) of a 128 bit word
1109		 * and pattern 1 the upper half. If you examine the data of
1110		 * the cursor image the graphics card uses then from the
1111		 * beginning you see line one of pattern 0, line one of
1112		 * pattern 1, line two of pattern 0, line two of pattern 1,
1113		 * etc etc. The linear stride for the cursor is always 16 bytes
1114		 * (128 bits) which is the maximum cursor width times two for
1115		 * the two monochrome patterns.
1116		 */
1117		u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len;
1118		u8 *bitmap = (u8 *)cursor->image.data;
1119		u8 *mask = (u8 *)cursor->mask;
1120		int i;
1121
1122		fb_memset_io(cursorbase, 0, 1024);
1123
1124		for (i = 0; i < cursor->image.height; i++) {
1125			int h = 0;
1126			int j = (cursor->image.width + 7) >> 3;
1127
1128			for (; j > 0; j--) {
1129				u8 data = *mask ^ *bitmap;
1130				if (cursor->rop == ROP_COPY)
1131					data = *mask & *bitmap;
1132				/* Pattern 0. Copy the cursor mask to it */
1133				fb_writeb(*mask, cursorbase + h);
1134				mask++;
1135				/* Pattern 1. Copy the cursor bitmap to it */
1136				fb_writeb(data, cursorbase + h + 8);
1137				bitmap++;
1138				h++;
1139			}
1140			cursorbase += 16;
1141		}
1142	}
1143	return 0;
1144}
1145
1146static const struct fb_ops tdfxfb_ops = {
1147	.owner		= THIS_MODULE,
1148	__FB_DEFAULT_IOMEM_OPS_RDWR,
1149	.fb_check_var	= tdfxfb_check_var,
1150	.fb_set_par	= tdfxfb_set_par,
1151	.fb_setcolreg	= tdfxfb_setcolreg,
1152	.fb_blank	= tdfxfb_blank,
1153	.fb_pan_display	= tdfxfb_pan_display,
1154	.fb_sync	= banshee_wait_idle,
1155	.fb_cursor	= tdfxfb_cursor,
1156#ifdef CONFIG_FB_3DFX_ACCEL
1157	.fb_fillrect	= tdfxfb_fillrect,
1158	.fb_copyarea	= tdfxfb_copyarea,
1159	.fb_imageblit	= tdfxfb_imageblit,
1160#else
1161	__FB_DEFAULT_IOMEM_OPS_DRAW,
1162#endif
1163	__FB_DEFAULT_IOMEM_OPS_MMAP,
1164};
1165
1166#ifdef CONFIG_FB_3DFX_I2C
1167/* The voo GPIO registers don't have individual masks for each bit
1168   so we always have to read before writing. */
1169
1170static void tdfxfb_i2c_setscl(void *data, int val)
1171{
1172	struct tdfxfb_i2c_chan 	*chan = data;
1173	struct tdfx_par 	*par = chan->par;
1174	unsigned int r;
1175
1176	r = tdfx_inl(par, VIDSERPARPORT);
1177	if (val)
1178		r |= I2C_SCL_OUT;
1179	else
1180		r &= ~I2C_SCL_OUT;
1181	tdfx_outl(par, VIDSERPARPORT, r);
1182	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1183}
1184
1185static void tdfxfb_i2c_setsda(void *data, int val)
1186{
1187	struct tdfxfb_i2c_chan 	*chan = data;
1188	struct tdfx_par 	*par = chan->par;
1189	unsigned int r;
1190
1191	r = tdfx_inl(par, VIDSERPARPORT);
1192	if (val)
1193		r |= I2C_SDA_OUT;
1194	else
1195		r &= ~I2C_SDA_OUT;
1196	tdfx_outl(par, VIDSERPARPORT, r);
1197	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1198}
1199
1200/* The GPIO pins are open drain, so the pins always remain outputs.
1201   We rely on the i2c-algo-bit routines to set the pins high before
1202   reading the input from other chips. */
1203
1204static int tdfxfb_i2c_getscl(void *data)
1205{
1206	struct tdfxfb_i2c_chan 	*chan = data;
1207	struct tdfx_par 	*par = chan->par;
1208
1209	return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
1210}
1211
1212static int tdfxfb_i2c_getsda(void *data)
1213{
1214	struct tdfxfb_i2c_chan 	*chan = data;
1215	struct tdfx_par 	*par = chan->par;
1216
1217	return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
1218}
1219
1220static void tdfxfb_ddc_setscl(void *data, int val)
1221{
1222	struct tdfxfb_i2c_chan 	*chan = data;
1223	struct tdfx_par 	*par = chan->par;
1224	unsigned int r;
1225
1226	r = tdfx_inl(par, VIDSERPARPORT);
1227	if (val)
1228		r |= DDC_SCL_OUT;
1229	else
1230		r &= ~DDC_SCL_OUT;
1231	tdfx_outl(par, VIDSERPARPORT, r);
1232	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1233}
1234
1235static void tdfxfb_ddc_setsda(void *data, int val)
1236{
1237	struct tdfxfb_i2c_chan 	*chan = data;
1238	struct tdfx_par 	*par = chan->par;
1239	unsigned int r;
1240
1241	r = tdfx_inl(par, VIDSERPARPORT);
1242	if (val)
1243		r |= DDC_SDA_OUT;
1244	else
1245		r &= ~DDC_SDA_OUT;
1246	tdfx_outl(par, VIDSERPARPORT, r);
1247	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1248}
1249
1250static int tdfxfb_ddc_getscl(void *data)
1251{
1252	struct tdfxfb_i2c_chan 	*chan = data;
1253	struct tdfx_par 	*par = chan->par;
1254
1255	return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
1256}
1257
1258static int tdfxfb_ddc_getsda(void *data)
1259{
1260	struct tdfxfb_i2c_chan 	*chan = data;
1261	struct tdfx_par 	*par = chan->par;
1262
1263	return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
1264}
1265
1266static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name,
1267				struct device *dev)
1268{
1269	int rc;
1270
1271	strscpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1272	chan->adapter.owner		= THIS_MODULE;
1273	chan->adapter.algo_data		= &chan->algo;
1274	chan->adapter.dev.parent	= dev;
1275	chan->algo.setsda		= tdfxfb_ddc_setsda;
1276	chan->algo.setscl		= tdfxfb_ddc_setscl;
1277	chan->algo.getsda		= tdfxfb_ddc_getsda;
1278	chan->algo.getscl		= tdfxfb_ddc_getscl;
1279	chan->algo.udelay		= 10;
1280	chan->algo.timeout		= msecs_to_jiffies(500);
1281	chan->algo.data 		= chan;
1282
1283	i2c_set_adapdata(&chan->adapter, chan);
1284
1285	rc = i2c_bit_add_bus(&chan->adapter);
1286	if (rc == 0)
1287		DPRINTK("I2C bus %s registered.\n", name);
1288	else
1289		chan->par = NULL;
1290
1291	return rc;
1292}
1293
1294static int tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, const char *name,
1295				struct device *dev)
1296{
1297	int rc;
1298
1299	strscpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1300	chan->adapter.owner		= THIS_MODULE;
1301	chan->adapter.algo_data		= &chan->algo;
1302	chan->adapter.dev.parent	= dev;
1303	chan->algo.setsda		= tdfxfb_i2c_setsda;
1304	chan->algo.setscl		= tdfxfb_i2c_setscl;
1305	chan->algo.getsda		= tdfxfb_i2c_getsda;
1306	chan->algo.getscl		= tdfxfb_i2c_getscl;
1307	chan->algo.udelay		= 10;
1308	chan->algo.timeout		= msecs_to_jiffies(500);
1309	chan->algo.data 		= chan;
1310
1311	i2c_set_adapdata(&chan->adapter, chan);
1312
1313	rc = i2c_bit_add_bus(&chan->adapter);
1314	if (rc == 0)
1315		DPRINTK("I2C bus %s registered.\n", name);
1316	else
1317		chan->par = NULL;
1318
1319	return rc;
1320}
1321
1322static void tdfxfb_create_i2c_busses(struct fb_info *info)
1323{
1324	struct tdfx_par *par = info->par;
1325
1326	tdfx_outl(par, VIDINFORMAT, 0x8160);
1327	tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
1328
1329	par->chan[0].par = par;
1330	par->chan[1].par = par;
1331
1332	tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->device);
1333	tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->device);
1334}
1335
1336static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
1337{
1338	if (par->chan[0].par)
1339		i2c_del_adapter(&par->chan[0].adapter);
1340	par->chan[0].par = NULL;
1341
1342	if (par->chan[1].par)
1343		i2c_del_adapter(&par->chan[1].adapter);
1344	par->chan[1].par = NULL;
1345}
1346
1347static int tdfxfb_probe_i2c_connector(struct tdfx_par *par,
1348				      struct fb_monspecs *specs)
1349{
1350	u8 *edid = NULL;
1351
1352	DPRINTK("Probe DDC Bus\n");
1353	if (par->chan[0].par)
1354		edid = fb_ddc_read(&par->chan[0].adapter);
1355
1356	if (edid) {
1357		fb_edid_to_monspecs(edid, specs);
1358		kfree(edid);
1359		return 0;
1360	}
1361	return 1;
1362}
1363#endif /* CONFIG_FB_3DFX_I2C */
1364
1365/**
1366 *      tdfxfb_probe - Device Initializiation
1367 *
1368 *      @pdev:  PCI Device to initialize
1369 *      @id:    PCI Device ID
1370 *
1371 *      Initializes and allocates resources for PCI device @pdev.
1372 *
1373 */
1374static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1375{
1376	struct tdfx_par *default_par;
1377	struct fb_info *info;
1378	int err, lpitch;
1379	struct fb_monspecs *specs;
1380	bool found;
1381
1382	err = aperture_remove_conflicting_pci_devices(pdev, "tdfxfb");
1383	if (err)
1384		return err;
1385
1386	err = pci_enable_device(pdev);
1387	if (err) {
1388		printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err);
1389		return err;
1390	}
1391
1392	info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
1393
1394	if (!info)
1395		return -ENOMEM;
1396
1397	default_par = info->par;
1398	info->fix = tdfx_fix;
1399
1400	/* Configure the default fb_fix_screeninfo first */
1401	switch (pdev->device) {
1402	case PCI_DEVICE_ID_3DFX_BANSHEE:
1403		strcpy(info->fix.id, "3Dfx Banshee");
1404		default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1405		break;
1406	case PCI_DEVICE_ID_3DFX_VOODOO3:
1407		strcpy(info->fix.id, "3Dfx Voodoo3");
1408		default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1409		break;
1410	case PCI_DEVICE_ID_3DFX_VOODOO5:
1411		strcpy(info->fix.id, "3Dfx Voodoo5");
1412		default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1413		break;
1414	}
1415
1416	info->fix.mmio_start = pci_resource_start(pdev, 0);
1417	info->fix.mmio_len = pci_resource_len(pdev, 0);
1418	if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len,
1419				"tdfx regbase")) {
1420		printk(KERN_ERR "tdfxfb: Can't reserve regbase\n");
1421		goto out_err;
1422	}
1423
1424	default_par->regbase_virt =
1425		ioremap(info->fix.mmio_start, info->fix.mmio_len);
1426	if (!default_par->regbase_virt) {
1427		printk(KERN_ERR "fb: Can't remap %s register area.\n",
1428				info->fix.id);
1429		goto out_err_regbase;
1430	}
1431
1432	info->fix.smem_start = pci_resource_start(pdev, 1);
1433	info->fix.smem_len = do_lfb_size(default_par, pdev->device);
1434	if (!info->fix.smem_len) {
1435		printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id);
1436		goto out_err_regbase;
1437	}
1438
1439	if (!request_mem_region(info->fix.smem_start,
1440				pci_resource_len(pdev, 1), "tdfx smem")) {
1441		printk(KERN_ERR "tdfxfb: Can't reserve smem\n");
1442		goto out_err_regbase;
1443	}
1444
1445	info->screen_base = ioremap_wc(info->fix.smem_start,
1446				       info->fix.smem_len);
1447	if (!info->screen_base) {
1448		printk(KERN_ERR "fb: Can't remap %s framebuffer.\n",
1449				info->fix.id);
1450		goto out_err_screenbase;
1451	}
1452
1453	default_par->iobase = pci_resource_start(pdev, 2);
1454
1455	if (!request_region(pci_resource_start(pdev, 2),
1456			    pci_resource_len(pdev, 2), "tdfx iobase")) {
1457		printk(KERN_ERR "tdfxfb: Can't reserve iobase\n");
1458		goto out_err_screenbase;
1459	}
1460
1461	printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id,
1462			info->fix.smem_len >> 10);
1463
1464	if (!nomtrr)
1465		default_par->wc_cookie= arch_phys_wc_add(info->fix.smem_start,
1466							 info->fix.smem_len);
1467
1468	info->fix.ypanstep	= nopan ? 0 : 1;
1469	info->fix.ywrapstep	= nowrap ? 0 : 1;
1470
1471	info->fbops		= &tdfxfb_ops;
1472	info->pseudo_palette	= default_par->palette;
1473	info->flags		= FBINFO_HWACCEL_YPAN;
1474#ifdef CONFIG_FB_3DFX_ACCEL
1475	info->flags		|= FBINFO_HWACCEL_FILLRECT |
1476				   FBINFO_HWACCEL_COPYAREA |
1477				   FBINFO_HWACCEL_IMAGEBLIT |
1478				   FBINFO_READS_FAST;
1479#endif
1480	/* reserve 8192 bits for cursor */
1481	/* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */
1482	if (hwcursor)
1483		info->fix.smem_len = (info->fix.smem_len - 1024) &
1484					(PAGE_MASK << 1);
1485	specs = &info->monspecs;
1486	found = false;
1487	info->var.bits_per_pixel = 8;
1488#ifdef CONFIG_FB_3DFX_I2C
1489	tdfxfb_create_i2c_busses(info);
1490	err = tdfxfb_probe_i2c_connector(default_par, specs);
1491
1492	if (!err) {
1493		if (specs->modedb == NULL)
1494			DPRINTK("Unable to get Mode Database\n");
1495		else {
1496			const struct fb_videomode *m;
1497
1498			fb_videomode_to_modelist(specs->modedb,
1499						 specs->modedb_len,
1500						 &info->modelist);
1501			m = fb_find_best_display(specs, &info->modelist);
1502			if (m) {
1503				fb_videomode_to_var(&info->var, m);
1504				/* fill all other info->var's fields */
1505				if (tdfxfb_check_var(&info->var, info) < 0)
1506					info->var = tdfx_var;
1507				else
1508					found = true;
1509			}
1510		}
1511	}
1512#endif
1513	if (!mode_option && !found)
1514		mode_option = "640x480@60";
1515
1516	if (mode_option) {
1517		err = fb_find_mode(&info->var, info, mode_option,
1518				   specs->modedb, specs->modedb_len,
1519				   NULL, info->var.bits_per_pixel);
1520		if (!err || err == 4)
1521			info->var = tdfx_var;
1522	}
1523
1524	if (found) {
1525		fb_destroy_modedb(specs->modedb);
1526		specs->modedb = NULL;
1527	}
1528
1529	/* maximize virtual vertical length */
1530	lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1531	info->var.yres_virtual = info->fix.smem_len / lpitch;
1532	if (info->var.yres_virtual < info->var.yres)
1533		goto out_err_iobase;
1534
1535	if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1536		printk(KERN_ERR "tdfxfb: Can't allocate color map\n");
1537		goto out_err_iobase;
1538	}
1539
1540	if (register_framebuffer(info) < 0) {
1541		printk(KERN_ERR "tdfxfb: can't register framebuffer\n");
1542		fb_dealloc_cmap(&info->cmap);
1543		goto out_err_iobase;
1544	}
1545	/*
1546	 * Our driver data
1547	 */
1548	pci_set_drvdata(pdev, info);
1549	return 0;
1550
1551out_err_iobase:
1552#ifdef CONFIG_FB_3DFX_I2C
1553	tdfxfb_delete_i2c_busses(default_par);
1554#endif
1555	arch_phys_wc_del(default_par->wc_cookie);
1556	release_region(pci_resource_start(pdev, 2),
1557		       pci_resource_len(pdev, 2));
1558out_err_screenbase:
1559	if (info->screen_base)
1560		iounmap(info->screen_base);
1561	release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1));
1562out_err_regbase:
1563	/*
1564	 * Cleanup after anything that was remapped/allocated.
1565	 */
1566	if (default_par->regbase_virt)
1567		iounmap(default_par->regbase_virt);
1568	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1569out_err:
1570	framebuffer_release(info);
1571	return -ENXIO;
1572}
1573
1574#ifndef MODULE
1575static void __init tdfxfb_setup(char *options)
1576{
1577	char *this_opt;
1578
1579	if (!options || !*options)
1580		return;
1581
1582	while ((this_opt = strsep(&options, ",")) != NULL) {
1583		if (!*this_opt)
1584			continue;
1585		if (!strcmp(this_opt, "nopan")) {
1586			nopan = 1;
1587		} else if (!strcmp(this_opt, "nowrap")) {
1588			nowrap = 1;
1589		} else if (!strncmp(this_opt, "hwcursor=", 9)) {
1590			hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1591		} else if (!strncmp(this_opt, "nomtrr", 6)) {
1592			nomtrr = 1;
1593		} else {
1594			mode_option = this_opt;
1595		}
1596	}
1597}
1598#endif
1599
1600/**
1601 *      tdfxfb_remove - Device removal
1602 *
1603 *      @pdev:  PCI Device to cleanup
1604 *
1605 *      Releases all resources allocated during the course of the driver's
1606 *      lifetime for the PCI device @pdev.
1607 *
1608 */
1609static void tdfxfb_remove(struct pci_dev *pdev)
1610{
1611	struct fb_info *info = pci_get_drvdata(pdev);
1612	struct tdfx_par *par = info->par;
1613
1614	unregister_framebuffer(info);
1615#ifdef CONFIG_FB_3DFX_I2C
1616	tdfxfb_delete_i2c_busses(par);
1617#endif
1618	arch_phys_wc_del(par->wc_cookie);
1619	iounmap(par->regbase_virt);
1620	iounmap(info->screen_base);
1621
1622	/* Clean up after reserved regions */
1623	release_region(pci_resource_start(pdev, 2),
1624		       pci_resource_len(pdev, 2));
1625	release_mem_region(pci_resource_start(pdev, 1),
1626			   pci_resource_len(pdev, 1));
1627	release_mem_region(pci_resource_start(pdev, 0),
1628			   pci_resource_len(pdev, 0));
1629	fb_dealloc_cmap(&info->cmap);
1630	framebuffer_release(info);
1631}
1632
1633static int __init tdfxfb_init(void)
1634{
1635#ifndef MODULE
1636	char *option = NULL;
1637#endif
1638
1639	if (fb_modesetting_disabled("tdfxfb"))
1640		return -ENODEV;
1641
1642#ifndef MODULE
1643	if (fb_get_options("tdfxfb", &option))
1644		return -ENODEV;
1645
1646	tdfxfb_setup(option);
1647#endif
1648	return pci_register_driver(&tdfxfb_driver);
1649}
1650
1651static void __exit tdfxfb_exit(void)
1652{
1653	pci_unregister_driver(&tdfxfb_driver);
1654}
1655
1656MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1657MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1658MODULE_LICENSE("GPL");
1659
1660module_param(hwcursor, int, 0644);
1661MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1662			"(1=enable, 0=disable, default=1)");
1663module_param(mode_option, charp, 0);
1664MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1665module_param(nomtrr, bool, 0);
1666MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)");
1667
1668module_init(tdfxfb_init);
1669module_exit(tdfxfb_exit);