sstfb.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
   4 *
   5 *     Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
   6 *
   7 *     Created 15 Jan 2000 by Ghozlane Toumi
   8 *
   9 * Contributions (and many thanks) :
  10 *
  11 * 03/2001 James Simmons   <jsimmons@infradead.org>
  12 * 04/2001 Paul Mundt      <lethal@chaoticdreams.org>
  13 * 05/2001 Urs Ganse       <ursg@uni.de>
  14 *	(initial work on voodoo2 port, interlace)
  15 * 09/2002 Helge Deller    <deller@gmx.de>
  16 *	(enable driver on big-endian machines (hppa), ioctl fixes)
  17 * 12/2002 Helge Deller    <deller@gmx.de>
  18 *	(port driver to new frambuffer infrastructure)
  19 * 01/2003 Helge Deller    <deller@gmx.de>
  20 *	(initial work on fb hardware acceleration for voodoo2)
  21 * 08/2006 Alan Cox 	   <alan@redhat.com>
  22 *	Remove never finished and bogus 24/32bit support
  23 *	Clean up macro abuse
  24 *	Minor tidying for format.
  25 * 12/2006 Helge Deller    <deller@gmx.de>
  26 *	add /sys/class/graphics/fbX/vgapass sysfs-interface
  27 *	add module option "mode_option" to set initial screen mode
  28 *	use fbdev default videomode database
  29 *	remove debug functions from ioctl
  30 */
  31
  32/*
  33 * The voodoo1 has the following memory mapped address space:
  34 * 0x000000 - 0x3fffff : registers              (4MB)
  35 * 0x400000 - 0x7fffff : linear frame buffer    (4MB)
  36 * 0x800000 - 0xffffff : texture memory         (8MB)
  37 */
  38
  39/*
  40 * misc notes, TODOs, toASKs, and deep thoughts
  41
  42-TODO: at one time or another test that the mode is acceptable by the monitor
  43-ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
  44      which one should i use ? is there any preferred one ? It seems ARGB is
  45      the one ...
  46-TODO: in  set_var check the validity of timings (hsync vsync)...
  47-TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
  48       a nop command. so it's ok as long as the commands we pass don't go
  49       through the fifo. warning: issuing a nop command seems to need pci_fifo
  50-FIXME: in case of failure in the init sequence, be sure we return to a safe
  51        state.
  52- FIXME: Use accelerator for 2D scroll
  53-FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
  54 */
  55
  56/*
  57 * debug info
  58 * SST_DEBUG : enable debugging
  59 * SST_DEBUG_REG : debug registers
  60 *   0 :  no debug
  61 *   1 : dac calls, [un]set_bits, FbiInit
  62 *   2 : insane debug level (log every register read/write)
  63 * SST_DEBUG_FUNC : functions
  64 *   0 : no debug
  65 *   1 : function call / debug ioctl
  66 *   2 : variables
  67 *   3 : flood . you don't want to do that. trust me.
  68 * SST_DEBUG_VAR : debug display/var structs
  69 *   0 : no debug
  70 *   1 : dumps display, fb_var
  71 *
  72 * sstfb specific ioctls:
  73 *   		toggle vga (0x46db) : toggle vga_pass_through
  74 */
  75
  76#undef SST_DEBUG
  77
  78
  79/*
  80 * Includes
  81 */
  82
  83#include <linux/aperture.h>
  84#include <linux/string.h>
  85#include <linux/kernel.h>
  86#include <linux/module.h>
  87#include <linux/fb.h>
  88#include <linux/pci.h>
  89#include <linux/delay.h>
  90#include <linux/init.h>
  91#include <asm/io.h>
  92#include <linux/uaccess.h>
  93#include <video/sstfb.h>
  94
  95
  96/* initialized by setup */
  97
  98static bool vgapass;		/* enable VGA passthrough cable */
  99static int mem;			/* mem size in MB, 0 = autodetect */
 100static bool clipping = 1;	/* use clipping (slower, safer) */
 101static int gfxclk;		/* force FBI freq in Mhz . Dangerous */
 102static bool slowpci;		/* slow PCI settings */
 103
 104/*
 105  Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60
 106*/
 107#define DEFAULT_VIDEO_MODE "640x480@60"
 108
 109static char *mode_option = DEFAULT_VIDEO_MODE;
 110
 111enum {
 112	ID_VOODOO1 = 0,
 113	ID_VOODOO2 = 1,
 114};
 115
 116#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
 117
 118static struct sst_spec voodoo_spec[] = {
 119 { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
 120 { .name = "Voodoo2",	      .default_gfx_clock = 75000, .max_gfxclk = 85 },
 121};
 122
 123
 124/*
 125 * debug functions
 126 */
 127
 128#if (SST_DEBUG_REG > 0)
 129static void sst_dbg_print_read_reg(u32 reg, u32 val) {
 130	const char *regname;
 131	switch (reg) {
 132	case FBIINIT0:	regname = "FbiInit0"; break;
 133	case FBIINIT1:	regname = "FbiInit1"; break;
 134	case FBIINIT2:	regname = "FbiInit2"; break;
 135	case FBIINIT3:	regname = "FbiInit3"; break;
 136	case FBIINIT4:	regname = "FbiInit4"; break;
 137	case FBIINIT5:	regname = "FbiInit5"; break;
 138	case FBIINIT6:	regname = "FbiInit6"; break;
 139	default:	regname = NULL;       break;
 140	}
 141	if (regname == NULL)
 142		r_ddprintk("sst_read(%#x): %#x\n", reg, val);
 143	else
 144		r_dprintk(" sst_read(%s): %#x\n", regname, val);
 145}
 146
 147static void sst_dbg_print_write_reg(u32 reg, u32 val) {
 148	const char *regname;
 149	switch (reg) {
 150	case FBIINIT0:	regname = "FbiInit0"; break;
 151	case FBIINIT1:	regname = "FbiInit1"; break;
 152	case FBIINIT2:	regname = "FbiInit2"; break;
 153	case FBIINIT3:	regname = "FbiInit3"; break;
 154	case FBIINIT4:	regname = "FbiInit4"; break;
 155	case FBIINIT5:	regname = "FbiInit5"; break;
 156	case FBIINIT6:	regname = "FbiInit6"; break;
 157	default:	regname = NULL;       break;
 158	}
 159	if (regname == NULL)
 160		r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
 161	else
 162		r_dprintk(" sst_write(%s, %#x)\n", regname, val);
 163}
 164#else /*  (SST_DEBUG_REG > 0) */
 165#  define sst_dbg_print_read_reg(reg, val)	do {} while(0)
 166#  define sst_dbg_print_write_reg(reg, val)	do {} while(0)
 167#endif /*  (SST_DEBUG_REG > 0) */
 168
 169/*
 170 * hardware access functions
 171 */
 172
 173/* register access */
 174#define sst_read(reg)		__sst_read(par->mmio_vbase, reg)
 175#define sst_write(reg,val)	__sst_write(par->mmio_vbase, reg, val)
 176#define sst_set_bits(reg,val)	__sst_set_bits(par->mmio_vbase, reg, val)
 177#define sst_unset_bits(reg,val)	__sst_unset_bits(par->mmio_vbase, reg, val)
 178#define sst_dac_read(reg)	__sst_dac_read(par->mmio_vbase, reg)
 179#define sst_dac_write(reg,val)	__sst_dac_write(par->mmio_vbase, reg, val)
 180#define dac_i_read(reg)		__dac_i_read(par->mmio_vbase, reg)
 181#define dac_i_write(reg,val)	__dac_i_write(par->mmio_vbase, reg, val)
 182
 183static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
 184{
 185	u32 ret = readl(vbase + reg);
 186	sst_dbg_print_read_reg(reg, ret);
 187	return ret;
 188}
 189
 190static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
 191{
 192	sst_dbg_print_write_reg(reg, val);
 193	writel(val, vbase + reg);
 194}
 195
 196static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
 197{
 198	r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
 199	__sst_write(vbase, reg, __sst_read(vbase, reg) | val);
 200}
 201
 202static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
 203{
 204	r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
 205	__sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
 206}
 207
 208/*
 209 * wait for the fbi chip. ASK: what happens if the fbi is stuck ?
 210 *
 211 * the FBI is supposed to be ready if we receive 5 time
 212 * in a row a "idle" answer to our requests
 213 */
 214
 215#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
 216
 217static int __sst_wait_idle(u8 __iomem *vbase)
 218{
 219	int count = 0;
 220
 221	/* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
 222
 223	while(1) {
 224		if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
 225			f_dddprintk("status: busy\n");
 226/* FIXME basically, this is a busy wait. maybe not that good. oh well;
 227 * this is a small loop after all.
 228 * Or maybe we should use mdelay() or udelay() here instead ? */
 229			count = 0;
 230		} else {
 231			count++;
 232			f_dddprintk("status: idle(%d)\n", count);
 233		}
 234		if (count >= 5) return 1;
 235/* XXX  do something to avoid hanging the machine if the voodoo is out */
 236	}
 237}
 238
 239
 240/* dac access */
 241/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
 242static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
 243{
 244	u8 ret;
 245
 246	reg &= 0x07;
 247	__sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
 248	__sst_wait_idle(vbase);
 249	/* udelay(10); */
 250	ret = __sst_read(vbase, DAC_READ) & 0xff;
 251	r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
 252
 253	return ret;
 254}
 255
 256static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
 257{
 258	r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
 259	reg &= 0x07;
 260	__sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
 261	__sst_wait_idle(vbase);
 262}
 263
 264/* indexed access to ti/att dacs */
 265static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
 266{
 267	u32 ret;
 268
 269	__sst_dac_write(vbase, DACREG_ADDR_I, reg);
 270	ret = __sst_dac_read(vbase, DACREG_DATA_I);
 271	r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
 272	return ret;
 273}
 274static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
 275{
 276	r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
 277	__sst_dac_write(vbase, DACREG_ADDR_I, reg);
 278	__sst_dac_write(vbase, DACREG_DATA_I, val);
 279}
 280
 281/* compute the m,n,p  , returns the real freq
 282 * (ics datasheet :  N <-> N1 , P <-> N2)
 283 *
 284 * Fout= Fref * (M+2)/( 2^P * (N+2))
 285 *  we try to get close to the asked freq
 286 *  with P as high, and M as low as possible
 287 * range:
 288 * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
 289 * ics    : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
 290 * we'll use the lowest limitation, should be precise enouth
 291 */
 292static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
 293{
 294	int m, m2, n, p, best_err, fout;
 295	int best_n = -1;
 296	int best_m = -1;
 297
 298	best_err = freq;
 299	p = 3;
 300	/* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
 301	while (((1 << p) * freq > VCO_MAX) && (p >= 0))
 302		p--;
 303	if (p == -1)
 304		return -EINVAL;
 305	for (n = 1; n < 32; n++) {
 306		/* calc 2 * m so we can round it later*/
 307		m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
 308
 309		m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
 310		if (m >= 128)
 311			break;
 312		fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
 313		if ((abs(fout - freq) < best_err) && (m > 0)) {
 314			best_n = n;
 315			best_m = m;
 316			best_err = abs(fout - freq);
 317			/* we get the lowest m , allowing 0.5% error in freq*/
 318			if (200*best_err < freq) break;
 319		}
 320	}
 321	if (best_n == -1)  /* unlikely, but who knows ? */
 322		return -EINVAL;
 323	t->p = p;
 324	t->n = best_n;
 325	t->m = best_m;
 326	*freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
 327	f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
 328		  t->m, t->n, t->p, *freq_out);
 329	return 0;
 330}
 331
 332/*
 333 * clear lfb screen
 334 */
 335static void sstfb_clear_screen(struct fb_info *info)
 336{
 337	/* clear screen */
 338	fb_memset_io(info->screen_base, 0, info->fix.smem_len);
 339}
 340
 341
 342/**
 343 *      sstfb_check_var - Optional function.  Validates a var passed in.
 344 *      @var: frame buffer variable screen structure
 345 *      @info: frame buffer structure that represents a single frame buffer
 346 *
 347 *	Limit to the abilities of a single chip as SLI is not supported
 348 *	by this driver.
 349 */
 350
 351static int sstfb_check_var(struct fb_var_screeninfo *var,
 352		struct fb_info *info)
 353{
 354	struct sstfb_par *par = info->par;
 355	int hSyncOff   = var->xres + var->right_margin + var->left_margin;
 356	int vSyncOff   = var->yres + var->lower_margin + var->upper_margin;
 357	int vBackPorch = var->left_margin, yDim = var->yres;
 358	int vSyncOn    = var->vsync_len;
 359	int tiles_in_X, real_length;
 360	unsigned int freq;
 361
 362	if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
 363		printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n",
 364				PICOS2KHZ(var->pixclock));
 365		return -EINVAL;
 366	}
 367	var->pixclock = KHZ2PICOS(freq);
 368
 369	if (var->vmode & FB_VMODE_INTERLACED)
 370		vBackPorch += (vBackPorch % 2);
 371	if (var->vmode & FB_VMODE_DOUBLE) {
 372		vBackPorch <<= 1;
 373		yDim <<=1;
 374		vSyncOn <<=1;
 375		vSyncOff <<=1;
 376	}
 377
 378	switch (var->bits_per_pixel) {
 379	case 0 ... 16 :
 380		var->bits_per_pixel = 16;
 381		break;
 382	default :
 383		printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel);
 384		return -EINVAL;
 385	}
 386
 387	/* validity tests */
 388	if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1  ||
 389	    hSyncOff <= 1  || var->left_margin <= 2  || vSyncOn <= 0 ||
 390	    vSyncOff <= 0 || vBackPorch <= 0) {
 391		return -EINVAL;
 392	}
 393
 394	if (IS_VOODOO2(par)) {
 395		/* Voodoo 2 limits */
 396		tiles_in_X = (var->xres + 63 ) / 64 * 2;
 397
 398		if (var->xres  > POW2(11) || yDim >= POW2(11)) {
 399			printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
 400			         var->xres, var->yres);
 401			return -EINVAL;
 402		}
 403
 404		if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) ||
 405		    var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) ||
 406		    vSyncOff >= POW2(13) || vBackPorch >= POW2(9) ||
 407		    tiles_in_X >= POW2(6) || tiles_in_X <= 0) {
 408			printk(KERN_ERR "sstfb: Unsupported timings\n");
 409			return -EINVAL;
 410		}
 411	} else {
 412		/* Voodoo limits */
 413		tiles_in_X = (var->xres + 63 ) / 64;
 414
 415		if (var->vmode) {
 416			printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n",
 417				var->vmode);
 418			return -EINVAL;
 419		}
 420		if (var->xres > POW2(10) || var->yres >= POW2(10)) {
 421			printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
 422			         var->xres, var->yres);
 423			return -EINVAL;
 424		}
 425		if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) ||
 426		    var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) ||
 427		    vSyncOff >= POW2(12) || vBackPorch >= POW2(8) ||
 428		    tiles_in_X >= POW2(4) || tiles_in_X <= 0) {
 429			printk(KERN_ERR "sstfb: Unsupported timings\n");
 430			return -EINVAL;
 431		}
 432	}
 433
 434	/* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
 435	/* FIXME: i don't like this... looks wrong */
 436	real_length = tiles_in_X  * (IS_VOODOO2(par) ? 32 : 64 )
 437	              * ((var->bits_per_pixel == 16) ? 2 : 4);
 438
 439	if (real_length * yDim > info->fix.smem_len) {
 440		printk(KERN_ERR "sstfb: Not enough video memory\n");
 441		return -ENOMEM;
 442	}
 443
 444	var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
 445	var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
 446	var->xoffset = 0;
 447	var->yoffset = 0;
 448	var->height  = -1;
 449	var->width   = -1;
 450
 451	/*
 452	 * correct the color bit fields
 453	 */
 454	/* var->{red|green|blue}.msb_right = 0; */
 455
 456	switch (var->bits_per_pixel) {
 457	case 16:	/* RGB 565  LfbMode 0 */
 458		var->red.length    = 5;
 459		var->green.length  = 6;
 460		var->blue.length   = 5;
 461		var->transp.length = 0;
 462
 463		var->red.offset    = 11;
 464		var->green.offset  = 5;
 465		var->blue.offset   = 0;
 466		var->transp.offset = 0;
 467		break;
 468	default:
 469		return -EINVAL;
 470	}
 471	return 0;
 472}
 473
 474/**
 475 *      sstfb_set_par - Optional function.  Alters the hardware state.
 476 *      @info: frame buffer structure that represents a single frame buffer
 477 */
 478static int sstfb_set_par(struct fb_info *info)
 479{
 480	struct sstfb_par *par = info->par;
 481	u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
 482	struct pci_dev *sst_dev = par->dev;
 483	unsigned int freq;
 484	int ntiles;
 485
 486	par->hSyncOff	= info->var.xres + info->var.right_margin + info->var.left_margin;
 487
 488	par->yDim 	= info->var.yres;
 489	par->vSyncOn 	= info->var.vsync_len;
 490	par->vSyncOff	= info->var.yres + info->var.lower_margin + info->var.upper_margin;
 491	par->vBackPorch = info->var.upper_margin;
 492
 493	/* We need par->pll */
 494	sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
 495
 496	if (info->var.vmode & FB_VMODE_INTERLACED)
 497		par->vBackPorch += (par->vBackPorch % 2);
 498	if (info->var.vmode & FB_VMODE_DOUBLE) {
 499		par->vBackPorch <<= 1;
 500		par->yDim <<=1;
 501		par->vSyncOn <<=1;
 502		par->vSyncOff <<=1;
 503	}
 504
 505	if (IS_VOODOO2(par)) {
 506		/* voodoo2 has 32 pixel wide tiles , BUT strange things
 507		   happen with odd number of tiles */
 508		par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
 509	} else {
 510		/* voodoo1 has 64 pixels wide tiles. */
 511		par->tiles_in_X = (info->var.xres + 63 ) / 64;
 512	}
 513
 514	f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
 515	f_ddprintk("%-7d %-8d %-7d %-8d\n",
 516	           info->var.hsync_len, par->hSyncOff,
 517	           par->vSyncOn, par->vSyncOff);
 518	f_ddprintk("left_margin upper_margin xres yres Freq\n");
 519	f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
 520	           info->var.left_margin, info->var.upper_margin,
 521	           info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
 522
 523	sst_write(NOPCMD, 0);
 524	sst_wait_idle();
 525	pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
 526	sst_set_bits(FBIINIT1, VIDEO_RESET);
 527	sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
 528	sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
 529	sst_wait_idle();
 530
 531	/*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
 532
 533	sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
 534	sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
 535	sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
 536	sst_write(VSYNC,       par->vSyncOff << 16 | par->vSyncOn);
 537
 538	fbiinit2 = sst_read(FBIINIT2);
 539	fbiinit3 = sst_read(FBIINIT3);
 540
 541	/* everything is reset. we enable fbiinit2/3 remap : dac access ok */
 542	pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
 543	                       PCI_EN_INIT_WR | PCI_REMAP_DAC );
 544
 545	par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
 546
 547	/* set video clock */
 548	par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
 549
 550	/* disable fbiinit2/3 remap */
 551	pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
 552	                       PCI_EN_INIT_WR);
 553
 554	/* restore fbiinit2/3 */
 555	sst_write(FBIINIT2,fbiinit2);
 556	sst_write(FBIINIT3,fbiinit3);
 557
 558	fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
 559	            | EN_DATA_OE
 560	            | EN_BLANK_OE
 561	            | EN_HVSYNC_OE
 562	            | EN_DCLK_OE
 563		 /* | (15 << TILES_IN_X_SHIFT) */
 564	            | SEL_INPUT_VCLK_2X
 565		 /* | (2 << VCLK_2X_SEL_DEL_SHIFT)
 566	            | (2 << VCLK_DEL_SHIFT) */;
 567/* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
 568 in (near) future set them accordingly to revision + resolution (cf glide)
 569 first understand what it stands for :)
 570 FIXME: there are some artefacts... check for the vclk_in_delay
 571 lets try with 6ns delay in both vclk_out & in...
 572 doh... they're still there :\
 573*/
 574
 575	ntiles = par->tiles_in_X;
 576	if (IS_VOODOO2(par)) {
 577		fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
 578		            | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
 579/* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
 580   and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
 581   write our value. BTW due to the dac unable to read odd number of tiles, this
 582   field is always null ... */
 583		fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
 584	}
 585	else
 586		fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
 587
 588	switch (info->var.bits_per_pixel) {
 589	case 16:
 590		fbiinit1 |=  SEL_SOURCE_VCLK_2X_SEL;
 591		break;
 592	default:
 593		return -EINVAL;
 594	}
 595	sst_write(FBIINIT1, fbiinit1);
 596	if (IS_VOODOO2(par)) {
 597		sst_write(FBIINIT6, fbiinit6);
 598		fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
 599		if (info->var.vmode & FB_VMODE_INTERLACED)
 600			fbiinit5 |= INTERLACE;
 601		if (info->var.vmode & FB_VMODE_DOUBLE)
 602			fbiinit5 |= VDOUBLESCAN;
 603		if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 604			fbiinit5 |= HSYNC_HIGH;
 605		if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 606			fbiinit5 |= VSYNC_HIGH;
 607		sst_write(FBIINIT5, fbiinit5);
 608	}
 609	sst_wait_idle();
 610	sst_unset_bits(FBIINIT1, VIDEO_RESET);
 611	sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
 612	sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
 613	/* disables fbiinit writes */
 614	pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
 615
 616	/* set lfbmode : set mode + front buffer for reads/writes
 617	   + disable pipeline */
 618	switch (info->var.bits_per_pixel) {
 619	case 16:
 620		lfbmode = LFB_565;
 621		break;
 622	default:
 623		return -EINVAL;
 624	}
 625
 626#if defined(__BIG_ENDIAN)
 627	/* Enable byte-swizzle functionality in hardware.
 628	 * With this enabled, all our read- and write-accesses to
 629	 * the voodoo framebuffer can be done in native format, and
 630	 * the hardware will automatically convert it to little-endian.
 631	 * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
 632	lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
 633		     LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
 634#endif
 635
 636	if (clipping) {
 637		sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
 638	/*
 639	 * Set "clipping" dimensions. If clipping is disabled and
 640	 * writes to offscreen areas of the framebuffer are performed,
 641	 * the "behaviour is undefined" (_very_ undefined) - Urs
 642	 */
 643	/* btw, it requires enabling pixel pipeline in LFBMODE .
 644	   off screen read/writes will just wrap and read/print pixels
 645	   on screen. Ugly but not that dangerous */
 646		f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
 647		            info->var.xres - 1, par->yDim - 1);
 648
 649		sst_write(CLIP_LEFT_RIGHT, info->var.xres);
 650		sst_write(CLIP_LOWY_HIGHY, par->yDim);
 651		sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
 652	} else {
 653		/* no clipping : direct access, no pipeline */
 654		sst_write(LFBMODE, lfbmode);
 655	}
 656	return 0;
 657}
 658
 659/**
 660 *      sstfb_setcolreg - Optional function. Sets a color register.
 661 *      @regno: hardware colormap register
 662 *      @red: frame buffer colormap structure
 663 *      @green: The green value which can be up to 16 bits wide
 664 *      @blue:  The blue value which can be up to 16 bits wide.
 665 *      @transp: If supported the alpha value which can be up to 16 bits wide.
 666 *      @info: frame buffer info structure
 667 */
 668static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 669                           u_int transp, struct fb_info *info)
 670{
 671	struct sstfb_par *par = info->par;
 672	u32 col;
 673
 674	f_dddprintk("sstfb_setcolreg\n");
 675	f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
 676	            regno, red, green, blue, transp);
 677	if (regno > 15)
 678		return 0;
 679
 680	red    >>= (16 - info->var.red.length);
 681	green  >>= (16 - info->var.green.length);
 682	blue   >>= (16 - info->var.blue.length);
 683	transp >>= (16 - info->var.transp.length);
 684	col = (red << info->var.red.offset)
 685	    | (green << info->var.green.offset)
 686	    | (blue  << info->var.blue.offset)
 687	    | (transp << info->var.transp.offset);
 688
 689	par->palette[regno] = col;
 690
 691	return 0;
 692}
 693
 694static void sstfb_setvgapass( struct fb_info *info, int enable )
 695{
 696	struct sstfb_par *par = info->par;
 697	struct pci_dev *sst_dev = par->dev;
 698	u32 fbiinit0, tmp;
 699
 700	enable = enable ? 1:0;
 701	if (par->vgapass == enable)
 702		return;
 703	par->vgapass = enable;
 704
 705	pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
 706	pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
 707			       tmp | PCI_EN_INIT_WR );
 708	fbiinit0 = sst_read (FBIINIT0);
 709	if (par->vgapass) {
 710		sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH);
 711		fb_info(info, "Enabling VGA pass-through\n");
 712	} else {
 713		sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH);
 714		fb_info(info, "Disabling VGA pass-through\n");
 715	}
 716	pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
 717}
 718
 719#ifdef CONFIG_FB_DEVICE
 720static ssize_t store_vgapass(struct device *device, struct device_attribute *attr,
 721			const char *buf, size_t count)
 722{
 723	struct fb_info *info = dev_get_drvdata(device);
 724	char ** last = NULL;
 725	int val;
 726
 727	val = simple_strtoul(buf, last, 0);
 728	sstfb_setvgapass(info, val);
 729
 730	return count;
 731}
 732
 733static ssize_t show_vgapass(struct device *device, struct device_attribute *attr,
 734			char *buf)
 735{
 736	struct fb_info *info = dev_get_drvdata(device);
 737	struct sstfb_par *par = info->par;
 738	return sprintf(buf, "%d\n", par->vgapass);
 739}
 740
 741static struct device_attribute device_attrs[] = {
 742	__ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass)
 743};
 744#endif
 745
 746static int sstfb_ioctl(struct fb_info *info, unsigned int cmd,
 747			unsigned long arg)
 748{
 749	struct sstfb_par *par;
 750	u32 val;
 751
 752	switch (cmd) {
 753	/* set/get VGA pass_through mode */
 754	case SSTFB_SET_VGAPASS:
 755		if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
 756			return -EFAULT;
 757		sstfb_setvgapass(info, val);
 758		return 0;
 759	case SSTFB_GET_VGAPASS:
 760		par = info->par;
 761		val = par->vgapass;
 762		if (copy_to_user((void __user *)arg, &val, sizeof(val)))
 763			return -EFAULT;
 764		return 0;
 765	}
 766
 767	return -EINVAL;
 768}
 769
 770
 771/*
 772 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
 773 */
 774#if 0
 775static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
 776{
 777	struct sstfb_par *par = info->par;
 778	u32 stride = info->fix.line_length;
 779
 780	if (!IS_VOODOO2(par))
 781		return;
 782
 783	sst_write(BLTSRCBASEADDR, 0);
 784	sst_write(BLTDSTBASEADDR, 0);
 785	sst_write(BLTROP, BLTROP_COPY);
 786	sst_write(BLTXYSTRIDES, stride | (stride << 16));
 787	sst_write(BLTSRCXY, area->sx | (area->sy << 16));
 788	sst_write(BLTDSTXY, area->dx | (area->dy << 16));
 789	sst_write(BLTSIZE, area->width | (area->height << 16));
 790	sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
 791		(BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
 792	sst_wait_idle();
 793}
 794#endif
 795
 796
 797/*
 798 * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
 799 */
 800#if 0
 801static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 802{
 803	struct sstfb_par *par = info->par;
 804	u32 stride = info->fix.line_length;
 805
 806	if (!IS_VOODOO2(par))
 807		return;
 808
 809	sst_write(BLTCLIPX, info->var.xres);
 810	sst_write(BLTCLIPY, info->var.yres);
 811
 812	sst_write(BLTDSTBASEADDR, 0);
 813	sst_write(BLTCOLOR, rect->color);
 814	sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
 815	sst_write(BLTXYSTRIDES, stride | (stride << 16));
 816	sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
 817	sst_write(BLTSIZE, rect->width | (rect->height << 16));
 818	sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
 819		 | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
 820	sst_wait_idle();
 821}
 822#endif
 823
 824
 825
 826/*
 827 * get lfb size
 828 */
 829static int sst_get_memsize(struct fb_info *info, __u32 *memsize)
 830{
 831	u8 __iomem *fbbase_virt = info->screen_base;
 832
 833	/* force memsize */
 834	if (mem >= 1  && mem <= 4) {
 835		*memsize = (mem * 0x100000);
 836		printk(KERN_INFO "supplied memsize: %#x\n", *memsize);
 837		return 1;
 838	}
 839
 840	writel(0xdeadbeef, fbbase_virt);
 841	writel(0xdeadbeef, fbbase_virt+0x100000);
 842	writel(0xdeadbeef, fbbase_virt+0x200000);
 843	f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
 844	           readl(fbbase_virt), readl(fbbase_virt + 0x100000),
 845	           readl(fbbase_virt + 0x200000));
 846
 847	writel(0xabcdef01, fbbase_virt);
 848
 849	f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
 850	           readl(fbbase_virt), readl(fbbase_virt + 0x100000),
 851	           readl(fbbase_virt + 0x200000));
 852
 853	/* checks for 4mb lfb, then 2, then defaults to 1 */
 854	if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
 855		*memsize = 0x400000;
 856	else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
 857		*memsize = 0x200000;
 858	else
 859		*memsize = 0x100000;
 860	f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
 861	return 1;
 862}
 863
 864
 865/*
 866 * DAC detection routines
 867 */
 868
 869/* fbi should be idle, and fifo emty and mem disabled */
 870/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
 871
 872static int sst_detect_att(struct fb_info *info)
 873{
 874	struct sstfb_par *par = info->par;
 875	int i, mir, dir;
 876
 877	for (i = 0; i < 3; i++) {
 878		sst_dac_write(DACREG_WMA, 0); 	/* backdoor */
 879		sst_dac_read(DACREG_RMR);	/* read 4 times RMR */
 880		sst_dac_read(DACREG_RMR);
 881		sst_dac_read(DACREG_RMR);
 882		sst_dac_read(DACREG_RMR);
 883		/* the fifth time,  CR0 is read */
 884		sst_dac_read(DACREG_RMR);
 885		/* the 6th, manufacturer id register */
 886		mir = sst_dac_read(DACREG_RMR);
 887		/*the 7th, device ID register */
 888		dir = sst_dac_read(DACREG_RMR);
 889		f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
 890		if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) {
 891			return 1;
 892		}
 893	}
 894	return 0;
 895}
 896
 897static int sst_detect_ti(struct fb_info *info)
 898{
 899	struct sstfb_par *par = info->par;
 900	int i, mir, dir;
 901
 902	for (i = 0; i<3; i++) {
 903		sst_dac_write(DACREG_WMA, 0); 	/* backdoor */
 904		sst_dac_read(DACREG_RMR);	/* read 4 times RMR */
 905		sst_dac_read(DACREG_RMR);
 906		sst_dac_read(DACREG_RMR);
 907		sst_dac_read(DACREG_RMR);
 908		/* the fifth time,  CR0 is read */
 909		sst_dac_read(DACREG_RMR);
 910		/* the 6th, manufacturer id register */
 911		mir = sst_dac_read(DACREG_RMR);
 912		/*the 7th, device ID register */
 913		dir = sst_dac_read(DACREG_RMR);
 914		f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
 915		if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
 916			return 1;
 917		}
 918	}
 919	return 0;
 920}
 921
 922/*
 923 * try to detect ICS5342  ramdac
 924 * we get the 1st byte (M value) of preset f1,f7 and fB
 925 * why those 3 ? mmmh... for now, i'll do it the glide way...
 926 * and ask questions later. anyway, it seems that all the freq registers are
 927 * really at their default state (cf specs) so i ask again, why those 3 regs ?
 928 * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
 929 * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
 930 * touched...
 931 * is it really safe ? how can i reset this ramdac ? geee...
 932 */
 933static int sst_detect_ics(struct fb_info *info)
 934{
 935	struct sstfb_par *par = info->par;
 936	int m_clk0_1, m_clk0_7, m_clk1_b;
 937	int n_clk0_1, n_clk0_7, n_clk1_b;
 938	int i;
 939
 940	for (i = 0; i<5; i++ ) {
 941		sst_dac_write(DACREG_ICS_PLLRMA, 0x1);	/* f1 */
 942		m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
 943		n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
 944		sst_dac_write(DACREG_ICS_PLLRMA, 0x7);	/* f7 */
 945		m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
 946		n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
 947		sst_dac_write(DACREG_ICS_PLLRMA, 0xb);	/* fB */
 948		m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
 949		n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
 950		f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
 951			m_clk0_1, m_clk0_7, m_clk1_b);
 952		f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
 953			n_clk0_1, n_clk0_7, n_clk1_b);
 954		if ((   m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
 955		    && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
 956		    && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
 957			return 1;
 958		}
 959	}
 960	return 0;
 961}
 962
 963
 964/*
 965 * gfx, video, pci fifo should be reset, dram refresh disabled
 966 * see detect_dac
 967 */
 968
 969static int sst_set_pll_att_ti(struct fb_info *info,
 970		const struct pll_timing *t, const int clock)
 971{
 972	struct sstfb_par *par = info->par;
 973	u8 cr0, cc;
 974
 975	/* enable indexed mode */
 976	sst_dac_write(DACREG_WMA, 0); 	/* backdoor */
 977	sst_dac_read(DACREG_RMR);	/* 1 time:  RMR */
 978	sst_dac_read(DACREG_RMR);	/* 2 RMR */
 979	sst_dac_read(DACREG_RMR);	/* 3 //  */
 980	sst_dac_read(DACREG_RMR);	/* 4 //  */
 981	cr0 = sst_dac_read(DACREG_RMR);	/* 5 CR0 */
 982
 983	sst_dac_write(DACREG_WMA, 0);
 984	sst_dac_read(DACREG_RMR);
 985	sst_dac_read(DACREG_RMR);
 986	sst_dac_read(DACREG_RMR);
 987	sst_dac_read(DACREG_RMR);
 988	sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
 989	              | DACREG_CR0_EN_INDEXED
 990	              | DACREG_CR0_8BIT
 991	              | DACREG_CR0_PWDOWN );
 992	/* so, now we are in indexed mode . dunno if its common, but
 993	   i find this way of doing things a little bit weird :p */
 994
 995	udelay(300);
 996	cc = dac_i_read(DACREG_CC_I);
 997	switch (clock) {
 998	case VID_CLOCK:
 999		dac_i_write(DACREG_AC0_I, t->m);
1000		dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
1001		dac_i_write(DACREG_CC_I,
1002		            (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
1003		break;
1004	case GFX_CLOCK:
1005		dac_i_write(DACREG_BD0_I, t->m);
1006		dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
1007		dac_i_write(DACREG_CC_I,
1008		            (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
1009		break;
1010	default:
1011		dprintk("%s: wrong clock code '%d'\n",
1012		        __func__, clock);
1013		return 0;
1014		}
1015	udelay(300);
1016
1017	/* power up the dac & return to "normal" non-indexed mode */
1018	dac_i_write(DACREG_CR0_I,
1019	            cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
1020	return 1;
1021}
1022
1023static int sst_set_pll_ics(struct fb_info *info,
1024		const struct pll_timing *t, const int clock)
1025{
1026	struct sstfb_par *par = info->par;
1027	u8 pll_ctrl;
1028
1029	sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
1030	pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
1031	switch(clock) {
1032	case VID_CLOCK:
1033		sst_dac_write(DACREG_ICS_PLLWMA, 0x0);	/* CLK0, f0 */
1034		sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1035		sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1036		/* selects freq f0 for clock 0 */
1037		sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1038		sst_dac_write(DACREG_ICS_PLLDATA,
1039		              (pll_ctrl & 0xd8)
1040		              | DACREG_ICS_CLK0
1041		              | DACREG_ICS_CLK0_0);
1042		break;
1043	case GFX_CLOCK :
1044		sst_dac_write(DACREG_ICS_PLLWMA, 0xa);	/* CLK1, fA */
1045		sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1046		sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1047		/* selects freq fA for clock 1 */
1048		sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1049		sst_dac_write(DACREG_ICS_PLLDATA,
1050		              (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
1051		break;
1052	default:
1053		dprintk("%s: wrong clock code '%d'\n",
1054		        __func__, clock);
1055		return 0;
1056		}
1057	udelay(300);
1058	return 1;
1059}
1060
1061static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
1062{
1063	struct sstfb_par *par = info->par;
1064	u8 cr0;
1065
1066	sst_dac_write(DACREG_WMA, 0); 	/* backdoor */
1067	sst_dac_read(DACREG_RMR);	/* read 4 times RMR */
1068	sst_dac_read(DACREG_RMR);
1069	sst_dac_read(DACREG_RMR);
1070	sst_dac_read(DACREG_RMR);
1071	/* the fifth time,  CR0 is read */
1072	cr0 = sst_dac_read(DACREG_RMR);
1073
1074	sst_dac_write(DACREG_WMA, 0); 	/* backdoor */
1075	sst_dac_read(DACREG_RMR);	/* read 4 times RMR */
1076	sst_dac_read(DACREG_RMR);
1077	sst_dac_read(DACREG_RMR);
1078	sst_dac_read(DACREG_RMR);
1079	/* cr0 */
1080	switch(bpp) {
1081	case 16:
1082		sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
1083		break;
1084	default:
1085		dprintk("%s: bad depth '%u'\n", __func__, bpp);
1086		break;
1087	}
1088}
1089
1090static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
1091{
1092	struct sstfb_par *par = info->par;
1093
1094	switch(bpp) {
1095	case 16:
1096		sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
1097		break;
1098	default:
1099		dprintk("%s: bad depth '%u'\n", __func__, bpp);
1100		break;
1101	}
1102}
1103
1104/*
1105 * detect dac type
1106 * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
1107 * dram refresh disabled, FbiInit remaped.
1108 * TODO: mmh.. maybe i should put the "prerequisite" in the func ...
1109 */
1110
1111
1112static struct dac_switch dacs[] = {
1113	{	.name		= "TI TVP3409",
1114		.detect		= sst_detect_ti,
1115		.set_pll	= sst_set_pll_att_ti,
1116		.set_vidmod	= sst_set_vidmod_att_ti },
1117
1118	{	.name		= "AT&T ATT20C409",
1119		.detect		= sst_detect_att,
1120		.set_pll	= sst_set_pll_att_ti,
1121		.set_vidmod	= sst_set_vidmod_att_ti },
1122	{	.name		= "ICS ICS5342",
1123		.detect		= sst_detect_ics,
1124		.set_pll	= sst_set_pll_ics,
1125		.set_vidmod	= sst_set_vidmod_ics },
1126};
1127
1128static int sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
1129{
1130	int i, ret = 0;
1131
1132	for (i = 0; i < ARRAY_SIZE(dacs); i++) {
1133		ret = dacs[i].detect(info);
1134		if (ret)
1135			break;
1136	}
1137	if (!ret)
1138		return 0;
1139	f_dprintk("%s found %s\n", __func__, dacs[i].name);
1140	par->dac_sw = dacs[i];
1141	return 1;
1142}
1143
1144/*
1145 * Internal Routines
1146 */
1147static int sst_init(struct fb_info *info, struct sstfb_par *par)
1148{
1149	u32 fbiinit0, fbiinit1, fbiinit4;
1150	struct pci_dev *dev = par->dev;
1151	struct pll_timing gfx_timings;
1152	struct sst_spec *spec;
1153	int Fout;
1154	int gfx_clock;
1155
1156	spec = &voodoo_spec[par->type];
1157	f_ddprintk(" fbiinit0   fbiinit1   fbiinit2   fbiinit3   fbiinit4  "
1158	           " fbiinit6\n");
1159	f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
1160	            sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
1161	            sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
1162	/* disable video clock */
1163	pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
1164
1165	/* enable writing to init registers, disable pci fifo */
1166	pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1167	/* reset video */
1168	sst_set_bits(FBIINIT1, VIDEO_RESET);
1169	sst_wait_idle();
1170	/* reset gfx + pci fifo */
1171	sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1172	sst_wait_idle();
1173
1174	/* unreset fifo */
1175	/*sst_unset_bits(FBIINIT0, FIFO_RESET);
1176	sst_wait_idle();*/
1177	/* unreset FBI */
1178	/*sst_unset_bits(FBIINIT0, FBI_RESET);
1179	sst_wait_idle();*/
1180
1181	/* disable dram refresh */
1182	sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1183	sst_wait_idle();
1184	/* remap fbinit2/3 to dac */
1185	pci_write_config_dword(dev, PCI_INIT_ENABLE,
1186				PCI_EN_INIT_WR | PCI_REMAP_DAC );
1187	/* detect dac type */
1188	if (!sst_detect_dactype(info, par)) {
1189		printk(KERN_ERR "sstfb: unknown dac type.\n");
1190		//FIXME watch it: we are not in a safe state, bad bad bad.
1191		return 0;
1192	}
1193
1194	/* set graphic clock */
1195	gfx_clock = spec->default_gfx_clock;
1196	if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
1197		printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk);
1198		 gfx_clock = gfxclk *1000;
1199	} else if (gfxclk) {
1200		printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk);
1201	}
1202
1203	sst_calc_pll(gfx_clock, &Fout, &gfx_timings);
1204	par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1205
1206	/* disable fbiinit remap */
1207	pci_write_config_dword(dev, PCI_INIT_ENABLE,
1208	                       PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
1209	/* defaults init registers */
1210	/* FbiInit0: unreset gfx, unreset fifo */
1211	fbiinit0 = FBIINIT0_DEFAULT;
1212	fbiinit1 = FBIINIT1_DEFAULT;
1213	fbiinit4 = FBIINIT4_DEFAULT;
1214	par->vgapass = vgapass;
1215	if (par->vgapass)
1216		fbiinit0 &= ~DIS_VGA_PASSTHROUGH;
1217	else
1218		fbiinit0 |= DIS_VGA_PASSTHROUGH;
1219	if (slowpci) {
1220		fbiinit1 |= SLOW_PCI_WRITES;
1221		fbiinit4 |= SLOW_PCI_READS;
1222	} else {
1223		fbiinit1 &= ~SLOW_PCI_WRITES;
1224		fbiinit4 &= ~SLOW_PCI_READS;
1225	}
1226	sst_write(FBIINIT0, fbiinit0);
1227	sst_wait_idle();
1228	sst_write(FBIINIT1, fbiinit1);
1229	sst_wait_idle();
1230	sst_write(FBIINIT2, FBIINIT2_DEFAULT);
1231	sst_wait_idle();
1232	sst_write(FBIINIT3, FBIINIT3_DEFAULT);
1233	sst_wait_idle();
1234	sst_write(FBIINIT4, fbiinit4);
1235	sst_wait_idle();
1236	if (IS_VOODOO2(par)) {
1237		sst_write(FBIINIT6, FBIINIT6_DEFAULT);
1238		sst_wait_idle();
1239	}
1240
1241	pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
1242	pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
1243	return 1;
1244}
1245
1246static void sst_shutdown(struct fb_info *info)
1247{
1248	struct sstfb_par *par = info->par;
1249	struct pci_dev *dev = par->dev;
1250	struct pll_timing gfx_timings;
1251	int Fout;
1252
1253	/* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
1254	pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1255	sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
1256	sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1257	sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1258	sst_wait_idle();
1259	pci_write_config_dword(dev, PCI_INIT_ENABLE,
1260	                       PCI_EN_INIT_WR | PCI_REMAP_DAC);
1261	/* set 20Mhz gfx clock */
1262	sst_calc_pll(20000, &Fout, &gfx_timings);
1263	par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1264	/* TODO maybe shutdown the dac, vrefresh and so on... */
1265	pci_write_config_dword(dev, PCI_INIT_ENABLE,
1266	                       PCI_EN_INIT_WR);
1267	sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH);
1268	pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
1269	/* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
1270	 * from start ? */
1271	pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
1272
1273}
1274
1275/*
1276 * Interface to the world
1277 */
1278static int sstfb_setup(char *options)
1279{
1280	char *this_opt;
1281
1282	if (!options || !*options)
1283		return 0;
1284
1285	while ((this_opt = strsep(&options, ",")) != NULL) {
1286		if (!*this_opt) continue;
1287
1288		f_ddprintk("option %s\n", this_opt);
1289
1290		if (!strcmp(this_opt, "vganopass"))
1291			vgapass = 0;
1292		else if (!strcmp(this_opt, "vgapass"))
1293			vgapass = 1;
1294		else if (!strcmp(this_opt, "clipping"))
1295		        clipping = 1;
1296		else if (!strcmp(this_opt, "noclipping"))
1297		        clipping = 0;
1298		else if (!strcmp(this_opt, "fastpci"))
1299		        slowpci = 0;
1300		else if (!strcmp(this_opt, "slowpci"))
1301		        slowpci = 1;
1302		else if (!strncmp(this_opt, "mem:",4))
1303			mem = simple_strtoul (this_opt+4, NULL, 0);
1304		else if (!strncmp(this_opt, "gfxclk:",7))
1305			gfxclk = simple_strtoul (this_opt+7, NULL, 0);
1306		else
1307			mode_option = this_opt;
1308	}
1309	return 0;
1310}
1311
1312
1313static const struct fb_ops sstfb_ops = {
1314	.owner		= THIS_MODULE,
1315	FB_DEFAULT_IOMEM_OPS,
1316	.fb_check_var	= sstfb_check_var,
1317	.fb_set_par	= sstfb_set_par,
1318	.fb_setcolreg	= sstfb_setcolreg,
1319	.fb_ioctl	= sstfb_ioctl,
1320};
1321
1322static int sstfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1323{
1324	struct fb_info *info;
1325	struct fb_fix_screeninfo *fix;
1326	struct sstfb_par *par;
1327	struct sst_spec *spec;
1328	int err;
1329
1330	err = aperture_remove_conflicting_pci_devices(pdev, "sstfb");
1331	if (err)
1332		return err;
1333
1334	/* Enable device in PCI config. */
1335	if ((err=pci_enable_device(pdev))) {
1336		printk(KERN_ERR "cannot enable device\n");
1337		return err;
1338	}
1339
1340	/* Allocate the fb and par structures.  */
1341	info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev);
1342	if (!info)
1343		return -ENOMEM;
1344
1345	pci_set_drvdata(pdev, info);
1346
1347	par  = info->par;
1348	fix  = &info->fix;
1349
1350	par->type = id->driver_data;
1351	spec = &voodoo_spec[par->type];
1352	f_ddprintk("found device : %s\n", spec->name);
1353
1354	par->dev = pdev;
1355	par->revision = pdev->revision;
1356
1357	fix->mmio_start = pci_resource_start(pdev,0);
1358	fix->mmio_len	= 0x400000;
1359	fix->smem_start = fix->mmio_start + 0x400000;
1360
1361	if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
1362		printk(KERN_ERR "sstfb: cannot reserve mmio memory\n");
1363		goto fail_mmio_mem;
1364	}
1365
1366	if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
1367		printk(KERN_ERR "sstfb: cannot reserve fb memory\n");
1368		goto fail_fb_mem;
1369	}
1370
1371	par->mmio_vbase = ioremap(fix->mmio_start,
1372					fix->mmio_len);
1373	if (!par->mmio_vbase) {
1374		printk(KERN_ERR "sstfb: cannot remap register area %#lx\n",
1375		        fix->mmio_start);
1376		goto fail_mmio_remap;
1377	}
1378	info->screen_base = ioremap(fix->smem_start, 0x400000);
1379	if (!info->screen_base) {
1380		printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n",
1381		        fix->smem_start);
1382		goto fail_fb_remap;
1383	}
1384
1385	if (!sst_init(info, par)) {
1386		printk(KERN_ERR "sstfb: Init failed\n");
1387		goto fail;
1388	}
1389	sst_get_memsize(info, &fix->smem_len);
1390	strscpy(fix->id, spec->name, sizeof(fix->id));
1391
1392	printk(KERN_INFO "%s (revision %d) with %s dac\n",
1393		fix->id, par->revision, par->dac_sw.name);
1394	printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
1395	        fix->smem_start, info->screen_base,
1396	        fix->smem_len >> 20);
1397
1398	f_ddprintk("regbase_virt: %p\n", par->mmio_vbase);
1399	f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
1400	f_ddprintk("fbbase_virt: %p\n", info->screen_base);
1401
1402	info->fbops	= &sstfb_ops;
1403	info->pseudo_palette = par->palette;
1404
1405	fix->type	= FB_TYPE_PACKED_PIXELS;
1406	fix->visual	= FB_VISUAL_TRUECOLOR;
1407	fix->accel	= FB_ACCEL_NONE;  /* FIXME */
1408	/*
1409	 * According to the specs, the linelength must be of 1024 *pixels*
1410	 * and the 24bpp mode is in fact a 32 bpp mode (and both are in
1411	 * fact dithered to 16bit).
1412	 */
1413	fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
1414
1415	fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16);
1416
1417	if (sstfb_check_var(&info->var, info)) {
1418		printk(KERN_ERR "sstfb: invalid video mode.\n");
1419		goto fail;
1420	}
1421
1422	if (sstfb_set_par(info)) {
1423		printk(KERN_ERR "sstfb: can't set default video mode.\n");
1424		goto fail;
1425	}
1426
1427	if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1428		printk(KERN_ERR "sstfb: can't alloc cmap memory.\n");
1429		goto fail;
1430	}
1431
1432	/* register fb */
1433	info->device = &pdev->dev;
1434	if (register_framebuffer(info) < 0) {
1435		printk(KERN_ERR "sstfb: can't register framebuffer.\n");
1436		goto fail_register;
1437	}
1438
1439	sstfb_clear_screen(info);
1440
1441#ifdef CONFIG_FB_DEVICE
1442	if (device_create_file(info->dev, &device_attrs[0]))
1443		printk(KERN_WARNING "sstfb: can't create sysfs entry.\n");
1444#endif
1445
1446	fb_info(info, "%s frame buffer device at 0x%p\n",
1447		fix->id, info->screen_base);
1448
1449	return 0;
1450
1451fail_register:
1452	fb_dealloc_cmap(&info->cmap);
1453fail:
1454	iounmap(info->screen_base);
1455fail_fb_remap:
1456	iounmap(par->mmio_vbase);
1457fail_mmio_remap:
1458	release_mem_region(fix->smem_start, 0x400000);
1459fail_fb_mem:
1460	release_mem_region(fix->mmio_start, info->fix.mmio_len);
1461fail_mmio_mem:
1462	framebuffer_release(info);
1463	return -ENXIO; 	/* no voodoo detected */
1464}
1465
1466static void sstfb_remove(struct pci_dev *pdev)
1467{
1468	struct sstfb_par *par;
1469	struct fb_info *info;
1470
1471	info = pci_get_drvdata(pdev);
1472	par = info->par;
1473
1474#ifdef CONFIG_FB_DEVICE
1475	device_remove_file(info->dev, &device_attrs[0]);
1476#endif
1477	sst_shutdown(info);
1478	iounmap(info->screen_base);
1479	iounmap(par->mmio_vbase);
1480	release_mem_region(info->fix.smem_start, 0x400000);
1481	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1482	fb_dealloc_cmap(&info->cmap);
1483	unregister_framebuffer(info);
1484	framebuffer_release(info);
1485}
1486
1487
1488static const struct pci_device_id sstfb_id_tbl[] = {
1489	{ PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ),
1490		.driver_data = ID_VOODOO1, },
1491	{ PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2),
1492		.driver_data = ID_VOODOO2, },
1493	{ 0 },
1494};
1495
1496static struct pci_driver sstfb_driver = {
1497	.name		= "sstfb",
1498	.id_table	= sstfb_id_tbl,
1499	.probe		= sstfb_probe,
1500	.remove		= sstfb_remove,
1501};
1502
1503
1504static int sstfb_init(void)
1505{
1506	char *option = NULL;
1507
1508	if (fb_modesetting_disabled("sstfb"))
1509		return -ENODEV;
1510
1511	if (fb_get_options("sstfb", &option))
1512		return -ENODEV;
1513	sstfb_setup(option);
1514
1515	return pci_register_driver(&sstfb_driver);
1516}
1517
1518static void sstfb_exit(void)
1519{
1520	pci_unregister_driver(&sstfb_driver);
1521}
1522
1523
1524module_init(sstfb_init);
1525module_exit(sstfb_exit);
1526
1527MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
1528MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
1529MODULE_LICENSE("GPL");
1530
1531module_param(mem, int, 0);
1532MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
1533module_param(vgapass, bool, 0);
1534MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
1535module_param(clipping, bool, 0);
1536MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
1537module_param(gfxclk, int, 0);
1538MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
1539module_param(slowpci, bool, 0);
1540MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
1541module_param(mode_option, charp, 0);
1542MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")");
1543