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riva_hw.c
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linux-6.19.14/drivers/video/fbdev/riva/riva_hw.c
1 /***************************************************************************\ 2|* *| 3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 4|* *| 5|* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6|* international laws. Users and possessors of this source code are *| 7|* hereby granted a nonexclusive, royalty-free copyright license to *| 8|* use this code in individual and commercial software. *| 9|* *| 10|* Any use of this source code must include, in the user documenta- *| 11|* tion and internal comments to the code, notices to the end user *| 12|* as follows: *| 13|* *| 14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 15|* *| 16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27|* *| 28|* U.S. Government End Users. This source code is a "commercial *| 29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30|* consisting of "commercial computer software" and "commercial *| 31|* computer software documentation," as such terms are used in *| 32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33|* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35|* all U.S. Government End Users acquire the source code with only *| 36|* those rights set forth herein. *| 37|* *| 38 \***************************************************************************/ 39 40/* 41 * GPL licensing note -- nVidia is allowing a liberal interpretation of 42 * the documentation restriction above, to merely say that this nVidia's 43 * copyright and disclaimer should be included with all code derived 44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 45 */ 46 47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */ 48 49#include <linux/kernel.h> 50#include <linux/pci.h> 51#include <linux/pci_ids.h> 52#include "riva_hw.h" 53#include "riva_tbl.h" 54#include "nv_type.h" 55 56/* 57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT 58 * operate identically (except TNT has more memory and better 3D quality. 59 */ 60static int nv3Busy 61( 62 RIVA_HW_INST *chip 63) 64{ 65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); 67} 68static int nv4Busy 69( 70 RIVA_HW_INST *chip 71) 72{ 73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); 75} 76static int nv10Busy 77( 78 RIVA_HW_INST *chip 79) 80{ 81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); 83} 84 85static void vgaLockUnlock 86( 87 RIVA_HW_INST *chip, 88 int Lock 89) 90{ 91 U008 cr11; 92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); 93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); 94 if(Lock) cr11 |= 0x80; 95 else cr11 &= ~0x80; 96 VGA_WR08(chip->PCIO, 0x3D5, cr11); 97} 98static void nv3LockUnlock 99( 100 RIVA_HW_INST *chip, 101 int Lock 102) 103{ 104 VGA_WR08(chip->PVIO, 0x3C4, 0x06); 105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); 106 vgaLockUnlock(chip, Lock); 107} 108static void nv4LockUnlock 109( 110 RIVA_HW_INST *chip, 111 int Lock 112) 113{ 114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); 115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); 116 vgaLockUnlock(chip, Lock); 117} 118 119static int ShowHideCursor 120( 121 RIVA_HW_INST *chip, 122 int ShowHide 123) 124{ 125 int cursor; 126 cursor = chip->CurrentState->cursor1; 127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | 128 (ShowHide & 0x01); 129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); 130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); 131 return (cursor & 0x01); 132} 133 134/****************************************************************************\ 135* * 136* The video arbitration routines calculate some "magic" numbers. Fixes * 137* the snow seen when accessing the framebuffer without it. * 138* It just works (I hope). * 139* * 140\****************************************************************************/ 141 142#define DEFAULT_GR_LWM 100 143#define DEFAULT_VID_LWM 100 144#define DEFAULT_GR_BURST_SIZE 256 145#define DEFAULT_VID_BURST_SIZE 128 146#define VIDEO 0 147#define GRAPHICS 1 148#define MPORT 2 149#define ENGINE 3 150#define GFIFO_SIZE 320 151#define GFIFO_SIZE_128 256 152#define MFIFO_SIZE 120 153#define VFIFO_SIZE 256 154 155typedef struct { 156 int gdrain_rate; 157 int vdrain_rate; 158 int mdrain_rate; 159 int gburst_size; 160 int vburst_size; 161 char vid_en; 162 char gr_en; 163 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; 164 int by_gfacc; 165 char vid_only_once; 166 char gr_only_once; 167 char first_vacc; 168 char first_gacc; 169 char first_macc; 170 int vocc; 171 int gocc; 172 int mocc; 173 char cur; 174 char engine_en; 175 char converged; 176 int priority; 177} nv3_arb_info; 178typedef struct { 179 int graphics_lwm; 180 int video_lwm; 181 int graphics_burst_size; 182 int video_burst_size; 183 int graphics_hi_priority; 184 int media_hi_priority; 185 int rtl_values; 186 int valid; 187} nv3_fifo_info; 188typedef struct { 189 char pix_bpp; 190 char enable_video; 191 char gr_during_vid; 192 char enable_mp; 193 int memory_width; 194 int video_scale; 195 int pclk_khz; 196 int mclk_khz; 197 int mem_page_miss; 198 int mem_latency; 199 char mem_aligned; 200} nv3_sim_state; 201typedef struct { 202 int graphics_lwm; 203 int video_lwm; 204 int graphics_burst_size; 205 int video_burst_size; 206 int valid; 207} nv4_fifo_info; 208typedef struct { 209 int pclk_khz; 210 int mclk_khz; 211 int nvclk_khz; 212 char mem_page_miss; 213 char mem_latency; 214 int memory_width; 215 char enable_video; 216 char gr_during_vid; 217 char pix_bpp; 218 char mem_aligned; 219 char enable_mp; 220} nv4_sim_state; 221typedef struct { 222 int graphics_lwm; 223 int video_lwm; 224 int graphics_burst_size; 225 int video_burst_size; 226 int valid; 227} nv10_fifo_info; 228typedef struct { 229 int pclk_khz; 230 int mclk_khz; 231 int nvclk_khz; 232 char mem_page_miss; 233 char mem_latency; 234 u32 memory_type; 235 int memory_width; 236 char enable_video; 237 char gr_during_vid; 238 char pix_bpp; 239 char mem_aligned; 240 char enable_mp; 241} nv10_sim_state; 242static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 243{ 244 int iter = 0; 245 int tmp; 246 int vfsize, mfsize, gfsize; 247 int mburst_size = 32; 248 int mmisses, gmisses, vmisses; 249 int misses; 250 int vlwm, glwm; 251 int last, next, cur; 252 int max_gfsize ; 253 long ns; 254 255 vlwm = 0; 256 glwm = 0; 257 vfsize = 0; 258 gfsize = 0; 259 cur = ainfo->cur; 260 mmisses = 2; 261 gmisses = 2; 262 vmisses = 2; 263 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; 264 else max_gfsize = GFIFO_SIZE; 265 max_gfsize = GFIFO_SIZE; 266 while (1) 267 { 268 if (ainfo->vid_en) 269 { 270 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; 271 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; 272 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; 273 vfsize = ns * ainfo->vdrain_rate / 1000000; 274 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; 275 } 276 if (state->enable_mp) 277 { 278 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; 279 } 280 if (ainfo->gr_en) 281 { 282 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; 283 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; 284 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; 285 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; 286 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; 287 } 288 mfsize = 0; 289 if (!state->gr_during_vid && ainfo->vid_en) 290 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) 291 next = VIDEO; 292 else if (ainfo->mocc < 0) 293 next = MPORT; 294 else if (ainfo->gocc< ainfo->by_gfacc) 295 next = GRAPHICS; 296 else return (0); 297 else switch (ainfo->priority) 298 { 299 case VIDEO: 300 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 301 next = VIDEO; 302 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 303 next = GRAPHICS; 304 else if (ainfo->mocc<0) 305 next = MPORT; 306 else return (0); 307 break; 308 case GRAPHICS: 309 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 310 next = GRAPHICS; 311 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 312 next = VIDEO; 313 else if (ainfo->mocc<0) 314 next = MPORT; 315 else return (0); 316 break; 317 default: 318 if (ainfo->mocc<0) 319 next = MPORT; 320 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 321 next = GRAPHICS; 322 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 323 next = VIDEO; 324 else return (0); 325 break; 326 } 327 last = cur; 328 cur = next; 329 iter++; 330 switch (cur) 331 { 332 case VIDEO: 333 if (last==cur) misses = 0; 334 else if (ainfo->first_vacc) misses = vmisses; 335 else misses = 1; 336 ainfo->first_vacc = 0; 337 if (last!=cur) 338 { 339 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 340 vlwm = ns * ainfo->vdrain_rate/ 1000000; 341 vlwm = ainfo->vocc - vlwm; 342 } 343 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; 344 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; 345 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; 346 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; 347 break; 348 case GRAPHICS: 349 if (last==cur) misses = 0; 350 else if (ainfo->first_gacc) misses = gmisses; 351 else misses = 1; 352 ainfo->first_gacc = 0; 353 if (last!=cur) 354 { 355 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; 356 glwm = ns * ainfo->gdrain_rate/1000000; 357 glwm = ainfo->gocc - glwm; 358 } 359 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; 360 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; 361 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; 362 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; 363 break; 364 default: 365 if (last==cur) misses = 0; 366 else if (ainfo->first_macc) misses = mmisses; 367 else misses = 1; 368 ainfo->first_macc = 0; 369 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; 370 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; 371 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; 372 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; 373 break; 374 } 375 if (iter>100) 376 { 377 ainfo->converged = 0; 378 return (1); 379 } 380 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; 381 tmp = ns * ainfo->gdrain_rate/1000000; 382 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) 383 { 384 ainfo->converged = 0; 385 return (1); 386 } 387 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; 388 tmp = ns * ainfo->vdrain_rate/1000000; 389 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) 390 { 391 ainfo->converged = 0; 392 return (1); 393 } 394 if (abs(ainfo->gocc) > max_gfsize) 395 { 396 ainfo->converged = 0; 397 return (1); 398 } 399 if (abs(ainfo->vocc) > VFIFO_SIZE) 400 { 401 ainfo->converged = 0; 402 return (1); 403 } 404 if (abs(ainfo->mocc) > MFIFO_SIZE) 405 { 406 ainfo->converged = 0; 407 return (1); 408 } 409 if (abs(vfsize) > VFIFO_SIZE) 410 { 411 ainfo->converged = 0; 412 return (1); 413 } 414 if (abs(gfsize) > max_gfsize) 415 { 416 ainfo->converged = 0; 417 return (1); 418 } 419 if (abs(mfsize) > MFIFO_SIZE) 420 { 421 ainfo->converged = 0; 422 return (1); 423 } 424 } 425} 426static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 427{ 428 long ens, vns, mns, gns; 429 int mmisses, gmisses, vmisses, eburst_size, mburst_size; 430 int refresh_cycle; 431 432 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; 433 mmisses = 2; 434 if (state->mem_aligned) gmisses = 2; 435 else gmisses = 3; 436 vmisses = 2; 437 eburst_size = state->memory_width * 1; 438 mburst_size = 32; 439 if (!state->mclk_khz) 440 return (0); 441 442 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 443 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; 444 ainfo->wcmocc = 0; 445 ainfo->wcgocc = 0; 446 ainfo->wcvocc = 0; 447 ainfo->wcvlwm = 0; 448 ainfo->wcglwm = 0; 449 ainfo->engine_en = 1; 450 ainfo->converged = 1; 451 if (ainfo->engine_en) 452 { 453 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; 454 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; 455 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; 456 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; 457 ainfo->cur = ENGINE; 458 ainfo->first_vacc = 1; 459 ainfo->first_gacc = 1; 460 ainfo->first_macc = 1; 461 nv3_iterate(res_info, state,ainfo); 462 } 463 if (state->enable_mp) 464 { 465 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 466 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; 467 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; 468 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; 469 ainfo->cur = MPORT; 470 ainfo->first_vacc = 1; 471 ainfo->first_gacc = 1; 472 ainfo->first_macc = 0; 473 nv3_iterate(res_info, state,ainfo); 474 } 475 if (ainfo->gr_en) 476 { 477 ainfo->first_vacc = 1; 478 ainfo->first_gacc = 0; 479 ainfo->first_macc = 1; 480 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 481 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; 482 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; 483 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; 484 ainfo->cur = GRAPHICS; 485 nv3_iterate(res_info, state,ainfo); 486 } 487 if (ainfo->vid_en) 488 { 489 ainfo->first_vacc = 0; 490 ainfo->first_gacc = 1; 491 ainfo->first_macc = 1; 492 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 493 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; 494 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; 495 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; 496 ainfo->cur = VIDEO; 497 nv3_iterate(res_info, state, ainfo); 498 } 499 if (ainfo->converged) 500 { 501 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16; 502 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32; 503 res_info->graphics_burst_size = ainfo->gburst_size; 504 res_info->video_burst_size = ainfo->vburst_size; 505 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); 506 res_info->media_hi_priority = (ainfo->priority == MPORT); 507 if (res_info->video_lwm > 160) 508 { 509 res_info->graphics_lwm = 256; 510 res_info->video_lwm = 128; 511 res_info->graphics_burst_size = 64; 512 res_info->video_burst_size = 64; 513 res_info->graphics_hi_priority = 0; 514 res_info->media_hi_priority = 0; 515 ainfo->converged = 0; 516 return (0); 517 } 518 if (res_info->video_lwm > 128) 519 { 520 res_info->video_lwm = 128; 521 } 522 return (1); 523 } 524 else 525 { 526 res_info->graphics_lwm = 256; 527 res_info->video_lwm = 128; 528 res_info->graphics_burst_size = 64; 529 res_info->video_burst_size = 64; 530 res_info->graphics_hi_priority = 0; 531 res_info->media_hi_priority = 0; 532 return (0); 533 } 534} 535static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 536{ 537 int done, g,v, p; 538 539 done = 0; 540 for (p=0; p < 2; p++) 541 { 542 for (g=128 ; g > 32; g= g>> 1) 543 { 544 for (v=128; v >=32; v = v>> 1) 545 { 546 ainfo->priority = p; 547 ainfo->gburst_size = g; 548 ainfo->vburst_size = v; 549 done = nv3_arb(res_info, state,ainfo); 550 if (done && (g==128)) 551 if ((res_info->graphics_lwm + g) > 256) 552 done = 0; 553 if (done) 554 goto Done; 555 } 556 } 557 } 558 559 Done: 560 return done; 561} 562static void nv3CalcArbitration 563( 564 nv3_fifo_info * res_info, 565 nv3_sim_state * state 566) 567{ 568 nv3_fifo_info save_info; 569 nv3_arb_info ainfo; 570 char res_gr, res_vid; 571 572 ainfo.gr_en = 1; 573 ainfo.vid_en = state->enable_video; 574 ainfo.vid_only_once = 0; 575 ainfo.gr_only_once = 0; 576 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); 577 ainfo.vdrain_rate = (int) state->pclk_khz * 2; 578 if (state->video_scale != 0) 579 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; 580 ainfo.mdrain_rate = 33000; 581 res_info->rtl_values = 0; 582 if (!state->gr_during_vid && state->enable_video) 583 { 584 ainfo.gr_only_once = 1; 585 ainfo.gr_en = 1; 586 ainfo.gdrain_rate = 0; 587 res_vid = nv3_get_param(res_info, state, &ainfo); 588 res_vid = ainfo.converged; 589 save_info.video_lwm = res_info->video_lwm; 590 save_info.video_burst_size = res_info->video_burst_size; 591 ainfo.vid_en = 1; 592 ainfo.vid_only_once = 1; 593 ainfo.gr_en = 1; 594 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); 595 ainfo.vdrain_rate = 0; 596 res_gr = nv3_get_param(res_info, state, &ainfo); 597 res_gr = ainfo.converged; 598 res_info->video_lwm = save_info.video_lwm; 599 res_info->video_burst_size = save_info.video_burst_size; 600 res_info->valid = res_gr & res_vid; 601 } 602 else 603 { 604 if (!ainfo.gr_en) ainfo.gdrain_rate = 0; 605 if (!ainfo.vid_en) ainfo.vdrain_rate = 0; 606 res_gr = nv3_get_param(res_info, state, &ainfo); 607 res_info->valid = ainfo.converged; 608 } 609} 610static void nv3UpdateArbitrationSettings 611( 612 unsigned VClk, 613 unsigned pixelDepth, 614 unsigned *burst, 615 unsigned *lwm, 616 RIVA_HW_INST *chip 617) 618{ 619 nv3_fifo_info fifo_data; 620 nv3_sim_state sim_data; 621 unsigned int M, N, P, pll, MClk; 622 623 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 624 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 625 MClk = (N * chip->CrystalFreqKHz / M) >> P; 626 sim_data.pix_bpp = (char)pixelDepth; 627 sim_data.enable_video = 0; 628 sim_data.enable_mp = 0; 629 sim_data.video_scale = 1; 630 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 631 128 : 64; 632 sim_data.memory_width = 128; 633 634 sim_data.mem_latency = 9; 635 sim_data.mem_aligned = 1; 636 sim_data.mem_page_miss = 11; 637 sim_data.gr_during_vid = 0; 638 sim_data.pclk_khz = VClk; 639 sim_data.mclk_khz = MClk; 640 nv3CalcArbitration(&fifo_data, &sim_data); 641 if (fifo_data.valid) 642 { 643 int b = fifo_data.graphics_burst_size >> 4; 644 *burst = 0; 645 while (b >>= 1) 646 (*burst)++; 647 *lwm = fifo_data.graphics_lwm >> 3; 648 } 649 else 650 { 651 *lwm = 0x24; 652 *burst = 0x2; 653 } 654} 655static void nv4CalcArbitration 656( 657 nv4_fifo_info *fifo, 658 nv4_sim_state *arb 659) 660{ 661 int data, pagemiss, cas,width, video_enable, bpp; 662 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; 663 int found, mclk_extra, mclk_loop, cbs, m1, p1; 664 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 665 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; 666 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; 667 668 fifo->valid = 1; 669 pclk_freq = arb->pclk_khz; 670 mclk_freq = arb->mclk_khz; 671 nvclk_freq = arb->nvclk_khz; 672 pagemiss = arb->mem_page_miss; 673 cas = arb->mem_latency; 674 width = arb->memory_width >> 6; 675 video_enable = arb->enable_video; 676 bpp = arb->pix_bpp; 677 mp_enable = arb->enable_mp; 678 clwm = 0; 679 vlwm = 0; 680 cbs = 128; 681 pclks = 2; 682 nvclks = 2; 683 nvclks += 2; 684 nvclks += 1; 685 mclks = 5; 686 mclks += 3; 687 mclks += 1; 688 mclks += cas; 689 mclks += 1; 690 mclks += 1; 691 mclks += 1; 692 mclks += 1; 693 mclk_extra = 3; 694 nvclks += 2; 695 nvclks += 1; 696 nvclks += 1; 697 nvclks += 1; 698 if (mp_enable) 699 mclks+=4; 700 nvclks += 0; 701 pclks += 0; 702 found = 0; 703 vbs = 0; 704 while (found != 1) 705 { 706 fifo->valid = 1; 707 found = 1; 708 mclk_loop = mclks+mclk_extra; 709 us_m = mclk_loop *1000*1000 / mclk_freq; 710 us_n = nvclks*1000*1000 / nvclk_freq; 711 us_p = nvclks*1000*1000 / pclk_freq; 712 if (video_enable) 713 { 714 video_drain_rate = pclk_freq * 2; 715 crtc_drain_rate = pclk_freq * bpp/8; 716 vpagemiss = 2; 717 vpagemiss += 1; 718 crtpagemiss = 2; 719 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; 720 if (nvclk_freq * 2 > mclk_freq * width) 721 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; 722 else 723 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; 724 us_video = vpm_us + us_m + us_n + us_p + video_fill_us; 725 vlwm = us_video * video_drain_rate/(1000*1000); 726 vlwm++; 727 vbs = 128; 728 if (vlwm > 128) vbs = 64; 729 if (vlwm > (256-64)) vbs = 32; 730 if (nvclk_freq * 2 > mclk_freq * width) 731 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; 732 else 733 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; 734 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 735 us_crt = 736 us_video 737 +video_fill_us 738 +cpm_us 739 +us_m + us_n +us_p 740 ; 741 clwm = us_crt * crtc_drain_rate/(1000*1000); 742 clwm++; 743 } 744 else 745 { 746 crtc_drain_rate = pclk_freq * bpp/8; 747 crtpagemiss = 2; 748 crtpagemiss += 1; 749 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 750 us_crt = cpm_us + us_m + us_n + us_p ; 751 clwm = us_crt * crtc_drain_rate/(1000*1000); 752 clwm++; 753 } 754 m1 = clwm + cbs - 512; 755 p1 = m1 * pclk_freq / mclk_freq; 756 p1 = p1 * bpp / 8; 757 if ((p1 < m1) && (m1 > 0)) 758 { 759 fifo->valid = 0; 760 found = 0; 761 if (mclk_extra ==0) found = 1; 762 mclk_extra--; 763 } 764 else if (video_enable) 765 { 766 if ((clwm > 511) || (vlwm > 255)) 767 { 768 fifo->valid = 0; 769 found = 0; 770 if (mclk_extra ==0) found = 1; 771 mclk_extra--; 772 } 773 } 774 else 775 { 776 if (clwm > 519) 777 { 778 fifo->valid = 0; 779 found = 0; 780 if (mclk_extra ==0) found = 1; 781 mclk_extra--; 782 } 783 } 784 if (clwm < 384) clwm = 384; 785 if (vlwm < 128) vlwm = 128; 786 data = (int)(clwm); 787 fifo->graphics_lwm = data; 788 fifo->graphics_burst_size = 128; 789 data = (int)((vlwm+15)); 790 fifo->video_lwm = data; 791 fifo->video_burst_size = vbs; 792 } 793} 794static void nv4UpdateArbitrationSettings 795( 796 unsigned VClk, 797 unsigned pixelDepth, 798 unsigned *burst, 799 unsigned *lwm, 800 RIVA_HW_INST *chip 801) 802{ 803 nv4_fifo_info fifo_data; 804 nv4_sim_state sim_data; 805 unsigned int M, N, P, pll, MClk, NVClk, cfg1; 806 807 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 808 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 809 MClk = (N * chip->CrystalFreqKHz / M) >> P; 810 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 811 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 812 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 813 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); 814 sim_data.pix_bpp = (char)pixelDepth; 815 sim_data.enable_video = 0; 816 sim_data.enable_mp = 0; 817 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 818 128 : 64; 819 sim_data.mem_latency = (char)cfg1 & 0x0F; 820 sim_data.mem_aligned = 1; 821 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); 822 sim_data.gr_during_vid = 0; 823 sim_data.pclk_khz = VClk; 824 sim_data.mclk_khz = MClk; 825 sim_data.nvclk_khz = NVClk; 826 nv4CalcArbitration(&fifo_data, &sim_data); 827 if (fifo_data.valid) 828 { 829 int b = fifo_data.graphics_burst_size >> 4; 830 *burst = 0; 831 while (b >>= 1) 832 (*burst)++; 833 *lwm = fifo_data.graphics_lwm >> 3; 834 } 835} 836static void nv10CalcArbitration 837( 838 nv10_fifo_info *fifo, 839 nv10_sim_state *arb 840) 841{ 842 int data, pagemiss, width, video_enable, bpp; 843 int nvclks, mclks, pclks, vpagemiss, crtpagemiss; 844 int nvclk_fill; 845 int found, mclk_extra, mclk_loop, cbs, m1; 846 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 847 int us_m, us_m_min, us_n, us_p, crtc_drain_rate; 848 int vus_m; 849 int vpm_us, us_video, cpm_us, us_crt,clwm; 850 int clwm_rnd_down; 851 int m2us, us_pipe_min, p1clk, p2; 852 int min_mclk_extra; 853 int us_min_mclk_extra; 854 855 fifo->valid = 1; 856 pclk_freq = arb->pclk_khz; /* freq in KHz */ 857 mclk_freq = arb->mclk_khz; 858 nvclk_freq = arb->nvclk_khz; 859 pagemiss = arb->mem_page_miss; 860 width = arb->memory_width/64; 861 video_enable = arb->enable_video; 862 bpp = arb->pix_bpp; 863 mp_enable = arb->enable_mp; 864 clwm = 0; 865 866 cbs = 512; 867 868 pclks = 4; /* lwm detect. */ 869 870 nvclks = 3; /* lwm -> sync. */ 871 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ 872 873 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ 874 875 mclks += 1; /* arb_hp_req */ 876 mclks += 5; /* ap_hp_req tiling pipeline */ 877 878 mclks += 2; /* tc_req latency fifo */ 879 mclks += 2; /* fb_cas_n_ memory request to fbio block */ 880 mclks += 7; /* sm_d_rdv data returned from fbio block */ 881 882 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ 883 if (arb->memory_type == 0) 884 if (arb->memory_width == 64) /* 64 bit bus */ 885 mclks += 4; 886 else 887 mclks += 2; 888 else 889 if (arb->memory_width == 64) /* 64 bit bus */ 890 mclks += 2; 891 else 892 mclks += 1; 893 894 if ((!video_enable) && (arb->memory_width == 128)) 895 { 896 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ 897 min_mclk_extra = 17; 898 } 899 else 900 { 901 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ 902 /* mclk_extra = 4; */ /* Margin of error */ 903 min_mclk_extra = 18; 904 } 905 906 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */ 907 nvclks += 1; /* fbi_d_rdv_n */ 908 nvclks += 1; /* Fbi_d_rdata */ 909 nvclks += 1; /* crtfifo load */ 910 911 if(mp_enable) 912 mclks+=4; /* Mp can get in with a burst of 8. */ 913 /* Extra clocks determined by heuristics */ 914 915 nvclks += 0; 916 pclks += 0; 917 found = 0; 918 while(found != 1) { 919 fifo->valid = 1; 920 found = 1; 921 mclk_loop = mclks+mclk_extra; 922 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ 923 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ 924 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq; 925 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */ 926 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */ 927 us_pipe_min = us_m_min + us_n + us_p; 928 929 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ 930 931 if(video_enable) { 932 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ 933 934 vpagemiss = 1; /* self generating page miss */ 935 vpagemiss += 1; /* One higher priority before */ 936 937 crtpagemiss = 2; /* self generating page miss */ 938 if(mp_enable) 939 crtpagemiss += 1; /* if MA0 conflict */ 940 941 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; 942 943 us_video = vpm_us + vus_m; /* Video has separate read return path */ 944 945 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 946 us_crt = 947 us_video /* Wait for video */ 948 +cpm_us /* CRT Page miss */ 949 +us_m + us_n +us_p /* other latency */ 950 ; 951 952 clwm = us_crt * crtc_drain_rate/(1000*1000); 953 clwm++; /* fixed point <= float_point - 1. Fixes that */ 954 } else { 955 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ 956 957 crtpagemiss = 1; /* self generating page miss */ 958 crtpagemiss += 1; /* MA0 page miss */ 959 if(mp_enable) 960 crtpagemiss += 1; /* if MA0 conflict */ 961 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 962 us_crt = cpm_us + us_m + us_n + us_p ; 963 clwm = us_crt * crtc_drain_rate/(1000*1000); 964 clwm++; /* fixed point <= float_point - 1. Fixes that */ 965 966 /* 967 // 968 // Another concern, only for high pclks so don't do this 969 // with video: 970 // What happens if the latency to fetch the cbs is so large that 971 // fifo empties. In that case we need to have an alternate clwm value 972 // based off the total burst fetch 973 // 974 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; 975 us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq; 976 clwm_mt = us_crt * crtc_drain_rate/(1000*1000); 977 clwm_mt ++; 978 if(clwm_mt > clwm) 979 clwm = clwm_mt; 980 */ 981 /* Finally, a heuristic check when width == 64 bits */ 982 if(width == 1){ 983 nvclk_fill = nvclk_freq * 8; 984 if(crtc_drain_rate * 100 >= nvclk_fill * 102) 985 clwm = 0xfff; /*Large number to fail */ 986 987 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) { 988 clwm = 1024; 989 cbs = 512; 990 } 991 } 992 } 993 994 995 /* 996 Overfill check: 997 998 */ 999 1000 clwm_rnd_down = ((int)clwm/8)*8; 1001 if (clwm_rnd_down < clwm) 1002 clwm += 8; 1003 1004 m1 = clwm + cbs - 1024; /* Amount of overfill */ 1005 m2us = us_pipe_min + us_min_mclk_extra; 1006 1007 /* pclk cycles to drain */ 1008 p1clk = m2us * pclk_freq/(1000*1000); 1009 p2 = p1clk * bpp / 8; /* bytes drained. */ 1010 1011 if((p2 < m1) && (m1 > 0)) { 1012 fifo->valid = 0; 1013 found = 0; 1014 if(min_mclk_extra == 0) { 1015 if(cbs <= 32) { 1016 found = 1; /* Can't adjust anymore! */ 1017 } else { 1018 cbs = cbs/2; /* reduce the burst size */ 1019 } 1020 } else { 1021 min_mclk_extra--; 1022 } 1023 } else { 1024 if (clwm > 1023){ /* Have some margin */ 1025 fifo->valid = 0; 1026 found = 0; 1027 if(min_mclk_extra == 0) 1028 found = 1; /* Can't adjust anymore! */ 1029 else 1030 min_mclk_extra--; 1031 } 1032 } 1033 1034 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; 1035 data = (int)(clwm); 1036 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ 1037 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; 1038 1039 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ 1040 fifo->video_lwm = 1024; fifo->video_burst_size = 512; 1041 } 1042} 1043static void nv10UpdateArbitrationSettings 1044( 1045 unsigned VClk, 1046 unsigned pixelDepth, 1047 unsigned *burst, 1048 unsigned *lwm, 1049 RIVA_HW_INST *chip 1050) 1051{ 1052 nv10_fifo_info fifo_data; 1053 nv10_sim_state sim_data; 1054 unsigned int M, N, P, pll, MClk, NVClk, cfg1; 1055 1056 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 1057 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1058 MClk = (N * chip->CrystalFreqKHz / M) >> P; 1059 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 1060 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1061 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 1062 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); 1063 sim_data.pix_bpp = (char)pixelDepth; 1064 sim_data.enable_video = 0; 1065 sim_data.enable_mp = 0; 1066 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? 1067 1 : 0; 1068 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 1069 128 : 64; 1070 sim_data.mem_latency = (char)cfg1 & 0x0F; 1071 sim_data.mem_aligned = 1; 1072 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); 1073 sim_data.gr_during_vid = 0; 1074 sim_data.pclk_khz = VClk; 1075 sim_data.mclk_khz = MClk; 1076 sim_data.nvclk_khz = NVClk; 1077 nv10CalcArbitration(&fifo_data, &sim_data); 1078 if (fifo_data.valid) 1079 { 1080 int b = fifo_data.graphics_burst_size >> 4; 1081 *burst = 0; 1082 while (b >>= 1) 1083 (*burst)++; 1084 *lwm = fifo_data.graphics_lwm >> 3; 1085 } 1086} 1087 1088static void nForceUpdateArbitrationSettings 1089( 1090 unsigned VClk, 1091 unsigned pixelDepth, 1092 unsigned *burst, 1093 unsigned *lwm, 1094 RIVA_HW_INST *chip, 1095 struct pci_dev *pdev 1096) 1097{ 1098 nv10_fifo_info fifo_data; 1099 nv10_sim_state sim_data; 1100 unsigned int M, N, P, pll, MClk, NVClk; 1101 unsigned int uMClkPostDiv; 1102 struct pci_dev *dev; 1103 int domain = pci_domain_nr(pdev->bus); 1104 1105 dev = pci_get_domain_bus_and_slot(domain, 0, 3); 1106 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); 1107 pci_dev_put(dev); 1108 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; 1109 1110 if(!uMClkPostDiv) uMClkPostDiv = 4; 1111 MClk = 400000 / uMClkPostDiv; 1112 1113 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 1114 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1115 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 1116 sim_data.pix_bpp = (char)pixelDepth; 1117 sim_data.enable_video = 0; 1118 sim_data.enable_mp = 0; 1119 1120 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 1121 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); 1122 pci_dev_put(dev); 1123 sim_data.memory_type = (sim_data.memory_type >> 12) & 1; 1124 1125 sim_data.memory_width = 64; 1126 sim_data.mem_latency = 3; 1127 sim_data.mem_aligned = 1; 1128 sim_data.mem_page_miss = 10; 1129 sim_data.gr_during_vid = 0; 1130 sim_data.pclk_khz = VClk; 1131 sim_data.mclk_khz = MClk; 1132 sim_data.nvclk_khz = NVClk; 1133 nv10CalcArbitration(&fifo_data, &sim_data); 1134 if (fifo_data.valid) 1135 { 1136 int b = fifo_data.graphics_burst_size >> 4; 1137 *burst = 0; 1138 while (b >>= 1) 1139 (*burst)++; 1140 *lwm = fifo_data.graphics_lwm >> 3; 1141 } 1142} 1143 1144/****************************************************************************\ 1145* * 1146* RIVA Mode State Routines * 1147* * 1148\****************************************************************************/ 1149 1150/* 1151 * Calculate the Video Clock parameters for the PLL. 1152 */ 1153static int CalcVClock 1154( 1155 int clockIn, 1156 int *clockOut, 1157 int *mOut, 1158 int *nOut, 1159 int *pOut, 1160 RIVA_HW_INST *chip 1161) 1162{ 1163 unsigned lowM, highM, highP; 1164 unsigned DeltaNew, DeltaOld; 1165 unsigned VClk, Freq; 1166 unsigned M, N, P; 1167 1168 DeltaOld = 0xFFFFFFFF; 1169 1170 VClk = (unsigned)clockIn; 1171 1172 if (chip->CrystalFreqKHz == 13500) 1173 { 1174 lowM = 7; 1175 highM = 13 - (chip->Architecture == NV_ARCH_03); 1176 } 1177 else 1178 { 1179 lowM = 8; 1180 highM = 14 - (chip->Architecture == NV_ARCH_03); 1181 } 1182 1183 highP = 4 - (chip->Architecture == NV_ARCH_03); 1184 for (P = 0; P <= highP; P ++) 1185 { 1186 Freq = VClk << P; 1187 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) 1188 { 1189 for (M = lowM; M <= highM; M++) 1190 { 1191 N = (VClk << P) * M / chip->CrystalFreqKHz; 1192 if(N <= 255) { 1193 Freq = (chip->CrystalFreqKHz * N / M) >> P; 1194 if (Freq > VClk) 1195 DeltaNew = Freq - VClk; 1196 else 1197 DeltaNew = VClk - Freq; 1198 if (DeltaNew < DeltaOld) 1199 { 1200 *mOut = M; 1201 *nOut = N; 1202 *pOut = P; 1203 *clockOut = Freq; 1204 DeltaOld = DeltaNew; 1205 } 1206 } 1207 } 1208 } 1209 } 1210 1211 /* non-zero: M/N/P/clock values assigned. zero: error (not set) */ 1212 return (DeltaOld != 0xFFFFFFFF); 1213} 1214/* 1215 * Calculate extended mode parameters (SVGA) and save in a 1216 * mode state structure. 1217 */ 1218int CalcStateExt 1219( 1220 RIVA_HW_INST *chip, 1221 RIVA_HW_STATE *state, 1222 struct pci_dev *pdev, 1223 int bpp, 1224 int width, 1225 int hDisplaySize, 1226 int height, 1227 int dotClock 1228) 1229{ 1230 int pixelDepth; 1231 int VClk, m, n, p; 1232 1233 /* 1234 * Save mode parameters. 1235 */ 1236 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ 1237 state->width = width; 1238 state->height = height; 1239 /* 1240 * Extended RIVA registers. 1241 */ 1242 pixelDepth = (bpp + 1)/8; 1243 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip)) 1244 return -EINVAL; 1245 1246 switch (chip->Architecture) 1247 { 1248 case NV_ARCH_03: 1249 nv3UpdateArbitrationSettings(VClk, 1250 pixelDepth * 8, 1251 &(state->arbitration0), 1252 &(state->arbitration1), 1253 chip); 1254 state->cursor0 = 0x00; 1255 state->cursor1 = 0x78; 1256 state->cursor2 = 0x00000000; 1257 state->pllsel = 0x10010100; 1258 state->config = ((width + 31)/32) 1259 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) 1260 | 0x1000; 1261 state->general = 0x00100100; 1262 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; 1263 break; 1264 case NV_ARCH_04: 1265 nv4UpdateArbitrationSettings(VClk, 1266 pixelDepth * 8, 1267 &(state->arbitration0), 1268 &(state->arbitration1), 1269 chip); 1270 state->cursor0 = 0x00; 1271 state->cursor1 = 0xFC; 1272 state->cursor2 = 0x00000000; 1273 state->pllsel = 0x10000700; 1274 state->config = 0x00001114; 1275 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 1276 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 1277 break; 1278 case NV_ARCH_10: 1279 case NV_ARCH_20: 1280 case NV_ARCH_30: 1281 if((chip->Chipset == NV_CHIP_IGEFORCE2) || 1282 (chip->Chipset == NV_CHIP_0x01F0)) 1283 { 1284 nForceUpdateArbitrationSettings(VClk, 1285 pixelDepth * 8, 1286 &(state->arbitration0), 1287 &(state->arbitration1), 1288 chip, pdev); 1289 } else { 1290 nv10UpdateArbitrationSettings(VClk, 1291 pixelDepth * 8, 1292 &(state->arbitration0), 1293 &(state->arbitration1), 1294 chip); 1295 } 1296 state->cursor0 = 0x80 | (chip->CursorStart >> 17); 1297 state->cursor1 = (chip->CursorStart >> 11) << 2; 1298 state->cursor2 = chip->CursorStart >> 24; 1299 state->pllsel = 0x10000700; 1300 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); 1301 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 1302 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 1303 break; 1304 } 1305 1306 /* Paul Richards: below if block borks things in kernel for some reason */ 1307 /* Tony: Below is needed to set hardware in DirectColor */ 1308 if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) 1309 state->general |= 0x00000030; 1310 1311 state->vpll = (p << 16) | (n << 8) | m; 1312 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; 1313 state->pixel = pixelDepth > 2 ? 3 : pixelDepth; 1314 state->offset0 = 1315 state->offset1 = 1316 state->offset2 = 1317 state->offset3 = 0; 1318 state->pitch0 = 1319 state->pitch1 = 1320 state->pitch2 = 1321 state->pitch3 = pixelDepth * width; 1322 1323 return 0; 1324} 1325/* 1326 * Load fixed function state and pre-calculated/stored state. 1327 */ 1328#define LOAD_FIXED_STATE(tbl,dev) \ 1329 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ 1330 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1]) 1331#define LOAD_FIXED_STATE_8BPP(tbl,dev) \ 1332 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ 1333 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1]) 1334#define LOAD_FIXED_STATE_15BPP(tbl,dev) \ 1335 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ 1336 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1]) 1337#define LOAD_FIXED_STATE_16BPP(tbl,dev) \ 1338 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ 1339 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1]) 1340#define LOAD_FIXED_STATE_32BPP(tbl,dev) \ 1341 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ 1342 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1]) 1343 1344static void UpdateFifoState 1345( 1346 RIVA_HW_INST *chip 1347) 1348{ 1349 int i; 1350 1351 switch (chip->Architecture) 1352 { 1353 case NV_ARCH_04: 1354 LOAD_FIXED_STATE(nv4,FIFO); 1355 chip->Tri03 = NULL; 1356 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); 1357 break; 1358 case NV_ARCH_10: 1359 case NV_ARCH_20: 1360 case NV_ARCH_30: 1361 /* 1362 * Initialize state for the RivaTriangle3D05 routines. 1363 */ 1364 LOAD_FIXED_STATE(nv10tri05,PGRAPH); 1365 LOAD_FIXED_STATE(nv10,FIFO); 1366 chip->Tri03 = NULL; 1367 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); 1368 break; 1369 } 1370} 1371static void LoadStateExt 1372( 1373 RIVA_HW_INST *chip, 1374 RIVA_HW_STATE *state 1375) 1376{ 1377 int i; 1378 1379 /* 1380 * Load HW fixed function state. 1381 */ 1382 LOAD_FIXED_STATE(Riva,PMC); 1383 LOAD_FIXED_STATE(Riva,PTIMER); 1384 switch (chip->Architecture) 1385 { 1386 case NV_ARCH_03: 1387 /* 1388 * Make sure frame buffer config gets set before loading PRAMIN. 1389 */ 1390 NV_WR32(chip->PFB, 0x00000200, state->config); 1391 LOAD_FIXED_STATE(nv3,PFIFO); 1392 LOAD_FIXED_STATE(nv3,PRAMIN); 1393 LOAD_FIXED_STATE(nv3,PGRAPH); 1394 switch (state->bpp) 1395 { 1396 case 15: 1397 case 16: 1398 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); 1399 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); 1400 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1401 break; 1402 case 24: 1403 case 32: 1404 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); 1405 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); 1406 chip->Tri03 = NULL; 1407 break; 1408 case 8: 1409 default: 1410 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); 1411 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); 1412 chip->Tri03 = NULL; 1413 break; 1414 } 1415 for (i = 0x00000; i < 0x00800; i++) 1416 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); 1417 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); 1418 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); 1419 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); 1420 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); 1421 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); 1422 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); 1423 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); 1424 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); 1425 break; 1426 case NV_ARCH_04: 1427 /* 1428 * Make sure frame buffer config gets set before loading PRAMIN. 1429 */ 1430 NV_WR32(chip->PFB, 0x00000200, state->config); 1431 LOAD_FIXED_STATE(nv4,PFIFO); 1432 LOAD_FIXED_STATE(nv4,PRAMIN); 1433 LOAD_FIXED_STATE(nv4,PGRAPH); 1434 switch (state->bpp) 1435 { 1436 case 15: 1437 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); 1438 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); 1439 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1440 break; 1441 case 16: 1442 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); 1443 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); 1444 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1445 break; 1446 case 24: 1447 case 32: 1448 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); 1449 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); 1450 chip->Tri03 = NULL; 1451 break; 1452 case 8: 1453 default: 1454 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); 1455 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); 1456 chip->Tri03 = NULL; 1457 break; 1458 } 1459 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); 1460 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); 1461 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); 1462 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); 1463 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); 1464 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); 1465 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); 1466 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); 1467 break; 1468 case NV_ARCH_10: 1469 case NV_ARCH_20: 1470 case NV_ARCH_30: 1471 if(chip->twoHeads) { 1472 VGA_WR08(chip->PCIO, 0x03D4, 0x44); 1473 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); 1474 chip->LockUnlock(chip, 0); 1475 } 1476 1477 LOAD_FIXED_STATE(nv10,PFIFO); 1478 LOAD_FIXED_STATE(nv10,PRAMIN); 1479 LOAD_FIXED_STATE(nv10,PGRAPH); 1480 switch (state->bpp) 1481 { 1482 case 15: 1483 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); 1484 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); 1485 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1486 break; 1487 case 16: 1488 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); 1489 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); 1490 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1491 break; 1492 case 24: 1493 case 32: 1494 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); 1495 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); 1496 chip->Tri03 = NULL; 1497 break; 1498 case 8: 1499 default: 1500 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); 1501 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); 1502 chip->Tri03 = NULL; 1503 break; 1504 } 1505 1506 if(chip->Architecture == NV_ARCH_10) { 1507 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); 1508 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); 1509 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); 1510 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); 1511 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); 1512 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); 1513 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); 1514 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); 1515 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); 1516 } else { 1517 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); 1518 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); 1519 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); 1520 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); 1521 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); 1522 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); 1523 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); 1524 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); 1525 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); 1526 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); 1527 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); 1528 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); 1529 } 1530 if(chip->twoHeads) { 1531 NV_WR32(chip->PCRTC0, 0x00000860, state->head); 1532 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); 1533 } 1534 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); 1535 1536 NV_WR32(chip->PMC, 0x00008704, 1); 1537 NV_WR32(chip->PMC, 0x00008140, 0); 1538 NV_WR32(chip->PMC, 0x00008920, 0); 1539 NV_WR32(chip->PMC, 0x00008924, 0); 1540 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); 1541 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); 1542 NV_WR32(chip->PMC, 0x00001588, 0); 1543 1544 NV_WR32(chip->PFB, 0x00000240, 0); 1545 NV_WR32(chip->PFB, 0x00000250, 0); 1546 NV_WR32(chip->PFB, 0x00000260, 0); 1547 NV_WR32(chip->PFB, 0x00000270, 0); 1548 NV_WR32(chip->PFB, 0x00000280, 0); 1549 NV_WR32(chip->PFB, 0x00000290, 0); 1550 NV_WR32(chip->PFB, 0x000002A0, 0); 1551 NV_WR32(chip->PFB, 0x000002B0, 0); 1552 1553 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); 1554 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); 1555 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); 1556 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); 1557 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); 1558 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); 1559 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); 1560 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); 1561 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); 1562 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); 1563 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); 1564 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); 1565 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); 1566 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); 1567 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); 1568 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); 1569 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); 1570 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); 1571 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); 1572 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); 1573 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); 1574 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); 1575 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); 1576 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); 1577 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); 1578 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); 1579 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); 1580 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); 1581 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); 1582 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); 1583 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); 1584 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); 1585 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); 1586 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); 1587 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1588 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); 1589 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); 1590 for (i = 0; i < (3*16); i++) 1591 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1592 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1593 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1594 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); 1595 for (i = 0; i < (16*16); i++) 1596 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1597 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); 1598 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); 1599 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); 1600 for (i = 0; i < (59*4); i++) 1601 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1602 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); 1603 for (i = 0; i < (47*4); i++) 1604 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1605 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); 1606 for (i = 0; i < (3*4); i++) 1607 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1608 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); 1609 for (i = 0; i < (19*4); i++) 1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); 1612 for (i = 0; i < (12*4); i++) 1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1614 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); 1615 for (i = 0; i < (12*4); i++) 1616 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1617 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); 1618 for (i = 0; i < (8*4); i++) 1619 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); 1621 for (i = 0; i < 16; i++) 1622 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1623 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1624 for (i = 0; i < 4; i++) 1625 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1626 1627 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); 1628 1629 if(chip->flatPanel) { 1630 if((chip->Chipset & 0x0ff0) == 0x0110) { 1631 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); 1632 } else 1633 if((chip->Chipset & 0x0ff0) >= 0x0170) { 1634 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); 1635 } 1636 1637 VGA_WR08(chip->PCIO, 0x03D4, 0x53); 1638 VGA_WR08(chip->PCIO, 0x03D5, 0); 1639 VGA_WR08(chip->PCIO, 0x03D4, 0x54); 1640 VGA_WR08(chip->PCIO, 0x03D5, 0); 1641 VGA_WR08(chip->PCIO, 0x03D4, 0x21); 1642 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); 1643 } 1644 1645 VGA_WR08(chip->PCIO, 0x03D4, 0x41); 1646 VGA_WR08(chip->PCIO, 0x03D5, state->extra); 1647 } 1648 LOAD_FIXED_STATE(Riva,FIFO); 1649 UpdateFifoState(chip); 1650 /* 1651 * Load HW mode state. 1652 */ 1653 VGA_WR08(chip->PCIO, 0x03D4, 0x19); 1654 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); 1655 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); 1656 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); 1657 VGA_WR08(chip->PCIO, 0x03D4, 0x25); 1658 VGA_WR08(chip->PCIO, 0x03D5, state->screen); 1659 VGA_WR08(chip->PCIO, 0x03D4, 0x28); 1660 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); 1661 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); 1662 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); 1663 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); 1664 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); 1665 VGA_WR08(chip->PCIO, 0x03D4, 0x20); 1666 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); 1667 VGA_WR08(chip->PCIO, 0x03D4, 0x30); 1668 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); 1669 VGA_WR08(chip->PCIO, 0x03D4, 0x31); 1670 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); 1671 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); 1672 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); 1673 VGA_WR08(chip->PCIO, 0x03D4, 0x39); 1674 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); 1675 1676 if(!chip->flatPanel) { 1677 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); 1678 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); 1679 if(chip->twoHeads) 1680 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); 1681 } else { 1682 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); 1683 } 1684 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); 1685 1686 /* 1687 * Turn off VBlank enable and reset. 1688 */ 1689 NV_WR32(chip->PCRTC, 0x00000140, 0); 1690 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); 1691 /* 1692 * Set interrupt enable. 1693 */ 1694 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); 1695 /* 1696 * Set current state pointer. 1697 */ 1698 chip->CurrentState = state; 1699 /* 1700 * Reset FIFO free and empty counts. 1701 */ 1702 chip->FifoFreeCount = 0; 1703 /* Free count from first subchannel */ 1704 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); 1705} 1706static void UnloadStateExt 1707( 1708 RIVA_HW_INST *chip, 1709 RIVA_HW_STATE *state 1710) 1711{ 1712 /* 1713 * Save current HW state. 1714 */ 1715 VGA_WR08(chip->PCIO, 0x03D4, 0x19); 1716 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); 1717 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); 1718 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); 1719 VGA_WR08(chip->PCIO, 0x03D4, 0x25); 1720 state->screen = VGA_RD08(chip->PCIO, 0x03D5); 1721 VGA_WR08(chip->PCIO, 0x03D4, 0x28); 1722 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); 1723 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); 1724 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); 1725 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); 1726 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); 1727 VGA_WR08(chip->PCIO, 0x03D4, 0x20); 1728 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); 1729 VGA_WR08(chip->PCIO, 0x03D4, 0x30); 1730 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); 1731 VGA_WR08(chip->PCIO, 0x03D4, 0x31); 1732 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); 1733 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); 1734 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); 1735 VGA_WR08(chip->PCIO, 0x03D4, 0x39); 1736 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); 1737 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); 1738 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); 1739 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); 1740 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); 1741 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); 1742 state->config = NV_RD32(chip->PFB, 0x00000200); 1743 switch (chip->Architecture) 1744 { 1745 case NV_ARCH_03: 1746 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); 1747 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); 1748 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); 1749 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); 1750 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); 1751 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); 1752 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); 1753 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); 1754 break; 1755 case NV_ARCH_04: 1756 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); 1757 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); 1758 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); 1759 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); 1760 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); 1761 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); 1762 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); 1763 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); 1764 break; 1765 case NV_ARCH_10: 1766 case NV_ARCH_20: 1767 case NV_ARCH_30: 1768 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); 1769 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); 1770 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); 1771 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); 1772 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); 1773 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); 1774 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); 1775 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); 1776 if(chip->twoHeads) { 1777 state->head = NV_RD32(chip->PCRTC0, 0x00000860); 1778 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); 1779 VGA_WR08(chip->PCIO, 0x03D4, 0x44); 1780 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); 1781 } 1782 VGA_WR08(chip->PCIO, 0x03D4, 0x41); 1783 state->extra = VGA_RD08(chip->PCIO, 0x03D5); 1784 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); 1785 1786 if((chip->Chipset & 0x0ff0) == 0x0110) { 1787 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); 1788 } else 1789 if((chip->Chipset & 0x0ff0) >= 0x0170) { 1790 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); 1791 } 1792 break; 1793 } 1794} 1795static void SetStartAddress 1796( 1797 RIVA_HW_INST *chip, 1798 unsigned start 1799) 1800{ 1801 NV_WR32(chip->PCRTC, 0x800, start); 1802} 1803 1804static void SetStartAddress3 1805( 1806 RIVA_HW_INST *chip, 1807 unsigned start 1808) 1809{ 1810 int offset = start >> 2; 1811 int pan = (start & 3) << 1; 1812 unsigned char tmp; 1813 1814 /* 1815 * Unlock extended registers. 1816 */ 1817 chip->LockUnlock(chip, 0); 1818 /* 1819 * Set start address. 1820 */ 1821 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); 1822 offset >>= 8; 1823 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); 1824 offset >>= 8; 1825 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); 1826 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); 1827 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); 1828 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); 1829 /* 1830 * 4 pixel pan register. 1831 */ 1832 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); 1833 VGA_WR08(chip->PCIO, 0x3C0, 0x13); 1834 VGA_WR08(chip->PCIO, 0x3C0, pan); 1835} 1836static void nv3SetSurfaces2D 1837( 1838 RIVA_HW_INST *chip, 1839 unsigned surf0, 1840 unsigned surf1 1841) 1842{ 1843 RivaSurface __iomem *Surface = 1844 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1845 1846 RIVA_FIFO_FREE(*chip,Tri03,5); 1847 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1848 NV_WR32(&Surface->Offset, 0, surf0); 1849 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1850 NV_WR32(&Surface->Offset, 0, surf1); 1851 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); 1852} 1853static void nv4SetSurfaces2D 1854( 1855 RIVA_HW_INST *chip, 1856 unsigned surf0, 1857 unsigned surf1 1858) 1859{ 1860 RivaSurface __iomem *Surface = 1861 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1862 1863 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1864 NV_WR32(&Surface->Offset, 0, surf0); 1865 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1866 NV_WR32(&Surface->Offset, 0, surf1); 1867 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1868} 1869static void nv10SetSurfaces2D 1870( 1871 RIVA_HW_INST *chip, 1872 unsigned surf0, 1873 unsigned surf1 1874) 1875{ 1876 RivaSurface __iomem *Surface = 1877 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1878 1879 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1880 NV_WR32(&Surface->Offset, 0, surf0); 1881 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1882 NV_WR32(&Surface->Offset, 0, surf1); 1883 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1884} 1885static void nv3SetSurfaces3D 1886( 1887 RIVA_HW_INST *chip, 1888 unsigned surf0, 1889 unsigned surf1 1890) 1891{ 1892 RivaSurface __iomem *Surface = 1893 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1894 1895 RIVA_FIFO_FREE(*chip,Tri03,5); 1896 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); 1897 NV_WR32(&Surface->Offset, 0, surf0); 1898 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); 1899 NV_WR32(&Surface->Offset, 0, surf1); 1900 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); 1901} 1902static void nv4SetSurfaces3D 1903( 1904 RIVA_HW_INST *chip, 1905 unsigned surf0, 1906 unsigned surf1 1907) 1908{ 1909 RivaSurface __iomem *Surface = 1910 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1911 1912 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); 1913 NV_WR32(&Surface->Offset, 0, surf0); 1914 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); 1915 NV_WR32(&Surface->Offset, 0, surf1); 1916 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1917} 1918static void nv10SetSurfaces3D 1919( 1920 RIVA_HW_INST *chip, 1921 unsigned surf0, 1922 unsigned surf1 1923) 1924{ 1925 RivaSurface3D __iomem *Surfaces3D = 1926 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); 1927 1928 RIVA_FIFO_FREE(*chip,Tri03,4); 1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); 1930 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); 1931 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); 1932 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1933} 1934 1935/****************************************************************************\ 1936* * 1937* Probe RIVA Chip Configuration * 1938* * 1939\****************************************************************************/ 1940 1941static void nv3GetConfig 1942( 1943 RIVA_HW_INST *chip 1944) 1945{ 1946 /* 1947 * Fill in chip configuration. 1948 */ 1949 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) 1950 { 1951 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) 1952 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) 1953 { 1954 /* 1955 * SDRAM 128 ZX. 1956 */ 1957 chip->RamBandwidthKBytesPerSec = 800000; 1958 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) 1959 { 1960 case 2: 1961 chip->RamAmountKBytes = 1024 * 4; 1962 break; 1963 case 1: 1964 chip->RamAmountKBytes = 1024 * 2; 1965 break; 1966 default: 1967 chip->RamAmountKBytes = 1024 * 8; 1968 break; 1969 } 1970 } 1971 else 1972 { 1973 chip->RamBandwidthKBytesPerSec = 1000000; 1974 chip->RamAmountKBytes = 1024 * 8; 1975 } 1976 } 1977 else 1978 { 1979 /* 1980 * SGRAM 128. 1981 */ 1982 chip->RamBandwidthKBytesPerSec = 1000000; 1983 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) 1984 { 1985 case 0: 1986 chip->RamAmountKBytes = 1024 * 8; 1987 break; 1988 case 2: 1989 chip->RamAmountKBytes = 1024 * 4; 1990 break; 1991 default: 1992 chip->RamAmountKBytes = 1024 * 2; 1993 break; 1994 } 1995 } 1996 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; 1997 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); 1998 chip->VBlankBit = 0x00000100; 1999 chip->MaxVClockFreqKHz = 256000; 2000 /* 2001 * Set chip functions. 2002 */ 2003 chip->Busy = nv3Busy; 2004 chip->ShowHideCursor = ShowHideCursor; 2005 chip->LoadStateExt = LoadStateExt; 2006 chip->UnloadStateExt = UnloadStateExt; 2007 chip->SetStartAddress = SetStartAddress3; 2008 chip->SetSurfaces2D = nv3SetSurfaces2D; 2009 chip->SetSurfaces3D = nv3SetSurfaces3D; 2010 chip->LockUnlock = nv3LockUnlock; 2011} 2012static void nv4GetConfig 2013( 2014 RIVA_HW_INST *chip 2015) 2016{ 2017 /* 2018 * Fill in chip configuration. 2019 */ 2020 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) 2021 { 2022 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 2023 + 1024 * 2; 2024 } 2025 else 2026 { 2027 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) 2028 { 2029 case 0: 2030 chip->RamAmountKBytes = 1024 * 32; 2031 break; 2032 case 1: 2033 chip->RamAmountKBytes = 1024 * 4; 2034 break; 2035 case 2: 2036 chip->RamAmountKBytes = 1024 * 8; 2037 break; 2038 case 3: 2039 default: 2040 chip->RamAmountKBytes = 1024 * 16; 2041 break; 2042 } 2043 } 2044 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) 2045 { 2046 case 3: 2047 chip->RamBandwidthKBytesPerSec = 800000; 2048 break; 2049 default: 2050 chip->RamBandwidthKBytesPerSec = 1000000; 2051 break; 2052 } 2053 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; 2054 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); 2055 chip->VBlankBit = 0x00000001; 2056 chip->MaxVClockFreqKHz = 350000; 2057 /* 2058 * Set chip functions. 2059 */ 2060 chip->Busy = nv4Busy; 2061 chip->ShowHideCursor = ShowHideCursor; 2062 chip->LoadStateExt = LoadStateExt; 2063 chip->UnloadStateExt = UnloadStateExt; 2064 chip->SetStartAddress = SetStartAddress; 2065 chip->SetSurfaces2D = nv4SetSurfaces2D; 2066 chip->SetSurfaces3D = nv4SetSurfaces3D; 2067 chip->LockUnlock = nv4LockUnlock; 2068} 2069static void nv10GetConfig 2070( 2071 RIVA_HW_INST *chip, 2072 struct pci_dev *pdev, 2073 unsigned int chipset 2074) 2075{ 2076 struct pci_dev* dev; 2077 int domain = pci_domain_nr(pdev->bus); 2078 u32 amt; 2079 2080#ifdef __BIG_ENDIAN 2081 /* turn on big endian register access */ 2082 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) 2083 NV_WR32(chip->PMC, 0x00000004, 0x01000001); 2084#endif 2085 2086 /* 2087 * Fill in chip configuration. 2088 */ 2089 if(chipset == NV_CHIP_IGEFORCE2) { 2090 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 2091 pci_read_config_dword(dev, 0x7C, &amt); 2092 pci_dev_put(dev); 2093 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; 2094 } else if(chipset == NV_CHIP_0x01F0) { 2095 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 2096 pci_read_config_dword(dev, 0x84, &amt); 2097 pci_dev_put(dev); 2098 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; 2099 } else { 2100 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) 2101 { 2102 case 0x02: 2103 chip->RamAmountKBytes = 1024 * 2; 2104 break; 2105 case 0x04: 2106 chip->RamAmountKBytes = 1024 * 4; 2107 break; 2108 case 0x08: 2109 chip->RamAmountKBytes = 1024 * 8; 2110 break; 2111 case 0x10: 2112 chip->RamAmountKBytes = 1024 * 16; 2113 break; 2114 case 0x20: 2115 chip->RamAmountKBytes = 1024 * 32; 2116 break; 2117 case 0x40: 2118 chip->RamAmountKBytes = 1024 * 64; 2119 break; 2120 case 0x80: 2121 chip->RamAmountKBytes = 1024 * 128; 2122 break; 2123 default: 2124 chip->RamAmountKBytes = 1024 * 16; 2125 break; 2126 } 2127 } 2128 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) 2129 { 2130 case 3: 2131 chip->RamBandwidthKBytesPerSec = 800000; 2132 break; 2133 default: 2134 chip->RamBandwidthKBytesPerSec = 1000000; 2135 break; 2136 } 2137 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? 2138 14318 : 13500; 2139 2140 switch (chipset & 0x0ff0) { 2141 case 0x0170: 2142 case 0x0180: 2143 case 0x01F0: 2144 case 0x0250: 2145 case 0x0280: 2146 case 0x0300: 2147 case 0x0310: 2148 case 0x0320: 2149 case 0x0330: 2150 case 0x0340: 2151 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) 2152 chip->CrystalFreqKHz = 27000; 2153 break; 2154 default: 2155 break; 2156 } 2157 2158 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; 2159 chip->CURSOR = NULL; /* can't set this here */ 2160 chip->VBlankBit = 0x00000001; 2161 chip->MaxVClockFreqKHz = 350000; 2162 /* 2163 * Set chip functions. 2164 */ 2165 chip->Busy = nv10Busy; 2166 chip->ShowHideCursor = ShowHideCursor; 2167 chip->LoadStateExt = LoadStateExt; 2168 chip->UnloadStateExt = UnloadStateExt; 2169 chip->SetStartAddress = SetStartAddress; 2170 chip->SetSurfaces2D = nv10SetSurfaces2D; 2171 chip->SetSurfaces3D = nv10SetSurfaces3D; 2172 chip->LockUnlock = nv4LockUnlock; 2173 2174 switch(chipset & 0x0ff0) { 2175 case 0x0110: 2176 case 0x0170: 2177 case 0x0180: 2178 case 0x01F0: 2179 case 0x0250: 2180 case 0x0280: 2181 case 0x0300: 2182 case 0x0310: 2183 case 0x0320: 2184 case 0x0330: 2185 case 0x0340: 2186 chip->twoHeads = TRUE; 2187 break; 2188 default: 2189 chip->twoHeads = FALSE; 2190 break; 2191 } 2192} 2193int RivaGetConfig 2194( 2195 RIVA_HW_INST *chip, 2196 struct pci_dev *pdev, 2197 unsigned int chipset 2198) 2199{ 2200 /* 2201 * Save this so future SW know whats it's dealing with. 2202 */ 2203 chip->Version = RIVA_SW_VERSION; 2204 /* 2205 * Chip specific configuration. 2206 */ 2207 switch (chip->Architecture) 2208 { 2209 case NV_ARCH_03: 2210 nv3GetConfig(chip); 2211 break; 2212 case NV_ARCH_04: 2213 nv4GetConfig(chip); 2214 break; 2215 case NV_ARCH_10: 2216 case NV_ARCH_20: 2217 case NV_ARCH_30: 2218 nv10GetConfig(chip, pdev, chipset); 2219 break; 2220 default: 2221 return (-1); 2222 } 2223 chip->Chipset = chipset; 2224 /* 2225 * Fill in FIFO pointers. 2226 */ 2227 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); 2228 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); 2229 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); 2230 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); 2231 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); 2232 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); 2233 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); 2234 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 2235 return (0); 2236} 2237
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