FILE
hdmi4_core.c
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linux-6.19.14/drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * ti_hdmi_4xxx_ip.c 4 * 5 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library 6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/ 7 * Authors: Yong Zhi 8 * Mythri pk <mythripk@ti.com> 9 */ 10 11#define DSS_SUBSYS_NAME "HDMICORE" 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/err.h> 16#include <linux/io.h> 17#include <linux/interrupt.h> 18#include <linux/mutex.h> 19#include <linux/delay.h> 20#include <linux/platform_device.h> 21#include <linux/string.h> 22#include <linux/seq_file.h> 23#include <sound/asound.h> 24#include <sound/asoundef.h> 25 26#include "hdmi4_core.h" 27#include "dss_features.h" 28 29#define HDMI_CORE_AV 0x500 30 31static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) 32{ 33 return core->base + HDMI_CORE_AV; 34} 35 36static int hdmi_core_ddc_init(struct hdmi_core_data *core) 37{ 38 void __iomem *base = core->base; 39 40 /* Turn on CLK for DDC */ 41 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); 42 43 /* IN_PROG */ 44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { 45 /* Abort transaction */ 46 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); 47 /* IN_PROG */ 48 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 49 4, 4, 0) != 0) { 50 DSSERR("Timeout aborting DDC transaction\n"); 51 return -ETIMEDOUT; 52 } 53 } 54 55 /* Clk SCL Devices */ 56 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); 57 58 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 59 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 60 4, 4, 0) != 0) { 61 DSSERR("Timeout starting SCL clock\n"); 62 return -ETIMEDOUT; 63 } 64 65 /* Clear FIFO */ 66 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); 67 68 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 69 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 70 4, 4, 0) != 0) { 71 DSSERR("Timeout clearing DDC fifo\n"); 72 return -ETIMEDOUT; 73 } 74 75 return 0; 76} 77 78static int hdmi_core_ddc_edid(struct hdmi_core_data *core, 79 u8 *pedid, int ext) 80{ 81 void __iomem *base = core->base; 82 u32 i; 83 char checksum; 84 u32 offset = 0; 85 86 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 87 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 88 4, 4, 0) != 0) { 89 DSSERR("Timeout waiting DDC to be ready\n"); 90 return -ETIMEDOUT; 91 } 92 93 if (ext % 2 != 0) 94 offset = 0x80; 95 96 /* Load Segment Address Register */ 97 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); 98 99 /* Load Slave Address Register */ 100 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); 101 102 /* Load Offset Address Register */ 103 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); 104 105 /* Load Byte Count */ 106 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); 107 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); 108 109 /* Set DDC_CMD */ 110 if (ext) 111 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); 112 else 113 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); 114 115 /* HDMI_CORE_DDC_STATUS_BUS_LOW */ 116 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { 117 DSSERR("I2C Bus Low?\n"); 118 return -EIO; 119 } 120 /* HDMI_CORE_DDC_STATUS_NO_ACK */ 121 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { 122 DSSERR("I2C No Ack\n"); 123 return -EIO; 124 } 125 126 for (i = 0; i < 0x80; ++i) { 127 int t; 128 129 /* IN_PROG */ 130 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { 131 DSSERR("operation stopped when reading edid\n"); 132 return -EIO; 133 } 134 135 t = 0; 136 /* FIFO_EMPTY */ 137 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { 138 if (t++ > 10000) { 139 DSSERR("timeout reading edid\n"); 140 return -ETIMEDOUT; 141 } 142 udelay(1); 143 } 144 145 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); 146 } 147 148 checksum = 0; 149 for (i = 0; i < 0x80; ++i) 150 checksum += pedid[i]; 151 152 if (checksum != 0) { 153 DSSERR("E-EDID checksum failed!!\n"); 154 return -EIO; 155 } 156 157 return 0; 158} 159 160int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) 161{ 162 int r, l; 163 164 if (len < 128) 165 return -EINVAL; 166 167 r = hdmi_core_ddc_init(core); 168 if (r) 169 return r; 170 171 r = hdmi_core_ddc_edid(core, edid, 0); 172 if (r) 173 return r; 174 175 l = 128; 176 177 if (len >= 128 * 2 && edid[0x7e] > 0) { 178 r = hdmi_core_ddc_edid(core, edid + 0x80, 1); 179 if (r) 180 return r; 181 l += 128; 182 } 183 184 return l; 185} 186 187static void hdmi_core_init(struct hdmi_core_video_config *video_cfg) 188{ 189 DSSDBG("Enter hdmi_core_init\n"); 190 191 /* video core */ 192 video_cfg->ip_bus_width = HDMI_INPUT_8BIT; 193 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; 194 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; 195 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; 196 video_cfg->hdmi_dvi = HDMI_DVI; 197 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; 198} 199 200static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) 201{ 202 DSSDBG("Enter hdmi_core_powerdown_disable\n"); 203 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); 204} 205 206static void hdmi_core_swreset_release(struct hdmi_core_data *core) 207{ 208 DSSDBG("Enter hdmi_core_swreset_release\n"); 209 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); 210} 211 212static void hdmi_core_swreset_assert(struct hdmi_core_data *core) 213{ 214 DSSDBG("Enter hdmi_core_swreset_assert\n"); 215 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); 216} 217 218/* HDMI_CORE_VIDEO_CONFIG */ 219static void hdmi_core_video_config(struct hdmi_core_data *core, 220 struct hdmi_core_video_config *cfg) 221{ 222 u32 r = 0; 223 void __iomem *core_sys_base = core->base; 224 void __iomem *core_av_base = hdmi_av_base(core); 225 226 /* sys_ctrl1 default configuration not tunable */ 227 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); 228 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); 229 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); 230 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); 231 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); 232 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r); 233 234 REG_FLD_MOD(core_sys_base, 235 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); 236 237 /* Vid_Mode */ 238 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); 239 240 /* dither truncation configuration */ 241 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { 242 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); 243 r = FLD_MOD(r, 1, 5, 5); 244 } else { 245 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); 246 r = FLD_MOD(r, 0, 5, 5); 247 } 248 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); 249 250 /* HDMI_Ctrl */ 251 r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); 252 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); 253 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); 254 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); 255 hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); 256 257 /* TMDS_CTRL */ 258 REG_FLD_MOD(core_sys_base, 259 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); 260} 261 262static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, 263 struct hdmi_avi_infoframe *frame) 264{ 265 void __iomem *av_base = hdmi_av_base(core); 266 u8 data[HDMI_INFOFRAME_SIZE(AVI)]; 267 int i; 268 269 hdmi_avi_infoframe_pack(frame, data, sizeof(data)); 270 271 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, 272 HDMI_INFOFRAME_SIZE(AVI), false); 273 274 for (i = 0; i < sizeof(data); ++i) { 275 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4, 276 data[i]); 277 } 278} 279 280static void hdmi_core_av_packet_config(struct hdmi_core_data *core, 281 struct hdmi_core_packet_enable_repeat repeat_cfg) 282{ 283 /* enable/repeat the infoframe */ 284 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, 285 (repeat_cfg.audio_pkt << 5) | 286 (repeat_cfg.audio_pkt_repeat << 4) | 287 (repeat_cfg.avi_infoframe << 1) | 288 (repeat_cfg.avi_infoframe_repeat)); 289 290 /* enable/repeat the packet */ 291 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, 292 (repeat_cfg.gen_cntrl_pkt << 3) | 293 (repeat_cfg.gen_cntrl_pkt_repeat << 2) | 294 (repeat_cfg.generic_pkt << 1) | 295 (repeat_cfg.generic_pkt_repeat)); 296} 297 298void hdmi4_configure(struct hdmi_core_data *core, 299 struct hdmi_wp_data *wp, struct hdmi_config *cfg) 300{ 301 /* HDMI */ 302 struct omap_video_timings video_timing; 303 struct hdmi_video_format video_format; 304 /* HDMI core */ 305 struct hdmi_core_video_config v_core_cfg; 306 struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 }; 307 308 hdmi_core_init(&v_core_cfg); 309 310 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 311 312 hdmi_wp_video_config_timing(wp, &video_timing); 313 314 /* video config */ 315 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 316 317 hdmi_wp_video_config_format(wp, &video_format); 318 319 hdmi_wp_video_config_interface(wp, &video_timing); 320 321 /* 322 * configure core video part 323 * set software reset in the core 324 */ 325 hdmi_core_swreset_assert(core); 326 327 /* power down off */ 328 hdmi_core_powerdown_disable(core); 329 330 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; 331 v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode; 332 333 hdmi_core_video_config(core, &v_core_cfg); 334 335 /* release software reset in the core */ 336 hdmi_core_swreset_release(core); 337 338 if (cfg->hdmi_dvi_mode == HDMI_HDMI) { 339 hdmi_core_write_avi_infoframe(core, &cfg->infoframe); 340 341 /* enable/repeat the infoframe */ 342 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; 343 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; 344 /* wakeup */ 345 repeat_cfg.audio_pkt = HDMI_PACKETENABLE; 346 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; 347 } 348 349 hdmi_core_av_packet_config(core, repeat_cfg); 350} 351 352void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) 353{ 354 int i; 355 356#define CORE_REG(i, name) name(i) 357#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ 358 hdmi_read_reg(core->base, r)) 359#define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ 360 hdmi_read_reg(hdmi_av_base(core), r)) 361#define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ 362 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ 363 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) 364 365 DUMPCORE(HDMI_CORE_SYS_VND_IDL); 366 DUMPCORE(HDMI_CORE_SYS_DEV_IDL); 367 DUMPCORE(HDMI_CORE_SYS_DEV_IDH); 368 DUMPCORE(HDMI_CORE_SYS_DEV_REV); 369 DUMPCORE(HDMI_CORE_SYS_SRST); 370 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1); 371 DUMPCORE(HDMI_CORE_SYS_SYS_STAT); 372 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3); 373 DUMPCORE(HDMI_CORE_SYS_DE_DLY); 374 DUMPCORE(HDMI_CORE_SYS_DE_CTRL); 375 DUMPCORE(HDMI_CORE_SYS_DE_TOP); 376 DUMPCORE(HDMI_CORE_SYS_DE_CNTL); 377 DUMPCORE(HDMI_CORE_SYS_DE_CNTH); 378 DUMPCORE(HDMI_CORE_SYS_DE_LINL); 379 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); 380 DUMPCORE(HDMI_CORE_SYS_HRES_L); 381 DUMPCORE(HDMI_CORE_SYS_HRES_H); 382 DUMPCORE(HDMI_CORE_SYS_VRES_L); 383 DUMPCORE(HDMI_CORE_SYS_VRES_H); 384 DUMPCORE(HDMI_CORE_SYS_IADJUST); 385 DUMPCORE(HDMI_CORE_SYS_POLDETECT); 386 DUMPCORE(HDMI_CORE_SYS_HWIDTH1); 387 DUMPCORE(HDMI_CORE_SYS_HWIDTH2); 388 DUMPCORE(HDMI_CORE_SYS_VWIDTH); 389 DUMPCORE(HDMI_CORE_SYS_VID_CTRL); 390 DUMPCORE(HDMI_CORE_SYS_VID_ACEN); 391 DUMPCORE(HDMI_CORE_SYS_VID_MODE); 392 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 393 DUMPCORE(HDMI_CORE_SYS_VID_BLANK3); 394 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 395 DUMPCORE(HDMI_CORE_SYS_DC_HEADER); 396 DUMPCORE(HDMI_CORE_SYS_VID_DITHER); 397 DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT); 398 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW); 399 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP); 400 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW); 401 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP); 402 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW); 403 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP); 404 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW); 405 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP); 406 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW); 407 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP); 408 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW); 409 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP); 410 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW); 411 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP); 412 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW); 413 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP); 414 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW); 415 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP); 416 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW); 417 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP); 418 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW); 419 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP); 420 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW); 421 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP); 422 DUMPCORE(HDMI_CORE_SYS_INTR_STATE); 423 DUMPCORE(HDMI_CORE_SYS_INTR1); 424 DUMPCORE(HDMI_CORE_SYS_INTR2); 425 DUMPCORE(HDMI_CORE_SYS_INTR3); 426 DUMPCORE(HDMI_CORE_SYS_INTR4); 427 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1); 428 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2); 429 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3); 430 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4); 431 DUMPCORE(HDMI_CORE_SYS_INTR_CTRL); 432 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); 433 434 DUMPCORE(HDMI_CORE_DDC_ADDR); 435 DUMPCORE(HDMI_CORE_DDC_SEGM); 436 DUMPCORE(HDMI_CORE_DDC_OFFSET); 437 DUMPCORE(HDMI_CORE_DDC_COUNT1); 438 DUMPCORE(HDMI_CORE_DDC_COUNT2); 439 DUMPCORE(HDMI_CORE_DDC_STATUS); 440 DUMPCORE(HDMI_CORE_DDC_CMD); 441 DUMPCORE(HDMI_CORE_DDC_DATA); 442 443 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL); 444 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL); 445 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1); 446 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2); 447 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3); 448 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1); 449 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2); 450 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3); 451 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1); 452 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2); 453 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3); 454 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE); 455 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL); 456 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS); 457 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S); 458 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH); 459 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP); 460 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL); 461 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0); 462 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1); 463 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2); 464 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4); 465 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5); 466 DUMPCOREAV(HDMI_CORE_AV_ASRC); 467 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN); 468 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL); 469 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT); 470 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1); 471 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2); 472 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3); 473 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL); 474 DUMPCOREAV(HDMI_CORE_AV_DPD); 475 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1); 476 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2); 477 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE); 478 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); 479 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); 480 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); 481 482 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) 483 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); 484 485 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE); 486 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS); 487 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN); 488 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM); 489 490 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) 491 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); 492 493 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE); 494 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS); 495 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN); 496 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM); 497 498 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) 499 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); 500 501 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE); 502 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS); 503 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN); 504 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM); 505 506 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) 507 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); 508 509 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) 510 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); 511 512 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1); 513 514 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) 515 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); 516 517 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); 518} 519 520static void hdmi_core_audio_config(struct hdmi_core_data *core, 521 struct hdmi_core_audio_config *cfg) 522{ 523 u32 r; 524 void __iomem *av_base = hdmi_av_base(core); 525 526 /* 527 * Parameters for generation of Audio Clock Recovery packets 528 */ 529 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); 530 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); 531 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); 532 533 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { 534 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); 535 REG_FLD_MOD(av_base, 536 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); 537 REG_FLD_MOD(av_base, 538 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); 539 } else { 540 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, 541 cfg->aud_par_busclk, 7, 0); 542 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, 543 (cfg->aud_par_busclk >> 8), 7, 0); 544 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, 545 (cfg->aud_par_busclk >> 16), 7, 0); 546 } 547 548 /* Set ACR clock divisor */ 549 REG_FLD_MOD(av_base, 550 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); 551 552 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); 553 /* 554 * Use TMDS clock for ACR packets. For devices that use 555 * the MCLK, this is the first part of the MCLK initialization. 556 */ 557 r = FLD_MOD(r, 0, 2, 2); 558 559 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); 560 r = FLD_MOD(r, cfg->cts_mode, 0, 0); 561 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); 562 563 /* For devices using MCLK, this completes its initialization. */ 564 if (cfg->use_mclk) 565 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); 566 567 /* Override of SPDIF sample frequency with value in I2S_CHST4 */ 568 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, 569 cfg->fs_override, 1, 1); 570 571 /* 572 * Set IEC-60958-3 channel status word. It is passed to the IP 573 * just as it is received. The user of the driver is responsible 574 * for its contents. 575 */ 576 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0, 577 cfg->iec60958_cfg->status[0]); 578 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1, 579 cfg->iec60958_cfg->status[1]); 580 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2, 581 cfg->iec60958_cfg->status[2]); 582 /* yes, this is correct: status[3] goes to CHST4 register */ 583 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4, 584 cfg->iec60958_cfg->status[3]); 585 /* yes, this is correct: status[4] goes to CHST5 register */ 586 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, 587 cfg->iec60958_cfg->status[4]); 588 589 /* set I2S parameters */ 590 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); 591 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); 592 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); 593 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); 594 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); 595 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); 596 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); 597 598 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, 599 cfg->i2s_cfg.in_length_bits, 3, 0); 600 601 /* Audio channels and mode parameters */ 602 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); 603 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); 604 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); 605 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); 606 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); 607 r = FLD_MOD(r, cfg->en_spdif, 1, 1); 608 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); 609 610 /* Audio channel mappings */ 611 /* TODO: Make channel mapping dynamic. For now, map channels 612 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as 613 * HDMI speaker order is different. See CEA-861 Section 6.6.2. 614 */ 615 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78); 616 REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); 617} 618 619static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, 620 struct snd_cea_861_aud_if *info_aud) 621{ 622 u8 sum = 0, checksum = 0; 623 void __iomem *av_base = hdmi_av_base(core); 624 625 /* 626 * Set audio info frame type, version and length as 627 * described in HDMI 1.4a Section 8.2.2 specification. 628 * Checksum calculation is defined in Section 5.3.5. 629 */ 630 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); 631 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); 632 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); 633 sum += 0x84 + 0x001 + 0x00a; 634 635 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), 636 info_aud->db1_ct_cc); 637 sum += info_aud->db1_ct_cc; 638 639 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), 640 info_aud->db2_sf_ss); 641 sum += info_aud->db2_sf_ss; 642 643 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); 644 sum += info_aud->db3; 645 646 /* 647 * The OMAP HDMI IP requires to use the 8-channel channel code when 648 * transmitting more than two channels. 649 */ 650 if (info_aud->db4_ca != 0x00) 651 info_aud->db4_ca = 0x13; 652 653 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); 654 sum += info_aud->db4_ca; 655 656 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), 657 info_aud->db5_dminh_lsv); 658 sum += info_aud->db5_dminh_lsv; 659 660 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); 661 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); 662 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); 663 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); 664 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); 665 666 checksum = 0x100 - sum; 667 hdmi_write_reg(av_base, 668 HDMI_CORE_AV_AUDIO_CHSUM, checksum); 669 670 /* 671 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing 672 * is available. 673 */ 674} 675 676int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 677 struct omap_dss_audio *audio, u32 pclk) 678{ 679 struct hdmi_audio_format audio_format; 680 struct hdmi_audio_dma audio_dma; 681 struct hdmi_core_audio_config acore; 682 int n, cts, channel_count; 683 unsigned int fs_nr; 684 bool word_length_16b = false; 685 686 if (!audio || !audio->iec || !audio->cea || !core) 687 return -EINVAL; 688 689 acore.iec60958_cfg = audio->iec; 690 /* 691 * In the IEC-60958 status word, check if the audio sample word length 692 * is 16-bit as several optimizations can be performed in such case. 693 */ 694 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)) 695 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16) 696 word_length_16b = true; 697 698 /* I2S configuration. See Phillips' specification */ 699 if (word_length_16b) 700 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; 701 else 702 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 703 /* 704 * The I2S input word length is twice the length given in the IEC-60958 705 * status word. If the word size is greater than 706 * 20 bits, increment by one. 707 */ 708 acore.i2s_cfg.in_length_bits = audio->iec->status[4] 709 & IEC958_AES4_CON_WORDLEN; 710 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) 711 acore.i2s_cfg.in_length_bits++; 712 acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; 713 acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; 714 acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; 715 acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; 716 717 /* convert sample frequency to a number */ 718 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { 719 case IEC958_AES3_CON_FS_32000: 720 fs_nr = 32000; 721 break; 722 case IEC958_AES3_CON_FS_44100: 723 fs_nr = 44100; 724 break; 725 case IEC958_AES3_CON_FS_48000: 726 fs_nr = 48000; 727 break; 728 case IEC958_AES3_CON_FS_88200: 729 fs_nr = 88200; 730 break; 731 case IEC958_AES3_CON_FS_96000: 732 fs_nr = 96000; 733 break; 734 case IEC958_AES3_CON_FS_176400: 735 fs_nr = 176400; 736 break; 737 case IEC958_AES3_CON_FS_192000: 738 fs_nr = 192000; 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 hdmi_compute_acr(pclk, fs_nr, &n, &cts); 745 746 /* Audio clock regeneration settings */ 747 acore.n = n; 748 acore.cts = cts; 749 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { 750 acore.aud_par_busclk = 0; 751 acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; 752 acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); 753 } else { 754 acore.aud_par_busclk = (((128 * 31) - 1) << 8); 755 acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; 756 acore.use_mclk = true; 757 } 758 759 if (acore.use_mclk) 760 acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; 761 762 /* Audio channels settings */ 763 channel_count = (audio->cea->db1_ct_cc & 764 CEA861_AUDIO_INFOFRAME_DB1CC) + 1; 765 766 switch (channel_count) { 767 case 2: 768 audio_format.active_chnnls_msk = 0x03; 769 break; 770 case 3: 771 audio_format.active_chnnls_msk = 0x07; 772 break; 773 case 4: 774 audio_format.active_chnnls_msk = 0x0f; 775 break; 776 case 5: 777 audio_format.active_chnnls_msk = 0x1f; 778 break; 779 case 6: 780 audio_format.active_chnnls_msk = 0x3f; 781 break; 782 case 7: 783 audio_format.active_chnnls_msk = 0x7f; 784 break; 785 case 8: 786 audio_format.active_chnnls_msk = 0xff; 787 break; 788 default: 789 return -EINVAL; 790 } 791 792 /* 793 * the HDMI IP needs to enable four stereo channels when transmitting 794 * more than 2 audio channels. Similarly, the channel count in the 795 * Audio InfoFrame has to match the sample_present bits (some channels 796 * are padded with zeroes) 797 */ 798 if (channel_count == 2) { 799 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; 800 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; 801 acore.layout = HDMI_AUDIO_LAYOUT_2CH; 802 } else { 803 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; 804 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | 805 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | 806 HDMI_AUDIO_I2S_SD3_EN; 807 acore.layout = HDMI_AUDIO_LAYOUT_8CH; 808 audio->cea->db1_ct_cc = 7; 809 } 810 811 acore.en_spdif = false; 812 /* use sample frequency from channel status word */ 813 acore.fs_override = true; 814 /* enable ACR packets */ 815 acore.en_acr_pkt = true; 816 /* disable direct streaming digital audio */ 817 acore.en_dsd_audio = false; 818 /* use parallel audio interface */ 819 acore.en_parallel_aud_input = true; 820 821 /* DMA settings */ 822 if (word_length_16b) 823 audio_dma.transfer_size = 0x10; 824 else 825 audio_dma.transfer_size = 0x20; 826 audio_dma.block_size = 0xC0; 827 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; 828 audio_dma.fifo_threshold = 0x20; /* in number of samples */ 829 830 /* audio FIFO format settings */ 831 if (word_length_16b) { 832 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; 833 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; 834 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; 835 } else { 836 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; 837 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; 838 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 839 } 840 audio_format.type = HDMI_AUDIO_TYPE_LPCM; 841 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 842 /* disable start/stop signals of IEC 60958 blocks */ 843 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; 844 845 /* configure DMA and audio FIFO format*/ 846 hdmi_wp_audio_config_dma(wp, &audio_dma); 847 hdmi_wp_audio_config_format(wp, &audio_format); 848 849 /* configure the core*/ 850 hdmi_core_audio_config(core, &acore); 851 852 /* configure CEA 861 audio infoframe*/ 853 hdmi_core_audio_infoframe_cfg(core, audio->cea); 854 855 return 0; 856} 857 858int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 859{ 860 REG_FLD_MOD(hdmi_av_base(core), 861 HDMI_CORE_AV_AUD_MODE, true, 0, 0); 862 863 hdmi_wp_audio_core_req_enable(wp, true); 864 865 return 0; 866} 867 868void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 869{ 870 REG_FLD_MOD(hdmi_av_base(core), 871 HDMI_CORE_AV_AUD_MODE, false, 0, 0); 872 873 hdmi_wp_audio_core_req_enable(wp, false); 874} 875 876int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) 877{ 878 core->base = devm_platform_ioremap_resource_byname(pdev, "core"); 879 if (IS_ERR(core->base)) { 880 DSSERR("can't ioremap CORE\n"); 881 return PTR_ERR(core->base); 882 } 883 884 return 0; 885}
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