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dispc.c
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linux-6.19.14/drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/drivers/video/omap2/dss/dispc.c 4 * 5 * Copyright (C) 2009 Nokia Corporation 6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 7 * 8 * Some code and ideas taken from drivers/video/omap/ driver 9 * by Imre Deak. 10 */ 11 12#define DSS_SUBSYS_NAME "DISPC" 13 14#include <linux/kernel.h> 15#include <linux/dma-mapping.h> 16#include <linux/vmalloc.h> 17#include <linux/export.h> 18#include <linux/clk.h> 19#include <linux/io.h> 20#include <linux/jiffies.h> 21#include <linux/seq_file.h> 22#include <linux/delay.h> 23#include <linux/workqueue.h> 24#include <linux/hardirq.h> 25#include <linux/platform_device.h> 26#include <linux/pm_runtime.h> 27#include <linux/sizes.h> 28#include <linux/mfd/syscon.h> 29#include <linux/regmap.h> 30#include <linux/of.h> 31#include <linux/component.h> 32 33#include <video/omapfb_dss.h> 34 35#include "dss.h" 36#include "dss_features.h" 37#include "dispc.h" 38 39/* DISPC */ 40#define DISPC_SZ_REGS SZ_4K 41 42enum omap_burst_size { 43 BURST_SIZE_X2 = 0, 44 BURST_SIZE_X4 = 1, 45 BURST_SIZE_X8 = 2, 46}; 47 48#define REG_GET(idx, start, end) \ 49 FLD_GET(dispc_read_reg(idx), start, end) 50 51#define REG_FLD_MOD(idx, val, start, end) \ 52 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 53 54struct dispc_features { 55 u8 sw_start; 56 u8 fp_start; 57 u8 bp_start; 58 u16 sw_max; 59 u16 vp_max; 60 u16 hp_max; 61 u8 mgr_width_start; 62 u8 mgr_height_start; 63 u16 mgr_width_max; 64 u16 mgr_height_max; 65 unsigned long max_lcd_pclk; 66 unsigned long max_tv_pclk; 67 int (*calc_scaling) (unsigned long pclk, unsigned long lclk, 68 const struct omap_video_timings *mgr_timings, 69 u16 width, u16 height, u16 out_width, u16 out_height, 70 enum omap_color_mode color_mode, bool *five_taps, 71 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 72 u16 pos_x, unsigned long *core_clk, bool mem_to_mem); 73 unsigned long (*calc_core_clk) (unsigned long pclk, 74 u16 width, u16 height, u16 out_width, u16 out_height, 75 bool mem_to_mem); 76 u8 num_fifos; 77 78 /* swap GFX & WB fifos */ 79 bool gfx_fifo_workaround:1; 80 81 /* no DISPC_IRQ_FRAMEDONETV on this SoC */ 82 bool no_framedone_tv:1; 83 84 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ 85 bool mstandby_workaround:1; 86 87 bool set_max_preload:1; 88 89 /* PIXEL_INC is not added to the last pixel of a line */ 90 bool last_pixel_inc_missing:1; 91 92 /* POL_FREQ has ALIGN bit */ 93 bool supports_sync_align:1; 94 95 bool has_writeback:1; 96}; 97 98#define DISPC_MAX_NR_FIFOS 5 99 100static struct { 101 struct platform_device *pdev; 102 void __iomem *base; 103 104 int irq; 105 irq_handler_t user_handler; 106 void *user_data; 107 108 unsigned long core_clk_rate; 109 unsigned long tv_pclk_rate; 110 111 u32 fifo_size[DISPC_MAX_NR_FIFOS]; 112 /* maps which plane is using a fifo. fifo-id -> plane-id */ 113 int fifo_assignment[DISPC_MAX_NR_FIFOS]; 114 115 bool ctx_valid; 116 u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; 117 118 const struct dispc_features *feat; 119 120 bool is_enabled; 121 122 struct regmap *syscon_pol; 123 u32 syscon_pol_offset; 124 125 /* DISPC_CONTROL & DISPC_CONFIG lock*/ 126 spinlock_t control_lock; 127} dispc; 128 129enum omap_color_component { 130 /* used for all color formats for OMAP3 and earlier 131 * and for RGB and Y color component on OMAP4 132 */ 133 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, 134 /* used for UV component for 135 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 136 * color formats on OMAP4 137 */ 138 DISPC_COLOR_COMPONENT_UV = 1 << 1, 139}; 140 141enum mgr_reg_fields { 142 DISPC_MGR_FLD_ENABLE, 143 DISPC_MGR_FLD_STNTFT, 144 DISPC_MGR_FLD_GO, 145 DISPC_MGR_FLD_TFTDATALINES, 146 DISPC_MGR_FLD_STALLMODE, 147 DISPC_MGR_FLD_TCKENABLE, 148 DISPC_MGR_FLD_TCKSELECTION, 149 DISPC_MGR_FLD_CPR, 150 DISPC_MGR_FLD_FIFOHANDCHECK, 151 /* used to maintain a count of the above fields */ 152 DISPC_MGR_FLD_NUM, 153}; 154 155struct dispc_reg_field { 156 u16 reg; 157 u8 high; 158 u8 low; 159}; 160 161static const struct { 162 const char *name; 163 u32 vsync_irq; 164 u32 framedone_irq; 165 u32 sync_lost_irq; 166 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; 167} mgr_desc[] = { 168 [OMAP_DSS_CHANNEL_LCD] = { 169 .name = "LCD", 170 .vsync_irq = DISPC_IRQ_VSYNC, 171 .framedone_irq = DISPC_IRQ_FRAMEDONE, 172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST, 173 .reg_desc = { 174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, 175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, 176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, 177 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, 178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, 179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, 180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, 181 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, 182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 183 }, 184 }, 185 [OMAP_DSS_CHANNEL_DIGIT] = { 186 .name = "DIGIT", 187 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, 188 .framedone_irq = DISPC_IRQ_FRAMEDONETV, 189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, 190 .reg_desc = { 191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, 192 [DISPC_MGR_FLD_STNTFT] = { }, 193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, 194 [DISPC_MGR_FLD_TFTDATALINES] = { }, 195 [DISPC_MGR_FLD_STALLMODE] = { }, 196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, 197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, 198 [DISPC_MGR_FLD_CPR] = { }, 199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, 200 }, 201 }, 202 [OMAP_DSS_CHANNEL_LCD2] = { 203 .name = "LCD2", 204 .vsync_irq = DISPC_IRQ_VSYNC2, 205 .framedone_irq = DISPC_IRQ_FRAMEDONE2, 206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, 207 .reg_desc = { 208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, 209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, 210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, 211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, 212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, 213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, 214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, 215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, 216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, 217 }, 218 }, 219 [OMAP_DSS_CHANNEL_LCD3] = { 220 .name = "LCD3", 221 .vsync_irq = DISPC_IRQ_VSYNC3, 222 .framedone_irq = DISPC_IRQ_FRAMEDONE3, 223 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, 224 .reg_desc = { 225 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, 226 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, 227 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, 228 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, 229 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, 230 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, 231 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, 232 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, 233 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, 234 }, 235 }, 236}; 237 238struct color_conv_coef { 239 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; 240 int full_range; 241}; 242 243static unsigned long dispc_fclk_rate(void); 244static unsigned long dispc_core_clk_rate(void); 245static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 246static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 247 248static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); 249static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); 250 251static inline void dispc_write_reg(const u16 idx, u32 val) 252{ 253 __raw_writel(val, dispc.base + idx); 254} 255 256static inline u32 dispc_read_reg(const u16 idx) 257{ 258 return __raw_readl(dispc.base + idx); 259} 260 261static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) 262{ 263 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 264 return REG_GET(rfld.reg, rfld.high, rfld.low); 265} 266 267static void mgr_fld_write(enum omap_channel channel, 268 enum mgr_reg_fields regfld, int val) { 269 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 270 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; 271 unsigned long flags; 272 273 if (need_lock) 274 spin_lock_irqsave(&dispc.control_lock, flags); 275 276 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); 277 278 if (need_lock) 279 spin_unlock_irqrestore(&dispc.control_lock, flags); 280} 281 282#define SR(reg) \ 283 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) 284#define RR(reg) \ 285 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) 286 287static void dispc_save_context(void) 288{ 289 int i, j; 290 291 DSSDBG("dispc_save_context\n"); 292 293 SR(IRQENABLE); 294 SR(CONTROL); 295 SR(CONFIG); 296 SR(LINE_NUMBER); 297 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 298 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 299 SR(GLOBAL_ALPHA); 300 if (dss_has_feature(FEAT_MGR_LCD2)) { 301 SR(CONTROL2); 302 SR(CONFIG2); 303 } 304 if (dss_has_feature(FEAT_MGR_LCD3)) { 305 SR(CONTROL3); 306 SR(CONFIG3); 307 } 308 309 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 310 SR(DEFAULT_COLOR(i)); 311 SR(TRANS_COLOR(i)); 312 SR(SIZE_MGR(i)); 313 if (i == OMAP_DSS_CHANNEL_DIGIT) 314 continue; 315 SR(TIMING_H(i)); 316 SR(TIMING_V(i)); 317 SR(POL_FREQ(i)); 318 SR(DIVISORo(i)); 319 320 SR(DATA_CYCLE1(i)); 321 SR(DATA_CYCLE2(i)); 322 SR(DATA_CYCLE3(i)); 323 324 if (dss_has_feature(FEAT_CPR)) { 325 SR(CPR_COEF_R(i)); 326 SR(CPR_COEF_G(i)); 327 SR(CPR_COEF_B(i)); 328 } 329 } 330 331 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 332 SR(OVL_BA0(i)); 333 SR(OVL_BA1(i)); 334 SR(OVL_POSITION(i)); 335 SR(OVL_SIZE(i)); 336 SR(OVL_ATTRIBUTES(i)); 337 SR(OVL_FIFO_THRESHOLD(i)); 338 SR(OVL_ROW_INC(i)); 339 SR(OVL_PIXEL_INC(i)); 340 if (dss_has_feature(FEAT_PRELOAD)) 341 SR(OVL_PRELOAD(i)); 342 if (i == OMAP_DSS_GFX) { 343 SR(OVL_WINDOW_SKIP(i)); 344 SR(OVL_TABLE_BA(i)); 345 continue; 346 } 347 SR(OVL_FIR(i)); 348 SR(OVL_PICTURE_SIZE(i)); 349 SR(OVL_ACCU0(i)); 350 SR(OVL_ACCU1(i)); 351 352 for (j = 0; j < 8; j++) 353 SR(OVL_FIR_COEF_H(i, j)); 354 355 for (j = 0; j < 8; j++) 356 SR(OVL_FIR_COEF_HV(i, j)); 357 358 for (j = 0; j < 5; j++) 359 SR(OVL_CONV_COEF(i, j)); 360 361 if (dss_has_feature(FEAT_FIR_COEF_V)) { 362 for (j = 0; j < 8; j++) 363 SR(OVL_FIR_COEF_V(i, j)); 364 } 365 366 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 367 SR(OVL_BA0_UV(i)); 368 SR(OVL_BA1_UV(i)); 369 SR(OVL_FIR2(i)); 370 SR(OVL_ACCU2_0(i)); 371 SR(OVL_ACCU2_1(i)); 372 373 for (j = 0; j < 8; j++) 374 SR(OVL_FIR_COEF_H2(i, j)); 375 376 for (j = 0; j < 8; j++) 377 SR(OVL_FIR_COEF_HV2(i, j)); 378 379 for (j = 0; j < 8; j++) 380 SR(OVL_FIR_COEF_V2(i, j)); 381 } 382 if (dss_has_feature(FEAT_ATTR2)) 383 SR(OVL_ATTRIBUTES2(i)); 384 } 385 386 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 387 SR(DIVISOR); 388 389 dispc.ctx_valid = true; 390 391 DSSDBG("context saved\n"); 392} 393 394static void dispc_restore_context(void) 395{ 396 int i, j; 397 398 DSSDBG("dispc_restore_context\n"); 399 400 if (!dispc.ctx_valid) 401 return; 402 403 /*RR(IRQENABLE);*/ 404 /*RR(CONTROL);*/ 405 RR(CONFIG); 406 RR(LINE_NUMBER); 407 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 408 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 409 RR(GLOBAL_ALPHA); 410 if (dss_has_feature(FEAT_MGR_LCD2)) 411 RR(CONFIG2); 412 if (dss_has_feature(FEAT_MGR_LCD3)) 413 RR(CONFIG3); 414 415 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 416 RR(DEFAULT_COLOR(i)); 417 RR(TRANS_COLOR(i)); 418 RR(SIZE_MGR(i)); 419 if (i == OMAP_DSS_CHANNEL_DIGIT) 420 continue; 421 RR(TIMING_H(i)); 422 RR(TIMING_V(i)); 423 RR(POL_FREQ(i)); 424 RR(DIVISORo(i)); 425 426 RR(DATA_CYCLE1(i)); 427 RR(DATA_CYCLE2(i)); 428 RR(DATA_CYCLE3(i)); 429 430 if (dss_has_feature(FEAT_CPR)) { 431 RR(CPR_COEF_R(i)); 432 RR(CPR_COEF_G(i)); 433 RR(CPR_COEF_B(i)); 434 } 435 } 436 437 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 438 RR(OVL_BA0(i)); 439 RR(OVL_BA1(i)); 440 RR(OVL_POSITION(i)); 441 RR(OVL_SIZE(i)); 442 RR(OVL_ATTRIBUTES(i)); 443 RR(OVL_FIFO_THRESHOLD(i)); 444 RR(OVL_ROW_INC(i)); 445 RR(OVL_PIXEL_INC(i)); 446 if (dss_has_feature(FEAT_PRELOAD)) 447 RR(OVL_PRELOAD(i)); 448 if (i == OMAP_DSS_GFX) { 449 RR(OVL_WINDOW_SKIP(i)); 450 RR(OVL_TABLE_BA(i)); 451 continue; 452 } 453 RR(OVL_FIR(i)); 454 RR(OVL_PICTURE_SIZE(i)); 455 RR(OVL_ACCU0(i)); 456 RR(OVL_ACCU1(i)); 457 458 for (j = 0; j < 8; j++) 459 RR(OVL_FIR_COEF_H(i, j)); 460 461 for (j = 0; j < 8; j++) 462 RR(OVL_FIR_COEF_HV(i, j)); 463 464 for (j = 0; j < 5; j++) 465 RR(OVL_CONV_COEF(i, j)); 466 467 if (dss_has_feature(FEAT_FIR_COEF_V)) { 468 for (j = 0; j < 8; j++) 469 RR(OVL_FIR_COEF_V(i, j)); 470 } 471 472 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 473 RR(OVL_BA0_UV(i)); 474 RR(OVL_BA1_UV(i)); 475 RR(OVL_FIR2(i)); 476 RR(OVL_ACCU2_0(i)); 477 RR(OVL_ACCU2_1(i)); 478 479 for (j = 0; j < 8; j++) 480 RR(OVL_FIR_COEF_H2(i, j)); 481 482 for (j = 0; j < 8; j++) 483 RR(OVL_FIR_COEF_HV2(i, j)); 484 485 for (j = 0; j < 8; j++) 486 RR(OVL_FIR_COEF_V2(i, j)); 487 } 488 if (dss_has_feature(FEAT_ATTR2)) 489 RR(OVL_ATTRIBUTES2(i)); 490 } 491 492 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 493 RR(DIVISOR); 494 495 /* enable last, because LCD & DIGIT enable are here */ 496 RR(CONTROL); 497 if (dss_has_feature(FEAT_MGR_LCD2)) 498 RR(CONTROL2); 499 if (dss_has_feature(FEAT_MGR_LCD3)) 500 RR(CONTROL3); 501 /* clear spurious SYNC_LOST_DIGIT interrupts */ 502 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); 503 504 /* 505 * enable last so IRQs won't trigger before 506 * the context is fully restored 507 */ 508 RR(IRQENABLE); 509 510 DSSDBG("context restored\n"); 511} 512 513#undef SR 514#undef RR 515 516int dispc_runtime_get(void) 517{ 518 int r; 519 520 DSSDBG("dispc_runtime_get\n"); 521 522 r = pm_runtime_resume_and_get(&dispc.pdev->dev); 523 if (WARN_ON(r < 0)) 524 return r; 525 return 0; 526} 527EXPORT_SYMBOL(dispc_runtime_get); 528 529void dispc_runtime_put(void) 530{ 531 int r; 532 533 DSSDBG("dispc_runtime_put\n"); 534 535 r = pm_runtime_put_sync(&dispc.pdev->dev); 536 WARN_ON(r < 0 && r != -ENOSYS); 537} 538EXPORT_SYMBOL(dispc_runtime_put); 539 540u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) 541{ 542 return mgr_desc[channel].vsync_irq; 543} 544EXPORT_SYMBOL(dispc_mgr_get_vsync_irq); 545 546u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) 547{ 548 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) 549 return 0; 550 551 return mgr_desc[channel].framedone_irq; 552} 553EXPORT_SYMBOL(dispc_mgr_get_framedone_irq); 554 555u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) 556{ 557 return mgr_desc[channel].sync_lost_irq; 558} 559EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq); 560 561bool dispc_mgr_go_busy(enum omap_channel channel) 562{ 563 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; 564} 565EXPORT_SYMBOL(dispc_mgr_go_busy); 566 567void dispc_mgr_go(enum omap_channel channel) 568{ 569 WARN_ON(!dispc_mgr_is_enabled(channel)); 570 WARN_ON(dispc_mgr_go_busy(channel)); 571 572 DSSDBG("GO %s\n", mgr_desc[channel].name); 573 574 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); 575} 576EXPORT_SYMBOL(dispc_mgr_go); 577 578static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) 579{ 580 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); 581} 582 583static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) 584{ 585 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); 586} 587 588static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) 589{ 590 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); 591} 592 593static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) 594{ 595 BUG_ON(plane == OMAP_DSS_GFX); 596 597 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); 598} 599 600static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, 601 u32 value) 602{ 603 BUG_ON(plane == OMAP_DSS_GFX); 604 605 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 606} 607 608static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) 609{ 610 BUG_ON(plane == OMAP_DSS_GFX); 611 612 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); 613} 614 615static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, 616 int fir_vinc, int five_taps, 617 enum omap_color_component color_comp) 618{ 619 const struct dispc_coef *h_coef, *v_coef; 620 int i; 621 622 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); 623 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); 624 625 for (i = 0; i < 8; i++) { 626 u32 h, hv; 627 628 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) 629 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) 630 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) 631 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); 632 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) 633 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) 634 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) 635 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); 636 637 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 638 dispc_ovl_write_firh_reg(plane, i, h); 639 dispc_ovl_write_firhv_reg(plane, i, hv); 640 } else { 641 dispc_ovl_write_firh2_reg(plane, i, h); 642 dispc_ovl_write_firhv2_reg(plane, i, hv); 643 } 644 645 } 646 647 if (five_taps) { 648 for (i = 0; i < 8; i++) { 649 u32 v; 650 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) 651 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); 652 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) 653 dispc_ovl_write_firv_reg(plane, i, v); 654 else 655 dispc_ovl_write_firv2_reg(plane, i, v); 656 } 657 } 658} 659 660 661static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, 662 const struct color_conv_coef *ct) 663{ 664#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 665 666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); 667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); 668 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); 669 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 670 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 671 672 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 673 674#undef CVAL 675} 676 677static void dispc_setup_color_conv_coef(void) 678{ 679 int i; 680 int num_ovl = dss_feat_get_num_ovls(); 681 const struct color_conv_coef ctbl_bt601_5_ovl = { 682 /* YUV -> RGB */ 683 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, 684 }; 685 const struct color_conv_coef ctbl_bt601_5_wb = { 686 /* RGB -> YUV */ 687 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, 688 }; 689 690 for (i = 1; i < num_ovl; i++) 691 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); 692 693 if (dispc.feat->has_writeback) 694 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); 695} 696 697static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) 698{ 699 dispc_write_reg(DISPC_OVL_BA0(plane), paddr); 700} 701 702static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) 703{ 704 dispc_write_reg(DISPC_OVL_BA1(plane), paddr); 705} 706 707static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) 708{ 709 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); 710} 711 712static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) 713{ 714 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); 715} 716 717static void dispc_ovl_set_pos(enum omap_plane plane, 718 enum omap_overlay_caps caps, int x, int y) 719{ 720 u32 val; 721 722 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) 723 return; 724 725 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 726 727 dispc_write_reg(DISPC_OVL_POSITION(plane), val); 728} 729 730static void dispc_ovl_set_input_size(enum omap_plane plane, int width, 731 int height) 732{ 733 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 734 735 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) 736 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 737 else 738 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 739} 740 741static void dispc_ovl_set_output_size(enum omap_plane plane, int width, 742 int height) 743{ 744 u32 val; 745 746 BUG_ON(plane == OMAP_DSS_GFX); 747 748 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 749 750 if (plane == OMAP_DSS_WB) 751 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 752 else 753 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 754} 755 756static void dispc_ovl_set_zorder(enum omap_plane plane, 757 enum omap_overlay_caps caps, u8 zorder) 758{ 759 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 760 return; 761 762 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 763} 764 765static void dispc_ovl_enable_zorder_planes(void) 766{ 767 int i; 768 769 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 770 return; 771 772 for (i = 0; i < dss_feat_get_num_ovls(); i++) 773 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 774} 775 776static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, 777 enum omap_overlay_caps caps, bool enable) 778{ 779 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 780 return; 781 782 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 783} 784 785static void dispc_ovl_setup_global_alpha(enum omap_plane plane, 786 enum omap_overlay_caps caps, u8 global_alpha) 787{ 788 static const unsigned shifts[] = { 0, 8, 16, 24, }; 789 int shift; 790 791 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) 792 return; 793 794 shift = shifts[plane]; 795 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 796} 797 798static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) 799{ 800 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); 801} 802 803static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) 804{ 805 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); 806} 807 808static void dispc_ovl_set_color_mode(enum omap_plane plane, 809 enum omap_color_mode color_mode) 810{ 811 u32 m = 0; 812 if (plane != OMAP_DSS_GFX) { 813 switch (color_mode) { 814 case OMAP_DSS_COLOR_NV12: 815 m = 0x0; break; 816 case OMAP_DSS_COLOR_RGBX16: 817 m = 0x1; break; 818 case OMAP_DSS_COLOR_RGBA16: 819 m = 0x2; break; 820 case OMAP_DSS_COLOR_RGB12U: 821 m = 0x4; break; 822 case OMAP_DSS_COLOR_ARGB16: 823 m = 0x5; break; 824 case OMAP_DSS_COLOR_RGB16: 825 m = 0x6; break; 826 case OMAP_DSS_COLOR_ARGB16_1555: 827 m = 0x7; break; 828 case OMAP_DSS_COLOR_RGB24U: 829 m = 0x8; break; 830 case OMAP_DSS_COLOR_RGB24P: 831 m = 0x9; break; 832 case OMAP_DSS_COLOR_YUV2: 833 m = 0xa; break; 834 case OMAP_DSS_COLOR_UYVY: 835 m = 0xb; break; 836 case OMAP_DSS_COLOR_ARGB32: 837 m = 0xc; break; 838 case OMAP_DSS_COLOR_RGBA32: 839 m = 0xd; break; 840 case OMAP_DSS_COLOR_RGBX32: 841 m = 0xe; break; 842 case OMAP_DSS_COLOR_XRGB16_1555: 843 m = 0xf; break; 844 default: 845 BUG(); return; 846 } 847 } else { 848 switch (color_mode) { 849 case OMAP_DSS_COLOR_CLUT1: 850 m = 0x0; break; 851 case OMAP_DSS_COLOR_CLUT2: 852 m = 0x1; break; 853 case OMAP_DSS_COLOR_CLUT4: 854 m = 0x2; break; 855 case OMAP_DSS_COLOR_CLUT8: 856 m = 0x3; break; 857 case OMAP_DSS_COLOR_RGB12U: 858 m = 0x4; break; 859 case OMAP_DSS_COLOR_ARGB16: 860 m = 0x5; break; 861 case OMAP_DSS_COLOR_RGB16: 862 m = 0x6; break; 863 case OMAP_DSS_COLOR_ARGB16_1555: 864 m = 0x7; break; 865 case OMAP_DSS_COLOR_RGB24U: 866 m = 0x8; break; 867 case OMAP_DSS_COLOR_RGB24P: 868 m = 0x9; break; 869 case OMAP_DSS_COLOR_RGBX16: 870 m = 0xa; break; 871 case OMAP_DSS_COLOR_RGBA16: 872 m = 0xb; break; 873 case OMAP_DSS_COLOR_ARGB32: 874 m = 0xc; break; 875 case OMAP_DSS_COLOR_RGBA32: 876 m = 0xd; break; 877 case OMAP_DSS_COLOR_RGBX32: 878 m = 0xe; break; 879 case OMAP_DSS_COLOR_XRGB16_1555: 880 m = 0xf; break; 881 default: 882 BUG(); return; 883 } 884 } 885 886 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 887} 888 889static void dispc_ovl_configure_burst_type(enum omap_plane plane, 890 enum omap_dss_rotation_type rotation_type) 891{ 892 if (!dss_has_feature(FEAT_BURST_2D)) 893 return; 894 895 if (rotation_type == OMAP_DSS_ROT_TILER) 896 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); 897 else 898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 899} 900 901void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) 902{ 903 int shift; 904 u32 val; 905 int chan = 0, chan2 = 0; 906 907 switch (plane) { 908 case OMAP_DSS_GFX: 909 shift = 8; 910 break; 911 case OMAP_DSS_VIDEO1: 912 case OMAP_DSS_VIDEO2: 913 case OMAP_DSS_VIDEO3: 914 shift = 16; 915 break; 916 default: 917 BUG(); 918 return; 919 } 920 921 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 922 if (dss_has_feature(FEAT_MGR_LCD2)) { 923 switch (channel) { 924 case OMAP_DSS_CHANNEL_LCD: 925 chan = 0; 926 chan2 = 0; 927 break; 928 case OMAP_DSS_CHANNEL_DIGIT: 929 chan = 1; 930 chan2 = 0; 931 break; 932 case OMAP_DSS_CHANNEL_LCD2: 933 chan = 0; 934 chan2 = 1; 935 break; 936 case OMAP_DSS_CHANNEL_LCD3: 937 if (dss_has_feature(FEAT_MGR_LCD3)) { 938 chan = 0; 939 chan2 = 2; 940 } else { 941 BUG(); 942 return; 943 } 944 break; 945 case OMAP_DSS_CHANNEL_WB: 946 chan = 0; 947 chan2 = 3; 948 break; 949 default: 950 BUG(); 951 return; 952 } 953 954 val = FLD_MOD(val, chan, shift, shift); 955 val = FLD_MOD(val, chan2, 31, 30); 956 } else { 957 val = FLD_MOD(val, channel, shift, shift); 958 } 959 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 960} 961EXPORT_SYMBOL(dispc_ovl_set_channel_out); 962 963static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) 964{ 965 int shift; 966 u32 val; 967 968 switch (plane) { 969 case OMAP_DSS_GFX: 970 shift = 8; 971 break; 972 case OMAP_DSS_VIDEO1: 973 case OMAP_DSS_VIDEO2: 974 case OMAP_DSS_VIDEO3: 975 shift = 16; 976 break; 977 default: 978 BUG(); 979 return 0; 980 } 981 982 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 983 984 if (FLD_GET(val, shift, shift) == 1) 985 return OMAP_DSS_CHANNEL_DIGIT; 986 987 if (!dss_has_feature(FEAT_MGR_LCD2)) 988 return OMAP_DSS_CHANNEL_LCD; 989 990 switch (FLD_GET(val, 31, 30)) { 991 case 0: 992 default: 993 return OMAP_DSS_CHANNEL_LCD; 994 case 1: 995 return OMAP_DSS_CHANNEL_LCD2; 996 case 2: 997 return OMAP_DSS_CHANNEL_LCD3; 998 case 3: 999 return OMAP_DSS_CHANNEL_WB; 1000 } 1001} 1002 1003static void dispc_ovl_set_burst_size(enum omap_plane plane, 1004 enum omap_burst_size burst_size) 1005{ 1006 static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; 1007 int shift; 1008 1009 shift = shifts[plane]; 1010 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); 1011} 1012 1013static void dispc_configure_burst_sizes(void) 1014{ 1015 int i; 1016 const int burst_size = BURST_SIZE_X8; 1017 1018 /* Configure burst size always to maximum size */ 1019 for (i = 0; i < dss_feat_get_num_ovls(); ++i) 1020 dispc_ovl_set_burst_size(i, burst_size); 1021 if (dispc.feat->has_writeback) 1022 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); 1023} 1024 1025static u32 dispc_ovl_get_burst_size(enum omap_plane plane) 1026{ 1027 unsigned unit = dss_feat_get_burst_size_unit(); 1028 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1029 return unit * 8; 1030} 1031 1032void dispc_enable_gamma_table(bool enable) 1033{ 1034 /* 1035 * This is partially implemented to support only disabling of 1036 * the gamma table. 1037 */ 1038 if (enable) { 1039 DSSWARN("Gamma table enabling for TV not yet supported"); 1040 return; 1041 } 1042 1043 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); 1044} 1045 1046static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) 1047{ 1048 if (channel == OMAP_DSS_CHANNEL_DIGIT) 1049 return; 1050 1051 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); 1052} 1053 1054static void dispc_mgr_set_cpr_coef(enum omap_channel channel, 1055 const struct omap_dss_cpr_coefs *coefs) 1056{ 1057 u32 coef_r, coef_g, coef_b; 1058 1059 if (!dss_mgr_is_lcd(channel)) 1060 return; 1061 1062 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | 1063 FLD_VAL(coefs->rb, 9, 0); 1064 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | 1065 FLD_VAL(coefs->gb, 9, 0); 1066 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | 1067 FLD_VAL(coefs->bb, 9, 0); 1068 1069 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); 1070 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); 1071 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); 1072} 1073 1074static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) 1075{ 1076 u32 val; 1077 1078 BUG_ON(plane == OMAP_DSS_GFX); 1079 1080 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1081 val = FLD_MOD(val, enable, 9, 9); 1082 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1083} 1084 1085static void dispc_ovl_enable_replication(enum omap_plane plane, 1086 enum omap_overlay_caps caps, bool enable) 1087{ 1088 static const unsigned shifts[] = { 5, 10, 10, 10 }; 1089 int shift; 1090 1091 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) 1092 return; 1093 1094 shift = shifts[plane]; 1095 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); 1096} 1097 1098static void dispc_mgr_set_size(enum omap_channel channel, u16 width, 1099 u16 height) 1100{ 1101 u32 val; 1102 1103 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | 1104 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); 1105 1106 dispc_write_reg(DISPC_SIZE_MGR(channel), val); 1107} 1108 1109static void dispc_init_fifos(void) 1110{ 1111 u32 size; 1112 int fifo; 1113 u8 start, end; 1114 u32 unit; 1115 int i; 1116 1117 unit = dss_feat_get_buffer_size_unit(); 1118 1119 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); 1120 1121 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1122 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); 1123 size *= unit; 1124 dispc.fifo_size[fifo] = size; 1125 1126 /* 1127 * By default fifos are mapped directly to overlays, fifo 0 to 1128 * ovl 0, fifo 1 to ovl 1, etc. 1129 */ 1130 dispc.fifo_assignment[fifo] = fifo; 1131 } 1132 1133 /* 1134 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo 1135 * causes problems with certain use cases, like using the tiler in 2D 1136 * mode. The below hack swaps the fifos of GFX and WB planes, thus 1137 * giving GFX plane a larger fifo. WB but should work fine with a 1138 * smaller fifo. 1139 */ 1140 if (dispc.feat->gfx_fifo_workaround) { 1141 u32 v; 1142 1143 v = dispc_read_reg(DISPC_GLOBAL_BUFFER); 1144 1145 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ 1146 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ 1147 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ 1148 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ 1149 1150 dispc_write_reg(DISPC_GLOBAL_BUFFER, v); 1151 1152 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; 1153 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; 1154 } 1155 1156 /* 1157 * Setup default fifo thresholds. 1158 */ 1159 for (i = 0; i < dss_feat_get_num_ovls(); ++i) { 1160 u32 low, high; 1161 const bool use_fifomerge = false; 1162 const bool manual_update = false; 1163 1164 dispc_ovl_compute_fifo_thresholds(i, &low, &high, 1165 use_fifomerge, manual_update); 1166 1167 dispc_ovl_set_fifo_threshold(i, low, high); 1168 } 1169 1170 if (dispc.feat->has_writeback) { 1171 u32 low, high; 1172 const bool use_fifomerge = false; 1173 const bool manual_update = false; 1174 1175 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high, 1176 use_fifomerge, manual_update); 1177 1178 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high); 1179 } 1180} 1181 1182static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) 1183{ 1184 int fifo; 1185 u32 size = 0; 1186 1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1188 if (dispc.fifo_assignment[fifo] == plane) 1189 size += dispc.fifo_size[fifo]; 1190 } 1191 1192 return size; 1193} 1194 1195void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) 1196{ 1197 u8 hi_start, hi_end, lo_start, lo_end; 1198 u32 unit; 1199 1200 unit = dss_feat_get_buffer_size_unit(); 1201 1202 WARN_ON(low % unit != 0); 1203 WARN_ON(high % unit != 0); 1204 1205 low /= unit; 1206 high /= unit; 1207 1208 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); 1209 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); 1210 1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", 1212 plane, 1213 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1214 lo_start, lo_end) * unit, 1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1216 hi_start, hi_end) * unit, 1217 low * unit, high * unit); 1218 1219 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), 1220 FLD_VAL(high, hi_start, hi_end) | 1221 FLD_VAL(low, lo_start, lo_end)); 1222 1223 /* 1224 * configure the preload to the pipeline's high threhold, if HT it's too 1225 * large for the preload field, set the threshold to the maximum value 1226 * that can be held by the preload register 1227 */ 1228 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && 1229 plane != OMAP_DSS_WB) 1230 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); 1231} 1232 1233void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, 1234 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 1235 bool manual_update) 1236{ 1237 /* 1238 * All sizes are in bytes. Both the buffer and burst are made of 1239 * buffer_units, and the fifo thresholds must be buffer_unit aligned. 1240 */ 1241 1242 unsigned buf_unit = dss_feat_get_buffer_size_unit(); 1243 unsigned ovl_fifo_size, total_fifo_size, burst_size; 1244 int i; 1245 1246 burst_size = dispc_ovl_get_burst_size(plane); 1247 ovl_fifo_size = dispc_ovl_get_fifo_size(plane); 1248 1249 if (use_fifomerge) { 1250 total_fifo_size = 0; 1251 for (i = 0; i < dss_feat_get_num_ovls(); ++i) 1252 total_fifo_size += dispc_ovl_get_fifo_size(i); 1253 } else { 1254 total_fifo_size = ovl_fifo_size; 1255 } 1256 1257 /* 1258 * We use the same low threshold for both fifomerge and non-fifomerge 1259 * cases, but for fifomerge we calculate the high threshold using the 1260 * combined fifo size 1261 */ 1262 1263 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { 1264 *fifo_low = ovl_fifo_size - burst_size * 2; 1265 *fifo_high = total_fifo_size - burst_size; 1266 } else if (plane == OMAP_DSS_WB) { 1267 /* 1268 * Most optimal configuration for writeback is to push out data 1269 * to the interconnect the moment writeback pushes enough pixels 1270 * in the FIFO to form a burst 1271 */ 1272 *fifo_low = 0; 1273 *fifo_high = burst_size; 1274 } else { 1275 *fifo_low = ovl_fifo_size - burst_size; 1276 *fifo_high = total_fifo_size - buf_unit; 1277 } 1278} 1279 1280static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) 1281{ 1282 int bit; 1283 1284 if (plane == OMAP_DSS_GFX) 1285 bit = 14; 1286 else 1287 bit = 23; 1288 1289 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1290} 1291 1292static void dispc_ovl_set_mflag_threshold(enum omap_plane plane, 1293 int low, int high) 1294{ 1295 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), 1296 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 1297} 1298 1299static void dispc_init_mflag(void) 1300{ 1301 int i; 1302 1303 /* 1304 * HACK: NV12 color format and MFLAG seem to have problems working 1305 * together: using two displays, and having an NV12 overlay on one of 1306 * the displays will cause underflows/synclosts when MFLAG_CTRL=2. 1307 * Changing MFLAG thresholds and PRELOAD to certain values seem to 1308 * remove the errors, but there doesn't seem to be a clear logic on 1309 * which values work and which not. 1310 * 1311 * As a work-around, set force MFLAG to always on. 1312 */ 1313 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, 1314 (1 << 0) | /* MFLAG_CTRL = force always on */ 1315 (0 << 2)); /* MFLAG_START = disable */ 1316 1317 for (i = 0; i < dss_feat_get_num_ovls(); ++i) { 1318 u32 size = dispc_ovl_get_fifo_size(i); 1319 u32 unit = dss_feat_get_buffer_size_unit(); 1320 u32 low, high; 1321 1322 dispc_ovl_set_mflag(i, true); 1323 1324 /* 1325 * Simulation team suggests below thesholds: 1326 * HT = fifosize * 5 / 8; 1327 * LT = fifosize * 4 / 8; 1328 */ 1329 1330 low = size * 4 / 8 / unit; 1331 high = size * 5 / 8 / unit; 1332 1333 dispc_ovl_set_mflag_threshold(i, low, high); 1334 } 1335 1336 if (dispc.feat->has_writeback) { 1337 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); 1338 u32 unit = dss_feat_get_buffer_size_unit(); 1339 u32 low, high; 1340 1341 dispc_ovl_set_mflag(OMAP_DSS_WB, true); 1342 1343 /* 1344 * Simulation team suggests below thesholds: 1345 * HT = fifosize * 5 / 8; 1346 * LT = fifosize * 4 / 8; 1347 */ 1348 1349 low = size * 4 / 8 / unit; 1350 high = size * 5 / 8 / unit; 1351 1352 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high); 1353 } 1354} 1355 1356static void dispc_ovl_set_fir(enum omap_plane plane, 1357 int hinc, int vinc, 1358 enum omap_color_component color_comp) 1359{ 1360 u32 val; 1361 1362 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 1363 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1364 1365 dss_feat_get_reg_field(FEAT_REG_FIRHINC, 1366 &hinc_start, &hinc_end); 1367 dss_feat_get_reg_field(FEAT_REG_FIRVINC, 1368 &vinc_start, &vinc_end); 1369 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1370 FLD_VAL(hinc, hinc_start, hinc_end); 1371 1372 dispc_write_reg(DISPC_OVL_FIR(plane), val); 1373 } else { 1374 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); 1375 dispc_write_reg(DISPC_OVL_FIR2(plane), val); 1376 } 1377} 1378 1379static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) 1380{ 1381 u32 val; 1382 u8 hor_start, hor_end, vert_start, vert_end; 1383 1384 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1385 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1386 1387 val = FLD_VAL(vaccu, vert_start, vert_end) | 1388 FLD_VAL(haccu, hor_start, hor_end); 1389 1390 dispc_write_reg(DISPC_OVL_ACCU0(plane), val); 1391} 1392 1393static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) 1394{ 1395 u32 val; 1396 u8 hor_start, hor_end, vert_start, vert_end; 1397 1398 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1399 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1400 1401 val = FLD_VAL(vaccu, vert_start, vert_end) | 1402 FLD_VAL(haccu, hor_start, hor_end); 1403 1404 dispc_write_reg(DISPC_OVL_ACCU1(plane), val); 1405} 1406 1407static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, 1408 int vaccu) 1409{ 1410 u32 val; 1411 1412 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1413 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); 1414} 1415 1416static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, 1417 int vaccu) 1418{ 1419 u32 val; 1420 1421 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1422 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); 1423} 1424 1425static void dispc_ovl_set_scale_param(enum omap_plane plane, 1426 u16 orig_width, u16 orig_height, 1427 u16 out_width, u16 out_height, 1428 bool five_taps, u8 rotation, 1429 enum omap_color_component color_comp) 1430{ 1431 int fir_hinc, fir_vinc; 1432 1433 fir_hinc = 1024 * orig_width / out_width; 1434 fir_vinc = 1024 * orig_height / out_height; 1435 1436 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, 1437 color_comp); 1438 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); 1439} 1440 1441static void dispc_ovl_set_accu_uv(enum omap_plane plane, 1442 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, 1443 bool ilace, enum omap_color_mode color_mode, u8 rotation) 1444{ 1445 int h_accu2_0, h_accu2_1; 1446 int v_accu2_0, v_accu2_1; 1447 int chroma_hinc, chroma_vinc; 1448 int idx; 1449 1450 struct accu { 1451 s8 h0_m, h0_n; 1452 s8 h1_m, h1_n; 1453 s8 v0_m, v0_n; 1454 s8 v1_m, v1_n; 1455 }; 1456 1457 const struct accu *accu_table; 1458 const struct accu *accu_val; 1459 1460 static const struct accu accu_nv12[4] = { 1461 { 0, 1, 0, 1 , -1, 2, 0, 1 }, 1462 { 1, 2, -3, 4 , 0, 1, 0, 1 }, 1463 { -1, 1, 0, 1 , -1, 2, 0, 1 }, 1464 { -1, 2, -1, 2 , -1, 1, 0, 1 }, 1465 }; 1466 1467 static const struct accu accu_nv12_ilace[4] = { 1468 { 0, 1, 0, 1 , -3, 4, -1, 4 }, 1469 { -1, 4, -3, 4 , 0, 1, 0, 1 }, 1470 { -1, 1, 0, 1 , -1, 4, -3, 4 }, 1471 { -3, 4, -3, 4 , -1, 1, 0, 1 }, 1472 }; 1473 1474 static const struct accu accu_yuv[4] = { 1475 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1476 { 0, 1, 0, 1, 0, 1, 0, 1 }, 1477 { -1, 1, 0, 1, 0, 1, 0, 1 }, 1478 { 0, 1, 0, 1, -1, 1, 0, 1 }, 1479 }; 1480 1481 switch (rotation) { 1482 case OMAP_DSS_ROT_0: 1483 idx = 0; 1484 break; 1485 case OMAP_DSS_ROT_90: 1486 idx = 1; 1487 break; 1488 case OMAP_DSS_ROT_180: 1489 idx = 2; 1490 break; 1491 case OMAP_DSS_ROT_270: 1492 idx = 3; 1493 break; 1494 default: 1495 BUG(); 1496 return; 1497 } 1498 1499 switch (color_mode) { 1500 case OMAP_DSS_COLOR_NV12: 1501 if (ilace) 1502 accu_table = accu_nv12_ilace; 1503 else 1504 accu_table = accu_nv12; 1505 break; 1506 case OMAP_DSS_COLOR_YUV2: 1507 case OMAP_DSS_COLOR_UYVY: 1508 accu_table = accu_yuv; 1509 break; 1510 default: 1511 BUG(); 1512 return; 1513 } 1514 1515 accu_val = &accu_table[idx]; 1516 1517 chroma_hinc = 1024 * orig_width / out_width; 1518 chroma_vinc = 1024 * orig_height / out_height; 1519 1520 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; 1521 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; 1522 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; 1523 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; 1524 1525 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); 1526 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); 1527} 1528 1529static void dispc_ovl_set_scaling_common(enum omap_plane plane, 1530 u16 orig_width, u16 orig_height, 1531 u16 out_width, u16 out_height, 1532 bool ilace, bool five_taps, 1533 bool fieldmode, enum omap_color_mode color_mode, 1534 u8 rotation) 1535{ 1536 int accu0 = 0; 1537 int accu1 = 0; 1538 u32 l; 1539 1540 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1541 out_width, out_height, five_taps, 1542 rotation, DISPC_COLOR_COMPONENT_RGB_Y); 1543 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1544 1545 /* RESIZEENABLE and VERTICALTAPS */ 1546 l &= ~((0x3 << 5) | (0x1 << 21)); 1547 l |= (orig_width != out_width) ? (1 << 5) : 0; 1548 l |= (orig_height != out_height) ? (1 << 6) : 0; 1549 l |= five_taps ? (1 << 21) : 0; 1550 1551 /* VRESIZECONF and HRESIZECONF */ 1552 if (dss_has_feature(FEAT_RESIZECONF)) { 1553 l &= ~(0x3 << 7); 1554 l |= (orig_width <= out_width) ? 0 : (1 << 7); 1555 l |= (orig_height <= out_height) ? 0 : (1 << 8); 1556 } 1557 1558 /* LINEBUFFERSPLIT */ 1559 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { 1560 l &= ~(0x1 << 22); 1561 l |= five_taps ? (1 << 22) : 0; 1562 } 1563 1564 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 1565 1566 /* 1567 * field 0 = even field = bottom field 1568 * field 1 = odd field = top field 1569 */ 1570 if (ilace && !fieldmode) { 1571 accu1 = 0; 1572 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; 1573 if (accu0 >= 1024/2) { 1574 accu1 = 1024/2; 1575 accu0 -= accu1; 1576 } 1577 } 1578 1579 dispc_ovl_set_vid_accu0(plane, 0, accu0); 1580 dispc_ovl_set_vid_accu1(plane, 0, accu1); 1581} 1582 1583static void dispc_ovl_set_scaling_uv(enum omap_plane plane, 1584 u16 orig_width, u16 orig_height, 1585 u16 out_width, u16 out_height, 1586 bool ilace, bool five_taps, 1587 bool fieldmode, enum omap_color_mode color_mode, 1588 u8 rotation) 1589{ 1590 int scale_x = out_width != orig_width; 1591 int scale_y = out_height != orig_height; 1592 bool chroma_upscale = plane != OMAP_DSS_WB; 1593 1594 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) 1595 return; 1596 if ((color_mode != OMAP_DSS_COLOR_YUV2 && 1597 color_mode != OMAP_DSS_COLOR_UYVY && 1598 color_mode != OMAP_DSS_COLOR_NV12)) { 1599 /* reset chroma resampling for RGB formats */ 1600 if (plane != OMAP_DSS_WB) 1601 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); 1602 return; 1603 } 1604 1605 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, 1606 out_height, ilace, color_mode, rotation); 1607 1608 switch (color_mode) { 1609 case OMAP_DSS_COLOR_NV12: 1610 if (chroma_upscale) { 1611 /* UV is subsampled by 2 horizontally and vertically */ 1612 orig_height >>= 1; 1613 orig_width >>= 1; 1614 } else { 1615 /* UV is downsampled by 2 horizontally and vertically */ 1616 orig_height <<= 1; 1617 orig_width <<= 1; 1618 } 1619 1620 break; 1621 case OMAP_DSS_COLOR_YUV2: 1622 case OMAP_DSS_COLOR_UYVY: 1623 /* For YUV422 with 90/270 rotation, we don't upsample chroma */ 1624 if (rotation == OMAP_DSS_ROT_0 || 1625 rotation == OMAP_DSS_ROT_180) { 1626 if (chroma_upscale) 1627 /* UV is subsampled by 2 horizontally */ 1628 orig_width >>= 1; 1629 else 1630 /* UV is downsampled by 2 horizontally */ 1631 orig_width <<= 1; 1632 } 1633 1634 /* must use FIR for YUV422 if rotated */ 1635 if (rotation != OMAP_DSS_ROT_0) 1636 scale_x = scale_y = true; 1637 1638 break; 1639 default: 1640 BUG(); 1641 return; 1642 } 1643 1644 if (out_width != orig_width) 1645 scale_x = true; 1646 if (out_height != orig_height) 1647 scale_y = true; 1648 1649 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1650 out_width, out_height, five_taps, 1651 rotation, DISPC_COLOR_COMPONENT_UV); 1652 1653 if (plane != OMAP_DSS_WB) 1654 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 1655 (scale_x || scale_y) ? 1 : 0, 8, 8); 1656 1657 /* set H scaling */ 1658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); 1659 /* set V scaling */ 1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1661} 1662 1663static void dispc_ovl_set_scaling(enum omap_plane plane, 1664 u16 orig_width, u16 orig_height, 1665 u16 out_width, u16 out_height, 1666 bool ilace, bool five_taps, 1667 bool fieldmode, enum omap_color_mode color_mode, 1668 u8 rotation) 1669{ 1670 BUG_ON(plane == OMAP_DSS_GFX); 1671 1672 dispc_ovl_set_scaling_common(plane, 1673 orig_width, orig_height, 1674 out_width, out_height, 1675 ilace, five_taps, 1676 fieldmode, color_mode, 1677 rotation); 1678 1679 dispc_ovl_set_scaling_uv(plane, 1680 orig_width, orig_height, 1681 out_width, out_height, 1682 ilace, five_taps, 1683 fieldmode, color_mode, 1684 rotation); 1685} 1686 1687static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, 1688 enum omap_dss_rotation_type rotation_type, 1689 bool mirroring, enum omap_color_mode color_mode) 1690{ 1691 bool row_repeat = false; 1692 int vidrot = 0; 1693 1694 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1695 color_mode == OMAP_DSS_COLOR_UYVY) { 1696 1697 if (mirroring) { 1698 switch (rotation) { 1699 case OMAP_DSS_ROT_0: 1700 vidrot = 2; 1701 break; 1702 case OMAP_DSS_ROT_90: 1703 vidrot = 1; 1704 break; 1705 case OMAP_DSS_ROT_180: 1706 vidrot = 0; 1707 break; 1708 case OMAP_DSS_ROT_270: 1709 vidrot = 3; 1710 break; 1711 } 1712 } else { 1713 switch (rotation) { 1714 case OMAP_DSS_ROT_0: 1715 vidrot = 0; 1716 break; 1717 case OMAP_DSS_ROT_90: 1718 vidrot = 1; 1719 break; 1720 case OMAP_DSS_ROT_180: 1721 vidrot = 2; 1722 break; 1723 case OMAP_DSS_ROT_270: 1724 vidrot = 3; 1725 break; 1726 } 1727 } 1728 1729 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) 1730 row_repeat = true; 1731 else 1732 row_repeat = false; 1733 } 1734 1735 /* 1736 * OMAP4/5 Errata i631: 1737 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra 1738 * rows beyond the framebuffer, which may cause OCP error. 1739 */ 1740 if (color_mode == OMAP_DSS_COLOR_NV12 && 1741 rotation_type != OMAP_DSS_ROT_TILER) 1742 vidrot = 1; 1743 1744 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); 1745 if (dss_has_feature(FEAT_ROWREPEATENABLE)) 1746 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1747 row_repeat ? 1 : 0, 18, 18); 1748 1749 if (color_mode == OMAP_DSS_COLOR_NV12) { 1750 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) && 1751 (rotation == OMAP_DSS_ROT_0 || 1752 rotation == OMAP_DSS_ROT_180); 1753 /* DOUBLESTRIDE */ 1754 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); 1755 } 1756 1757} 1758 1759static int color_mode_to_bpp(enum omap_color_mode color_mode) 1760{ 1761 switch (color_mode) { 1762 case OMAP_DSS_COLOR_CLUT1: 1763 return 1; 1764 case OMAP_DSS_COLOR_CLUT2: 1765 return 2; 1766 case OMAP_DSS_COLOR_CLUT4: 1767 return 4; 1768 case OMAP_DSS_COLOR_CLUT8: 1769 case OMAP_DSS_COLOR_NV12: 1770 return 8; 1771 case OMAP_DSS_COLOR_RGB12U: 1772 case OMAP_DSS_COLOR_RGB16: 1773 case OMAP_DSS_COLOR_ARGB16: 1774 case OMAP_DSS_COLOR_YUV2: 1775 case OMAP_DSS_COLOR_UYVY: 1776 case OMAP_DSS_COLOR_RGBA16: 1777 case OMAP_DSS_COLOR_RGBX16: 1778 case OMAP_DSS_COLOR_ARGB16_1555: 1779 case OMAP_DSS_COLOR_XRGB16_1555: 1780 return 16; 1781 case OMAP_DSS_COLOR_RGB24P: 1782 return 24; 1783 case OMAP_DSS_COLOR_RGB24U: 1784 case OMAP_DSS_COLOR_ARGB32: 1785 case OMAP_DSS_COLOR_RGBA32: 1786 case OMAP_DSS_COLOR_RGBX32: 1787 return 32; 1788 default: 1789 BUG(); 1790 return 0; 1791 } 1792} 1793 1794static s32 pixinc(int pixels, u8 ps) 1795{ 1796 if (pixels == 1) 1797 return 1; 1798 else if (pixels > 1) 1799 return 1 + (pixels - 1) * ps; 1800 else if (pixels < 0) 1801 return 1 - (-pixels + 1) * ps; 1802 else 1803 BUG(); 1804 return 0; 1805} 1806 1807static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, 1808 u16 screen_width, 1809 u16 width, u16 height, 1810 enum omap_color_mode color_mode, bool fieldmode, 1811 unsigned int field_offset, 1812 unsigned *offset0, unsigned *offset1, 1813 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) 1814{ 1815 u8 ps; 1816 1817 /* FIXME CLUT formats */ 1818 switch (color_mode) { 1819 case OMAP_DSS_COLOR_CLUT1: 1820 case OMAP_DSS_COLOR_CLUT2: 1821 case OMAP_DSS_COLOR_CLUT4: 1822 case OMAP_DSS_COLOR_CLUT8: 1823 BUG(); 1824 return; 1825 case OMAP_DSS_COLOR_YUV2: 1826 case OMAP_DSS_COLOR_UYVY: 1827 ps = 4; 1828 break; 1829 default: 1830 ps = color_mode_to_bpp(color_mode) / 8; 1831 break; 1832 } 1833 1834 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, 1835 width, height); 1836 1837 /* 1838 * field 0 = even field = bottom field 1839 * field 1 = odd field = top field 1840 */ 1841 switch (rotation + mirror * 4) { 1842 case OMAP_DSS_ROT_0: 1843 case OMAP_DSS_ROT_180: 1844 /* 1845 * If the pixel format is YUV or UYVY divide the width 1846 * of the image by 2 for 0 and 180 degree rotation. 1847 */ 1848 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1849 color_mode == OMAP_DSS_COLOR_UYVY) 1850 width = width >> 1; 1851 fallthrough; 1852 case OMAP_DSS_ROT_90: 1853 case OMAP_DSS_ROT_270: 1854 *offset1 = 0; 1855 if (field_offset) 1856 *offset0 = field_offset * screen_width * ps; 1857 else 1858 *offset0 = 0; 1859 1860 *row_inc = pixinc(1 + 1861 (y_predecim * screen_width - x_predecim * width) + 1862 (fieldmode ? screen_width : 0), ps); 1863 *pix_inc = pixinc(x_predecim, ps); 1864 break; 1865 1866 case OMAP_DSS_ROT_0 + 4: 1867 case OMAP_DSS_ROT_180 + 4: 1868 /* If the pixel format is YUV or UYVY divide the width 1869 * of the image by 2 for 0 degree and 180 degree 1870 */ 1871 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1872 color_mode == OMAP_DSS_COLOR_UYVY) 1873 width = width >> 1; 1874 fallthrough; 1875 case OMAP_DSS_ROT_90 + 4: 1876 case OMAP_DSS_ROT_270 + 4: 1877 *offset1 = 0; 1878 if (field_offset) 1879 *offset0 = field_offset * screen_width * ps; 1880 else 1881 *offset0 = 0; 1882 *row_inc = pixinc(1 - 1883 (y_predecim * screen_width + x_predecim * width) - 1884 (fieldmode ? screen_width : 0), ps); 1885 *pix_inc = pixinc(x_predecim, ps); 1886 break; 1887 1888 default: 1889 BUG(); 1890 return; 1891 } 1892} 1893 1894static void calc_dma_rotation_offset(u8 rotation, bool mirror, 1895 u16 screen_width, 1896 u16 width, u16 height, 1897 enum omap_color_mode color_mode, bool fieldmode, 1898 unsigned int field_offset, 1899 unsigned *offset0, unsigned *offset1, 1900 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) 1901{ 1902 u8 ps; 1903 u16 fbw, fbh; 1904 1905 /* FIXME CLUT formats */ 1906 switch (color_mode) { 1907 case OMAP_DSS_COLOR_CLUT1: 1908 case OMAP_DSS_COLOR_CLUT2: 1909 case OMAP_DSS_COLOR_CLUT4: 1910 case OMAP_DSS_COLOR_CLUT8: 1911 BUG(); 1912 return; 1913 default: 1914 ps = color_mode_to_bpp(color_mode) / 8; 1915 break; 1916 } 1917 1918 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, 1919 width, height); 1920 1921 /* width & height are overlay sizes, convert to fb sizes */ 1922 1923 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { 1924 fbw = width; 1925 fbh = height; 1926 } else { 1927 fbw = height; 1928 fbh = width; 1929 } 1930 1931 /* 1932 * field 0 = even field = bottom field 1933 * field 1 = odd field = top field 1934 */ 1935 switch (rotation + mirror * 4) { 1936 case OMAP_DSS_ROT_0: 1937 *offset1 = 0; 1938 if (field_offset) 1939 *offset0 = *offset1 + field_offset * screen_width * ps; 1940 else 1941 *offset0 = *offset1; 1942 *row_inc = pixinc(1 + 1943 (y_predecim * screen_width - fbw * x_predecim) + 1944 (fieldmode ? screen_width : 0), ps); 1945 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1946 color_mode == OMAP_DSS_COLOR_UYVY) 1947 *pix_inc = pixinc(x_predecim, 2 * ps); 1948 else 1949 *pix_inc = pixinc(x_predecim, ps); 1950 break; 1951 case OMAP_DSS_ROT_90: 1952 *offset1 = screen_width * (fbh - 1) * ps; 1953 if (field_offset) 1954 *offset0 = *offset1 + field_offset * ps; 1955 else 1956 *offset0 = *offset1; 1957 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + 1958 y_predecim + (fieldmode ? 1 : 0), ps); 1959 *pix_inc = pixinc(-x_predecim * screen_width, ps); 1960 break; 1961 case OMAP_DSS_ROT_180: 1962 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; 1963 if (field_offset) 1964 *offset0 = *offset1 - field_offset * screen_width * ps; 1965 else 1966 *offset0 = *offset1; 1967 *row_inc = pixinc(-1 - 1968 (y_predecim * screen_width - fbw * x_predecim) - 1969 (fieldmode ? screen_width : 0), ps); 1970 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1971 color_mode == OMAP_DSS_COLOR_UYVY) 1972 *pix_inc = pixinc(-x_predecim, 2 * ps); 1973 else 1974 *pix_inc = pixinc(-x_predecim, ps); 1975 break; 1976 case OMAP_DSS_ROT_270: 1977 *offset1 = (fbw - 1) * ps; 1978 if (field_offset) 1979 *offset0 = *offset1 - field_offset * ps; 1980 else 1981 *offset0 = *offset1; 1982 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - 1983 y_predecim - (fieldmode ? 1 : 0), ps); 1984 *pix_inc = pixinc(x_predecim * screen_width, ps); 1985 break; 1986 1987 /* mirroring */ 1988 case OMAP_DSS_ROT_0 + 4: 1989 *offset1 = (fbw - 1) * ps; 1990 if (field_offset) 1991 *offset0 = *offset1 + field_offset * screen_width * ps; 1992 else 1993 *offset0 = *offset1; 1994 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + 1995 (fieldmode ? screen_width : 0), 1996 ps); 1997 if (color_mode == OMAP_DSS_COLOR_YUV2 || 1998 color_mode == OMAP_DSS_COLOR_UYVY) 1999 *pix_inc = pixinc(-x_predecim, 2 * ps); 2000 else 2001 *pix_inc = pixinc(-x_predecim, ps); 2002 break; 2003 2004 case OMAP_DSS_ROT_90 + 4: 2005 *offset1 = 0; 2006 if (field_offset) 2007 *offset0 = *offset1 + field_offset * ps; 2008 else 2009 *offset0 = *offset1; 2010 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + 2011 y_predecim + (fieldmode ? 1 : 0), 2012 ps); 2013 *pix_inc = pixinc(x_predecim * screen_width, ps); 2014 break; 2015 2016 case OMAP_DSS_ROT_180 + 4: 2017 *offset1 = screen_width * (fbh - 1) * ps; 2018 if (field_offset) 2019 *offset0 = *offset1 - field_offset * screen_width * ps; 2020 else 2021 *offset0 = *offset1; 2022 *row_inc = pixinc(1 - y_predecim * screen_width * 2 - 2023 (fieldmode ? screen_width : 0), 2024 ps); 2025 if (color_mode == OMAP_DSS_COLOR_YUV2 || 2026 color_mode == OMAP_DSS_COLOR_UYVY) 2027 *pix_inc = pixinc(x_predecim, 2 * ps); 2028 else 2029 *pix_inc = pixinc(x_predecim, ps); 2030 break; 2031 2032 case OMAP_DSS_ROT_270 + 4: 2033 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; 2034 if (field_offset) 2035 *offset0 = *offset1 - field_offset * ps; 2036 else 2037 *offset0 = *offset1; 2038 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - 2039 y_predecim - (fieldmode ? 1 : 0), 2040 ps); 2041 *pix_inc = pixinc(-x_predecim * screen_width, ps); 2042 break; 2043 2044 default: 2045 BUG(); 2046 return; 2047 } 2048} 2049 2050static void calc_tiler_rotation_offset(u16 screen_width, u16 width, 2051 enum omap_color_mode color_mode, bool fieldmode, 2052 unsigned int field_offset, unsigned *offset0, unsigned *offset1, 2053 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) 2054{ 2055 u8 ps; 2056 2057 switch (color_mode) { 2058 case OMAP_DSS_COLOR_CLUT1: 2059 case OMAP_DSS_COLOR_CLUT2: 2060 case OMAP_DSS_COLOR_CLUT4: 2061 case OMAP_DSS_COLOR_CLUT8: 2062 BUG(); 2063 return; 2064 default: 2065 ps = color_mode_to_bpp(color_mode) / 8; 2066 break; 2067 } 2068 2069 DSSDBG("scrw %d, width %d\n", screen_width, width); 2070 2071 /* 2072 * field 0 = even field = bottom field 2073 * field 1 = odd field = top field 2074 */ 2075 *offset1 = 0; 2076 if (field_offset) 2077 *offset0 = *offset1 + field_offset * screen_width * ps; 2078 else 2079 *offset0 = *offset1; 2080 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + 2081 (fieldmode ? screen_width : 0), ps); 2082 if (color_mode == OMAP_DSS_COLOR_YUV2 || 2083 color_mode == OMAP_DSS_COLOR_UYVY) 2084 *pix_inc = pixinc(x_predecim, 2 * ps); 2085 else 2086 *pix_inc = pixinc(x_predecim, ps); 2087} 2088 2089/* 2090 * This function is used to avoid synclosts in OMAP3, because of some 2091 * undocumented horizontal position and timing related limitations. 2092 */ 2093static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 2094 const struct omap_video_timings *t, u16 pos_x, 2095 u16 width, u16 height, u16 out_width, u16 out_height, 2096 bool five_taps) 2097{ 2098 const int ds = DIV_ROUND_UP(height, out_height); 2099 unsigned long nonactive; 2100 static const u8 limits[3] = { 8, 10, 20 }; 2101 u64 val, blank; 2102 int i; 2103 2104 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; 2105 2106 i = 0; 2107 if (out_height < height) 2108 i++; 2109 if (out_width < width) 2110 i++; 2111 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); 2112 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 2113 if (blank <= limits[i]) 2114 return -EINVAL; 2115 2116 /* FIXME add checks for 3-tap filter once the limitations are known */ 2117 if (!five_taps) 2118 return 0; 2119 2120 /* 2121 * Pixel data should be prepared before visible display point starts. 2122 * So, atleast DS-2 lines must have already been fetched by DISPC 2123 * during nonactive - pos_x period. 2124 */ 2125 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); 2126 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", 2127 val, max(0, ds - 2) * width); 2128 if (val < max(0, ds - 2) * width) 2129 return -EINVAL; 2130 2131 /* 2132 * All lines need to be refilled during the nonactive period of which 2133 * only one line can be loaded during the active period. So, atleast 2134 * DS - 1 lines should be loaded during nonactive period. 2135 */ 2136 val = div_u64((u64)nonactive * lclk, pclk); 2137 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", 2138 val, max(0, ds - 1) * width); 2139 if (val < max(0, ds - 1) * width) 2140 return -EINVAL; 2141 2142 return 0; 2143} 2144 2145static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2146 const struct omap_video_timings *mgr_timings, u16 width, 2147 u16 height, u16 out_width, u16 out_height, 2148 enum omap_color_mode color_mode) 2149{ 2150 u32 core_clk = 0; 2151 u64 tmp; 2152 2153 if (height <= out_height && width <= out_width) 2154 return (unsigned long) pclk; 2155 2156 if (height > out_height) { 2157 unsigned int ppl = mgr_timings->x_res; 2158 2159 tmp = (u64)pclk * height * out_width; 2160 do_div(tmp, 2 * out_height * ppl); 2161 core_clk = tmp; 2162 2163 if (height > 2 * out_height) { 2164 if (ppl == out_width) 2165 return 0; 2166 2167 tmp = (u64)pclk * (height - 2 * out_height) * out_width; 2168 do_div(tmp, 2 * out_height * (ppl - out_width)); 2169 core_clk = max_t(u32, core_clk, tmp); 2170 } 2171 } 2172 2173 if (width > out_width) { 2174 tmp = (u64)pclk * width; 2175 do_div(tmp, out_width); 2176 core_clk = max_t(u32, core_clk, tmp); 2177 2178 if (color_mode == OMAP_DSS_COLOR_RGB24U) 2179 core_clk <<= 1; 2180 } 2181 2182 return core_clk; 2183} 2184 2185static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, 2186 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2187{ 2188 if (height > out_height && width > out_width) 2189 return pclk * 4; 2190 else 2191 return pclk * 2; 2192} 2193 2194static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, 2195 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2196{ 2197 unsigned int hf, vf; 2198 2199 /* 2200 * FIXME how to determine the 'A' factor 2201 * for the no downscaling case ? 2202 */ 2203 2204 if (width > 3 * out_width) 2205 hf = 4; 2206 else if (width > 2 * out_width) 2207 hf = 3; 2208 else if (width > out_width) 2209 hf = 2; 2210 else 2211 hf = 1; 2212 if (height > out_height) 2213 vf = 2; 2214 else 2215 vf = 1; 2216 2217 return pclk * vf * hf; 2218} 2219 2220static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, 2221 u16 height, u16 out_width, u16 out_height, bool mem_to_mem) 2222{ 2223 /* 2224 * If the overlay/writeback is in mem to mem mode, there are no 2225 * downscaling limitations with respect to pixel clock, return 1 as 2226 * required core clock to represent that we have sufficient enough 2227 * core clock to do maximum downscaling 2228 */ 2229 if (mem_to_mem) 2230 return 1; 2231 2232 if (width > out_width) 2233 return DIV_ROUND_UP(pclk, out_width) * width; 2234 else 2235 return pclk; 2236} 2237 2238static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, 2239 const struct omap_video_timings *mgr_timings, 2240 u16 width, u16 height, u16 out_width, u16 out_height, 2241 enum omap_color_mode color_mode, bool *five_taps, 2242 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2243 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2244{ 2245 int error; 2246 u16 in_width, in_height; 2247 int min_factor = min(*decim_x, *decim_y); 2248 const int maxsinglelinewidth = 2249 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2250 2251 *five_taps = false; 2252 2253 do { 2254 in_height = height / *decim_y; 2255 in_width = width / *decim_x; 2256 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2257 in_height, out_width, out_height, mem_to_mem); 2258 error = (in_width > maxsinglelinewidth || !*core_clk || 2259 *core_clk > dispc_core_clk_rate()); 2260 if (error) { 2261 if (*decim_x == *decim_y) { 2262 *decim_x = min_factor; 2263 ++*decim_y; 2264 } else { 2265 swap(*decim_x, *decim_y); 2266 if (*decim_x < *decim_y) 2267 ++*decim_x; 2268 } 2269 } 2270 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2271 2272 if (error) { 2273 DSSERR("failed to find scaling settings\n"); 2274 return -EINVAL; 2275 } 2276 2277 if (in_width > maxsinglelinewidth) { 2278 DSSERR("Cannot scale max input width exceeded"); 2279 return -EINVAL; 2280 } 2281 return 0; 2282} 2283 2284static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, 2285 const struct omap_video_timings *mgr_timings, 2286 u16 width, u16 height, u16 out_width, u16 out_height, 2287 enum omap_color_mode color_mode, bool *five_taps, 2288 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2289 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2290{ 2291 int error; 2292 u16 in_width, in_height; 2293 const int maxsinglelinewidth = 2294 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2295 2296 do { 2297 in_height = height / *decim_y; 2298 in_width = width / *decim_x; 2299 *five_taps = in_height > out_height; 2300 2301 if (in_width > maxsinglelinewidth) 2302 if (in_height > out_height && 2303 in_height < out_height * 2) 2304 *five_taps = false; 2305again: 2306 if (*five_taps) 2307 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, 2308 in_width, in_height, out_width, 2309 out_height, color_mode); 2310 else 2311 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2312 in_height, out_width, out_height, 2313 mem_to_mem); 2314 2315 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, 2316 pos_x, in_width, in_height, out_width, 2317 out_height, *five_taps); 2318 if (error && *five_taps) { 2319 *five_taps = false; 2320 goto again; 2321 } 2322 2323 error = (error || in_width > maxsinglelinewidth * 2 || 2324 (in_width > maxsinglelinewidth && *five_taps) || 2325 !*core_clk || *core_clk > dispc_core_clk_rate()); 2326 2327 if (!error) { 2328 /* verify that we're inside the limits of scaler */ 2329 if (in_width / 4 > out_width) 2330 error = 1; 2331 2332 if (*five_taps) { 2333 if (in_height / 4 > out_height) 2334 error = 1; 2335 } else { 2336 if (in_height / 2 > out_height) 2337 error = 1; 2338 } 2339 } 2340 2341 if (error) 2342 ++*decim_y; 2343 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); 2344 2345 if (error) { 2346 DSSERR("failed to find scaling settings\n"); 2347 return -EINVAL; 2348 } 2349 2350 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, 2351 in_height, out_width, out_height, *five_taps)) { 2352 DSSERR("horizontal timing too tight\n"); 2353 return -EINVAL; 2354 } 2355 2356 if (in_width > (maxsinglelinewidth * 2)) { 2357 DSSERR("Cannot setup scaling"); 2358 DSSERR("width exceeds maximum width possible"); 2359 return -EINVAL; 2360 } 2361 2362 if (in_width > maxsinglelinewidth && *five_taps) { 2363 DSSERR("cannot setup scaling with five taps"); 2364 return -EINVAL; 2365 } 2366 return 0; 2367} 2368 2369static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, 2370 const struct omap_video_timings *mgr_timings, 2371 u16 width, u16 height, u16 out_width, u16 out_height, 2372 enum omap_color_mode color_mode, bool *five_taps, 2373 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2374 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2375{ 2376 u16 in_width, in_width_max; 2377 int decim_x_min = *decim_x; 2378 u16 in_height = height / *decim_y; 2379 const int maxsinglelinewidth = 2380 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); 2381 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); 2382 2383 if (mem_to_mem) { 2384 in_width_max = out_width * maxdownscale; 2385 } else { 2386 in_width_max = dispc_core_clk_rate() / 2387 DIV_ROUND_UP(pclk, out_width); 2388 } 2389 2390 *decim_x = DIV_ROUND_UP(width, in_width_max); 2391 2392 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; 2393 if (*decim_x > *x_predecim) 2394 return -EINVAL; 2395 2396 do { 2397 in_width = width / *decim_x; 2398 } while (*decim_x <= *x_predecim && 2399 in_width > maxsinglelinewidth && ++*decim_x); 2400 2401 if (in_width > maxsinglelinewidth) { 2402 DSSERR("Cannot scale width exceeds max line width"); 2403 return -EINVAL; 2404 } 2405 2406 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, 2407 out_width, out_height, mem_to_mem); 2408 return 0; 2409} 2410 2411#define DIV_FRAC(dividend, divisor) \ 2412 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) 2413 2414static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, 2415 enum omap_overlay_caps caps, 2416 const struct omap_video_timings *mgr_timings, 2417 u16 width, u16 height, u16 out_width, u16 out_height, 2418 enum omap_color_mode color_mode, bool *five_taps, 2419 int *x_predecim, int *y_predecim, u16 pos_x, 2420 enum omap_dss_rotation_type rotation_type, bool mem_to_mem) 2421{ 2422 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); 2423 const int max_decim_limit = 16; 2424 unsigned long core_clk = 0; 2425 int decim_x, decim_y, ret; 2426 2427 if (width == out_width && height == out_height) 2428 return 0; 2429 2430 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) { 2431 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2432 return -EINVAL; 2433 } 2434 2435 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) 2436 return -EINVAL; 2437 2438 if (mem_to_mem) { 2439 *x_predecim = *y_predecim = 1; 2440 } else { 2441 *x_predecim = max_decim_limit; 2442 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && 2443 dss_has_feature(FEAT_BURST_2D)) ? 2444 2 : max_decim_limit; 2445 } 2446 2447 if (color_mode == OMAP_DSS_COLOR_CLUT1 || 2448 color_mode == OMAP_DSS_COLOR_CLUT2 || 2449 color_mode == OMAP_DSS_COLOR_CLUT4 || 2450 color_mode == OMAP_DSS_COLOR_CLUT8) { 2451 *x_predecim = 1; 2452 *y_predecim = 1; 2453 *five_taps = false; 2454 return 0; 2455 } 2456 2457 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); 2458 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); 2459 2460 if (decim_x > *x_predecim || out_width > width * 8) 2461 return -EINVAL; 2462 2463 if (decim_y > *y_predecim || out_height > height * 8) 2464 return -EINVAL; 2465 2466 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, 2467 out_width, out_height, color_mode, five_taps, 2468 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, 2469 mem_to_mem); 2470 if (ret) 2471 return ret; 2472 2473 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", 2474 width, height, 2475 out_width, out_height, 2476 out_width / width, DIV_FRAC(out_width, width), 2477 out_height / height, DIV_FRAC(out_height, height), 2478 2479 decim_x, decim_y, 2480 width / decim_x, height / decim_y, 2481 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), 2482 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), 2483 2484 *five_taps ? 5 : 3, 2485 core_clk, dispc_core_clk_rate()); 2486 2487 if (!core_clk || core_clk > dispc_core_clk_rate()) { 2488 DSSERR("failed to set up scaling, " 2489 "required core clk rate = %lu Hz, " 2490 "current core clk rate = %lu Hz\n", 2491 core_clk, dispc_core_clk_rate()); 2492 return -EINVAL; 2493 } 2494 2495 *x_predecim = decim_x; 2496 *y_predecim = decim_y; 2497 return 0; 2498} 2499 2500int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, 2501 const struct omap_overlay_info *oi, 2502 const struct omap_video_timings *timings, 2503 int *x_predecim, int *y_predecim) 2504{ 2505 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); 2506 bool five_taps = true; 2507 bool fieldmode = false; 2508 u16 in_height = oi->height; 2509 u16 in_width = oi->width; 2510 bool ilace = timings->interlace; 2511 u16 out_width, out_height; 2512 int pos_x = oi->pos_x; 2513 unsigned long pclk = dispc_mgr_pclk_rate(channel); 2514 unsigned long lclk = dispc_mgr_lclk_rate(channel); 2515 2516 out_width = oi->out_width == 0 ? oi->width : oi->out_width; 2517 out_height = oi->out_height == 0 ? oi->height : oi->out_height; 2518 2519 if (ilace && oi->height == out_height) 2520 fieldmode = true; 2521 2522 if (ilace) { 2523 if (fieldmode) 2524 in_height /= 2; 2525 out_height /= 2; 2526 2527 DSSDBG("adjusting for ilace: height %d, out_height %d\n", 2528 in_height, out_height); 2529 } 2530 2531 if (!dss_feat_color_mode_supported(plane, oi->color_mode)) 2532 return -EINVAL; 2533 2534 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width, 2535 in_height, out_width, out_height, oi->color_mode, 2536 &five_taps, x_predecim, y_predecim, pos_x, 2537 oi->rotation_type, false); 2538} 2539EXPORT_SYMBOL(dispc_ovl_check); 2540 2541static int dispc_ovl_setup_common(enum omap_plane plane, 2542 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, 2543 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, 2544 u16 out_width, u16 out_height, enum omap_color_mode color_mode, 2545 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, 2546 u8 global_alpha, enum omap_dss_rotation_type rotation_type, 2547 bool replication, const struct omap_video_timings *mgr_timings, 2548 bool mem_to_mem) 2549{ 2550 bool five_taps = true; 2551 bool fieldmode = false; 2552 int r, cconv = 0; 2553 unsigned offset0, offset1; 2554 s32 row_inc; 2555 s32 pix_inc; 2556 u16 frame_width, frame_height; 2557 unsigned int field_offset = 0; 2558 u16 in_height = height; 2559 u16 in_width = width; 2560 int x_predecim = 1, y_predecim = 1; 2561 bool ilace = mgr_timings->interlace; 2562 unsigned long pclk = dispc_plane_pclk_rate(plane); 2563 unsigned long lclk = dispc_plane_lclk_rate(plane); 2564 2565 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) 2566 return -EINVAL; 2567 2568 switch (color_mode) { 2569 case OMAP_DSS_COLOR_YUV2: 2570 case OMAP_DSS_COLOR_UYVY: 2571 case OMAP_DSS_COLOR_NV12: 2572 if (in_width & 1) { 2573 DSSERR("input width %d is not even for YUV format\n", 2574 in_width); 2575 return -EINVAL; 2576 } 2577 break; 2578 2579 default: 2580 break; 2581 } 2582 2583 out_width = out_width == 0 ? width : out_width; 2584 out_height = out_height == 0 ? height : out_height; 2585 2586 if (ilace && height == out_height) 2587 fieldmode = true; 2588 2589 if (ilace) { 2590 if (fieldmode) 2591 in_height /= 2; 2592 pos_y /= 2; 2593 out_height /= 2; 2594 2595 DSSDBG("adjusting for ilace: height %d, pos_y %d, " 2596 "out_height %d\n", in_height, pos_y, 2597 out_height); 2598 } 2599 2600 if (!dss_feat_color_mode_supported(plane, color_mode)) 2601 return -EINVAL; 2602 2603 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width, 2604 in_height, out_width, out_height, color_mode, 2605 &five_taps, &x_predecim, &y_predecim, pos_x, 2606 rotation_type, mem_to_mem); 2607 if (r) 2608 return r; 2609 2610 in_width = in_width / x_predecim; 2611 in_height = in_height / y_predecim; 2612 2613 if (x_predecim > 1 || y_predecim > 1) 2614 DSSDBG("predecimation %d x %x, new input size %d x %d\n", 2615 x_predecim, y_predecim, in_width, in_height); 2616 2617 switch (color_mode) { 2618 case OMAP_DSS_COLOR_YUV2: 2619 case OMAP_DSS_COLOR_UYVY: 2620 case OMAP_DSS_COLOR_NV12: 2621 if (in_width & 1) { 2622 DSSDBG("predecimated input width is not even for YUV format\n"); 2623 DSSDBG("adjusting input width %d -> %d\n", 2624 in_width, in_width & ~1); 2625 2626 in_width &= ~1; 2627 } 2628 break; 2629 2630 default: 2631 break; 2632 } 2633 2634 if (color_mode == OMAP_DSS_COLOR_YUV2 || 2635 color_mode == OMAP_DSS_COLOR_UYVY || 2636 color_mode == OMAP_DSS_COLOR_NV12) 2637 cconv = 1; 2638 2639 if (ilace && !fieldmode) { 2640 /* 2641 * when downscaling the bottom field may have to start several 2642 * source lines below the top field. Unfortunately ACCUI 2643 * registers will only hold the fractional part of the offset 2644 * so the integer part must be added to the base address of the 2645 * bottom field. 2646 */ 2647 if (!in_height || in_height == out_height) 2648 field_offset = 0; 2649 else 2650 field_offset = in_height / out_height / 2; 2651 } 2652 2653 /* Fields are independent but interleaved in memory. */ 2654 if (fieldmode) 2655 field_offset = 1; 2656 2657 offset0 = 0; 2658 offset1 = 0; 2659 row_inc = 0; 2660 pix_inc = 0; 2661 2662 frame_width = in_width; 2663 frame_height = height; 2664 2665 if (rotation_type == OMAP_DSS_ROT_TILER) 2666 calc_tiler_rotation_offset(screen_width, frame_width, 2667 color_mode, fieldmode, field_offset, 2668 &offset0, &offset1, &row_inc, &pix_inc, 2669 x_predecim, y_predecim); 2670 else if (rotation_type == OMAP_DSS_ROT_DMA) 2671 calc_dma_rotation_offset(rotation, mirror, screen_width, 2672 frame_width, frame_height, 2673 color_mode, fieldmode, field_offset, 2674 &offset0, &offset1, &row_inc, &pix_inc, 2675 x_predecim, y_predecim); 2676 else 2677 calc_vrfb_rotation_offset(rotation, mirror, 2678 screen_width, frame_width, frame_height, 2679 color_mode, fieldmode, field_offset, 2680 &offset0, &offset1, &row_inc, &pix_inc, 2681 x_predecim, y_predecim); 2682 2683 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", 2684 offset0, offset1, row_inc, pix_inc); 2685 2686 dispc_ovl_set_color_mode(plane, color_mode); 2687 2688 dispc_ovl_configure_burst_type(plane, rotation_type); 2689 2690 dispc_ovl_set_ba0(plane, paddr + offset0); 2691 dispc_ovl_set_ba1(plane, paddr + offset1); 2692 2693 if (OMAP_DSS_COLOR_NV12 == color_mode) { 2694 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); 2695 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); 2696 } 2697 2698 if (dispc.feat->last_pixel_inc_missing) 2699 row_inc += pix_inc - 1; 2700 2701 dispc_ovl_set_row_inc(plane, row_inc); 2702 dispc_ovl_set_pix_inc(plane, pix_inc); 2703 2704 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, 2705 in_height, out_width, out_height); 2706 2707 dispc_ovl_set_pos(plane, caps, pos_x, pos_y); 2708 2709 dispc_ovl_set_input_size(plane, in_width, in_height); 2710 2711 if (caps & OMAP_DSS_OVL_CAP_SCALE) { 2712 dispc_ovl_set_scaling(plane, in_width, in_height, out_width, 2713 out_height, ilace, five_taps, fieldmode, 2714 color_mode, rotation); 2715 dispc_ovl_set_output_size(plane, out_width, out_height); 2716 dispc_ovl_set_vid_color_conv(plane, cconv); 2717 } 2718 2719 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror, 2720 color_mode); 2721 2722 dispc_ovl_set_zorder(plane, caps, zorder); 2723 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); 2724 dispc_ovl_setup_global_alpha(plane, caps, global_alpha); 2725 2726 dispc_ovl_enable_replication(plane, caps, replication); 2727 2728 return 0; 2729} 2730 2731int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 2732 bool replication, const struct omap_video_timings *mgr_timings, 2733 bool mem_to_mem) 2734{ 2735 int r; 2736 enum omap_overlay_caps caps; 2737 enum omap_channel channel; 2738 2739 if (plane == OMAP_DSS_WB) 2740 return -EINVAL; 2741 2742 caps = dss_feat_get_overlay_caps(plane); 2743 channel = dispc_ovl_get_channel_out(plane); 2744 2745 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2746 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", 2747 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, 2748 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, 2749 oi->color_mode, oi->rotation, oi->mirror, channel, replication); 2750 2751 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, 2752 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2753 oi->out_width, oi->out_height, oi->color_mode, oi->rotation, 2754 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2755 oi->rotation_type, replication, mgr_timings, mem_to_mem); 2756 2757 return r; 2758} 2759EXPORT_SYMBOL(dispc_ovl_setup); 2760 2761int dispc_ovl_enable(enum omap_plane plane, bool enable) 2762{ 2763 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2764 2765 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2766 2767 return 0; 2768} 2769EXPORT_SYMBOL(dispc_ovl_enable); 2770 2771bool dispc_ovl_enabled(enum omap_plane plane) 2772{ 2773 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); 2774} 2775EXPORT_SYMBOL(dispc_ovl_enabled); 2776 2777void dispc_mgr_enable(enum omap_channel channel, bool enable) 2778{ 2779 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); 2780 /* flush posted write */ 2781 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 2782} 2783EXPORT_SYMBOL(dispc_mgr_enable); 2784 2785bool dispc_mgr_is_enabled(enum omap_channel channel) 2786{ 2787 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 2788} 2789EXPORT_SYMBOL(dispc_mgr_is_enabled); 2790 2791static void dispc_lcd_enable_signal_polarity(bool act_high) 2792{ 2793 if (!dss_has_feature(FEAT_LCDENABLEPOL)) 2794 return; 2795 2796 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2797} 2798 2799void dispc_lcd_enable_signal(bool enable) 2800{ 2801 if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) 2802 return; 2803 2804 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2805} 2806 2807void dispc_pck_free_enable(bool enable) 2808{ 2809 if (!dss_has_feature(FEAT_PCKFREEENABLE)) 2810 return; 2811 2812 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2813} 2814 2815static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) 2816{ 2817 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2818} 2819 2820 2821static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) 2822{ 2823 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); 2824} 2825 2826static void dispc_set_loadmode(enum omap_dss_load_mode mode) 2827{ 2828 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); 2829} 2830 2831 2832static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) 2833{ 2834 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); 2835} 2836 2837static void dispc_mgr_set_trans_key(enum omap_channel ch, 2838 enum omap_dss_trans_key_type type, 2839 u32 trans_key) 2840{ 2841 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); 2842 2843 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); 2844} 2845 2846static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) 2847{ 2848 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); 2849} 2850 2851static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, 2852 bool enable) 2853{ 2854 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) 2855 return; 2856 2857 if (ch == OMAP_DSS_CHANNEL_LCD) 2858 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); 2859 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2860 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); 2861} 2862 2863void dispc_mgr_setup(enum omap_channel channel, 2864 const struct omap_overlay_manager_info *info) 2865{ 2866 dispc_mgr_set_default_color(channel, info->default_color); 2867 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); 2868 dispc_mgr_enable_trans_key(channel, info->trans_enabled); 2869 dispc_mgr_enable_alpha_fixed_zorder(channel, 2870 info->partial_alpha_enabled); 2871 if (dss_has_feature(FEAT_CPR)) { 2872 dispc_mgr_enable_cpr(channel, info->cpr_enable); 2873 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); 2874 } 2875} 2876EXPORT_SYMBOL(dispc_mgr_setup); 2877 2878static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) 2879{ 2880 int code; 2881 2882 switch (data_lines) { 2883 case 12: 2884 code = 0; 2885 break; 2886 case 16: 2887 code = 1; 2888 break; 2889 case 18: 2890 code = 2; 2891 break; 2892 case 24: 2893 code = 3; 2894 break; 2895 default: 2896 BUG(); 2897 return; 2898 } 2899 2900 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); 2901} 2902 2903static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) 2904{ 2905 u32 l; 2906 int gpout0, gpout1; 2907 2908 switch (mode) { 2909 case DSS_IO_PAD_MODE_RESET: 2910 gpout0 = 0; 2911 gpout1 = 0; 2912 break; 2913 case DSS_IO_PAD_MODE_RFBI: 2914 gpout0 = 1; 2915 gpout1 = 0; 2916 break; 2917 case DSS_IO_PAD_MODE_BYPASS: 2918 gpout0 = 1; 2919 gpout1 = 1; 2920 break; 2921 default: 2922 BUG(); 2923 return; 2924 } 2925 2926 l = dispc_read_reg(DISPC_CONTROL); 2927 l = FLD_MOD(l, gpout0, 15, 15); 2928 l = FLD_MOD(l, gpout1, 16, 16); 2929 dispc_write_reg(DISPC_CONTROL, l); 2930} 2931 2932static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 2933{ 2934 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); 2935} 2936 2937void dispc_mgr_set_lcd_config(enum omap_channel channel, 2938 const struct dss_lcd_mgr_config *config) 2939{ 2940 dispc_mgr_set_io_pad_mode(config->io_pad_mode); 2941 2942 dispc_mgr_enable_stallmode(channel, config->stallmode); 2943 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); 2944 2945 dispc_mgr_set_clock_div(channel, &config->clock_info); 2946 2947 dispc_mgr_set_tft_data_lines(channel, config->video_port_width); 2948 2949 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); 2950 2951 dispc_mgr_set_lcd_type_tft(channel); 2952} 2953EXPORT_SYMBOL(dispc_mgr_set_lcd_config); 2954 2955static bool _dispc_mgr_size_ok(u16 width, u16 height) 2956{ 2957 return width <= dispc.feat->mgr_width_max && 2958 height <= dispc.feat->mgr_height_max; 2959} 2960 2961static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, 2962 int vsw, int vfp, int vbp) 2963{ 2964 if (hsw < 1 || hsw > dispc.feat->sw_max || 2965 hfp < 1 || hfp > dispc.feat->hp_max || 2966 hbp < 1 || hbp > dispc.feat->hp_max || 2967 vsw < 1 || vsw > dispc.feat->sw_max || 2968 vfp < 0 || vfp > dispc.feat->vp_max || 2969 vbp < 0 || vbp > dispc.feat->vp_max) 2970 return false; 2971 return true; 2972} 2973 2974static bool _dispc_mgr_pclk_ok(enum omap_channel channel, 2975 unsigned long pclk) 2976{ 2977 if (dss_mgr_is_lcd(channel)) 2978 return pclk <= dispc.feat->max_lcd_pclk; 2979 else 2980 return pclk <= dispc.feat->max_tv_pclk; 2981} 2982 2983bool dispc_mgr_timings_ok(enum omap_channel channel, 2984 const struct omap_video_timings *timings) 2985{ 2986 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) 2987 return false; 2988 2989 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) 2990 return false; 2991 2992 if (dss_mgr_is_lcd(channel)) { 2993 /* TODO: OMAP4+ supports interlace for LCD outputs */ 2994 if (timings->interlace) 2995 return false; 2996 2997 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, 2998 timings->hbp, timings->vsw, timings->vfp, 2999 timings->vbp)) 3000 return false; 3001 } 3002 3003 return true; 3004} 3005 3006static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, 3007 int hfp, int hbp, int vsw, int vfp, int vbp, 3008 enum omap_dss_signal_level vsync_level, 3009 enum omap_dss_signal_level hsync_level, 3010 enum omap_dss_signal_edge data_pclk_edge, 3011 enum omap_dss_signal_level de_level, 3012 enum omap_dss_signal_edge sync_pclk_edge) 3013 3014{ 3015 u32 timing_h, timing_v, l; 3016 bool onoff, rf, ipc, vs, hs, de; 3017 3018 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | 3019 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | 3020 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); 3021 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | 3022 FLD_VAL(vfp, dispc.feat->fp_start, 8) | 3023 FLD_VAL(vbp, dispc.feat->bp_start, 20); 3024 3025 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 3026 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 3027 3028 switch (vsync_level) { 3029 case OMAPDSS_SIG_ACTIVE_LOW: 3030 vs = true; 3031 break; 3032 case OMAPDSS_SIG_ACTIVE_HIGH: 3033 vs = false; 3034 break; 3035 default: 3036 BUG(); 3037 } 3038 3039 switch (hsync_level) { 3040 case OMAPDSS_SIG_ACTIVE_LOW: 3041 hs = true; 3042 break; 3043 case OMAPDSS_SIG_ACTIVE_HIGH: 3044 hs = false; 3045 break; 3046 default: 3047 BUG(); 3048 } 3049 3050 switch (de_level) { 3051 case OMAPDSS_SIG_ACTIVE_LOW: 3052 de = true; 3053 break; 3054 case OMAPDSS_SIG_ACTIVE_HIGH: 3055 de = false; 3056 break; 3057 default: 3058 BUG(); 3059 } 3060 3061 switch (data_pclk_edge) { 3062 case OMAPDSS_DRIVE_SIG_RISING_EDGE: 3063 ipc = false; 3064 break; 3065 case OMAPDSS_DRIVE_SIG_FALLING_EDGE: 3066 ipc = true; 3067 break; 3068 default: 3069 BUG(); 3070 } 3071 3072 /* always use the 'rf' setting */ 3073 onoff = true; 3074 3075 switch (sync_pclk_edge) { 3076 case OMAPDSS_DRIVE_SIG_FALLING_EDGE: 3077 rf = false; 3078 break; 3079 case OMAPDSS_DRIVE_SIG_RISING_EDGE: 3080 rf = true; 3081 break; 3082 default: 3083 BUG(); 3084 } 3085 3086 l = FLD_VAL(onoff, 17, 17) | 3087 FLD_VAL(rf, 16, 16) | 3088 FLD_VAL(de, 15, 15) | 3089 FLD_VAL(ipc, 14, 14) | 3090 FLD_VAL(hs, 13, 13) | 3091 FLD_VAL(vs, 12, 12); 3092 3093 /* always set ALIGN bit when available */ 3094 if (dispc.feat->supports_sync_align) 3095 l |= (1 << 18); 3096 3097 dispc_write_reg(DISPC_POL_FREQ(channel), l); 3098 3099 if (dispc.syscon_pol) { 3100 const int shifts[] = { 3101 [OMAP_DSS_CHANNEL_LCD] = 0, 3102 [OMAP_DSS_CHANNEL_LCD2] = 1, 3103 [OMAP_DSS_CHANNEL_LCD3] = 2, 3104 }; 3105 3106 u32 mask, val; 3107 3108 mask = (1 << 0) | (1 << 3) | (1 << 6); 3109 val = (rf << 0) | (ipc << 3) | (onoff << 6); 3110 3111 mask <<= 16 + shifts[channel]; 3112 val <<= 16 + shifts[channel]; 3113 3114 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, 3115 mask, val); 3116 } 3117} 3118 3119/* change name to mode? */ 3120void dispc_mgr_set_timings(enum omap_channel channel, 3121 const struct omap_video_timings *timings) 3122{ 3123 unsigned xtot, ytot; 3124 unsigned long ht, vt; 3125 struct omap_video_timings t = *timings; 3126 3127 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res); 3128 3129 if (!dispc_mgr_timings_ok(channel, &t)) { 3130 BUG(); 3131 return; 3132 } 3133 3134 if (dss_mgr_is_lcd(channel)) { 3135 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, 3136 t.vfp, t.vbp, t.vsync_level, t.hsync_level, 3137 t.data_pclk_edge, t.de_level, t.sync_pclk_edge); 3138 3139 xtot = t.x_res + t.hfp + t.hsw + t.hbp; 3140 ytot = t.y_res + t.vfp + t.vsw + t.vbp; 3141 3142 ht = timings->pixelclock / xtot; 3143 vt = timings->pixelclock / xtot / ytot; 3144 3145 DSSDBG("pck %u\n", timings->pixelclock); 3146 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3147 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); 3148 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 3149 t.vsync_level, t.hsync_level, t.data_pclk_edge, 3150 t.de_level, t.sync_pclk_edge); 3151 3152 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); 3153 } else { 3154 if (t.interlace) 3155 t.y_res /= 2; 3156 } 3157 3158 dispc_mgr_set_size(channel, t.x_res, t.y_res); 3159} 3160EXPORT_SYMBOL(dispc_mgr_set_timings); 3161 3162static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, 3163 u16 pck_div) 3164{ 3165 BUG_ON(lck_div < 1); 3166 BUG_ON(pck_div < 1); 3167 3168 dispc_write_reg(DISPC_DIVISORo(channel), 3169 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 3170 3171 if (!dss_has_feature(FEAT_CORE_CLK_DIV) && 3172 channel == OMAP_DSS_CHANNEL_LCD) 3173 dispc.core_clk_rate = dispc_fclk_rate() / lck_div; 3174} 3175 3176static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, 3177 int *pck_div) 3178{ 3179 u32 l; 3180 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3181 *lck_div = FLD_GET(l, 23, 16); 3182 *pck_div = FLD_GET(l, 7, 0); 3183} 3184 3185static unsigned long dispc_fclk_rate(void) 3186{ 3187 struct dss_pll *pll; 3188 unsigned long r = 0; 3189 3190 switch (dss_get_dispc_clk_source()) { 3191 case OMAP_DSS_CLK_SRC_FCK: 3192 r = dss_get_dispc_clk_rate(); 3193 break; 3194 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 3195 pll = dss_pll_find("dsi0"); 3196 if (!pll) 3197 pll = dss_pll_find("video0"); 3198 3199 r = pll->cinfo.clkout[0]; 3200 break; 3201 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 3202 pll = dss_pll_find("dsi1"); 3203 if (!pll) 3204 pll = dss_pll_find("video1"); 3205 3206 r = pll->cinfo.clkout[0]; 3207 break; 3208 default: 3209 BUG(); 3210 return 0; 3211 } 3212 3213 return r; 3214} 3215 3216static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) 3217{ 3218 struct dss_pll *pll; 3219 int lcd; 3220 unsigned long r; 3221 u32 l; 3222 3223 if (dss_mgr_is_lcd(channel)) { 3224 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3225 3226 lcd = FLD_GET(l, 23, 16); 3227 3228 switch (dss_get_lcd_clk_source(channel)) { 3229 case OMAP_DSS_CLK_SRC_FCK: 3230 r = dss_get_dispc_clk_rate(); 3231 break; 3232 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 3233 pll = dss_pll_find("dsi0"); 3234 if (!pll) 3235 pll = dss_pll_find("video0"); 3236 3237 r = pll->cinfo.clkout[0]; 3238 break; 3239 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 3240 pll = dss_pll_find("dsi1"); 3241 if (!pll) 3242 pll = dss_pll_find("video1"); 3243 3244 r = pll->cinfo.clkout[0]; 3245 break; 3246 default: 3247 BUG(); 3248 return 0; 3249 } 3250 3251 return r / lcd; 3252 } else { 3253 return dispc_fclk_rate(); 3254 } 3255} 3256 3257static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) 3258{ 3259 unsigned long r; 3260 3261 if (dss_mgr_is_lcd(channel)) { 3262 int pcd; 3263 u32 l; 3264 3265 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3266 3267 pcd = FLD_GET(l, 7, 0); 3268 3269 r = dispc_mgr_lclk_rate(channel); 3270 3271 return r / pcd; 3272 } else { 3273 return dispc.tv_pclk_rate; 3274 } 3275} 3276 3277void dispc_set_tv_pclk(unsigned long pclk) 3278{ 3279 dispc.tv_pclk_rate = pclk; 3280} 3281 3282static unsigned long dispc_core_clk_rate(void) 3283{ 3284 return dispc.core_clk_rate; 3285} 3286 3287static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) 3288{ 3289 enum omap_channel channel; 3290 3291 if (plane == OMAP_DSS_WB) 3292 return 0; 3293 3294 channel = dispc_ovl_get_channel_out(plane); 3295 3296 return dispc_mgr_pclk_rate(channel); 3297} 3298 3299static unsigned long dispc_plane_lclk_rate(enum omap_plane plane) 3300{ 3301 enum omap_channel channel; 3302 3303 if (plane == OMAP_DSS_WB) 3304 return 0; 3305 3306 channel = dispc_ovl_get_channel_out(plane); 3307 3308 return dispc_mgr_lclk_rate(channel); 3309} 3310 3311static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) 3312{ 3313 int lcd, pcd; 3314 enum omap_dss_clk_source lcd_clk_src; 3315 3316 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3317 3318 lcd_clk_src = dss_get_lcd_clk_source(channel); 3319 3320 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name, 3321 dss_get_generic_clk_source_name(lcd_clk_src), 3322 dss_feat_get_clk_source_name(lcd_clk_src)); 3323 3324 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); 3325 3326 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3327 dispc_mgr_lclk_rate(channel), lcd); 3328 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", 3329 dispc_mgr_pclk_rate(channel), pcd); 3330} 3331 3332void dispc_dump_clocks(struct seq_file *s) 3333{ 3334 int lcd; 3335 u32 l; 3336 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); 3337 3338 if (dispc_runtime_get()) 3339 return; 3340 3341 seq_printf(s, "- DISPC -\n"); 3342 3343 seq_printf(s, "dispc fclk source = %s (%s)\n", 3344 dss_get_generic_clk_source_name(dispc_clk_src), 3345 dss_feat_get_clk_source_name(dispc_clk_src)); 3346 3347 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); 3348 3349 if (dss_has_feature(FEAT_CORE_CLK_DIV)) { 3350 seq_printf(s, "- DISPC-CORE-CLK -\n"); 3351 l = dispc_read_reg(DISPC_DIVISOR); 3352 lcd = FLD_GET(l, 23, 16); 3353 3354 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3355 (dispc_fclk_rate()/lcd), lcd); 3356 } 3357 3358 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); 3359 3360 if (dss_has_feature(FEAT_MGR_LCD2)) 3361 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); 3362 if (dss_has_feature(FEAT_MGR_LCD3)) 3363 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); 3364 3365 dispc_runtime_put(); 3366} 3367 3368static void dispc_dump_regs(struct seq_file *s) 3369{ 3370 int i, j; 3371 const char *mgr_names[] = { 3372 [OMAP_DSS_CHANNEL_LCD] = "LCD", 3373 [OMAP_DSS_CHANNEL_DIGIT] = "TV", 3374 [OMAP_DSS_CHANNEL_LCD2] = "LCD2", 3375 [OMAP_DSS_CHANNEL_LCD3] = "LCD3", 3376 }; 3377 const char *ovl_names[] = { 3378 [OMAP_DSS_GFX] = "GFX", 3379 [OMAP_DSS_VIDEO1] = "VID1", 3380 [OMAP_DSS_VIDEO2] = "VID2", 3381 [OMAP_DSS_VIDEO3] = "VID3", 3382 [OMAP_DSS_WB] = "WB", 3383 }; 3384 const char **p_names; 3385 3386#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) 3387 3388 if (dispc_runtime_get()) 3389 return; 3390 3391 /* DISPC common registers */ 3392 DUMPREG(DISPC_REVISION); 3393 DUMPREG(DISPC_SYSCONFIG); 3394 DUMPREG(DISPC_SYSSTATUS); 3395 DUMPREG(DISPC_IRQSTATUS); 3396 DUMPREG(DISPC_IRQENABLE); 3397 DUMPREG(DISPC_CONTROL); 3398 DUMPREG(DISPC_CONFIG); 3399 DUMPREG(DISPC_CAPABLE); 3400 DUMPREG(DISPC_LINE_STATUS); 3401 DUMPREG(DISPC_LINE_NUMBER); 3402 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 3403 dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) 3404 DUMPREG(DISPC_GLOBAL_ALPHA); 3405 if (dss_has_feature(FEAT_MGR_LCD2)) { 3406 DUMPREG(DISPC_CONTROL2); 3407 DUMPREG(DISPC_CONFIG2); 3408 } 3409 if (dss_has_feature(FEAT_MGR_LCD3)) { 3410 DUMPREG(DISPC_CONTROL3); 3411 DUMPREG(DISPC_CONFIG3); 3412 } 3413 if (dss_has_feature(FEAT_MFLAG)) 3414 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); 3415 3416#undef DUMPREG 3417 3418#define DISPC_REG(i, name) name(i) 3419#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ 3420 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ 3421 dispc_read_reg(DISPC_REG(i, r))) 3422 3423 p_names = mgr_names; 3424 3425 /* DISPC channel specific registers */ 3426 for (i = 0; i < dss_feat_get_num_mgrs(); i++) { 3427 DUMPREG(i, DISPC_DEFAULT_COLOR); 3428 DUMPREG(i, DISPC_TRANS_COLOR); 3429 DUMPREG(i, DISPC_SIZE_MGR); 3430 3431 if (i == OMAP_DSS_CHANNEL_DIGIT) 3432 continue; 3433 3434 DUMPREG(i, DISPC_TIMING_H); 3435 DUMPREG(i, DISPC_TIMING_V); 3436 DUMPREG(i, DISPC_POL_FREQ); 3437 DUMPREG(i, DISPC_DIVISORo); 3438 3439 DUMPREG(i, DISPC_DATA_CYCLE1); 3440 DUMPREG(i, DISPC_DATA_CYCLE2); 3441 DUMPREG(i, DISPC_DATA_CYCLE3); 3442 3443 if (dss_has_feature(FEAT_CPR)) { 3444 DUMPREG(i, DISPC_CPR_COEF_R); 3445 DUMPREG(i, DISPC_CPR_COEF_G); 3446 DUMPREG(i, DISPC_CPR_COEF_B); 3447 } 3448 } 3449 3450 p_names = ovl_names; 3451 3452 for (i = 0; i < dss_feat_get_num_ovls(); i++) { 3453 DUMPREG(i, DISPC_OVL_BA0); 3454 DUMPREG(i, DISPC_OVL_BA1); 3455 DUMPREG(i, DISPC_OVL_POSITION); 3456 DUMPREG(i, DISPC_OVL_SIZE); 3457 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3458 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3459 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3460 DUMPREG(i, DISPC_OVL_ROW_INC); 3461 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3462 3463 if (dss_has_feature(FEAT_PRELOAD)) 3464 DUMPREG(i, DISPC_OVL_PRELOAD); 3465 if (dss_has_feature(FEAT_MFLAG)) 3466 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3467 3468 if (i == OMAP_DSS_GFX) { 3469 DUMPREG(i, DISPC_OVL_WINDOW_SKIP); 3470 DUMPREG(i, DISPC_OVL_TABLE_BA); 3471 continue; 3472 } 3473 3474 DUMPREG(i, DISPC_OVL_FIR); 3475 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3476 DUMPREG(i, DISPC_OVL_ACCU0); 3477 DUMPREG(i, DISPC_OVL_ACCU1); 3478 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3479 DUMPREG(i, DISPC_OVL_BA0_UV); 3480 DUMPREG(i, DISPC_OVL_BA1_UV); 3481 DUMPREG(i, DISPC_OVL_FIR2); 3482 DUMPREG(i, DISPC_OVL_ACCU2_0); 3483 DUMPREG(i, DISPC_OVL_ACCU2_1); 3484 } 3485 if (dss_has_feature(FEAT_ATTR2)) 3486 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3487 } 3488 3489 if (dispc.feat->has_writeback) { 3490 i = OMAP_DSS_WB; 3491 DUMPREG(i, DISPC_OVL_BA0); 3492 DUMPREG(i, DISPC_OVL_BA1); 3493 DUMPREG(i, DISPC_OVL_SIZE); 3494 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3495 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3496 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3497 DUMPREG(i, DISPC_OVL_ROW_INC); 3498 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3499 3500 if (dss_has_feature(FEAT_MFLAG)) 3501 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3502 3503 DUMPREG(i, DISPC_OVL_FIR); 3504 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3505 DUMPREG(i, DISPC_OVL_ACCU0); 3506 DUMPREG(i, DISPC_OVL_ACCU1); 3507 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3508 DUMPREG(i, DISPC_OVL_BA0_UV); 3509 DUMPREG(i, DISPC_OVL_BA1_UV); 3510 DUMPREG(i, DISPC_OVL_FIR2); 3511 DUMPREG(i, DISPC_OVL_ACCU2_0); 3512 DUMPREG(i, DISPC_OVL_ACCU2_1); 3513 } 3514 if (dss_has_feature(FEAT_ATTR2)) 3515 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3516 } 3517 3518#undef DISPC_REG 3519#undef DUMPREG 3520 3521#define DISPC_REG(plane, name, i) name(plane, i) 3522#define DUMPREG(plane, name, i) \ 3523 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ 3524 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ 3525 dispc_read_reg(DISPC_REG(plane, name, i))) 3526 3527 /* Video pipeline coefficient registers */ 3528 3529 /* start from OMAP_DSS_VIDEO1 */ 3530 for (i = 1; i < dss_feat_get_num_ovls(); i++) { 3531 for (j = 0; j < 8; j++) 3532 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); 3533 3534 for (j = 0; j < 8; j++) 3535 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); 3536 3537 for (j = 0; j < 5; j++) 3538 DUMPREG(i, DISPC_OVL_CONV_COEF, j); 3539 3540 if (dss_has_feature(FEAT_FIR_COEF_V)) { 3541 for (j = 0; j < 8; j++) 3542 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); 3543 } 3544 3545 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3546 for (j = 0; j < 8; j++) 3547 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); 3548 3549 for (j = 0; j < 8; j++) 3550 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); 3551 3552 for (j = 0; j < 8; j++) 3553 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); 3554 } 3555 } 3556 3557 dispc_runtime_put(); 3558 3559#undef DISPC_REG 3560#undef DUMPREG 3561} 3562 3563/* calculate clock rates using dividers in cinfo */ 3564int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 3565 struct dispc_clock_info *cinfo) 3566{ 3567 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) 3568 return -EINVAL; 3569 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) 3570 return -EINVAL; 3571 3572 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; 3573 cinfo->pck = cinfo->lck / cinfo->pck_div; 3574 3575 return 0; 3576} 3577 3578bool dispc_div_calc(unsigned long dispc, 3579 unsigned long pck_min, unsigned long pck_max, 3580 dispc_div_calc_func func, void *data) 3581{ 3582 int lckd, lckd_start, lckd_stop; 3583 int pckd, pckd_start, pckd_stop; 3584 unsigned long pck, lck; 3585 unsigned long lck_max; 3586 unsigned long pckd_hw_min, pckd_hw_max; 3587 unsigned min_fck_per_pck; 3588 unsigned long fck; 3589 3590#ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK 3591 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK; 3592#else 3593 min_fck_per_pck = 0; 3594#endif 3595 3596 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); 3597 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); 3598 3599 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); 3600 3601 pck_min = pck_min ? pck_min : 1; 3602 pck_max = pck_max ? pck_max : ULONG_MAX; 3603 3604 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); 3605 lckd_stop = min(dispc / pck_min, 255ul); 3606 3607 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { 3608 lck = dispc / lckd; 3609 3610 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); 3611 pckd_stop = min(lck / pck_min, pckd_hw_max); 3612 3613 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { 3614 pck = lck / pckd; 3615 3616 /* 3617 * For OMAP2/3 the DISPC fclk is the same as LCD's logic 3618 * clock, which means we're configuring DISPC fclk here 3619 * also. Thus we need to use the calculated lck. For 3620 * OMAP4+ the DISPC fclk is a separate clock. 3621 */ 3622 if (dss_has_feature(FEAT_CORE_CLK_DIV)) 3623 fck = dispc_core_clk_rate(); 3624 else 3625 fck = lck; 3626 3627 if (fck < pck * min_fck_per_pck) 3628 continue; 3629 3630 if (func(lckd, pckd, lck, pck, data)) 3631 return true; 3632 } 3633 } 3634 3635 return false; 3636} 3637 3638void dispc_mgr_set_clock_div(enum omap_channel channel, 3639 const struct dispc_clock_info *cinfo) 3640{ 3641 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); 3642 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); 3643 3644 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); 3645} 3646 3647u32 dispc_read_irqstatus(void) 3648{ 3649 return dispc_read_reg(DISPC_IRQSTATUS); 3650} 3651EXPORT_SYMBOL(dispc_read_irqstatus); 3652 3653void dispc_clear_irqstatus(u32 mask) 3654{ 3655 dispc_write_reg(DISPC_IRQSTATUS, mask); 3656} 3657EXPORT_SYMBOL(dispc_clear_irqstatus); 3658 3659u32 dispc_read_irqenable(void) 3660{ 3661 return dispc_read_reg(DISPC_IRQENABLE); 3662} 3663EXPORT_SYMBOL(dispc_read_irqenable); 3664 3665void dispc_write_irqenable(u32 mask) 3666{ 3667 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); 3668 3669 /* clear the irqstatus for newly enabled irqs */ 3670 dispc_clear_irqstatus((mask ^ old_mask) & mask); 3671 3672 dispc_write_reg(DISPC_IRQENABLE, mask); 3673} 3674EXPORT_SYMBOL(dispc_write_irqenable); 3675 3676void dispc_enable_sidle(void) 3677{ 3678 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ 3679} 3680 3681void dispc_disable_sidle(void) 3682{ 3683 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ 3684} 3685 3686static void _omap_dispc_initial_config(void) 3687{ 3688 u32 l; 3689 3690 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ 3691 if (dss_has_feature(FEAT_CORE_CLK_DIV)) { 3692 l = dispc_read_reg(DISPC_DIVISOR); 3693 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ 3694 l = FLD_MOD(l, 1, 0, 0); 3695 l = FLD_MOD(l, 1, 23, 16); 3696 dispc_write_reg(DISPC_DIVISOR, l); 3697 3698 dispc.core_clk_rate = dispc_fclk_rate(); 3699 } 3700 3701 /* FUNCGATED */ 3702 if (dss_has_feature(FEAT_FUNCGATED)) 3703 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); 3704 3705 dispc_setup_color_conv_coef(); 3706 3707 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); 3708 3709 dispc_init_fifos(); 3710 3711 dispc_configure_burst_sizes(); 3712 3713 dispc_ovl_enable_zorder_planes(); 3714 3715 if (dispc.feat->mstandby_workaround) 3716 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); 3717 3718 if (dss_has_feature(FEAT_MFLAG)) 3719 dispc_init_mflag(); 3720} 3721 3722static const struct dispc_features omap24xx_dispc_feats = { 3723 .sw_start = 5, 3724 .fp_start = 15, 3725 .bp_start = 27, 3726 .sw_max = 64, 3727 .vp_max = 255, 3728 .hp_max = 256, 3729 .mgr_width_start = 10, 3730 .mgr_height_start = 26, 3731 .mgr_width_max = 2048, 3732 .mgr_height_max = 2048, 3733 .max_lcd_pclk = 66500000, 3734 .calc_scaling = dispc_ovl_calc_scaling_24xx, 3735 .calc_core_clk = calc_core_clk_24xx, 3736 .num_fifos = 3, 3737 .no_framedone_tv = true, 3738 .set_max_preload = false, 3739 .last_pixel_inc_missing = true, 3740}; 3741 3742static const struct dispc_features omap34xx_rev1_0_dispc_feats = { 3743 .sw_start = 5, 3744 .fp_start = 15, 3745 .bp_start = 27, 3746 .sw_max = 64, 3747 .vp_max = 255, 3748 .hp_max = 256, 3749 .mgr_width_start = 10, 3750 .mgr_height_start = 26, 3751 .mgr_width_max = 2048, 3752 .mgr_height_max = 2048, 3753 .max_lcd_pclk = 173000000, 3754 .max_tv_pclk = 59000000, 3755 .calc_scaling = dispc_ovl_calc_scaling_34xx, 3756 .calc_core_clk = calc_core_clk_34xx, 3757 .num_fifos = 3, 3758 .no_framedone_tv = true, 3759 .set_max_preload = false, 3760 .last_pixel_inc_missing = true, 3761}; 3762 3763static const struct dispc_features omap34xx_rev3_0_dispc_feats = { 3764 .sw_start = 7, 3765 .fp_start = 19, 3766 .bp_start = 31, 3767 .sw_max = 256, 3768 .vp_max = 4095, 3769 .hp_max = 4096, 3770 .mgr_width_start = 10, 3771 .mgr_height_start = 26, 3772 .mgr_width_max = 2048, 3773 .mgr_height_max = 2048, 3774 .max_lcd_pclk = 173000000, 3775 .max_tv_pclk = 59000000, 3776 .calc_scaling = dispc_ovl_calc_scaling_34xx, 3777 .calc_core_clk = calc_core_clk_34xx, 3778 .num_fifos = 3, 3779 .no_framedone_tv = true, 3780 .set_max_preload = false, 3781 .last_pixel_inc_missing = true, 3782}; 3783 3784static const struct dispc_features omap44xx_dispc_feats = { 3785 .sw_start = 7, 3786 .fp_start = 19, 3787 .bp_start = 31, 3788 .sw_max = 256, 3789 .vp_max = 4095, 3790 .hp_max = 4096, 3791 .mgr_width_start = 10, 3792 .mgr_height_start = 26, 3793 .mgr_width_max = 2048, 3794 .mgr_height_max = 2048, 3795 .max_lcd_pclk = 170000000, 3796 .max_tv_pclk = 185625000, 3797 .calc_scaling = dispc_ovl_calc_scaling_44xx, 3798 .calc_core_clk = calc_core_clk_44xx, 3799 .num_fifos = 5, 3800 .gfx_fifo_workaround = true, 3801 .set_max_preload = true, 3802 .supports_sync_align = true, 3803 .has_writeback = true, 3804}; 3805 3806static const struct dispc_features omap54xx_dispc_feats = { 3807 .sw_start = 7, 3808 .fp_start = 19, 3809 .bp_start = 31, 3810 .sw_max = 256, 3811 .vp_max = 4095, 3812 .hp_max = 4096, 3813 .mgr_width_start = 11, 3814 .mgr_height_start = 27, 3815 .mgr_width_max = 4096, 3816 .mgr_height_max = 4096, 3817 .max_lcd_pclk = 170000000, 3818 .max_tv_pclk = 186000000, 3819 .calc_scaling = dispc_ovl_calc_scaling_44xx, 3820 .calc_core_clk = calc_core_clk_44xx, 3821 .num_fifos = 5, 3822 .gfx_fifo_workaround = true, 3823 .mstandby_workaround = true, 3824 .set_max_preload = true, 3825 .supports_sync_align = true, 3826 .has_writeback = true, 3827}; 3828 3829static const struct dispc_features *dispc_get_features(void) 3830{ 3831 switch (omapdss_get_version()) { 3832 case OMAPDSS_VER_OMAP24xx: 3833 return &omap24xx_dispc_feats; 3834 3835 case OMAPDSS_VER_OMAP34xx_ES1: 3836 return &omap34xx_rev1_0_dispc_feats; 3837 3838 case OMAPDSS_VER_OMAP34xx_ES3: 3839 case OMAPDSS_VER_OMAP3630: 3840 case OMAPDSS_VER_AM35xx: 3841 case OMAPDSS_VER_AM43xx: 3842 return &omap34xx_rev3_0_dispc_feats; 3843 3844 case OMAPDSS_VER_OMAP4430_ES1: 3845 case OMAPDSS_VER_OMAP4430_ES2: 3846 case OMAPDSS_VER_OMAP4: 3847 return &omap44xx_dispc_feats; 3848 3849 case OMAPDSS_VER_OMAP5: 3850 case OMAPDSS_VER_DRA7xx: 3851 return &omap54xx_dispc_feats; 3852 3853 default: 3854 return NULL; 3855 } 3856} 3857 3858static irqreturn_t dispc_irq_handler(int irq, void *arg) 3859{ 3860 if (!dispc.is_enabled) 3861 return IRQ_NONE; 3862 3863 return dispc.user_handler(irq, dispc.user_data); 3864} 3865 3866int dispc_request_irq(irq_handler_t handler, void *dev_id) 3867{ 3868 int r; 3869 3870 if (dispc.user_handler != NULL) 3871 return -EBUSY; 3872 3873 dispc.user_handler = handler; 3874 dispc.user_data = dev_id; 3875 3876 /* ensure the dispc_irq_handler sees the values above */ 3877 smp_wmb(); 3878 3879 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, 3880 IRQF_SHARED, "OMAP DISPC", &dispc); 3881 if (r) { 3882 dispc.user_handler = NULL; 3883 dispc.user_data = NULL; 3884 } 3885 3886 return r; 3887} 3888EXPORT_SYMBOL(dispc_request_irq); 3889 3890void dispc_free_irq(void *dev_id) 3891{ 3892 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); 3893 3894 dispc.user_handler = NULL; 3895 dispc.user_data = NULL; 3896} 3897EXPORT_SYMBOL(dispc_free_irq); 3898 3899/* DISPC HW IP initialisation */ 3900static int dispc_bind(struct device *dev, struct device *master, void *data) 3901{ 3902 struct platform_device *pdev = to_platform_device(dev); 3903 u32 rev; 3904 int r = 0; 3905 struct resource *dispc_mem; 3906 struct device_node *np = pdev->dev.of_node; 3907 3908 dispc.pdev = pdev; 3909 3910 spin_lock_init(&dispc.control_lock); 3911 3912 dispc.feat = dispc_get_features(); 3913 if (!dispc.feat) 3914 return -ENODEV; 3915 3916 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); 3917 if (!dispc_mem) { 3918 DSSERR("can't get IORESOURCE_MEM DISPC\n"); 3919 return -EINVAL; 3920 } 3921 3922 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, 3923 resource_size(dispc_mem)); 3924 if (!dispc.base) { 3925 DSSERR("can't ioremap DISPC\n"); 3926 return -ENOMEM; 3927 } 3928 3929 dispc.irq = platform_get_irq(dispc.pdev, 0); 3930 if (dispc.irq < 0) { 3931 DSSERR("platform_get_irq failed\n"); 3932 return -ENODEV; 3933 } 3934 3935 if (np && of_property_present(np, "syscon-pol")) { 3936 dispc.syscon_pol = syscon_regmap_lookup_by_phandle_args(np, "syscon-pol", 3937 1, &dispc.syscon_pol_offset); 3938 if (IS_ERR(dispc.syscon_pol)) { 3939 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); 3940 return PTR_ERR(dispc.syscon_pol); 3941 } 3942 } 3943 3944 pm_runtime_enable(&pdev->dev); 3945 3946 r = dispc_runtime_get(); 3947 if (r) 3948 goto err_runtime_get; 3949 3950 _omap_dispc_initial_config(); 3951 3952 rev = dispc_read_reg(DISPC_REVISION); 3953 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", 3954 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 3955 3956 dispc_runtime_put(); 3957 3958 dss_init_overlay_managers(); 3959 3960 dss_debugfs_create_file("dispc", dispc_dump_regs); 3961 3962 return 0; 3963 3964err_runtime_get: 3965 pm_runtime_disable(&pdev->dev); 3966 return r; 3967} 3968 3969static void dispc_unbind(struct device *dev, struct device *master, 3970 void *data) 3971{ 3972 pm_runtime_disable(dev); 3973 3974 dss_uninit_overlay_managers(); 3975} 3976 3977static const struct component_ops dispc_component_ops = { 3978 .bind = dispc_bind, 3979 .unbind = dispc_unbind, 3980}; 3981 3982static int dispc_probe(struct platform_device *pdev) 3983{ 3984 return component_add(&pdev->dev, &dispc_component_ops); 3985} 3986 3987static void dispc_remove(struct platform_device *pdev) 3988{ 3989 component_del(&pdev->dev, &dispc_component_ops); 3990} 3991 3992static int dispc_runtime_suspend(struct device *dev) 3993{ 3994 dispc.is_enabled = false; 3995 /* ensure the dispc_irq_handler sees the is_enabled value */ 3996 smp_wmb(); 3997 /* wait for current handler to finish before turning the DISPC off */ 3998 synchronize_irq(dispc.irq); 3999 4000 dispc_save_context(); 4001 4002 return 0; 4003} 4004 4005static int dispc_runtime_resume(struct device *dev) 4006{ 4007 /* 4008 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) 4009 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in 4010 * _omap_dispc_initial_config(). We can thus use it to detect if 4011 * we have lost register context. 4012 */ 4013 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { 4014 _omap_dispc_initial_config(); 4015 4016 dispc_restore_context(); 4017 } 4018 4019 dispc.is_enabled = true; 4020 /* ensure the dispc_irq_handler sees the is_enabled value */ 4021 smp_wmb(); 4022 4023 return 0; 4024} 4025 4026static const struct dev_pm_ops dispc_pm_ops = { 4027 .runtime_suspend = dispc_runtime_suspend, 4028 .runtime_resume = dispc_runtime_resume, 4029}; 4030 4031static const struct of_device_id dispc_of_match[] = { 4032 { .compatible = "ti,omap2-dispc", }, 4033 { .compatible = "ti,omap3-dispc", }, 4034 { .compatible = "ti,omap4-dispc", }, 4035 { .compatible = "ti,omap5-dispc", }, 4036 { .compatible = "ti,dra7-dispc", }, 4037 {}, 4038}; 4039 4040static struct platform_driver omap_dispchw_driver = { 4041 .probe = dispc_probe, 4042 .remove = dispc_remove, 4043 .driver = { 4044 .name = "omapdss_dispc", 4045 .pm = &dispc_pm_ops, 4046 .of_match_table = dispc_of_match, 4047 .suppress_bind_attrs = true, 4048 }, 4049}; 4050 4051int __init dispc_init_platform_driver(void) 4052{ 4053 return platform_driver_register(&omap_dispchw_driver); 4054} 4055 4056void dispc_uninit_platform_driver(void) 4057{ 4058 platform_driver_unregister(&omap_dispchw_driver); 4059}
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