nvidia.c

   1/*
   2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
   3 *
   4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
   5 *
   6 * This file is subject to the terms and conditions of the GNU General Public
   7 * License.  See the file COPYING in the main directory of this archive
   8 * for more details.
   9 *
  10 */
  11
  12#include <linux/aperture.h>
  13#include <linux/module.h>
  14#include <linux/kernel.h>
  15#include <linux/errno.h>
  16#include <linux/string.h>
  17#include <linux/mm.h>
  18#include <linux/slab.h>
  19#include <linux/delay.h>
  20#include <linux/fb.h>
  21#include <linux/init.h>
  22#include <linux/pci.h>
  23#include <linux/console.h>
  24#include <linux/backlight.h>
  25#include <linux/string_choices.h>
  26#ifdef CONFIG_BOOTX_TEXT
  27#include <asm/btext.h>
  28#endif
  29
  30#include "nv_local.h"
  31#include "nv_type.h"
  32#include "nv_proto.h"
  33#include "nv_dma.h"
  34
  35#ifdef CONFIG_FB_NVIDIA_DEBUG
  36#define NVTRACE          printk
  37#else
  38#define NVTRACE          if (0) printk
  39#endif
  40
  41#define NVTRACE_ENTER(...)  NVTRACE("%s START\n", __func__)
  42#define NVTRACE_LEAVE(...)  NVTRACE("%s END\n", __func__)
  43
  44#ifdef CONFIG_FB_NVIDIA_DEBUG
  45#define assert(expr) \
  46	if (!(expr)) { \
  47	printk( "Assertion failed! %s,%s,%s,line=%d\n",\
  48	#expr,__FILE__,__func__,__LINE__); \
  49	BUG(); \
  50	}
  51#else
  52#define assert(expr)
  53#endif
  54
  55#define PFX "nvidiafb: "
  56
  57/* HW cursor parameters */
  58#define MAX_CURS		32
  59
  60static const struct pci_device_id nvidiafb_pci_tbl[] = {
  61	{PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  62	 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
  63	{ 0, }
  64};
  65MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
  66
  67/* command line data, set in nvidiafb_setup() */
  68static int flatpanel = -1;	/* Autodetect later */
  69static int fpdither = -1;
  70static int forceCRTC = -1;
  71static int hwcur = 0;
  72static int noaccel = 0;
  73static int noscale = 0;
  74static int paneltweak = 0;
  75static int vram = 0;
  76static int bpp = 8;
  77static int reverse_i2c;
  78static bool nomtrr = false;
  79static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
  80
  81static char *mode_option = NULL;
  82
  83static struct fb_fix_screeninfo nvidiafb_fix = {
  84	.type = FB_TYPE_PACKED_PIXELS,
  85	.xpanstep = 8,
  86	.ypanstep = 1,
  87};
  88
  89static struct fb_var_screeninfo nvidiafb_default_var = {
  90	.xres = 640,
  91	.yres = 480,
  92	.xres_virtual = 640,
  93	.yres_virtual = 480,
  94	.bits_per_pixel = 8,
  95	.red = {0, 8, 0},
  96	.green = {0, 8, 0},
  97	.blue = {0, 8, 0},
  98	.transp = {0, 0, 0},
  99	.activate = FB_ACTIVATE_NOW,
 100	.height = -1,
 101	.width = -1,
 102	.pixclock = 39721,
 103	.left_margin = 40,
 104	.right_margin = 24,
 105	.upper_margin = 32,
 106	.lower_margin = 11,
 107	.hsync_len = 96,
 108	.vsync_len = 2,
 109	.vmode = FB_VMODE_NONINTERLACED
 110};
 111
 112static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
 113				       u16 bg, u16 fg, u32 w, u32 h)
 114{
 115	u32 *data = (u32 *) data8;
 116	int i, j, k = 0;
 117	u32 b, tmp;
 118
 119	w = (w + 1) & ~1;
 120
 121	for (i = 0; i < h; i++) {
 122		b = *data++;
 123		reverse_order(&b);
 124
 125		for (j = 0; j < w / 2; j++) {
 126			tmp = 0;
 127#if defined (__BIG_ENDIAN)
 128			tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
 129			b <<= 1;
 130			tmp |= (b & (1 << 31)) ? fg : bg;
 131			b <<= 1;
 132#else
 133			tmp = (b & 1) ? fg : bg;
 134			b >>= 1;
 135			tmp |= (b & 1) ? fg << 16 : bg << 16;
 136			b >>= 1;
 137#endif
 138			NV_WR32(&par->CURSOR[k++], 0, tmp);
 139		}
 140		k += (MAX_CURS - w) / 2;
 141	}
 142}
 143
 144static void nvidia_write_clut(struct nvidia_par *par,
 145			      u8 regnum, u8 red, u8 green, u8 blue)
 146{
 147	NVWriteDacMask(par, 0xff);
 148	NVWriteDacWriteAddr(par, regnum);
 149	NVWriteDacData(par, red);
 150	NVWriteDacData(par, green);
 151	NVWriteDacData(par, blue);
 152}
 153
 154static void nvidia_read_clut(struct nvidia_par *par,
 155			     u8 regnum, u8 * red, u8 * green, u8 * blue)
 156{
 157	NVWriteDacMask(par, 0xff);
 158	NVWriteDacReadAddr(par, regnum);
 159	*red = NVReadDacData(par);
 160	*green = NVReadDacData(par);
 161	*blue = NVReadDacData(par);
 162}
 163
 164static int nvidia_panel_tweak(struct nvidia_par *par,
 165			      struct _riva_hw_state *state)
 166{
 167	int tweak = 0;
 168
 169	if (par->paneltweak) {
 170		tweak = par->paneltweak;
 171	} else {
 172		/* Begin flat panel hacks.
 173		 * This is unfortunate, but some chips need this register
 174		 * tweaked or else you get artifacts where adjacent pixels are
 175		 * swapped.  There are no hard rules for what to set here so all
 176		 * we can do is experiment and apply hacks.
 177		 */
 178		if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
 179			/* At least one NV34 laptop needs this workaround. */
 180			tweak = -1;
 181		}
 182
 183		if ((par->Chipset & 0xfff0) == 0x0310)
 184			tweak = 1;
 185		/* end flat panel hacks */
 186	}
 187
 188	return tweak;
 189}
 190
 191static void nvidia_screen_off(struct nvidia_par *par, int on)
 192{
 193	unsigned char tmp;
 194
 195	if (on) {
 196		/*
 197		 * Turn off screen and disable sequencer.
 198		 */
 199		tmp = NVReadSeq(par, 0x01);
 200
 201		NVWriteSeq(par, 0x00, 0x01);		/* Synchronous Reset */
 202		NVWriteSeq(par, 0x01, tmp | 0x20);	/* disable the display */
 203	} else {
 204		/*
 205		 * Reenable sequencer, then turn on screen.
 206		 */
 207
 208		tmp = NVReadSeq(par, 0x01);
 209
 210		NVWriteSeq(par, 0x01, tmp & ~0x20);	/* reenable display */
 211		NVWriteSeq(par, 0x00, 0x03);		/* End Reset */
 212	}
 213}
 214
 215static void nvidia_save_vga(struct nvidia_par *par,
 216			    struct _riva_hw_state *state)
 217{
 218	int i;
 219
 220	NVTRACE_ENTER();
 221	NVLockUnlock(par, 0);
 222
 223	NVUnloadStateExt(par, state);
 224
 225	state->misc_output = NVReadMiscOut(par);
 226
 227	for (i = 0; i < NUM_CRT_REGS; i++)
 228		state->crtc[i] = NVReadCrtc(par, i);
 229
 230	for (i = 0; i < NUM_ATC_REGS; i++)
 231		state->attr[i] = NVReadAttr(par, i);
 232
 233	for (i = 0; i < NUM_GRC_REGS; i++)
 234		state->gra[i] = NVReadGr(par, i);
 235
 236	for (i = 0; i < NUM_SEQ_REGS; i++)
 237		state->seq[i] = NVReadSeq(par, i);
 238	NVTRACE_LEAVE();
 239}
 240
 241#undef DUMP_REG
 242
 243static void nvidia_write_regs(struct nvidia_par *par,
 244			      struct _riva_hw_state *state)
 245{
 246	int i;
 247
 248	NVTRACE_ENTER();
 249
 250	NVLoadStateExt(par, state);
 251
 252	NVWriteMiscOut(par, state->misc_output);
 253
 254	for (i = 1; i < NUM_SEQ_REGS; i++) {
 255#ifdef DUMP_REG
 256		printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
 257#endif
 258		NVWriteSeq(par, i, state->seq[i]);
 259	}
 260
 261	/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
 262	NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
 263
 264	for (i = 0; i < NUM_CRT_REGS; i++) {
 265		switch (i) {
 266		case 0x19:
 267		case 0x20 ... 0x40:
 268			break;
 269		default:
 270#ifdef DUMP_REG
 271			printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
 272#endif
 273			NVWriteCrtc(par, i, state->crtc[i]);
 274		}
 275	}
 276
 277	for (i = 0; i < NUM_GRC_REGS; i++) {
 278#ifdef DUMP_REG
 279		printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
 280#endif
 281		NVWriteGr(par, i, state->gra[i]);
 282	}
 283
 284	for (i = 0; i < NUM_ATC_REGS; i++) {
 285#ifdef DUMP_REG
 286		printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
 287#endif
 288		NVWriteAttr(par, i, state->attr[i]);
 289	}
 290
 291	NVTRACE_LEAVE();
 292}
 293
 294static int nvidia_calc_regs(struct fb_info *info)
 295{
 296	struct nvidia_par *par = info->par;
 297	struct _riva_hw_state *state = &par->ModeReg;
 298	int i, depth = fb_get_color_depth(&info->var, &info->fix);
 299	int h_display = info->var.xres / 8 - 1;
 300	int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
 301	int h_end = (info->var.xres + info->var.right_margin +
 302		     info->var.hsync_len) / 8 - 1;
 303	int h_total = (info->var.xres + info->var.right_margin +
 304		       info->var.hsync_len + info->var.left_margin) / 8 - 5;
 305	int h_blank_s = h_display;
 306	int h_blank_e = h_total + 4;
 307	int v_display = info->var.yres - 1;
 308	int v_start = info->var.yres + info->var.lower_margin - 1;
 309	int v_end = (info->var.yres + info->var.lower_margin +
 310		     info->var.vsync_len) - 1;
 311	int v_total = (info->var.yres + info->var.lower_margin +
 312		       info->var.vsync_len + info->var.upper_margin) - 2;
 313	int v_blank_s = v_display;
 314	int v_blank_e = v_total + 1;
 315
 316	/*
 317	 * Set all CRTC values.
 318	 */
 319
 320	if (info->var.vmode & FB_VMODE_INTERLACED)
 321		v_total |= 1;
 322
 323	if (par->FlatPanel == 1) {
 324		v_start = v_total - 3;
 325		v_end = v_total - 2;
 326		v_blank_s = v_start;
 327		h_start = h_total - 5;
 328		h_end = h_total - 2;
 329		h_blank_e = h_total + 4;
 330	}
 331
 332	state->crtc[0x0] = Set8Bits(h_total);
 333	state->crtc[0x1] = Set8Bits(h_display);
 334	state->crtc[0x2] = Set8Bits(h_blank_s);
 335	state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
 336		| SetBit(7);
 337	state->crtc[0x4] = Set8Bits(h_start);
 338	state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
 339		| SetBitField(h_end, 4: 0, 4:0);
 340	state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
 341	state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
 342		| SetBitField(v_display, 8: 8, 1:1)
 343		| SetBitField(v_start, 8: 8, 2:2)
 344		| SetBitField(v_blank_s, 8: 8, 3:3)
 345		| SetBit(4)
 346		| SetBitField(v_total, 9: 9, 5:5)
 347		| SetBitField(v_display, 9: 9, 6:6)
 348		| SetBitField(v_start, 9: 9, 7:7);
 349	state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
 350		| SetBit(6)
 351		| ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
 352	state->crtc[0x10] = Set8Bits(v_start);
 353	state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
 354	state->crtc[0x12] = Set8Bits(v_display);
 355	state->crtc[0x13] = ((info->var.xres_virtual / 8) *
 356			     (info->var.bits_per_pixel / 8));
 357	state->crtc[0x15] = Set8Bits(v_blank_s);
 358	state->crtc[0x16] = Set8Bits(v_blank_e);
 359
 360	state->attr[0x10] = 0x01;
 361
 362	if (par->Television)
 363		state->attr[0x11] = 0x00;
 364
 365	state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
 366		| SetBitField(v_blank_s, 10: 10, 3:3)
 367		| SetBitField(v_start, 10: 10, 2:2)
 368		| SetBitField(v_display, 10: 10, 1:1)
 369		| SetBitField(v_total, 10: 10, 0:0);
 370
 371	state->horiz = SetBitField(h_total, 8: 8, 0:0)
 372		| SetBitField(h_display, 8: 8, 1:1)
 373		| SetBitField(h_blank_s, 8: 8, 2:2)
 374		| SetBitField(h_start, 8: 8, 3:3);
 375
 376	state->extra = SetBitField(v_total, 11: 11, 0:0)
 377		| SetBitField(v_display, 11: 11, 2:2)
 378		| SetBitField(v_start, 11: 11, 4:4)
 379		| SetBitField(v_blank_s, 11: 11, 6:6);
 380
 381	if (info->var.vmode & FB_VMODE_INTERLACED) {
 382		h_total = (h_total >> 1) & ~1;
 383		state->interlace = Set8Bits(h_total);
 384		state->horiz |= SetBitField(h_total, 8: 8, 4:4);
 385	} else {
 386		state->interlace = 0xff;	/* interlace off */
 387	}
 388
 389	/*
 390	 * Calculate the extended registers.
 391	 */
 392
 393	if (depth < 24)
 394		i = depth;
 395	else
 396		i = 32;
 397
 398	if (par->Architecture >= NV_ARCH_10)
 399		par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
 400						       par->CursorStart);
 401
 402	if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 403		state->misc_output &= ~0x40;
 404	else
 405		state->misc_output |= 0x40;
 406	if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 407		state->misc_output &= ~0x80;
 408	else
 409		state->misc_output |= 0x80;
 410
 411	NVCalcStateExt(par, state, i, info->var.xres_virtual,
 412		       info->var.xres, info->var.yres_virtual,
 413		       1000000000 / info->var.pixclock, info->var.vmode);
 414
 415	state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
 416	if (par->FlatPanel == 1) {
 417		state->pixel |= (1 << 7);
 418
 419		if (!par->fpScaler || (par->fpWidth <= info->var.xres)
 420		    || (par->fpHeight <= info->var.yres)) {
 421			state->scale |= (1 << 8);
 422		}
 423
 424		if (!par->crtcSync_read) {
 425			state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
 426			par->crtcSync_read = 1;
 427		}
 428
 429		par->PanelTweak = nvidia_panel_tweak(par, state);
 430	}
 431
 432	state->vpll = state->pll;
 433	state->vpll2 = state->pll;
 434	state->vpllB = state->pllB;
 435	state->vpll2B = state->pllB;
 436
 437	VGA_WR08(par->PCIO, 0x03D4, 0x1C);
 438	state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
 439
 440	if (par->CRTCnumber) {
 441		state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
 442		state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
 443		state->crtcOwner = 3;
 444		state->pllsel |= 0x20000800;
 445		state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
 446		if (par->twoStagePLL)
 447			state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
 448	} else if (par->twoHeads) {
 449		state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
 450		state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
 451		state->crtcOwner = 0;
 452		state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
 453		if (par->twoStagePLL)
 454			state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
 455	}
 456
 457	state->cursorConfig = 0x00000100;
 458
 459	if (info->var.vmode & FB_VMODE_DOUBLE)
 460		state->cursorConfig |= (1 << 4);
 461
 462	if (par->alphaCursor) {
 463		if ((par->Chipset & 0x0ff0) != 0x0110)
 464			state->cursorConfig |= 0x04011000;
 465		else
 466			state->cursorConfig |= 0x14011000;
 467		state->general |= (1 << 29);
 468	} else
 469		state->cursorConfig |= 0x02000000;
 470
 471	if (par->twoHeads) {
 472		if ((par->Chipset & 0x0ff0) == 0x0110) {
 473			state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
 474			    ~0x00010000;
 475			if (par->FPDither)
 476				state->dither |= 0x00010000;
 477		} else {
 478			state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
 479			if (par->FPDither)
 480				state->dither |= 1;
 481		}
 482	}
 483
 484	state->timingH = 0;
 485	state->timingV = 0;
 486	state->displayV = info->var.xres;
 487
 488	return 0;
 489}
 490
 491static void nvidia_init_vga(struct fb_info *info)
 492{
 493	struct nvidia_par *par = info->par;
 494	struct _riva_hw_state *state = &par->ModeReg;
 495	int i;
 496
 497	for (i = 0; i < 0x10; i++)
 498		state->attr[i] = i;
 499	state->attr[0x10] = 0x41;
 500	state->attr[0x11] = 0xff;
 501	state->attr[0x12] = 0x0f;
 502	state->attr[0x13] = 0x00;
 503	state->attr[0x14] = 0x00;
 504
 505	memset(state->crtc, 0x00, NUM_CRT_REGS);
 506	state->crtc[0x0a] = 0x20;
 507	state->crtc[0x17] = 0xe3;
 508	state->crtc[0x18] = 0xff;
 509	state->crtc[0x28] = 0x40;
 510
 511	memset(state->gra, 0x00, NUM_GRC_REGS);
 512	state->gra[0x05] = 0x40;
 513	state->gra[0x06] = 0x05;
 514	state->gra[0x07] = 0x0f;
 515	state->gra[0x08] = 0xff;
 516
 517	state->seq[0x00] = 0x03;
 518	state->seq[0x01] = 0x01;
 519	state->seq[0x02] = 0x0f;
 520	state->seq[0x03] = 0x00;
 521	state->seq[0x04] = 0x0e;
 522
 523	state->misc_output = 0xeb;
 524}
 525
 526static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 527{
 528	struct nvidia_par *par = info->par;
 529	u8 data[MAX_CURS * MAX_CURS / 8];
 530	int i, set = cursor->set;
 531	u16 fg, bg;
 532
 533	if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
 534		return -ENXIO;
 535
 536	NVShowHideCursor(par, 0);
 537
 538	if (par->cursor_reset) {
 539		set = FB_CUR_SETALL;
 540		par->cursor_reset = 0;
 541	}
 542
 543	if (set & FB_CUR_SETSIZE)
 544		memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
 545
 546	if (set & FB_CUR_SETPOS) {
 547		u32 xx, yy, temp;
 548
 549		yy = cursor->image.dy - info->var.yoffset;
 550		xx = cursor->image.dx - info->var.xoffset;
 551		temp = xx & 0xFFFF;
 552		temp |= yy << 16;
 553
 554		NV_WR32(par->PRAMDAC, 0x0000300, temp);
 555	}
 556
 557	if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
 558		u32 bg_idx = cursor->image.bg_color;
 559		u32 fg_idx = cursor->image.fg_color;
 560		u32 s_pitch = (cursor->image.width + 7) >> 3;
 561		u32 d_pitch = MAX_CURS / 8;
 562		u8 *dat = (u8 *) cursor->image.data;
 563		u8 *msk = (u8 *) cursor->mask;
 564		u8 *src;
 565
 566		src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
 567
 568		if (src) {
 569			switch (cursor->rop) {
 570			case ROP_XOR:
 571				for (i = 0; i < s_pitch * cursor->image.height; i++)
 572					src[i] = dat[i] ^ msk[i];
 573				break;
 574			case ROP_COPY:
 575			default:
 576				for (i = 0; i < s_pitch * cursor->image.height; i++)
 577					src[i] = dat[i] & msk[i];
 578				break;
 579			}
 580
 581			fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
 582						cursor->image.height);
 583
 584			bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
 585			    ((info->cmap.green[bg_idx] & 0xf8) << 2) |
 586			    ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
 587
 588			fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
 589			    ((info->cmap.green[fg_idx] & 0xf8) << 2) |
 590			    ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
 591
 592			NVLockUnlock(par, 0);
 593
 594			nvidiafb_load_cursor_image(par, data, bg, fg,
 595						   cursor->image.width,
 596						   cursor->image.height);
 597			kfree(src);
 598		}
 599	}
 600
 601	if (cursor->enable)
 602		NVShowHideCursor(par, 1);
 603
 604	return 0;
 605}
 606
 607static struct fb_ops nvidia_fb_ops;
 608
 609static int nvidiafb_set_par(struct fb_info *info)
 610{
 611	struct nvidia_par *par = info->par;
 612
 613	NVTRACE_ENTER();
 614
 615	NVLockUnlock(par, 1);
 616	if (!par->FlatPanel || !par->twoHeads)
 617		par->FPDither = 0;
 618
 619	if (par->FPDither < 0) {
 620		if ((par->Chipset & 0x0ff0) == 0x0110)
 621			par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
 622					   & 0x00010000);
 623		else
 624			par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
 625		printk(KERN_INFO PFX "Flat panel dithering %s\n",
 626		       str_enabled_disabled(par->FPDither));
 627	}
 628
 629	info->fix.visual = (info->var.bits_per_pixel == 8) ?
 630	    FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
 631
 632	nvidia_init_vga(info);
 633	nvidia_calc_regs(info);
 634
 635	NVLockUnlock(par, 0);
 636	if (par->twoHeads) {
 637		VGA_WR08(par->PCIO, 0x03D4, 0x44);
 638		VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
 639		NVLockUnlock(par, 0);
 640	}
 641
 642	nvidia_screen_off(par, 1);
 643
 644	nvidia_write_regs(par, &par->ModeReg);
 645	NVSetStartAddress(par, 0);
 646
 647#if defined (__BIG_ENDIAN)
 648	/* turn on LFB swapping */
 649	{
 650		unsigned char tmp;
 651
 652		VGA_WR08(par->PCIO, 0x3d4, 0x46);
 653		tmp = VGA_RD08(par->PCIO, 0x3d5);
 654		tmp |= (1 << 7);
 655		VGA_WR08(par->PCIO, 0x3d5, tmp);
 656    }
 657#endif
 658
 659	info->fix.line_length = (info->var.xres_virtual *
 660				 info->var.bits_per_pixel) >> 3;
 661	if (info->var.accel_flags) {
 662		nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit;
 663		nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect;
 664		nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea;
 665		nvidia_fb_ops.fb_sync = nvidiafb_sync;
 666		info->pixmap.scan_align = 4;
 667		info->flags &= ~FBINFO_HWACCEL_DISABLED;
 668		info->flags |= FBINFO_READS_FAST;
 669		NVResetGraphics(info);
 670	} else {
 671		nvidia_fb_ops.fb_imageblit = cfb_imageblit;
 672		nvidia_fb_ops.fb_fillrect = cfb_fillrect;
 673		nvidia_fb_ops.fb_copyarea = cfb_copyarea;
 674		nvidia_fb_ops.fb_sync = NULL;
 675		info->pixmap.scan_align = 1;
 676		info->flags |= FBINFO_HWACCEL_DISABLED;
 677		info->flags &= ~FBINFO_READS_FAST;
 678	}
 679
 680	par->cursor_reset = 1;
 681
 682	nvidia_screen_off(par, 0);
 683
 684#ifdef CONFIG_BOOTX_TEXT
 685	/* Update debug text engine */
 686	btext_update_display(info->fix.smem_start,
 687			     info->var.xres, info->var.yres,
 688			     info->var.bits_per_pixel, info->fix.line_length);
 689#endif
 690
 691	NVLockUnlock(par, 0);
 692	NVTRACE_LEAVE();
 693	return 0;
 694}
 695
 696static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
 697			      unsigned blue, unsigned transp,
 698			      struct fb_info *info)
 699{
 700	struct nvidia_par *par = info->par;
 701	int i;
 702
 703	NVTRACE_ENTER();
 704	if (regno >= (1 << info->var.green.length))
 705		return -EINVAL;
 706
 707	if (info->var.grayscale) {
 708		/* gray = 0.30*R + 0.59*G + 0.11*B */
 709		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 710	}
 711
 712	if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 713		((u32 *) info->pseudo_palette)[regno] =
 714		    (regno << info->var.red.offset) |
 715		    (regno << info->var.green.offset) |
 716		    (regno << info->var.blue.offset);
 717	}
 718
 719	switch (info->var.bits_per_pixel) {
 720	case 8:
 721		/* "transparent" stuff is completely ignored. */
 722		nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
 723		break;
 724	case 16:
 725		if (info->var.green.length == 5) {
 726			for (i = 0; i < 8; i++) {
 727				nvidia_write_clut(par, regno * 8 + i, red >> 8,
 728						  green >> 8, blue >> 8);
 729			}
 730		} else {
 731			u8 r, g, b;
 732
 733			if (regno < 32) {
 734				for (i = 0; i < 8; i++) {
 735					nvidia_write_clut(par, regno * 8 + i,
 736							  red >> 8, green >> 8,
 737							  blue >> 8);
 738				}
 739			}
 740
 741			nvidia_read_clut(par, regno * 4, &r, &g, &b);
 742
 743			for (i = 0; i < 4; i++)
 744				nvidia_write_clut(par, regno * 4 + i, r,
 745						  green >> 8, b);
 746		}
 747		break;
 748	case 32:
 749		nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
 750		break;
 751	default:
 752		/* do nothing */
 753		break;
 754	}
 755
 756	NVTRACE_LEAVE();
 757	return 0;
 758}
 759
 760static int nvidiafb_check_var(struct fb_var_screeninfo *var,
 761			      struct fb_info *info)
 762{
 763	struct nvidia_par *par = info->par;
 764	int memlen, vramlen, mode_valid = 0;
 765	int pitch, err = 0;
 766
 767	NVTRACE_ENTER();
 768	if (!var->pixclock)
 769		return -EINVAL;
 770
 771	var->transp.offset = 0;
 772	var->transp.length = 0;
 773
 774	var->xres &= ~7;
 775
 776	if (var->bits_per_pixel <= 8)
 777		var->bits_per_pixel = 8;
 778	else if (var->bits_per_pixel <= 16)
 779		var->bits_per_pixel = 16;
 780	else
 781		var->bits_per_pixel = 32;
 782
 783	switch (var->bits_per_pixel) {
 784	case 8:
 785		var->red.offset = 0;
 786		var->red.length = 8;
 787		var->green.offset = 0;
 788		var->green.length = 8;
 789		var->blue.offset = 0;
 790		var->blue.length = 8;
 791		var->transp.offset = 0;
 792		var->transp.length = 0;
 793		break;
 794	case 16:
 795		var->green.length = (var->green.length < 6) ? 5 : 6;
 796		var->red.length = 5;
 797		var->blue.length = 5;
 798		var->transp.length = 6 - var->green.length;
 799		var->blue.offset = 0;
 800		var->green.offset = 5;
 801		var->red.offset = 5 + var->green.length;
 802		var->transp.offset = (5 + var->red.offset) & 15;
 803		break;
 804	case 32:		/* RGBA 8888 */
 805		var->red.offset = 16;
 806		var->red.length = 8;
 807		var->green.offset = 8;
 808		var->green.length = 8;
 809		var->blue.offset = 0;
 810		var->blue.length = 8;
 811		var->transp.length = 8;
 812		var->transp.offset = 24;
 813		break;
 814	}
 815
 816	var->red.msb_right = 0;
 817	var->green.msb_right = 0;
 818	var->blue.msb_right = 0;
 819	var->transp.msb_right = 0;
 820
 821	if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
 822	    !info->monspecs.dclkmax || !fb_validate_mode(var, info))
 823		mode_valid = 1;
 824
 825	/* calculate modeline if supported by monitor */
 826	if (!mode_valid && info->monspecs.gtf) {
 827		if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
 828			mode_valid = 1;
 829	}
 830
 831	if (!mode_valid) {
 832		const struct fb_videomode *mode;
 833
 834		mode = fb_find_best_mode(var, &info->modelist);
 835		if (mode) {
 836			fb_videomode_to_var(var, mode);
 837			mode_valid = 1;
 838		}
 839	}
 840
 841	if (!mode_valid && info->monspecs.modedb_len)
 842		return -EINVAL;
 843
 844	/*
 845	 * If we're on a flat panel, check if the mode is outside of the
 846	 * panel dimensions. If so, cap it and try for the next best mode
 847	 * before bailing out.
 848	 */
 849	if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
 850					      par->fpHeight < var->yres)) {
 851		const struct fb_videomode *mode;
 852
 853		var->xres = par->fpWidth;
 854		var->yres = par->fpHeight;
 855
 856		mode = fb_find_best_mode(var, &info->modelist);
 857		if (!mode) {
 858			printk(KERN_ERR PFX "mode out of range of flat "
 859			       "panel dimensions\n");
 860			return -EINVAL;
 861		}
 862
 863		fb_videomode_to_var(var, mode);
 864	}
 865
 866	if (var->yres_virtual < var->yres)
 867		var->yres_virtual = var->yres;
 868
 869	if (var->xres_virtual < var->xres)
 870		var->xres_virtual = var->xres;
 871
 872	var->xres_virtual = (var->xres_virtual + 63) & ~63;
 873
 874	vramlen = info->screen_size;
 875	pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
 876	memlen = pitch * var->yres_virtual;
 877
 878	if (memlen > vramlen) {
 879		var->yres_virtual = vramlen / pitch;
 880
 881		if (var->yres_virtual < var->yres) {
 882			var->yres_virtual = var->yres;
 883			var->xres_virtual = vramlen / var->yres_virtual;
 884			var->xres_virtual /= var->bits_per_pixel / 8;
 885			var->xres_virtual &= ~63;
 886			pitch = (var->xres_virtual *
 887				 var->bits_per_pixel + 7) / 8;
 888			memlen = pitch * var->yres;
 889
 890			if (var->xres_virtual < var->xres) {
 891				printk("nvidiafb: required video memory, "
 892				       "%d bytes, for %dx%d-%d (virtual) "
 893				       "is out of range\n",
 894				       memlen, var->xres_virtual,
 895				       var->yres_virtual, var->bits_per_pixel);
 896				err = -ENOMEM;
 897			}
 898		}
 899	}
 900
 901	if (var->accel_flags) {
 902		if (var->yres_virtual > 0x7fff)
 903			var->yres_virtual = 0x7fff;
 904		if (var->xres_virtual > 0x7fff)
 905			var->xres_virtual = 0x7fff;
 906	}
 907
 908	var->xres_virtual &= ~63;
 909
 910	NVTRACE_LEAVE();
 911
 912	return err;
 913}
 914
 915static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
 916				struct fb_info *info)
 917{
 918	struct nvidia_par *par = info->par;
 919	u32 total;
 920
 921	total = var->yoffset * info->fix.line_length + var->xoffset;
 922
 923	NVSetStartAddress(par, total);
 924
 925	return 0;
 926}
 927
 928static int nvidiafb_blank(int blank, struct fb_info *info)
 929{
 930	struct nvidia_par *par = info->par;
 931	unsigned char tmp, vesa;
 932
 933	tmp = NVReadSeq(par, 0x01) & ~0x20;	/* screen on/off */
 934	vesa = NVReadCrtc(par, 0x1a) & ~0xc0;	/* sync on/off */
 935
 936	NVTRACE_ENTER();
 937
 938	if (blank)
 939		tmp |= 0x20;
 940
 941	switch (blank) {
 942	case FB_BLANK_UNBLANK:
 943	case FB_BLANK_NORMAL:
 944		break;
 945	case FB_BLANK_VSYNC_SUSPEND:
 946		vesa |= 0x80;
 947		break;
 948	case FB_BLANK_HSYNC_SUSPEND:
 949		vesa |= 0x40;
 950		break;
 951	case FB_BLANK_POWERDOWN:
 952		vesa |= 0xc0;
 953		break;
 954	}
 955
 956	NVWriteSeq(par, 0x01, tmp);
 957	NVWriteCrtc(par, 0x1a, vesa);
 958
 959	NVTRACE_LEAVE();
 960
 961	return 0;
 962}
 963
 964/*
 965 * Because the VGA registers are not mapped linearly in its MMIO space,
 966 * restrict VGA register saving and restore to x86 only, where legacy VGA IO
 967 * access is legal. Consequently, we must also check if the device is the
 968 * primary display.
 969 */
 970#ifdef CONFIG_X86
 971static void save_vga_x86(struct nvidia_par *par)
 972{
 973	struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
 974
 975	if (res && res->flags & IORESOURCE_ROM_SHADOW) {
 976		memset(&par->vgastate, 0, sizeof(par->vgastate));
 977		par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
 978			VGA_SAVE_CMAP;
 979		save_vga(&par->vgastate);
 980	}
 981}
 982
 983static void restore_vga_x86(struct nvidia_par *par)
 984{
 985	struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
 986
 987	if (res && res->flags & IORESOURCE_ROM_SHADOW)
 988		restore_vga(&par->vgastate);
 989}
 990#else
 991#define save_vga_x86(x) do {} while (0)
 992#define restore_vga_x86(x) do {} while (0)
 993#endif /* X86 */
 994
 995static int nvidiafb_open(struct fb_info *info, int user)
 996{
 997	struct nvidia_par *par = info->par;
 998
 999	if (!par->open_count) {
1000		save_vga_x86(par);
1001		nvidia_save_vga(par, &par->initial_state);
1002	}
1003
1004	par->open_count++;
1005	return 0;
1006}
1007
1008static int nvidiafb_release(struct fb_info *info, int user)
1009{
1010	struct nvidia_par *par = info->par;
1011	int err = 0;
1012
1013	if (!par->open_count) {
1014		err = -EINVAL;
1015		goto done;
1016	}
1017
1018	if (par->open_count == 1) {
1019		nvidia_write_regs(par, &par->initial_state);
1020		restore_vga_x86(par);
1021	}
1022
1023	par->open_count--;
1024done:
1025	return err;
1026}
1027
1028static struct fb_ops nvidia_fb_ops = {
1029	.owner          = THIS_MODULE,
1030	.fb_open        = nvidiafb_open,
1031	.fb_release     = nvidiafb_release,
1032	__FB_DEFAULT_IOMEM_OPS_RDWR,
1033	.fb_check_var   = nvidiafb_check_var,
1034	.fb_set_par     = nvidiafb_set_par,
1035	.fb_setcolreg   = nvidiafb_setcolreg,
1036	.fb_pan_display = nvidiafb_pan_display,
1037	.fb_blank       = nvidiafb_blank,
1038	.fb_fillrect    = nvidiafb_fillrect,
1039	.fb_copyarea    = nvidiafb_copyarea,
1040	.fb_imageblit   = nvidiafb_imageblit,
1041	.fb_cursor      = nvidiafb_cursor,
1042	.fb_sync        = nvidiafb_sync,
1043	__FB_DEFAULT_IOMEM_OPS_MMAP,
1044};
1045
1046static int nvidiafb_suspend_late(struct device *dev, pm_message_t mesg)
1047{
1048	struct fb_info *info = dev_get_drvdata(dev);
1049	struct nvidia_par *par = info->par;
1050
1051	if (mesg.event == PM_EVENT_PRETHAW)
1052		mesg.event = PM_EVENT_FREEZE;
1053	console_lock();
1054	par->pm_state = mesg.event;
1055
1056	if (mesg.event & PM_EVENT_SLEEP) {
1057		fb_set_suspend(info, 1);
1058		nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1059		nvidia_write_regs(par, &par->SavedReg);
1060	}
1061	dev->power.power_state = mesg;
1062
1063	console_unlock();
1064	return 0;
1065}
1066
1067static int __maybe_unused nvidiafb_suspend(struct device *dev)
1068{
1069	return nvidiafb_suspend_late(dev, PMSG_SUSPEND);
1070}
1071
1072static int __maybe_unused nvidiafb_hibernate(struct device *dev)
1073{
1074	return nvidiafb_suspend_late(dev, PMSG_HIBERNATE);
1075}
1076
1077static int __maybe_unused nvidiafb_freeze(struct device *dev)
1078{
1079	return nvidiafb_suspend_late(dev, PMSG_FREEZE);
1080}
1081
1082static int __maybe_unused nvidiafb_resume(struct device *dev)
1083{
1084	struct fb_info *info = dev_get_drvdata(dev);
1085	struct nvidia_par *par = info->par;
1086
1087	console_lock();
1088
1089	par->pm_state = PM_EVENT_ON;
1090	nvidiafb_set_par(info);
1091	fb_set_suspend (info, 0);
1092	nvidiafb_blank(FB_BLANK_UNBLANK, info);
1093
1094	console_unlock();
1095	return 0;
1096}
1097
1098static const struct dev_pm_ops nvidiafb_pm_ops = {
1099#ifdef CONFIG_PM_SLEEP
1100	.suspend	= nvidiafb_suspend,
1101	.resume		= nvidiafb_resume,
1102	.freeze		= nvidiafb_freeze,
1103	.thaw		= nvidiafb_resume,
1104	.poweroff	= nvidiafb_hibernate,
1105	.restore	= nvidiafb_resume,
1106#endif /* CONFIG_PM_SLEEP */
1107};
1108
1109static int nvidia_set_fbinfo(struct fb_info *info)
1110{
1111	struct fb_monspecs *specs = &info->monspecs;
1112	struct fb_videomode modedb;
1113	struct nvidia_par *par = info->par;
1114	int lpitch;
1115
1116	NVTRACE_ENTER();
1117	info->flags =
1118	      FBINFO_HWACCEL_IMAGEBLIT
1119	    | FBINFO_HWACCEL_FILLRECT
1120	    | FBINFO_HWACCEL_COPYAREA
1121	    | FBINFO_HWACCEL_YPAN;
1122
1123	fb_videomode_to_modelist(info->monspecs.modedb,
1124				 info->monspecs.modedb_len, &info->modelist);
1125	fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1126
1127	switch (bpp) {
1128	case 0 ... 8:
1129		bpp = 8;
1130		break;
1131	case 9 ... 16:
1132		bpp = 16;
1133		break;
1134	default:
1135		bpp = 32;
1136		break;
1137	}
1138
1139	if (specs->modedb != NULL) {
1140		const struct fb_videomode *mode;
1141
1142		mode = fb_find_best_display(specs, &info->modelist);
1143		fb_videomode_to_var(&nvidiafb_default_var, mode);
1144		nvidiafb_default_var.bits_per_pixel = bpp;
1145	} else if (par->fpWidth && par->fpHeight) {
1146		char buf[16];
1147
1148		memset(buf, 0, 16);
1149		snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1150		fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1151			     specs->modedb_len, &modedb, bpp);
1152	}
1153
1154	if (mode_option)
1155		fb_find_mode(&nvidiafb_default_var, info, mode_option,
1156			     specs->modedb, specs->modedb_len, &modedb, bpp);
1157
1158	info->var = nvidiafb_default_var;
1159	info->fix.visual = (info->var.bits_per_pixel == 8) ?
1160		FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1161	info->pseudo_palette = par->pseudo_palette;
1162	fb_alloc_cmap(&info->cmap, 256, 0);
1163	fb_destroy_modedb(info->monspecs.modedb);
1164	info->monspecs.modedb = NULL;
1165
1166	/* maximize virtual vertical length */
1167	lpitch = info->var.xres_virtual *
1168		((info->var.bits_per_pixel + 7) >> 3);
1169	info->var.yres_virtual = info->screen_size / lpitch;
1170
1171	info->pixmap.scan_align = 4;
1172	info->pixmap.buf_align = 4;
1173	info->pixmap.access_align = 32;
1174	info->pixmap.size = 8 * 1024;
1175	info->pixmap.flags = FB_PIXMAP_SYSTEM;
1176
1177	if (!hwcur)
1178	    nvidia_fb_ops.fb_cursor = NULL;
1179
1180	info->var.accel_flags = (!noaccel);
1181
1182	switch (par->Architecture) {
1183	case NV_ARCH_04:
1184		info->fix.accel = FB_ACCEL_NV4;
1185		break;
1186	case NV_ARCH_10:
1187		info->fix.accel = FB_ACCEL_NV_10;
1188		break;
1189	case NV_ARCH_20:
1190		info->fix.accel = FB_ACCEL_NV_20;
1191		break;
1192	case NV_ARCH_30:
1193		info->fix.accel = FB_ACCEL_NV_30;
1194		break;
1195	case NV_ARCH_40:
1196		info->fix.accel = FB_ACCEL_NV_40;
1197		break;
1198	}
1199
1200	NVTRACE_LEAVE();
1201
1202	return nvidiafb_check_var(&info->var, info);
1203}
1204
1205static u32 nvidia_get_chipset(struct pci_dev *pci_dev,
1206			      volatile u32 __iomem *REGS)
1207{
1208	u32 id = (pci_dev->vendor << 16) | pci_dev->device;
1209
1210	printk(KERN_INFO PFX "Device ID: %x \n", id);
1211
1212	if ((id & 0xfff0) == 0x00f0 ||
1213	    (id & 0xfff0) == 0x02e0) {
1214		/* pci-e */
1215		id = NV_RD32(REGS, 0x1800);
1216
1217		if ((id & 0x0000ffff) == 0x000010DE)
1218			id = 0x10DE0000 | (id >> 16);
1219		else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1220			id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1221                            ((id >> 8) & 0x000000ff);
1222		printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1223	}
1224
1225	return id;
1226}
1227
1228static u32 nvidia_get_arch(u32 Chipset)
1229{
1230	u32 arch = 0;
1231
1232	switch (Chipset & 0x0ff0) {
1233	case 0x0100:		/* GeForce 256 */
1234	case 0x0110:		/* GeForce2 MX */
1235	case 0x0150:		/* GeForce2 */
1236	case 0x0170:		/* GeForce4 MX */
1237	case 0x0180:		/* GeForce4 MX (8x AGP) */
1238	case 0x01A0:		/* nForce */
1239	case 0x01F0:		/* nForce2 */
1240		arch = NV_ARCH_10;
1241		break;
1242	case 0x0200:		/* GeForce3 */
1243	case 0x0250:		/* GeForce4 Ti */
1244	case 0x0280:		/* GeForce4 Ti (8x AGP) */
1245		arch = NV_ARCH_20;
1246		break;
1247	case 0x0300:		/* GeForceFX 5800 */
1248	case 0x0310:		/* GeForceFX 5600 */
1249	case 0x0320:		/* GeForceFX 5200 */
1250	case 0x0330:		/* GeForceFX 5900 */
1251	case 0x0340:		/* GeForceFX 5700 */
1252		arch = NV_ARCH_30;
1253		break;
1254	case 0x0040:		/* GeForce 6800 */
1255	case 0x00C0:		/* GeForce 6800 */
1256	case 0x0120:		/* GeForce 6800 */
1257	case 0x0140:		/* GeForce 6600 */
1258	case 0x0160:		/* GeForce 6200 */
1259	case 0x01D0:		/* GeForce 7200, 7300, 7400 */
1260	case 0x0090:		/* GeForce 7800 */
1261	case 0x0210:		/* GeForce 6800 */
1262	case 0x0220:		/* GeForce 6200 */
1263	case 0x0240:		/* GeForce 6100 */
1264	case 0x0290:		/* GeForce 7900 */
1265	case 0x0390:		/* GeForce 7600 */
1266	case 0x03D0:
1267		arch = NV_ARCH_40;
1268		break;
1269	case 0x0020:		/* TNT, TNT2 */
1270		arch = NV_ARCH_04;
1271		break;
1272	default:		/* unknown architecture */
1273		break;
1274	}
1275
1276	return arch;
1277}
1278
1279static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1280{
1281	struct nvidia_par *par;
1282	struct fb_info *info;
1283	unsigned short cmd;
1284	int ret;
1285	volatile u32 __iomem *REGS;
1286	int Chipset;
1287	u32 Architecture;
1288
1289	NVTRACE_ENTER();
1290	assert(pd != NULL);
1291
1292	if (pci_enable_device(pd)) {
1293		printk(KERN_ERR PFX "cannot enable PCI device\n");
1294		return -ENODEV;
1295	}
1296
1297	/* enable IO and mem if not already done */
1298	pci_read_config_word(pd, PCI_COMMAND, &cmd);
1299	cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1300	pci_write_config_word(pd, PCI_COMMAND, cmd);
1301
1302	nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1303	nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1304
1305	REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1306	if (!REGS) {
1307		printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1308		return -ENODEV;
1309	}
1310
1311	Chipset = nvidia_get_chipset(pd, REGS);
1312	Architecture = nvidia_get_arch(Chipset);
1313	if (Architecture == 0) {
1314		printk(KERN_ERR PFX "unknown NV_ARCH\n");
1315		goto err_out;
1316	}
1317
1318	ret = aperture_remove_conflicting_pci_devices(pd, "nvidiafb");
1319	if (ret)
1320		goto err_out;
1321
1322	info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1323	if (!info)
1324		goto err_out;
1325
1326	par = info->par;
1327	par->pci_dev = pd;
1328	info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1329
1330	if (info->pixmap.addr == NULL)
1331		goto err_out_kfree;
1332
1333	if (pci_request_regions(pd, "nvidiafb")) {
1334		printk(KERN_ERR PFX "cannot request PCI regions\n");
1335		goto err_out_enable;
1336	}
1337
1338	par->FlatPanel = flatpanel;
1339	if (flatpanel == 1)
1340		printk(KERN_INFO PFX "flatpanel support enabled\n");
1341	par->FPDither = fpdither;
1342
1343	par->CRTCnumber = forceCRTC;
1344	par->FpScale = (!noscale);
1345	par->paneltweak = paneltweak;
1346	par->reverse_i2c = reverse_i2c;
1347
1348	nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1349
1350	par->REGS = REGS;
1351
1352	par->Chipset = Chipset;
1353	par->Architecture = Architecture;
1354
1355	sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1356
1357	if (NVCommonSetup(info))
1358		goto err_out_free_base0;
1359
1360	par->FbAddress = nvidiafb_fix.smem_start;
1361	par->FbMapSize = par->RamAmountKBytes * 1024;
1362	if (vram && vram * 1024 * 1024 < par->FbMapSize)
1363		par->FbMapSize = vram * 1024 * 1024;
1364
1365	/* Limit amount of vram to 64 MB */
1366	if (par->FbMapSize > 64 * 1024 * 1024)
1367		par->FbMapSize = 64 * 1024 * 1024;
1368
1369	if(par->Architecture >= NV_ARCH_40)
1370  	        par->FbUsableSize = par->FbMapSize - (560 * 1024);
1371	else
1372		par->FbUsableSize = par->FbMapSize - (128 * 1024);
1373	par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1374	    16 * 1024;
1375	par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1376	par->CursorStart = par->FbUsableSize + (32 * 1024);
1377
1378	info->screen_base = ioremap_wc(nvidiafb_fix.smem_start,
1379				       par->FbMapSize);
1380	info->screen_size = par->FbUsableSize;
1381	nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1382
1383	if (!info->screen_base) {
1384		printk(KERN_ERR PFX "cannot ioremap FB base\n");
1385		goto err_out_free_base1;
1386	}
1387
1388	par->FbStart = info->screen_base;
1389
1390	if (!nomtrr)
1391		par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start,
1392						  par->RamAmountKBytes * 1024);
1393
1394	info->fbops = &nvidia_fb_ops;
1395	info->fix = nvidiafb_fix;
1396
1397	if (nvidia_set_fbinfo(info) < 0) {
1398		printk(KERN_ERR PFX "error setting initial video mode\n");
1399		goto err_out_iounmap_fb;
1400	}
1401
1402	nvidia_save_vga(par, &par->SavedReg);
1403
1404	pci_set_drvdata(pd, info);
1405
1406	if (register_framebuffer(info) < 0) {
1407		printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1408		goto err_out_iounmap_fb;
1409	}
1410
1411	if (backlight)
1412		nvidia_bl_init(par);
1413
1414	printk(KERN_INFO PFX
1415	       "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1416	       info->fix.id,
1417	       par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1418
1419	NVTRACE_LEAVE();
1420	return 0;
1421
1422err_out_iounmap_fb:
1423	iounmap(info->screen_base);
1424err_out_free_base1:
1425	fb_destroy_modedb(info->monspecs.modedb);
1426	nvidia_delete_i2c_busses(par);
1427err_out_free_base0:
1428	pci_release_regions(pd);
1429err_out_enable:
1430	kfree(info->pixmap.addr);
1431err_out_kfree:
1432	framebuffer_release(info);
1433err_out:
1434	iounmap(REGS);
1435	return -ENODEV;
1436}
1437
1438static void nvidiafb_remove(struct pci_dev *pd)
1439{
1440	struct fb_info *info = pci_get_drvdata(pd);
1441	struct nvidia_par *par = info->par;
1442
1443	NVTRACE_ENTER();
1444
1445	nvidia_bl_exit(par);
1446	unregister_framebuffer(info);
1447
1448	arch_phys_wc_del(par->wc_cookie);
1449	iounmap(info->screen_base);
1450	fb_destroy_modedb(info->monspecs.modedb);
1451	nvidia_delete_i2c_busses(par);
1452	iounmap(par->REGS);
1453	pci_release_regions(pd);
1454	kfree(info->pixmap.addr);
1455	framebuffer_release(info);
1456	NVTRACE_LEAVE();
1457}
1458
1459/* ------------------------------------------------------------------------- *
1460 *
1461 * initialization
1462 *
1463 * ------------------------------------------------------------------------- */
1464
1465#ifndef MODULE
1466static int nvidiafb_setup(char *options)
1467{
1468	char *this_opt;
1469
1470	NVTRACE_ENTER();
1471	if (!options || !*options)
1472		return 0;
1473
1474	while ((this_opt = strsep(&options, ",")) != NULL) {
1475		if (!strncmp(this_opt, "forceCRTC", 9)) {
1476			char *p;
1477
1478			p = this_opt + 9;
1479			if (!*p || !*(++p))
1480				continue;
1481			forceCRTC = *p - '0';
1482			if (forceCRTC < 0 || forceCRTC > 1)
1483				forceCRTC = -1;
1484		} else if (!strncmp(this_opt, "flatpanel", 9)) {
1485			flatpanel = 1;
1486		} else if (!strncmp(this_opt, "hwcur", 5)) {
1487			hwcur = 1;
1488		} else if (!strncmp(this_opt, "noaccel", 7)) {
1489			noaccel = 1;
1490		} else if (!strncmp(this_opt, "noscale", 7)) {
1491			noscale = 1;
1492		} else if (!strncmp(this_opt, "reverse_i2c", 11)) {
1493			reverse_i2c = 1;
1494		} else if (!strncmp(this_opt, "paneltweak:", 11)) {
1495			paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1496		} else if (!strncmp(this_opt, "vram:", 5)) {
1497			vram = simple_strtoul(this_opt+5, NULL, 0);
1498		} else if (!strncmp(this_opt, "backlight:", 10)) {
1499			backlight = simple_strtoul(this_opt+10, NULL, 0);
1500		} else if (!strncmp(this_opt, "nomtrr", 6)) {
1501			nomtrr = true;
1502		} else if (!strncmp(this_opt, "fpdither:", 9)) {
1503			fpdither = simple_strtol(this_opt+9, NULL, 0);
1504		} else if (!strncmp(this_opt, "bpp:", 4)) {
1505			bpp = simple_strtoul(this_opt+4, NULL, 0);
1506		} else
1507			mode_option = this_opt;
1508	}
1509	NVTRACE_LEAVE();
1510	return 0;
1511}
1512#endif				/* !MODULE */
1513
1514static struct pci_driver nvidiafb_driver = {
1515	.name      = "nvidiafb",
1516	.id_table  = nvidiafb_pci_tbl,
1517	.probe     = nvidiafb_probe,
1518	.driver.pm = &nvidiafb_pm_ops,
1519	.remove    = nvidiafb_remove,
1520};
1521
1522/* ------------------------------------------------------------------------- *
1523 *
1524 * modularization
1525 *
1526 * ------------------------------------------------------------------------- */
1527
1528static int nvidiafb_init(void)
1529{
1530#ifndef MODULE
1531	char *option = NULL;
1532#endif
1533
1534	if (fb_modesetting_disabled("nvidiafb"))
1535		return -ENODEV;
1536
1537#ifndef MODULE
1538	if (fb_get_options("nvidiafb", &option))
1539		return -ENODEV;
1540	nvidiafb_setup(option);
1541#endif
1542	return pci_register_driver(&nvidiafb_driver);
1543}
1544
1545module_init(nvidiafb_init);
1546
1547static void __exit nvidiafb_exit(void)
1548{
1549	pci_unregister_driver(&nvidiafb_driver);
1550}
1551
1552module_exit(nvidiafb_exit);
1553
1554module_param(flatpanel, int, 0);
1555MODULE_PARM_DESC(flatpanel,
1556		 "Enables experimental flat panel support for some chipsets. "
1557		 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1558module_param(fpdither, int, 0);
1559MODULE_PARM_DESC(fpdither,
1560		 "Enables dithering of flat panel for 6 bits panels. "
1561		 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1562module_param(hwcur, int, 0);
1563MODULE_PARM_DESC(hwcur,
1564		 "Enables hardware cursor implementation. (0 or 1=enabled) "
1565		 "(default=0)");
1566module_param(noaccel, int, 0);
1567MODULE_PARM_DESC(noaccel,
1568		 "Disables hardware acceleration. (0 or 1=disable) "
1569		 "(default=0)");
1570module_param(noscale, int, 0);
1571MODULE_PARM_DESC(noscale,
1572		 "Disables screen scaling. (0 or 1=disable) "
1573		 "(default=0, do scaling)");
1574module_param(paneltweak, int, 0);
1575MODULE_PARM_DESC(paneltweak,
1576		 "Tweak display settings for flatpanels. "
1577		 "(default=0, no tweaks)");
1578module_param(forceCRTC, int, 0);
1579MODULE_PARM_DESC(forceCRTC,
1580		 "Forces usage of a particular CRTC in case autodetection "
1581		 "fails. (0 or 1) (default=autodetect)");
1582module_param(vram, int, 0);
1583MODULE_PARM_DESC(vram,
1584		 "amount of framebuffer memory to remap in MiB"
1585		 "(default=0 - remap entire memory)");
1586module_param(mode_option, charp, 0);
1587MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1588module_param(bpp, int, 0);
1589MODULE_PARM_DESC(bpp, "pixel width in bits"
1590		 "(default=8)");
1591module_param(reverse_i2c, int, 0);
1592MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus");
1593module_param(nomtrr, bool, false);
1594MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1595		 "(default=0)");
1596
1597MODULE_AUTHOR("Antonino Daplas");
1598MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1599MODULE_LICENSE("GPL");