mmp_ctrl.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * drivers/video/mmp/hw/mmp_ctrl.h
   4 *
   5 * Copyright (C) 2012 Marvell Technology Group Ltd.
   6 * Authors:  Guoqing Li <ligq@marvell.com>
   7 *          Lisa Du <cldu@marvell.com>
   8 *          Zhou Zhu <zzhu3@marvell.com>
   9 */
  10
  11#ifndef _MMP_CTRL_H_
  12#define _MMP_CTRL_H_
  13
  14#include <video/mmp_disp.h>
  15
  16/* ------------< LCD register >------------ */
  17struct lcd_regs {
  18/* TV patch register for MMP2 */
  19/* 32 bit		TV Video Frame0 Y Starting Address */
  20#define LCD_TVD_START_ADDR_Y0			(0x0000)
  21/* 32 bit		TV Video Frame0 U Starting Address */
  22#define LCD_TVD_START_ADDR_U0			(0x0004)
  23/* 32 bit		TV Video Frame0 V Starting Address */
  24#define LCD_TVD_START_ADDR_V0			(0x0008)
  25/* 32 bit		TV Video Frame0 Command Starting Address */
  26#define LCD_TVD_START_ADDR_C0			(0x000C)
  27/* 32 bit		TV Video Frame1 Y Starting Address Register*/
  28#define LCD_TVD_START_ADDR_Y1			(0x0010)
  29/* 32 bit		TV Video Frame1 U Starting Address Register*/
  30#define LCD_TVD_START_ADDR_U1			(0x0014)
  31/* 32 bit		TV Video Frame1 V Starting Address Register*/
  32#define LCD_TVD_START_ADDR_V1			(0x0018)
  33/* 32 bit		TV Video Frame1 Command Starting Address Register*/
  34#define LCD_TVD_START_ADDR_C1			(0x001C)
  35/* 32 bit		TV Video Y andC Line Length(Pitch)Register*/
  36#define LCD_TVD_PITCH_YC			(0x0020)
  37/* 32 bit		TV Video U andV Line Length(Pitch)Register*/
  38#define LCD_TVD_PITCH_UV			(0x0024)
  39/* 32 bit	  TV Video Starting Point on Screen Register*/
  40#define LCD_TVD_OVSA_HPXL_VLN			(0x0028)
  41/* 32 bit		TV Video Source Size Register*/
  42#define LCD_TVD_HPXL_VLN			(0x002C)
  43/* 32 bit	  TV Video Destination Size (After Zooming)Register*/
  44#define LCD_TVDZM_HPXL_VLN			(0x0030)
  45	u32 v_y0;
  46	u32 v_u0;
  47	u32 v_v0;
  48	u32 v_c0;
  49	u32 v_y1;
  50	u32 v_u1;
  51	u32 v_v1;
  52	u32 v_c1;
  53	u32 v_pitch_yc;		/* Video Y and C Line Length (Pitch) */
  54	u32 v_pitch_uv;		/* Video U and V Line Length (Pitch) */
  55	u32 v_start;		/* Video Starting Point on Screen */
  56	u32 v_size;			/* Video Source Size */
  57	u32 v_size_z;		/* Video Destination Size (After Zooming) */
  58
  59/* 32 bit	   TV Graphic Frame 0 Starting Address Register*/
  60#define LCD_TVG_START_ADDR0				(0x0034)
  61/* 32 bit	  TV Graphic Frame 1 Starting Address Register*/
  62#define LCD_TVG_START_ADDR1				(0x0038)
  63/* 32 bit		TV Graphic Line Length(Pitch)Register*/
  64#define LCD_TVG_PITCH					(0x003C)
  65/* 32 bit		TV Graphic Starting Point on Screen Register*/
  66#define LCD_TVG_OVSA_HPXL_VLN				(0x0040)
  67/* 32 bit		TV Graphic Source Size Register*/
  68#define LCD_TVG_HPXL_VLN				(0x0044)
  69/* 32 bit		TV Graphic Destination size (after Zooming)Register*/
  70#define LCD_TVGZM_HPXL_VLN				(0x0048)
  71	u32 g_0;			/* Graphic Frame 0/1 Starting Address */
  72	u32 g_1;
  73	u32 g_pitch;		/* Graphic Line Length (Pitch) */
  74	u32 g_start;		/* Graphic Starting Point on Screen */
  75	u32 g_size;			/* Graphic Source Size */
  76	u32 g_size_z;		/* Graphic Destination Size (After Zooming) */
  77
  78/* 32 bit	  TV Hardware Cursor Starting Point on screen Register*/
  79#define LCD_TVC_OVSA_HPXL_VLN				(0x004C)
  80/* 32 bit		TV Hardware Cursor Size Register */
  81#define LCD_TVC_HPXL_VLN				(0x0050)
  82	u32 hc_start;			/* Hardware Cursor */
  83	u32 hc_size;			/* Hardware Cursor */
  84
  85/* 32 bit		TV Total Screen Size Register*/
  86#define LCD_TV_V_H_TOTAL				(0x0054)
  87/* 32 bit		TV Screen Active Size Register*/
  88#define LCD_TV_V_H_ACTIVE				(0x0058)
  89/* 32 bit		TV Screen Horizontal Porch Register*/
  90#define LCD_TV_H_PORCH					(0x005C)
  91/* 32 bit		TV Screen Vertical Porch Register*/
  92#define LCD_TV_V_PORCH					(0x0060)
  93	u32 screen_size;		/* Screen Total Size */
  94	u32 screen_active;		/* Screen Active Size */
  95	u32 screen_h_porch;		/* Screen Horizontal Porch */
  96	u32 screen_v_porch;		/* Screen Vertical Porch */
  97
  98/* 32 bit		TV Screen Blank Color Register*/
  99#define LCD_TV_BLANKCOLOR				(0x0064)
 100/* 32 bit		TV Hardware Cursor Color1 Register*/
 101#define LCD_TV_ALPHA_COLOR1				(0x0068)
 102/* 32 bit		TV Hardware Cursor Color2 Register*/
 103#define LCD_TV_ALPHA_COLOR2				(0x006C)
 104	u32 blank_color;		/* Screen Blank Color */
 105	u32 hc_Alpha_color1;	/* Hardware Cursor Color1 */
 106	u32 hc_Alpha_color2;	/* Hardware Cursor Color2 */
 107
 108/* 32 bit		TV Video Y Color Key Control*/
 109#define LCD_TV_COLORKEY_Y				(0x0070)
 110/* 32 bit		TV Video U Color Key Control*/
 111#define LCD_TV_COLORKEY_U				(0x0074)
 112/* 32 bit		TV Video V Color Key Control*/
 113#define LCD_TV_COLORKEY_V				(0x0078)
 114	u32 v_colorkey_y;		/* Video Y Color Key Control */
 115	u32 v_colorkey_u;		/* Video U Color Key Control */
 116	u32 v_colorkey_v;		/* Video V Color Key Control */
 117
 118/* 32 bit		TV VSYNC PulsePixel Edge Control Register*/
 119#define LCD_TV_SEPXLCNT					(0x007C)
 120	u32 vsync_ctrl;			/* VSYNC PulsePixel Edge Control */
 121};
 122
 123#define intf_ctrl(id)		((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \
 124				LCD_DUMB2_CTRL) : LCD_SPU_DUMB_CTRL)
 125#define dma_ctrl0(id)	   ((id) ? (((id) & 1) ? LCD_TV_CTRL0 : \
 126				LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0)
 127#define dma_ctrl1(id)	   ((id) ? (((id) & 1) ? LCD_TV_CTRL1 : \
 128				LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1)
 129#define dma_ctrl(ctrl1, id)	 (ctrl1 ? dma_ctrl1(id) : dma_ctrl0(id))
 130
 131/* 32 bit		TV Path DMA Control 0*/
 132#define LCD_TV_CTRL0					(0x0080)
 133/* 32 bit		TV Path DMA Control 1*/
 134#define LCD_TV_CTRL1					(0x0084)
 135/* 32 bit		TV Path Video Contrast*/
 136#define LCD_TV_CONTRAST					(0x0088)
 137/* 32 bit		TV Path Video Saturation*/
 138#define LCD_TV_SATURATION				(0x008C)
 139/* 32 bit		TV Path Video Hue Adjust*/
 140#define LCD_TV_CBSH_HUE					(0x0090)
 141/* 32 bit TV Path TVIF Control	Register */
 142#define LCD_TVIF_CTRL					(0x0094)
 143#define TV_VBLNK_VALID_EN				(1 << 12)
 144
 145/* 32 bit TV Path I/O Pad Control*/
 146#define LCD_TVIOPAD_CTRL				(0x0098)
 147/* 32 bit TV Path Cloc	Divider  */
 148#define LCD_TCLK_DIV					(0x009C)
 149
 150#define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
 151	((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
 152#define intf_rbswap_ctrl(id)	((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \
 153				PN2_IOPAD_CONTROL) : LCD_TOP_CTRL)
 154
 155/* dither configure */
 156#define LCD_DITHER_CTRL				(0x00A0)
 157
 158#define DITHER_TBL_INDEX_SEL(s)		((s) << 16)
 159#define DITHER_MODE2(m)				((m) << 12)
 160#define DITHER_MODE2_SHIFT			(12)
 161#define DITHER_4X8_EN2				(1 << 9)
 162#define DITHER_4X8_EN2_SHIFT		(9)
 163#define DITHER_EN2					(1 << 8)
 164#define DITHER_MODE1(m)				((m) << 4)
 165#define DITHER_MODE1_SHIFT			(4)
 166#define DITHER_4X8_EN1				(1 << 1)
 167#define DITHER_4X8_EN1_SHIFT		(1)
 168#define DITHER_EN1					(1)
 169
 170/* dither table data was fixed by video bpp of input and output*/
 171#define DITHER_TB_4X4_INDEX0		(0x3b19f7d5)
 172#define DITHER_TB_4X4_INDEX1		(0x082ac4e6)
 173#define DITHER_TB_4X8_INDEX0		(0xf7d508e6)
 174#define DITHER_TB_4X8_INDEX1		(0x3b194c2a)
 175#define DITHER_TB_4X8_INDEX2		(0xc4e6d5f7)
 176#define DITHER_TB_4X8_INDEX3		(0x082a193b)
 177#define LCD_DITHER_TBL_DATA		(0x00A4)
 178
 179/* Video Frame 0&1 start address registers */
 180#define	LCD_SPU_DMA_START_ADDR_Y0	0x00C0
 181#define	LCD_SPU_DMA_START_ADDR_U0	0x00C4
 182#define	LCD_SPU_DMA_START_ADDR_V0	0x00C8
 183#define LCD_CFG_DMA_START_ADDR_0	0x00CC /* Cmd address */
 184#define	LCD_SPU_DMA_START_ADDR_Y1	0x00D0
 185#define	LCD_SPU_DMA_START_ADDR_U1	0x00D4
 186#define	LCD_SPU_DMA_START_ADDR_V1	0x00D8
 187#define LCD_CFG_DMA_START_ADDR_1	0x00DC /* Cmd address */
 188
 189/* YC & UV Pitch */
 190#define LCD_SPU_DMA_PITCH_YC		0x00E0
 191#define	 SPU_DMA_PITCH_C(c)		((c)<<16)
 192#define	 SPU_DMA_PITCH_Y(y)		(y)
 193#define LCD_SPU_DMA_PITCH_UV		0x00E4
 194#define	 SPU_DMA_PITCH_V(v)		((v)<<16)
 195#define	 SPU_DMA_PITCH_U(u)		(u)
 196
 197/* Video Starting Point on Screen Register */
 198#define LCD_SPUT_DMA_OVSA_HPXL_VLN		0x00E8
 199#define	 CFG_DMA_OVSA_VLN(y)			((y)<<16) /* 0~0xfff */
 200#define	 CFG_DMA_OVSA_HPXL(x)			(x)	 /* 0~0xfff */
 201
 202/* Video Size Register */
 203#define LCD_SPU_DMA_HPXL_VLN			0x00EC
 204#define	 CFG_DMA_VLN(y)				((y)<<16)
 205#define	 CFG_DMA_HPXL(x)			(x)
 206
 207/* Video Size After zooming Register */
 208#define LCD_SPU_DZM_HPXL_VLN			0x00F0
 209#define	 CFG_DZM_VLN(y)				((y)<<16)
 210#define	 CFG_DZM_HPXL(x)			(x)
 211
 212/* Graphic Frame 0&1 Starting Address Register */
 213#define LCD_CFG_GRA_START_ADDR0			0x00F4
 214#define LCD_CFG_GRA_START_ADDR1			0x00F8
 215
 216/* Graphic Frame Pitch */
 217#define LCD_CFG_GRA_PITCH			0x00FC
 218
 219/* Graphic Starting Point on Screen Register */
 220#define LCD_SPU_GRA_OVSA_HPXL_VLN		0x0100
 221#define	 CFG_GRA_OVSA_VLN(y)			((y)<<16)
 222#define	 CFG_GRA_OVSA_HPXL(x)			(x)
 223
 224/* Graphic Size Register */
 225#define LCD_SPU_GRA_HPXL_VLN			0x0104
 226#define	 CFG_GRA_VLN(y)				((y)<<16)
 227#define	 CFG_GRA_HPXL(x)			(x)
 228
 229/* Graphic Size after Zooming Register */
 230#define LCD_SPU_GZM_HPXL_VLN			0x0108
 231#define	 CFG_GZM_VLN(y)				((y)<<16)
 232#define	 CFG_GZM_HPXL(x)			(x)
 233
 234/* HW Cursor Starting Point on Screen Register */
 235#define LCD_SPU_HWC_OVSA_HPXL_VLN		0x010C
 236#define	 CFG_HWC_OVSA_VLN(y)			((y)<<16)
 237#define	 CFG_HWC_OVSA_HPXL(x)			(x)
 238
 239/* HW Cursor Size */
 240#define LCD_SPU_HWC_HPXL_VLN			0x0110
 241#define	 CFG_HWC_VLN(y)				((y)<<16)
 242#define	 CFG_HWC_HPXL(x)			(x)
 243
 244/* Total Screen Size Register */
 245#define LCD_SPUT_V_H_TOTAL			0x0114
 246#define	 CFG_V_TOTAL(y)				((y)<<16)
 247#define	 CFG_H_TOTAL(x)				(x)
 248
 249/* Total Screen Active Size Register */
 250#define LCD_SPU_V_H_ACTIVE			0x0118
 251#define	 CFG_V_ACTIVE(y)			((y)<<16)
 252#define	 CFG_H_ACTIVE(x)			(x)
 253
 254/* Screen H&V Porch Register */
 255#define LCD_SPU_H_PORCH				0x011C
 256#define	 CFG_H_BACK_PORCH(b)			((b)<<16)
 257#define	 CFG_H_FRONT_PORCH(f)			(f)
 258#define LCD_SPU_V_PORCH				0x0120
 259#define	 CFG_V_BACK_PORCH(b)			((b)<<16)
 260#define	 CFG_V_FRONT_PORCH(f)			(f)
 261
 262/* Screen Blank Color Register */
 263#define LCD_SPU_BLANKCOLOR			0x0124
 264#define  CFG_BLANKCOLOR_MASK			0x00FFFFFF
 265#define  CFG_BLANKCOLOR_R_MASK			0x000000FF
 266#define  CFG_BLANKCOLOR_G_MASK			0x0000FF00
 267#define  CFG_BLANKCOLOR_B_MASK			0x00FF0000
 268
 269/* HW Cursor Color 1&2 Register */
 270#define LCD_SPU_ALPHA_COLOR1			0x0128
 271#define	 CFG_HWC_COLOR1				0x00FFFFFF
 272#define	 CFG_HWC_COLOR1_R(red)			((red)<<16)
 273#define	 CFG_HWC_COLOR1_G(green)		((green)<<8)
 274#define	 CFG_HWC_COLOR1_B(blue)			(blue)
 275#define	 CFG_HWC_COLOR1_R_MASK			0x000000FF
 276#define	 CFG_HWC_COLOR1_G_MASK			0x0000FF00
 277#define	 CFG_HWC_COLOR1_B_MASK			0x00FF0000
 278#define LCD_SPU_ALPHA_COLOR2			0x012C
 279#define	 CFG_HWC_COLOR2				0x00FFFFFF
 280#define	 CFG_HWC_COLOR2_R_MASK			0x000000FF
 281#define	 CFG_HWC_COLOR2_G_MASK			0x0000FF00
 282#define	 CFG_HWC_COLOR2_B_MASK			0x00FF0000
 283
 284/* Video YUV Color Key Control */
 285#define LCD_SPU_COLORKEY_Y			0x0130
 286#define	 CFG_CKEY_Y2(y2)			((y2)<<24)
 287#define	 CFG_CKEY_Y2_MASK			0xFF000000
 288#define	 CFG_CKEY_Y1(y1)			((y1)<<16)
 289#define	 CFG_CKEY_Y1_MASK			0x00FF0000
 290#define	 CFG_CKEY_Y(y)				((y)<<8)
 291#define	 CFG_CKEY_Y_MASK			0x0000FF00
 292#define	 CFG_ALPHA_Y(y)				(y)
 293#define	 CFG_ALPHA_Y_MASK			0x000000FF
 294#define LCD_SPU_COLORKEY_U			0x0134
 295#define	 CFG_CKEY_U2(u2)			((u2)<<24)
 296#define	 CFG_CKEY_U2_MASK			0xFF000000
 297#define	 CFG_CKEY_U1(u1)			((u1)<<16)
 298#define	 CFG_CKEY_U1_MASK			0x00FF0000
 299#define	 CFG_CKEY_U(u)				((u)<<8)
 300#define	 CFG_CKEY_U_MASK			0x0000FF00
 301#define	 CFG_ALPHA_U(u)				(u)
 302#define	 CFG_ALPHA_U_MASK			0x000000FF
 303#define LCD_SPU_COLORKEY_V			0x0138
 304#define	 CFG_CKEY_V2(v2)			((v2)<<24)
 305#define	 CFG_CKEY_V2_MASK			0xFF000000
 306#define	 CFG_CKEY_V1(v1)			((v1)<<16)
 307#define	 CFG_CKEY_V1_MASK			0x00FF0000
 308#define	 CFG_CKEY_V(v)				((v)<<8)
 309#define	 CFG_CKEY_V_MASK			0x0000FF00
 310#define	 CFG_ALPHA_V(v)				(v)
 311#define	 CFG_ALPHA_V_MASK			0x000000FF
 312
 313/* Graphics/Video DMA color key enable bits in LCD_TV_CTRL1 */
 314#define	 CFG_CKEY_GRA				0x2
 315#define	 CFG_CKEY_DMA				0x1
 316
 317/* Interlace mode enable bits in LCD_TV_CTRL1 */
 318#define     CFG_TV_INTERLACE_EN                 (1 << 22)
 319#define     CFG_TV_NIB                          (1 << 0)
 320
 321#define LCD_PN_SEPXLCNT				0x013c /* MMP2 */
 322
 323/* SPI Read Data Register */
 324#define LCD_SPU_SPI_RXDATA			0x0140
 325
 326/* Smart Panel Read Data Register */
 327#define LCD_SPU_ISA_RSDATA			0x0144
 328#define	 ISA_RXDATA_16BIT_1_DATA_MASK		0x000000FF
 329#define	 ISA_RXDATA_16BIT_2_DATA_MASK		0x0000FF00
 330#define	 ISA_RXDATA_16BIT_3_DATA_MASK		0x00FF0000
 331#define	 ISA_RXDATA_16BIT_4_DATA_MASK		0xFF000000
 332#define	 ISA_RXDATA_32BIT_1_DATA_MASK		0x00FFFFFF
 333
 334#define LCD_SPU_DBG_ISA				(0x0148) /* TTC */
 335#define LCD_SPU_DMAVLD_YC			(0x014C)
 336#define LCD_SPU_DMAVLD_UV			(0x0150)
 337#define LCD_SPU_DMAVLD_UVSPU_GRAVLD		(0x0154)
 338
 339#define LCD_READ_IOPAD				(0x0148) /* MMP2*/
 340#define LCD_DMAVLD_YC				(0x014C)
 341#define LCD_DMAVLD_UV				(0x0150)
 342#define LCD_TVGGRAVLD_HLEN			(0x0154)
 343
 344/* HWC SRAM Read Data Register */
 345#define LCD_SPU_HWC_RDDAT			0x0158
 346
 347/* Gamma Table SRAM Read Data Register */
 348#define LCD_SPU_GAMMA_RDDAT			0x015c
 349#define	 CFG_GAMMA_RDDAT_MASK			0x000000FF
 350
 351/* Palette Table SRAM Read Data Register */
 352#define LCD_SPU_PALETTE_RDDAT			0x0160
 353#define	 CFG_PALETTE_RDDAT_MASK			0x00FFFFFF
 354
 355#define LCD_SPU_DBG_DMATOP			(0x0164) /* TTC */
 356#define LCD_SPU_DBG_GRATOP			(0x0168)
 357#define LCD_SPU_DBG_TXCTRL			(0x016C)
 358#define LCD_SPU_DBG_SLVTOP			(0x0170)
 359#define LCD_SPU_DBG_MUXTOP			(0x0174)
 360
 361#define LCD_SLV_DBG				(0x0164) /* MMP2 */
 362#define LCD_TVDVLD_YC				(0x0168)
 363#define LCD_TVDVLD_UV				(0x016C)
 364#define LCD_TVC_RDDAT				(0x0170)
 365#define LCD_TV_GAMMA_RDDAT			(0x0174)
 366
 367/* I/O Pads Input Read Only Register */
 368#define LCD_SPU_IOPAD_IN			0x0178
 369#define	 CFG_IOPAD_IN_MASK			0x0FFFFFFF
 370
 371#define LCD_TV_PALETTE_RDDAT			(0x0178) /* MMP2 */
 372
 373/* Reserved Read Only Registers */
 374#define LCD_CFG_RDREG5F				0x017C
 375#define	 IRE_FRAME_CNT_MASK			0x000000C0
 376#define	 IPE_FRAME_CNT_MASK			0x00000030
 377#define	 GRA_FRAME_CNT_MASK			0x0000000C /* Graphic */
 378#define	 DMA_FRAME_CNT_MASK			0x00000003 /* Video */
 379
 380#define LCD_FRAME_CNT				(0x017C) /* MMP2 */
 381
 382/* SPI Control Register. */
 383#define LCD_SPU_SPI_CTRL			0x0180
 384#define	 CFG_SCLKCNT(div)			((div)<<24) /* 0xFF~0x2 */
 385#define	 CFG_SCLKCNT_MASK			0xFF000000
 386#define	 CFG_RXBITS(rx)				(((rx) - 1)<<16) /* 0x1F~0x1 */
 387#define	 CFG_RXBITS_MASK			0x00FF0000
 388#define	 CFG_TXBITS(tx)				(((tx) - 1)<<8) /* 0x1F~0x1 */
 389#define	 CFG_TXBITS_MASK			0x0000FF00
 390#define	 CFG_CLKINV(clk)			((clk)<<7)
 391#define	 CFG_CLKINV_MASK			0x00000080
 392#define	 CFG_KEEPXFER(transfer)			((transfer)<<6)
 393#define	 CFG_KEEPXFER_MASK			0x00000040
 394#define	 CFG_RXBITSTO0(rx)			((rx)<<5)
 395#define	 CFG_RXBITSTO0_MASK			0x00000020
 396#define	 CFG_TXBITSTO0(tx)			((tx)<<4)
 397#define	 CFG_TXBITSTO0_MASK			0x00000010
 398#define	 CFG_SPI_ENA(spi)			((spi)<<3)
 399#define	 CFG_SPI_ENA_MASK			0x00000008
 400#define	 CFG_SPI_SEL(spi)			((spi)<<2)
 401#define	 CFG_SPI_SEL_MASK			0x00000004
 402#define	 CFG_SPI_3W4WB(wire)			((wire)<<1)
 403#define	 CFG_SPI_3W4WB_MASK			0x00000002
 404#define	 CFG_SPI_START(start)			(start)
 405#define	 CFG_SPI_START_MASK			0x00000001
 406
 407/* SPI Tx Data Register */
 408#define LCD_SPU_SPI_TXDATA			0x0184
 409
 410/*
 411   1. Smart Pannel 8-bit Bus Control Register.
 412   2. AHB Slave Path Data Port Register
 413*/
 414#define LCD_SPU_SMPN_CTRL			0x0188
 415
 416/* DMA Control 0 Register */
 417#define LCD_SPU_DMA_CTRL0			0x0190
 418#define	 CFG_NOBLENDING(nb)			((nb)<<31)
 419#define	 CFG_NOBLENDING_MASK			0x80000000
 420#define	 CFG_GAMMA_ENA(gn)			((gn)<<30)
 421#define	 CFG_GAMMA_ENA_MASK			0x40000000
 422#define	 CFG_CBSH_ENA(cn)			((cn)<<29)
 423#define	 CFG_CBSH_ENA_MASK			0x20000000
 424#define	 CFG_PALETTE_ENA(pn)			((pn)<<28)
 425#define	 CFG_PALETTE_ENA_MASK			0x10000000
 426#define	 CFG_ARBFAST_ENA(an)			((an)<<27)
 427#define	 CFG_ARBFAST_ENA_MASK			0x08000000
 428#define	 CFG_HWC_1BITMOD(mode)			((mode)<<26)
 429#define	 CFG_HWC_1BITMOD_MASK			0x04000000
 430#define	 CFG_HWC_1BITENA(mn)			((mn)<<25)
 431#define	 CFG_HWC_1BITENA_MASK			0x02000000
 432#define	 CFG_HWC_ENA(cn)			((cn)<<24)
 433#define	 CFG_HWC_ENA_MASK			0x01000000
 434#define	 CFG_DMAFORMAT(dmaformat)		((dmaformat)<<20)
 435#define	 CFG_DMAFORMAT_MASK			0x00F00000
 436#define	 CFG_GRAFORMAT(graformat)		((graformat)<<16)
 437#define	 CFG_GRAFORMAT_MASK			0x000F0000
 438/* for graphic part */
 439#define	 CFG_GRA_FTOGGLE(toggle)		((toggle)<<15)
 440#define	 CFG_GRA_FTOGGLE_MASK			0x00008000
 441#define	 CFG_GRA_HSMOOTH(smooth)		((smooth)<<14)
 442#define	 CFG_GRA_HSMOOTH_MASK			0x00004000
 443#define	 CFG_GRA_TSTMODE(test)			((test)<<13)
 444#define	 CFG_GRA_TSTMODE_MASK			0x00002000
 445#define	 CFG_GRA_SWAPRB(swap)			((swap)<<12)
 446#define	 CFG_GRA_SWAPRB_MASK			0x00001000
 447#define	 CFG_GRA_SWAPUV(swap)			((swap)<<11)
 448#define	 CFG_GRA_SWAPUV_MASK			0x00000800
 449#define	 CFG_GRA_SWAPYU(swap)			((swap)<<10)
 450#define	 CFG_GRA_SWAPYU_MASK			0x00000400
 451#define	 CFG_GRA_SWAP_MASK			0x00001C00
 452#define	 CFG_YUV2RGB_GRA(cvrt)			((cvrt)<<9)
 453#define	 CFG_YUV2RGB_GRA_MASK			0x00000200
 454#define	 CFG_GRA_ENA(gra)			((gra)<<8)
 455#define	 CFG_GRA_ENA_MASK			0x00000100
 456#define dma0_gfx_masks	(CFG_GRAFORMAT_MASK | CFG_GRA_FTOGGLE_MASK | \
 457	CFG_GRA_HSMOOTH_MASK | CFG_GRA_TSTMODE_MASK | CFG_GRA_SWAP_MASK | \
 458	CFG_YUV2RGB_GRA_MASK | CFG_GRA_ENA_MASK)
 459/* for video part */
 460#define	 CFG_DMA_FTOGGLE(toggle)		((toggle)<<7)
 461#define	 CFG_DMA_FTOGGLE_MASK			0x00000080
 462#define	 CFG_DMA_HSMOOTH(smooth)		((smooth)<<6)
 463#define	 CFG_DMA_HSMOOTH_MASK			0x00000040
 464#define	 CFG_DMA_TSTMODE(test)			((test)<<5)
 465#define	 CFG_DMA_TSTMODE_MASK			0x00000020
 466#define	 CFG_DMA_SWAPRB(swap)			((swap)<<4)
 467#define	 CFG_DMA_SWAPRB_MASK			0x00000010
 468#define	 CFG_DMA_SWAPUV(swap)			((swap)<<3)
 469#define	 CFG_DMA_SWAPUV_MASK			0x00000008
 470#define	 CFG_DMA_SWAPYU(swap)			((swap)<<2)
 471#define	 CFG_DMA_SWAPYU_MASK			0x00000004
 472#define	 CFG_DMA_SWAP_MASK			0x0000001C
 473#define	 CFG_YUV2RGB_DMA(cvrt)			((cvrt)<<1)
 474#define	 CFG_YUV2RGB_DMA_MASK			0x00000002
 475#define	 CFG_DMA_ENA(video)			(video)
 476#define	 CFG_DMA_ENA_MASK			0x00000001
 477#define dma0_vid_masks	(CFG_DMAFORMAT_MASK | CFG_DMA_FTOGGLE_MASK | \
 478	CFG_DMA_HSMOOTH_MASK | CFG_DMA_TSTMODE_MASK | CFG_DMA_SWAP_MASK | \
 479	CFG_YUV2RGB_DMA_MASK | CFG_DMA_ENA_MASK)
 480#define dma_palette(val)		((val ? 1 : 0) << 28)
 481#define dma_fmt(vid, val)		((val & 0xf) << ((vid) ? 20 : 16))
 482#define dma_swaprb(vid, val)		((val ? 1 : 0) << ((vid) ? 4 : 12))
 483#define dma_swapuv(vid, val)		((val ? 1 : 0) << ((vid) ? 3 : 11))
 484#define dma_swapyuv(vid, val)		((val ? 1 : 0) << ((vid) ? 2 : 10))
 485#define dma_csc(vid, val)		((val ? 1 : 0) << ((vid) ? 1 : 9))
 486#define dma_hsmooth(vid, val)		((val ? 1 : 0) << ((vid) ? 6 : 14))
 487#define dma_mask(vid)	(dma_palette(1) | dma_fmt(vid, 0xf) | dma_csc(vid, 1) \
 488	| dma_swaprb(vid, 1) | dma_swapuv(vid, 1) | dma_swapyuv(vid, 1))
 489
 490/* DMA Control 1 Register */
 491#define LCD_SPU_DMA_CTRL1			0x0194
 492#define	 CFG_FRAME_TRIG(trig)			((trig)<<31)
 493#define	 CFG_FRAME_TRIG_MASK			0x80000000
 494#define	 CFG_VSYNC_TRIG(trig)			((trig)<<28)
 495#define	 CFG_VSYNC_TRIG_MASK			0x70000000
 496#define	 CFG_VSYNC_INV(inv)			((inv)<<27)
 497#define	 CFG_VSYNC_INV_MASK			0x08000000
 498#define	 CFG_COLOR_KEY_MODE(cmode)		((cmode)<<24)
 499#define	 CFG_COLOR_KEY_MASK			0x07000000
 500#define	 CFG_CARRY(carry)			((carry)<<23)
 501#define	 CFG_CARRY_MASK				0x00800000
 502#define	 CFG_LNBUF_ENA(lnbuf)			((lnbuf)<<22)
 503#define	 CFG_LNBUF_ENA_MASK			0x00400000
 504#define	 CFG_GATED_ENA(gated)			((gated)<<21)
 505#define	 CFG_GATED_ENA_MASK			0x00200000
 506#define	 CFG_PWRDN_ENA(power)			((power)<<20)
 507#define	 CFG_PWRDN_ENA_MASK			0x00100000
 508#define	 CFG_DSCALE(dscale)			((dscale)<<18)
 509#define	 CFG_DSCALE_MASK			0x000C0000
 510#define	 CFG_ALPHA_MODE(amode)			((amode)<<16)
 511#define	 CFG_ALPHA_MODE_MASK			0x00030000
 512#define	 CFG_ALPHA(alpha)			((alpha)<<8)
 513#define	 CFG_ALPHA_MASK				0x0000FF00
 514#define	 CFG_PXLCMD(pxlcmd)			(pxlcmd)
 515#define	 CFG_PXLCMD_MASK			0x000000FF
 516
 517/* SRAM Control Register */
 518#define LCD_SPU_SRAM_CTRL			0x0198
 519#define	 CFG_SRAM_INIT_WR_RD(mode)		((mode)<<14)
 520#define	 CFG_SRAM_INIT_WR_RD_MASK		0x0000C000
 521#define	 CFG_SRAM_ADDR_LCDID(id)		((id)<<8)
 522#define	 CFG_SRAM_ADDR_LCDID_MASK		0x00000F00
 523#define	 CFG_SRAM_ADDR(addr)			(addr)
 524#define	 CFG_SRAM_ADDR_MASK			0x000000FF
 525
 526/* SRAM Write Data Register */
 527#define LCD_SPU_SRAM_WRDAT			0x019C
 528
 529/* SRAM RTC/WTC Control Register */
 530#define LCD_SPU_SRAM_PARA0			0x01A0
 531
 532/* SRAM Power Down Control Register */
 533#define LCD_SPU_SRAM_PARA1			0x01A4
 534#define	 CFG_CSB_256x32(hwc)			((hwc)<<15)	/* HWC */
 535#define	 CFG_CSB_256x32_MASK			0x00008000
 536#define	 CFG_CSB_256x24(palette)		((palette)<<14)	/* Palette */
 537#define	 CFG_CSB_256x24_MASK			0x00004000
 538#define	 CFG_CSB_256x8(gamma)			((gamma)<<13)	/* Gamma */
 539#define	 CFG_CSB_256x8_MASK			0x00002000
 540#define	 CFG_PDWN256x32(pdwn)			((pdwn)<<7)	/* HWC */
 541#define	 CFG_PDWN256x32_MASK			0x00000080
 542#define	 CFG_PDWN256x24(pdwn)			((pdwn)<<6)	/* Palette */
 543#define	 CFG_PDWN256x24_MASK			0x00000040
 544#define	 CFG_PDWN256x8(pdwn)			((pdwn)<<5)	/* Gamma */
 545#define	 CFG_PDWN256x8_MASK			0x00000020
 546#define	 CFG_PDWN32x32(pdwn)			((pdwn)<<3)
 547#define	 CFG_PDWN32x32_MASK			0x00000008
 548#define	 CFG_PDWN16x66(pdwn)			((pdwn)<<2)
 549#define	 CFG_PDWN16x66_MASK			0x00000004
 550#define	 CFG_PDWN32x66(pdwn)			((pdwn)<<1)
 551#define	 CFG_PDWN32x66_MASK			0x00000002
 552#define	 CFG_PDWN64x66(pdwn)			(pdwn)
 553#define	 CFG_PDWN64x66_MASK			0x00000001
 554
 555/* Smart or Dumb Panel Clock Divider */
 556#define LCD_CFG_SCLK_DIV			0x01A8
 557#define	 SCLK_SRC_SEL(src)		((src)<<31)
 558#define	 SCLK_SRC_SEL_MASK		0x80000000
 559#define  SCLK_DISABLE				(1<<28)
 560#define	 CLK_FRACDIV(frac)			((frac)<<16)
 561#define	 CLK_FRACDIV_MASK			0x0FFF0000
 562#define	 DSI1_BITCLK_DIV(div)			(div<<8)
 563#define	 DSI1_BITCLK_DIV_MASK			0x00000F00
 564#define	 CLK_INT_DIV(div)			(div)
 565#define	 CLK_INT_DIV_MASK			0x000000FF
 566
 567/* Video Contrast Register */
 568#define LCD_SPU_CONTRAST			0x01AC
 569#define	 CFG_BRIGHTNESS(bright)			((bright)<<16)
 570#define	 CFG_BRIGHTNESS_MASK			0xFFFF0000
 571#define	 CFG_CONTRAST(contrast)			(contrast)
 572#define	 CFG_CONTRAST_MASK			0x0000FFFF
 573
 574/* Video Saturation Register */
 575#define LCD_SPU_SATURATION			0x01B0
 576#define	 CFG_C_MULTS(mult)			((mult)<<16)
 577#define	 CFG_C_MULTS_MASK			0xFFFF0000
 578#define	 CFG_SATURATION(sat)			(sat)
 579#define	 CFG_SATURATION_MASK			0x0000FFFF
 580
 581/* Video Hue Adjust Register */
 582#define LCD_SPU_CBSH_HUE			0x01B4
 583#define	 CFG_SIN0(sin0)				((sin0)<<16)
 584#define	 CFG_SIN0_MASK				0xFFFF0000
 585#define	 CFG_COS0(con0)				(con0)
 586#define	 CFG_COS0_MASK				0x0000FFFF
 587
 588/* Dump LCD Panel Control Register */
 589#define LCD_SPU_DUMB_CTRL			0x01B8
 590#define	 CFG_DUMBMODE(mode)			((mode)<<28)
 591#define	 CFG_DUMBMODE_MASK			0xF0000000
 592#define	 CFG_INTFRBSWAP(mode)			((mode)<<24)
 593#define	 CFG_INTFRBSWAP_MASK			0x0F000000
 594#define	 CFG_LCDGPIO_O(data)			((data)<<20)
 595#define	 CFG_LCDGPIO_O_MASK			0x0FF00000
 596#define	 CFG_LCDGPIO_ENA(gpio)			((gpio)<<12)
 597#define	 CFG_LCDGPIO_ENA_MASK			0x000FF000
 598#define	 CFG_BIAS_OUT(bias)			((bias)<<8)
 599#define	 CFG_BIAS_OUT_MASK			0x00000100
 600#define	 CFG_REVERSE_RGB(RGB)			((RGB)<<7)
 601#define	 CFG_REVERSE_RGB_MASK			0x00000080
 602#define	 CFG_INV_COMPBLANK(blank)		((blank)<<6)
 603#define	 CFG_INV_COMPBLANK_MASK			0x00000040
 604#define	 CFG_INV_COMPSYNC(sync)			((sync)<<5)
 605#define	 CFG_INV_COMPSYNC_MASK			0x00000020
 606#define	 CFG_INV_HENA(hena)			((hena)<<4)
 607#define	 CFG_INV_HENA_MASK			0x00000010
 608#define	 CFG_INV_VSYNC(vsync)			((vsync)<<3)
 609#define	 CFG_INV_VSYNC_MASK			0x00000008
 610#define	 CFG_INV_HSYNC(hsync)			((hsync)<<2)
 611#define	 CFG_INV_HSYNC_MASK			0x00000004
 612#define	 CFG_INV_PCLK(pclk)			((pclk)<<1)
 613#define	 CFG_INV_PCLK_MASK			0x00000002
 614#define	 CFG_DUMB_ENA(dumb)			(dumb)
 615#define	 CFG_DUMB_ENA_MASK			0x00000001
 616
 617/* LCD I/O Pads Control Register */
 618#define SPU_IOPAD_CONTROL			0x01BC
 619#define	 CFG_GRA_VM_ENA(vm)			((vm)<<15)
 620#define	 CFG_GRA_VM_ENA_MASK			0x00008000
 621#define	 CFG_DMA_VM_ENA(vm)			((vm)<<13)
 622#define	 CFG_DMA_VM_ENA_MASK			0x00002000
 623#define	 CFG_CMD_VM_ENA(vm)			((vm)<<12)
 624#define	 CFG_CMD_VM_ENA_MASK			0x00001000
 625#define	 CFG_CSC(csc)				((csc)<<8)
 626#define	 CFG_CSC_MASK				0x00000300
 627#define	 CFG_BOUNDARY(size)			((size)<<5)
 628#define	 CFG_BOUNDARY_MASK			0x00000020
 629#define	 CFG_BURST(len)				((len)<<4)
 630#define	 CFG_BURST_MASK				0x00000010
 631#define	 CFG_IOPADMODE(iopad)			(iopad)
 632#define	 CFG_IOPADMODE_MASK			0x0000000F
 633
 634/* LCD Interrupt Control Register */
 635#define SPU_IRQ_ENA				0x01C0
 636#define	 DMA_FRAME_IRQ0_ENA(irq)		((irq)<<31)
 637#define	 DMA_FRAME_IRQ0_ENA_MASK		0x80000000
 638#define	 DMA_FRAME_IRQ1_ENA(irq)		((irq)<<30)
 639#define	 DMA_FRAME_IRQ1_ENA_MASK		0x40000000
 640#define	 DMA_FF_UNDERFLOW_ENA(ff)		((ff)<<29)
 641#define	 DMA_FF_UNDERFLOW_ENA_MASK		0x20000000
 642#define	 AXI_BUS_ERROR_IRQ_ENA(irq)		((irq)<<28)
 643#define	 AXI_BUS_ERROR_IRQ_ENA_MASK		0x10000000
 644#define	 GRA_FRAME_IRQ0_ENA(irq)		((irq)<<27)
 645#define	 GRA_FRAME_IRQ0_ENA_MASK		0x08000000
 646#define	 GRA_FRAME_IRQ1_ENA(irq)		((irq)<<26)
 647#define	 GRA_FRAME_IRQ1_ENA_MASK		0x04000000
 648#define	 GRA_FF_UNDERFLOW_ENA(ff)		((ff)<<25)
 649#define	 GRA_FF_UNDERFLOW_ENA_MASK		0x02000000
 650#define	 VSYNC_IRQ_ENA(vsync_irq)		((vsync_irq)<<23)
 651#define	 VSYNC_IRQ_ENA_MASK			0x00800000
 652#define	 DUMB_FRAMEDONE_ENA(fdone)		((fdone)<<22)
 653#define	 DUMB_FRAMEDONE_ENA_MASK		0x00400000
 654#define	 TWC_FRAMEDONE_ENA(fdone)		((fdone)<<21)
 655#define	 TWC_FRAMEDONE_ENA_MASK			0x00200000
 656#define	 HWC_FRAMEDONE_ENA(fdone)		((fdone)<<20)
 657#define	 HWC_FRAMEDONE_ENA_MASK			0x00100000
 658#define	 SLV_IRQ_ENA(irq)			((irq)<<19)
 659#define	 SLV_IRQ_ENA_MASK			0x00080000
 660#define	 SPI_IRQ_ENA(irq)			((irq)<<18)
 661#define	 SPI_IRQ_ENA_MASK			0x00040000
 662#define	 PWRDN_IRQ_ENA(irq)			((irq)<<17)
 663#define	 PWRDN_IRQ_ENA_MASK			0x00020000
 664#define	 AXI_LATENCY_TOO_LONG_IRQ_ENA(irq)	((irq)<<16)
 665#define  AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK	0x00010000
 666#define	 CLEAN_SPU_IRQ_ISR(irq)			(irq)
 667#define	 CLEAN_SPU_IRQ_ISR_MASK			0x0000FFFF
 668#define	 TV_DMA_FRAME_IRQ0_ENA(irq)		((irq)<<15)
 669#define	 TV_DMA_FRAME_IRQ0_ENA_MASK		0x00008000
 670#define	 TV_DMA_FRAME_IRQ1_ENA(irq)		((irq)<<14)
 671#define	 TV_DMA_FRAME_IRQ1_ENA_MASK		0x00004000
 672#define	 TV_DMA_FF_UNDERFLOW_ENA(unerrun)	((unerrun)<<13)
 673#define	 TV_DMA_FF_UNDERFLOW_ENA_MASK		0x00002000
 674#define	 TVSYNC_IRQ_ENA(irq)			((irq)<<12)
 675#define	 TVSYNC_IRQ_ENA_MASK			0x00001000
 676#define	 TV_FRAME_IRQ0_ENA(irq)			((irq)<<11)
 677#define	 TV_FRAME_IRQ0_ENA_MASK			0x00000800
 678#define	 TV_FRAME_IRQ1_ENA(irq)			((irq)<<10)
 679#define	 TV_FRAME_IRQ1_ENA_MASK			0x00000400
 680#define	 TV_GRA_FF_UNDERFLOW_ENA(unerrun)	((unerrun)<<9)
 681#define	 TV_GRA_FF_UNDERFLOW_ENA_MASK		0x00000200
 682#define	 TV_FRAMEDONE_ENA(irq)			((irq)<<8)
 683#define	 TV_FRAMEDONE_ENA_MASK			0x00000100
 684
 685/* FIXME - JUST GUESS */
 686#define	 PN2_DMA_FRAME_IRQ0_ENA(irq)		((irq)<<7)
 687#define	 PN2_DMA_FRAME_IRQ0_ENA_MASK		0x00000080
 688#define	 PN2_DMA_FRAME_IRQ1_ENA(irq)		((irq)<<6)
 689#define	 PN2_DMA_FRAME_IRQ1_ENA_MASK		0x00000040
 690#define	 PN2_DMA_FF_UNDERFLOW_ENA(ff)		((ff)<<5)
 691#define	 PN2_DMA_FF_UNDERFLOW_ENA_MASK		0x00000020
 692#define	 PN2_GRA_FRAME_IRQ0_ENA(irq)		((irq)<<3)
 693#define	 PN2_GRA_FRAME_IRQ0_ENA_MASK		0x00000008
 694#define	 PN2_GRA_FRAME_IRQ1_ENA(irq)		((irq)<<2)
 695#define	 PN2_GRA_FRAME_IRQ1_ENA_MASK		0x04000004
 696#define	 PN2_GRA_FF_UNDERFLOW_ENA(ff)		((ff)<<1)
 697#define	 PN2_GRA_FF_UNDERFLOW_ENA_MASK		0x00000002
 698#define	 PN2_VSYNC_IRQ_ENA(irq)			((irq)<<0)
 699#define	 PN2_SYNC_IRQ_ENA_MASK			0x00000001
 700
 701#define gf0_imask(id)	((id) ? (((id) & 1) ? TV_FRAME_IRQ0_ENA_MASK \
 702		: PN2_GRA_FRAME_IRQ0_ENA_MASK) : GRA_FRAME_IRQ0_ENA_MASK)
 703#define gf1_imask(id)	((id) ? (((id) & 1) ? TV_FRAME_IRQ1_ENA_MASK \
 704		: PN2_GRA_FRAME_IRQ1_ENA_MASK) : GRA_FRAME_IRQ1_ENA_MASK)
 705#define vsync_imask(id)	((id) ? (((id) & 1) ? TVSYNC_IRQ_ENA_MASK \
 706		: PN2_SYNC_IRQ_ENA_MASK) : VSYNC_IRQ_ENA_MASK)
 707#define vsync_imasks	(vsync_imask(0) | vsync_imask(1))
 708
 709#define display_done_imask(id)	((id) ? (((id) & 1) ? TV_FRAMEDONE_ENA_MASK\
 710	: (PN2_DMA_FRAME_IRQ0_ENA_MASK | PN2_DMA_FRAME_IRQ1_ENA_MASK))\
 711	: DUMB_FRAMEDONE_ENA_MASK)
 712
 713#define display_done_imasks	(display_done_imask(0) | display_done_imask(1))
 714
 715#define vf0_imask(id)	((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ0_ENA_MASK \
 716		: PN2_DMA_FRAME_IRQ0_ENA_MASK) : DMA_FRAME_IRQ0_ENA_MASK)
 717#define vf1_imask(id)	((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ1_ENA_MASK \
 718		: PN2_DMA_FRAME_IRQ1_ENA_MASK) : DMA_FRAME_IRQ1_ENA_MASK)
 719
 720#define gfx_imasks	(gf0_imask(0) | gf1_imask(0) | gf0_imask(1) | \
 721		gf1_imask(1))
 722#define vid_imasks	(vf0_imask(0) | vf1_imask(0) | vf0_imask(1) | \
 723		vf1_imask(1))
 724#define vid_imask(id)	(display_done_imask(id))
 725
 726#define pn1_imasks	(gf0_imask(0) | gf1_imask(0) | vsync_imask(0) | \
 727		display_done_imask(0) | vf0_imask(0) | vf1_imask(0))
 728#define tv_imasks	(gf0_imask(1) | gf1_imask(1) | vsync_imask(1) | \
 729		display_done_imask(1) | vf0_imask(1) | vf1_imask(1))
 730#define path_imasks(id)	((id) ? (tv_imasks) : (pn1_imasks))
 731
 732/* error indications */
 733#define vid_udflow_imask(id)	((id) ? (((id) & 1) ? \
 734	(TV_DMA_FF_UNDERFLOW_ENA_MASK) : (PN2_DMA_FF_UNDERFLOW_ENA_MASK)) : \
 735	(DMA_FF_UNDERFLOW_ENA_MASK))
 736#define gfx_udflow_imask(id)	((id) ? (((id) & 1) ? \
 737	(TV_GRA_FF_UNDERFLOW_ENA_MASK) : (PN2_GRA_FF_UNDERFLOW_ENA_MASK)) : \
 738	(GRA_FF_UNDERFLOW_ENA_MASK))
 739
 740#define err_imask(id) (vid_udflow_imask(id) | gfx_udflow_imask(id) | \
 741	AXI_BUS_ERROR_IRQ_ENA_MASK | AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK)
 742#define err_imasks (err_imask(0) | err_imask(1) | err_imask(2))
 743/* LCD Interrupt Status Register */
 744#define SPU_IRQ_ISR			0x01C4
 745#define	 DMA_FRAME_IRQ0(irq)		((irq)<<31)
 746#define	 DMA_FRAME_IRQ0_MASK		0x80000000
 747#define	 DMA_FRAME_IRQ1(irq)		((irq)<<30)
 748#define	 DMA_FRAME_IRQ1_MASK		0x40000000
 749#define	 DMA_FF_UNDERFLOW(ff)		((ff)<<29)
 750#define	 DMA_FF_UNDERFLOW_MASK		0x20000000
 751#define	 AXI_BUS_ERROR_IRQ(irq)		((irq)<<28)
 752#define	 AXI_BUS_ERROR_IRQ_MASK		0x10000000
 753#define	 GRA_FRAME_IRQ0(irq)		((irq)<<27)
 754#define	 GRA_FRAME_IRQ0_MASK		0x08000000
 755#define	 GRA_FRAME_IRQ1(irq)		((irq)<<26)
 756#define	 GRA_FRAME_IRQ1_MASK		0x04000000
 757#define	 GRA_FF_UNDERFLOW(ff)		((ff)<<25)
 758#define	 GRA_FF_UNDERFLOW_MASK		0x02000000
 759#define	 VSYNC_IRQ(vsync_irq)		((vsync_irq)<<23)
 760#define	 VSYNC_IRQ_MASK			0x00800000
 761#define	 DUMB_FRAMEDONE(fdone)		((fdone)<<22)
 762#define	 DUMB_FRAMEDONE_MASK		0x00400000
 763#define	 TWC_FRAMEDONE(fdone)		((fdone)<<21)
 764#define	 TWC_FRAMEDONE_MASK		0x00200000
 765#define	 HWC_FRAMEDONE(fdone)		((fdone)<<20)
 766#define	 HWC_FRAMEDONE_MASK		0x00100000
 767#define	 SLV_IRQ(irq)			((irq)<<19)
 768#define	 SLV_IRQ_MASK			0x00080000
 769#define	 SPI_IRQ(irq)			((irq)<<18)
 770#define	 SPI_IRQ_MASK			0x00040000
 771#define	 PWRDN_IRQ(irq)			((irq)<<17)
 772#define	 PWRDN_IRQ_MASK			0x00020000
 773#define	 AXI_LATENCY_TOO_LONGR_IRQ(irq)	((irq)<<16)
 774#define	 AXI_LATENCY_TOO_LONGR_IRQ_MASK	0x00010000
 775#define	 TV_DMA_FRAME_IRQ0(irq)		((irq)<<15)
 776#define	 TV_DMA_FRAME_IRQ0_MASK		0x00008000
 777#define	 TV_DMA_FRAME_IRQ1(irq)		((irq)<<14)
 778#define	 TV_DMA_FRAME_IRQ1_MASK		0x00004000
 779#define	 TV_DMA_FF_UNDERFLOW(unerrun)	((unerrun)<<13)
 780#define	 TV_DMA_FF_UNDERFLOW_MASK	0x00002000
 781#define	 TVSYNC_IRQ(irq)		((irq)<<12)
 782#define	 TVSYNC_IRQ_MASK		0x00001000
 783#define	 TV_FRAME_IRQ0(irq)		((irq)<<11)
 784#define	 TV_FRAME_IRQ0_MASK		0x00000800
 785#define	 TV_FRAME_IRQ1(irq)		((irq)<<10)
 786#define	 TV_FRAME_IRQ1_MASK		0x00000400
 787#define	 TV_GRA_FF_UNDERFLOW(unerrun)	((unerrun)<<9)
 788#define	 TV_GRA_FF_UNDERFLOW_MASK	0x00000200
 789#define	 PN2_DMA_FRAME_IRQ0(irq)	((irq)<<7)
 790#define	 PN2_DMA_FRAME_IRQ0_MASK	0x00000080
 791#define	 PN2_DMA_FRAME_IRQ1(irq)	((irq)<<6)
 792#define	 PN2_DMA_FRAME_IRQ1_MASK	0x00000040
 793#define	 PN2_DMA_FF_UNDERFLOW(ff)	((ff)<<5)
 794#define	 PN2_DMA_FF_UNDERFLOW_MASK	0x00000020
 795#define	 PN2_GRA_FRAME_IRQ0(irq)	((irq)<<3)
 796#define	 PN2_GRA_FRAME_IRQ0_MASK	0x00000008
 797#define	 PN2_GRA_FRAME_IRQ1(irq)	((irq)<<2)
 798#define	 PN2_GRA_FRAME_IRQ1_MASK	0x04000004
 799#define	 PN2_GRA_FF_UNDERFLOW(ff)	((ff)<<1)
 800#define	 PN2_GRA_FF_UNDERFLOW_MASK	0x00000002
 801#define	 PN2_VSYNC_IRQ(irq)		((irq)<<0)
 802#define	 PN2_SYNC_IRQ_MASK		0x00000001
 803
 804/* LCD FIFO Depth register */
 805#define LCD_FIFO_DEPTH			0x01c8
 806#define	 VIDEO_FIFO(fi)			((fi) << 0)
 807#define	 VIDEO_FIFO_MASK		0x00000003
 808#define	 GRAPHIC_FIFO(fi)		((fi) << 2)
 809#define	 GRAPHIC_FIFO_MASK		0x0000000c
 810
 811/* read-only */
 812#define	 DMA_FRAME_IRQ0_LEVEL_MASK		0x00008000
 813#define	 DMA_FRAME_IRQ1_LEVEL_MASK		0x00004000
 814#define	 DMA_FRAME_CNT_ISR_MASK			0x00003000
 815#define	 GRA_FRAME_IRQ0_LEVEL_MASK		0x00000800
 816#define	 GRA_FRAME_IRQ1_LEVEL_MASK		0x00000400
 817#define	 GRA_FRAME_CNT_ISR_MASK			0x00000300
 818#define	 VSYNC_IRQ_LEVEL_MASK			0x00000080
 819#define	 DUMB_FRAMEDONE_LEVEL_MASK		0x00000040
 820#define	 TWC_FRAMEDONE_LEVEL_MASK		0x00000020
 821#define	 HWC_FRAMEDONE_LEVEL_MASK		0x00000010
 822#define	 SLV_FF_EMPTY_MASK			0x00000008
 823#define	 DMA_FF_ALLEMPTY_MASK			0x00000004
 824#define	 GRA_FF_ALLEMPTY_MASK			0x00000002
 825#define	 PWRDN_IRQ_LEVEL_MASK			0x00000001
 826
 827/* 32 bit LCD Interrupt Reset Status*/
 828#define SPU_IRQ_RSR				(0x01C8)
 829/* 32 bit Panel Path Graphic Partial Display Horizontal Control Register*/
 830#define LCD_GRA_CUTHPXL				(0x01CC)
 831/* 32 bit Panel Path Graphic Partial Display Vertical Control Register*/
 832#define LCD_GRA_CUTVLN				(0x01D0)
 833/* 32 bit TV Path Graphic Partial Display	  Horizontal Control Register*/
 834#define LCD_TVG_CUTHPXL				(0x01D4)
 835/* 32 bit TV Path Graphic Partial Display Vertical Control Register*/
 836#define LCD_TVG_CUTVLN				(0x01D8)
 837/* 32 bit LCD Global Control Register*/
 838#define LCD_TOP_CTRL				(0x01DC)
 839/* 32 bit LCD SQU Line Buffer Control Register 1*/
 840#define LCD_SQULN1_CTRL				(0x01E0)
 841/* 32 bit LCD SQU Line Buffer Control Register 2*/
 842#define LCD_SQULN2_CTRL				(0x01E4)
 843#define squln_ctrl(id)	((id) ? (((id) & 1) ? LCD_SQULN2_CTRL : \
 844			LCD_PN2_SQULN1_CTRL) : LCD_SQULN1_CTRL)
 845
 846/* 32 bit LCD Mixed Overlay Control Register */
 847#define LCD_AFA_ALL2ONE				(0x01E8)
 848
 849#define LCD_PN2_SCLK_DIV			(0x01EC)
 850#define LCD_PN2_TCLK_DIV			(0x01F0)
 851#define LCD_LVDS_SCLK_DIV_WR			(0x01F4)
 852#define LCD_LVDS_SCLK_DIV_RD			(0x01FC)
 853#define PN2_LCD_DMA_START_ADDR_Y0		(0x0200)
 854#define PN2_LCD_DMA_START_ADDR_U0		(0x0204)
 855#define PN2_LCD_DMA_START_ADDR_V0		(0x0208)
 856#define PN2_LCD_DMA_START_ADDR_C0		(0x020C)
 857#define PN2_LCD_DMA_START_ADDR_Y1		(0x0210)
 858#define PN2_LCD_DMA_START_ADDR_U1		(0x0214)
 859#define PN2_LCD_DMA_START_ADDR_V1		(0x0218)
 860#define PN2_LCD_DMA_START_ADDR_C1		(0x021C)
 861#define PN2_LCD_DMA_PITCH_YC			(0x0220)
 862#define PN2_LCD_DMA_PITCH_UV			(0x0224)
 863#define PN2_LCD_DMA_OVSA_HPXL_VLN		(0x0228)
 864#define PN2_LCD_DMA_HPXL_VLN			(0x022C)
 865#define PN2_LCD_DMAZM_HPXL_VLN			(0x0230)
 866#define PN2_LCD_GRA_START_ADDR0			(0x0234)
 867#define PN2_LCD_GRA_START_ADDR1			(0x0238)
 868#define PN2_LCD_GRA_PITCH			(0x023C)
 869#define PN2_LCD_GRA_OVSA_HPXL_VLN		(0x0240)
 870#define PN2_LCD_GRA_HPXL_VLN			(0x0244)
 871#define PN2_LCD_GRAZM_HPXL_VLN			(0x0248)
 872#define PN2_LCD_HWC_OVSA_HPXL_VLN		(0x024C)
 873#define PN2_LCD_HWC_HPXL_VLN			(0x0250)
 874#define LCD_PN2_V_H_TOTAL			(0x0254)
 875#define LCD_PN2_V_H_ACTIVE			(0x0258)
 876#define LCD_PN2_H_PORCH				(0x025C)
 877#define LCD_PN2_V_PORCH				(0x0260)
 878#define LCD_PN2_BLANKCOLOR			(0x0264)
 879#define LCD_PN2_ALPHA_COLOR1			(0x0268)
 880#define LCD_PN2_ALPHA_COLOR2			(0x026C)
 881#define LCD_PN2_COLORKEY_Y			(0x0270)
 882#define LCD_PN2_COLORKEY_U			(0x0274)
 883#define LCD_PN2_COLORKEY_V			(0x0278)
 884#define LCD_PN2_SEPXLCNT			(0x027C)
 885#define LCD_TV_V_H_TOTAL_FLD			(0x0280)
 886#define LCD_TV_V_PORCH_FLD			(0x0284)
 887#define LCD_TV_SEPXLCNT_FLD			(0x0288)
 888
 889#define LCD_2ND_ALPHA				(0x0294)
 890#define LCD_PN2_CONTRAST			(0x0298)
 891#define LCD_PN2_SATURATION			(0x029c)
 892#define LCD_PN2_CBSH_HUE			(0x02a0)
 893#define LCD_TIMING_EXT				(0x02C0)
 894#define LCD_PN2_LAYER_ALPHA_SEL1		(0x02c4)
 895#define LCD_PN2_CTRL0				(0x02C8)
 896#define TV_LAYER_ALPHA_SEL1			(0x02cc)
 897#define LCD_SMPN2_CTRL				(0x02D0)
 898#define LCD_IO_OVERL_MAP_CTRL			(0x02D4)
 899#define LCD_DUMB2_CTRL				(0x02d8)
 900#define LCD_PN2_CTRL1				(0x02DC)
 901#define PN2_IOPAD_CONTROL			(0x02E0)
 902#define LCD_PN2_SQULN1_CTRL			(0x02E4)
 903#define PN2_LCD_GRA_CUTHPXL			(0x02e8)
 904#define PN2_LCD_GRA_CUTVLN			(0x02ec)
 905#define LCD_PN2_SQULN2_CTRL			(0x02F0)
 906#define ALL_LAYER_ALPHA_SEL			(0x02F4)
 907
 908#define TIMING_MASTER_CONTROL			(0x02F8)
 909#define MASTER_ENH(id)				(1 << (id))
 910#define MASTER_ENV(id)				(1 << ((id) + 4))
 911
 912#define DSI_START_SEL_SHIFT(id)		(((id) << 1) + 8)
 913#define timing_master_config(path, dsi_id, lcd_id) \
 914	(MASTER_ENH(path) | MASTER_ENV(path) | \
 915	(((lcd_id) + ((dsi_id) << 1)) << DSI_START_SEL_SHIFT(path)))
 916
 917#define LCD_2ND_BLD_CTL				(0x02Fc)
 918#define LVDS_SRC_MASK				(3 << 30)
 919#define LVDS_SRC_SHIFT				(30)
 920#define LVDS_FMT_MASK				(1 << 28)
 921#define LVDS_FMT_SHIFT				(28)
 922
 923#define CLK_SCLK	(1 << 0)
 924#define CLK_LVDS_RD	(1 << 1)
 925#define CLK_LVDS_WR	(1 << 2)
 926
 927#define gra_partdisp_ctrl_hor(id)	((id) ? (((id) & 1) ? \
 928	LCD_TVG_CUTHPXL : PN2_LCD_GRA_CUTHPXL) : LCD_GRA_CUTHPXL)
 929#define gra_partdisp_ctrl_ver(id)	((id) ? (((id) & 1) ? \
 930	LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN)
 931
 932/*
 933 * defined for Configure Dumb Mode
 934 * defined for Configure Dumb Mode
 935 * DUMB LCD Panel bit[31:28]
 936 */
 937#define DUMB16_RGB565_0		0x0
 938#define DUMB16_RGB565_1		0x1
 939#define DUMB18_RGB666_0		0x2
 940#define DUMB18_RGB666_1		0x3
 941#define DUMB12_RGB444_0		0x4
 942#define DUMB12_RGB444_1		0x5
 943#define DUMB24_RGB888_0		0x6
 944#define DUMB_BLANK		0x7
 945
 946/*
 947 * defined for Configure I/O Pin Allocation Mode
 948 * LCD LCD I/O Pads control register bit[3:0]
 949 */
 950#define IOPAD_DUMB24		0x0
 951#define IOPAD_DUMB18SPI		0x1
 952#define IOPAD_DUMB18GPIO	0x2
 953#define IOPAD_DUMB16SPI		0x3
 954#define IOPAD_DUMB16GPIO	0x4
 955#define IOPAD_DUMB12		0x5
 956#define IOPAD_SMART18SPI	0x6
 957#define IOPAD_SMART16SPI	0x7
 958#define IOPAD_SMART8BOTH	0x8
 959#define IOPAD_DUMB18_SMART8	0x9
 960#define IOPAD_DUMB16_SMART8SPI	0xa
 961#define IOPAD_DUMB16_SMART8GPIO	0xb
 962#define IOPAD_DUMB16_DUMB16	0xc
 963#define IOPAD_SMART8_SMART8	0xc
 964
 965/*
 966 *defined for indicating boundary and cycle burst length
 967 */
 968#define  CFG_BOUNDARY_1KB			(1<<5)
 969#define  CFG_BOUNDARY_4KB			(0<<5)
 970#define	 CFG_CYC_BURST_LEN16			(1<<4)
 971#define	 CFG_CYC_BURST_LEN8			(0<<4)
 972
 973/* SRAM ID */
 974#define SRAMID_GAMMA_YR			0x0
 975#define SRAMID_GAMMA_UG			0x1
 976#define SRAMID_GAMMA_VB			0x2
 977#define SRAMID_PALATTE			0x3
 978#define SRAMID_HWC			0xf
 979
 980/* SRAM INIT Read/Write */
 981#define SRAMID_INIT_READ		0x0
 982#define SRAMID_INIT_WRITE		0x2
 983#define SRAMID_INIT_DEFAULT		0x3
 984
 985/*
 986 * defined VSYNC selection mode for DMA control 1 register
 987 * DMA1 bit[30:28]
 988 */
 989#define VMODE_SMPN			0x0
 990#define VMODE_SMPNIRQ			0x1
 991#define VMODE_DUMB			0x2
 992#define VMODE_IPE			0x3
 993#define VMODE_IRE			0x4
 994
 995/*
 996 * defined Configure Alpha and Alpha mode for DMA control 1 register
 997 * DMA1 bit[15:08](alpha) / bit[17:16](alpha mode)
 998 */
 999/* ALPHA mode */
1000#define MODE_ALPHA_DMA			0x0
1001#define MODE_ALPHA_GRA			0x1
1002#define MODE_ALPHA_CFG			0x2
1003
1004/* alpha value */
1005#define ALPHA_NOGRAPHIC			0xFF	  /* all video, no graphic */
1006#define ALPHA_NOVIDEO			0x00	  /* all graphic, no video */
1007#define ALPHA_GRAPHNVIDEO		0x0F	  /* Selects graphic & video */
1008
1009/*
1010 * defined Pixel Command for DMA control 1 register
1011 * DMA1 bit[07:00]
1012 */
1013#define PIXEL_CMD			0x81
1014
1015/* DSI */
1016/* DSI1 - 4 Lane Controller base */
1017#define DSI1_REGS_PHYSICAL_BASE		0xD420B800
1018/* DSI2 - 3 Lane Controller base */
1019#define DSI2_REGS_PHYSICAL_BASE		0xD420BA00
1020
1021/*	   DSI Controller Registers	   */
1022struct dsi_lcd_regs {
1023#define DSI_LCD1_CTRL_0  0x100   /* DSI Active Panel 1 Control register 0 */
1024#define DSI_LCD1_CTRL_1  0x104   /* DSI Active Panel 1 Control register 1 */
1025	u32 ctrl0;
1026	u32 ctrl1;
1027	u32 reserved1[2];
1028
1029#define DSI_LCD1_TIMING_0		0x110   /* Timing register 0 */
1030#define DSI_LCD1_TIMING_1		0x114   /* Timing register 1 */
1031#define DSI_LCD1_TIMING_2		0x118   /* Timing register 2 */
1032#define DSI_LCD1_TIMING_3		0x11C   /* Timing register 3 */
1033#define DSI_LCD1_WC_0			0x120   /* Word Count register 0 */
1034#define DSI_LCD1_WC_1			0x124   /* Word Count register 1 */
1035#define DSI_LCD1_WC_2			0x128	 /* Word Count register 2 */
1036	u32 timing0;
1037	u32 timing1;
1038	u32 timing2;
1039	u32 timing3;
1040	u32 wc0;
1041	u32 wc1;
1042	u32 wc2;
1043	u32 reserved2[1];
1044	u32 slot_cnt0;
1045	u32 slot_cnt1;
1046	u32 reserved3[2];
1047	u32 status_0;
1048	u32 status_1;
1049	u32 status_2;
1050	u32 status_3;
1051	u32 status_4;
1052};
1053
1054struct dsi_regs {
1055#define DSI_CTRL_0	  0x000   /* DSI control register 0 */
1056#define DSI_CTRL_1	  0x004   /* DSI control register 1 */
1057	u32 ctrl0;
1058	u32 ctrl1;
1059	u32 reserved1[2];
1060	u32 irq_status;
1061	u32 irq_mask;
1062	u32 reserved2[2];
1063
1064#define DSI_CPU_CMD_0   0x020   /* DSI CPU packet command register 0 */
1065#define DSI_CPU_CMD_1   0x024   /* DSU CPU Packet Command Register 1 */
1066#define DSI_CPU_CMD_3	0x02C   /* DSU CPU Packet Command Register 3 */
1067#define DSI_CPU_WDAT_0	0x030   /* DSI CUP */
1068	u32 cmd0;
1069	u32 cmd1;
1070	u32 cmd2;
1071	u32 cmd3;
1072	u32 dat0;
1073	u32 status0;
1074	u32 status1;
1075	u32 status2;
1076	u32 status3;
1077	u32 status4;
1078	u32 reserved3[2];
1079
1080	u32 smt_cmd;
1081	u32 smt_ctrl0;
1082	u32 smt_ctrl1;
1083	u32 reserved4[1];
1084
1085	u32 rx0_status;
1086
1087/* Rx Packet Header - data from slave device */
1088#define DSI_RX_PKT_HDR_0 0x064
1089	u32 rx0_header;
1090	u32 rx1_status;
1091	u32 rx1_header;
1092	u32 rx_ctrl;
1093	u32 rx_ctrl1;
1094	u32 rx2_status;
1095	u32 rx2_header;
1096	u32 reserved5[1];
1097
1098	u32 phy_ctrl1;
1099#define DSI_PHY_CTRL_2		0x088   /* DSI DPHI Control Register 2 */
1100#define DSI_PHY_CTRL_3		0x08C   /* DPHY Control Register 3 */
1101	u32 phy_ctrl2;
1102	u32 phy_ctrl3;
1103	u32 phy_status0;
1104	u32 phy_status1;
1105	u32 reserved6[5];
1106	u32 phy_status2;
1107
1108#define DSI_PHY_RCOMP_0		0x0B0   /* DPHY Rcomp Control Register */
1109	u32 phy_rcomp0;
1110	u32 reserved7[3];
1111#define DSI_PHY_TIME_0		0x0C0   /* DPHY Timing Control Register 0 */
1112#define DSI_PHY_TIME_1		0x0C4   /* DPHY Timing Control Register 1 */
1113#define DSI_PHY_TIME_2		0x0C8   /* DPHY Timing Control Register 2 */
1114#define DSI_PHY_TIME_3		0x0CC   /* DPHY Timing Control Register 3 */
1115#define DSI_PHY_TIME_4		0x0D0   /* DPHY Timing Control Register 4 */
1116#define DSI_PHY_TIME_5		0x0D4   /* DPHY Timing Control Register 5 */
1117	u32 phy_timing0;
1118	u32 phy_timing1;
1119	u32 phy_timing2;
1120	u32 phy_timing3;
1121	u32 phy_code_0;
1122	u32 phy_code_1;
1123	u32 reserved8[2];
1124	u32 mem_ctrl;
1125	u32 tx_timer;
1126	u32 rx_timer;
1127	u32 turn_timer;
1128	u32 reserved9[4];
1129
1130#define DSI_LCD1_CTRL_0  0x100   /* DSI Active Panel 1 Control register 0 */
1131#define DSI_LCD1_CTRL_1  0x104   /* DSI Active Panel 1 Control register 1 */
1132#define DSI_LCD1_TIMING_0		0x110   /* Timing register 0 */
1133#define DSI_LCD1_TIMING_1		0x114   /* Timing register 1 */
1134#define DSI_LCD1_TIMING_2		0x118   /* Timing register 2 */
1135#define DSI_LCD1_TIMING_3		0x11C   /* Timing register 3 */
1136#define DSI_LCD1_WC_0			0x120   /* Word Count register 0 */
1137#define DSI_LCD1_WC_1			0x124   /* Word Count register 1 */
1138#define DSI_LCD1_WC_2			0x128   /* Word Count register 2 */
1139	struct dsi_lcd_regs lcd1;
1140	u32 reserved10[11];
1141	struct dsi_lcd_regs lcd2;
1142};
1143
1144#define DSI_LCD2_CTRL_0  0x180   /* DSI Active Panel 2 Control register 0 */
1145#define DSI_LCD2_CTRL_1  0x184   /* DSI Active Panel 2 Control register 1 */
1146#define DSI_LCD2_TIMING_0		0x190   /* Timing register 0 */
1147#define DSI_LCD2_TIMING_1		0x194   /* Timing register 1 */
1148#define DSI_LCD2_TIMING_2		0x198   /* Timing register 2 */
1149#define DSI_LCD2_TIMING_3		0x19C   /* Timing register 3 */
1150#define DSI_LCD2_WC_0			0x1A0   /* Word Count register 0 */
1151#define DSI_LCD2_WC_1			0x1A4   /* Word Count register 1 */
1152#define DSI_LCD2_WC_2			0x1A8	 /* Word Count register 2 */
1153
1154/*	DSI_CTRL_0		0x0000	DSI Control Register 0 */
1155#define DSI_CTRL_0_CFG_SOFT_RST			(1<<31)
1156#define DSI_CTRL_0_CFG_SOFT_RST_REG		(1<<30)
1157#define DSI_CTRL_0_CFG_LCD1_TX_EN		(1<<8)
1158#define DSI_CTRL_0_CFG_LCD1_SLV			(1<<4)
1159#define DSI_CTRL_0_CFG_LCD1_EN			(1<<0)
1160
1161/*	DSI_CTRL_1		0x0004	DSI Control Register 1 */
1162#define DSI_CTRL_1_CFG_EOTP			(1<<8)
1163#define DSI_CTRL_1_CFG_RSVD			(2<<4)
1164#define DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK		(3<<2)
1165#define DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT	2
1166#define DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK		(3<<0)
1167#define DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT	0
1168
1169/*	DSI_LCD1_CTRL_1	0x0104	DSI Active Panel 1 Control Register 1 */
1170/* LCD 1 Vsync Reset Enable */
1171#define	DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN	(1<<31)
1172/* LCD 1 2K Pixel Buffer Mode Enable */
1173#define	DSI_LCD1_CTRL_1_CFG_L1_M2K_EN		(1<<30)
1174/*		Bit(s) DSI_LCD1_CTRL_1_RSRV_29_23 reserved */
1175/* Long Blanking Packet Enable */
1176#define	DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN	(1<<22)
1177/* Extra Long Blanking Packet Enable */
1178#define	DSI_LCD1_CTRL_1_CFG_L1_HEX_PKT_EN	(1<<21)
1179/* Front Porch Packet Enable */
1180#define	DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN	(1<<20)
1181/* hact Packet Enable */
1182#define	DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN	(1<<19)
1183/* Back Porch Packet Enable */
1184#define	DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN	(1<<18)
1185/* hse Packet Enable */
1186#define	DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN	(1<<17)
1187/* hsa Packet Enable */
1188#define	DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN	(1<<16)
1189/* All Item Enable after Pixel Data */
1190#define	DSI_LCD1_CTRL_1_CFG_L1_ALL_SLOT_EN	(1<<15)
1191/* Extra Long Packet Enable after Pixel Data */
1192#define	DSI_LCD1_CTRL_1_CFG_L1_HEX_SLOT_EN	(1<<14)
1193/*		Bit(s) DSI_LCD1_CTRL_1_RSRV_13_11 reserved */
1194/* Turn Around Bus at Last h Line */
1195#define	DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN	(1<<10)
1196/* Go to Low Power Every Frame */
1197#define	DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN	(1<<9)
1198/* Go to Low Power Every Line */
1199#define	DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN	(1<<8)
1200/*		Bit(s) DSI_LCD1_CTRL_1_RSRV_7_4 reserved */
1201/* DSI Transmission Mode for LCD 1 */
1202#define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT	2
1203#define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_MASK	(3<<2)
1204/* LCD 1 Input Data RGB Mode for LCD 1 */
1205#define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT	0
1206#define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_MASK	(3<<2)
1207
1208/*	DSI_PHY_CTRL_2		0x0088	DPHY Control Register 2 */
1209/*		Bit(s) DSI_PHY_CTRL_2_RSRV_31_12 reserved */
1210/* DPHY LP Receiver Enable */
1211#define	DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_MASK	(0xf<<8)
1212#define	DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_SHIFT	8
1213/* DPHY Data Lane Enable */
1214#define	DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_MASK		(0xf<<4)
1215#define	DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT		4
1216/* DPHY Bus Turn Around */
1217#define	DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_MASK		(0xf)
1218#define	DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_SHIFT		0
1219
1220/*	DSI_CPU_CMD_1		0x0024	DSI CPU Packet Command Register 1 */
1221/*		Bit(s) DSI_CPU_CMD_1_RSRV_31_24 reserved */
1222/* LPDT TX Enable */
1223#define	DSI_CPU_CMD_1_CFG_TXLP_LPDT_MASK		(0xf<<20)
1224#define	DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT		20
1225/* ULPS TX Enable */
1226#define	DSI_CPU_CMD_1_CFG_TXLP_ULPS_MASK		(0xf<<16)
1227#define	DSI_CPU_CMD_1_CFG_TXLP_ULPS_SHIFT		16
1228/* Low Power TX Trigger Code */
1229#define	DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_MASK	(0xffff)
1230#define	DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_SHIFT	0
1231
1232/*	DSI_PHY_TIME_0	0x00c0	DPHY Timing Control Register 0 */
1233/* Length of HS Exit Period in tx_clk_esc Cycles */
1234#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_MASK	(0xff<<24)
1235#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT	24
1236/* DPHY HS Trail Period Length */
1237#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_MASK	(0xff<<16)
1238#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT	16
1239/* DPHY HS Zero State Length */
1240#define	DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_MASK	(0xff<<8)
1241#define	DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT	8
1242/* DPHY HS Prepare State Length */
1243#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_MASK	(0xff)
1244#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_SHIFT	0
1245
1246/*	DSI_PHY_TIME_1		0x00c4	DPHY Timing Control Register 1 */
1247/* Time to Drive LP-00 by New Transmitter */
1248#define	DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_MASK		(0xff<<24)
1249#define	DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT	24
1250/* Time to Drive LP-00 after Turn Request */
1251#define	DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_MASK		(0xff<<16)
1252#define	DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT		16
1253/* DPHY HS Wakeup Period Length */
1254#define	DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_MASK		(0xffff)
1255#define	DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_SHIFT	0
1256
1257/*	DSI_PHY_TIME_2		0x00c8	DPHY Timing Control Register 2 */
1258/* DPHY CLK Exit Period Length */
1259#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_MASK	(0xff<<24)
1260#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT	24
1261/* DPHY CLK Trail Period Length */
1262#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_MASK	(0xff<<16)
1263#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT	16
1264/* DPHY CLK Zero State Length */
1265#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_MASK	(0xff<<8)
1266#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT	8
1267/* DPHY CLK LP Length */
1268#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_MASK		(0xff)
1269#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_SHIFT	0
1270
1271/*	DSI_PHY_TIME_3		0x00cc	DPHY Timing Control Register 3 */
1272/*		Bit(s) DSI_PHY_TIME_3_RSRV_31_16 reserved */
1273/* DPHY LP Length */
1274#define	DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_MASK		(0xff<<8)
1275#define	DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT		8
1276/* DPHY HS req to rdy Length */
1277#define	DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK		(0xff)
1278#define	DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT	0
1279
1280#define DSI_ESC_CLK				66  /* Unit: Mhz */
1281#define DSI_ESC_CLK_T				15  /* Unit: ns */
1282
1283/* LVDS */
1284/* LVDS_PHY_CTRL */
1285#define LVDS_PHY_CTL				0x2A4
1286#define LVDS_PLL_LOCK				(1 << 31)
1287#define LVDS_PHY_EXT_MASK			(7 << 28)
1288#define LVDS_PHY_EXT_SHIFT			(28)
1289#define LVDS_CLK_PHASE_MASK			(0x7f << 16)
1290#define LVDS_CLK_PHASE_SHIFT			(16)
1291#define LVDS_SSC_RESET_EXT			(1 << 13)
1292#define LVDS_SSC_MODE_DOWN_SPREAD		(1 << 12)
1293#define LVDS_SSC_EN				(1 << 11)
1294#define LVDS_PU_PLL				(1 << 10)
1295#define LVDS_PU_TX				(1 << 9)
1296#define LVDS_PU_IVREF				(1 << 8)
1297#define LVDS_CLK_SEL				(1 << 7)
1298#define LVDS_CLK_SEL_LVDS_PCLK			(1 << 7)
1299#define LVDS_PD_CH_MASK				(0x3f << 1)
1300#define LVDS_PD_CH(ch)				((ch) << 1)
1301#define LVDS_RST				(1 << 0)
1302
1303#define LVDS_PHY_CTL_EXT	0x2A8
1304
1305/* LVDS_PHY_CTRL_EXT1 */
1306#define LVDS_SSC_RNGE_MASK			(0x7ff << 16)
1307#define LVDS_SSC_RNGE_SHIFT			(16)
1308#define LVDS_RESERVE_IN_MASK			(0xf << 12)
1309#define LVDS_RESERVE_IN_SHIFT			(12)
1310#define LVDS_TEST_MON_MASK			(0x7 << 8)
1311#define LVDS_TEST_MON_SHIFT			(8)
1312#define LVDS_POL_SWAP_MASK			(0x3f << 0)
1313#define LVDS_POL_SWAP_SHIFT			(0)
1314
1315/* LVDS_PHY_CTRL_EXT2 */
1316#define LVDS_TX_DIF_AMP_MASK			(0xf << 24)
1317#define LVDS_TX_DIF_AMP_SHIFT			(24)
1318#define LVDS_TX_DIF_CM_MASK			(0x3 << 22)
1319#define LVDS_TX_DIF_CM_SHIFT			(22)
1320#define LVDS_SELLV_TXCLK_MASK			(0x1f << 16)
1321#define LVDS_SELLV_TXCLK_SHIFT			(16)
1322#define LVDS_TX_CMFB_EN				(0x1 << 15)
1323#define LVDS_TX_TERM_EN				(0x1 << 14)
1324#define LVDS_SELLV_TXDATA_MASK			(0x1f << 8)
1325#define LVDS_SELLV_TXDATA_SHIFT			(8)
1326#define LVDS_SELLV_OP7_MASK			(0x3 << 6)
1327#define LVDS_SELLV_OP7_SHIFT			(6)
1328#define LVDS_SELLV_OP6_MASK			(0x3 << 4)
1329#define LVDS_SELLV_OP6_SHIFT			(4)
1330#define LVDS_SELLV_OP9_MASK			(0x3 << 2)
1331#define LVDS_SELLV_OP9_SHIFT			(2)
1332#define LVDS_STRESSTST_EN			(0x1 << 0)
1333
1334/* LVDS_PHY_CTRL_EXT3 */
1335#define LVDS_KVCO_MASK				(0xf << 28)
1336#define LVDS_KVCO_SHIFT				(28)
1337#define LVDS_CTUNE_MASK				(0x3 << 26)
1338#define LVDS_CTUNE_SHIFT			(26)
1339#define LVDS_VREG_IVREF_MASK			(0x3 << 24)
1340#define LVDS_VREG_IVREF_SHIFT			(24)
1341#define LVDS_VDDL_MASK				(0xf << 20)
1342#define LVDS_VDDL_SHIFT				(20)
1343#define LVDS_VDDM_MASK				(0x3 << 18)
1344#define LVDS_VDDM_SHIFT				(18)
1345#define LVDS_FBDIV_MASK				(0xf << 8)
1346#define LVDS_FBDIV_SHIFT			(8)
1347#define LVDS_REFDIV_MASK			(0x7f << 0)
1348#define LVDS_REFDIV_SHIFT			(0)
1349
1350/* LVDS_PHY_CTRL_EXT4 */
1351#define LVDS_SSC_FREQ_DIV_MASK			(0xffff << 16)
1352#define LVDS_SSC_FREQ_DIV_SHIFT			(16)
1353#define LVDS_INTPI_MASK				(0xf << 12)
1354#define LVDS_INTPI_SHIFT			(12)
1355#define LVDS_VCODIV_SEL_SE_MASK			(0xf << 8)
1356#define LVDS_VCODIV_SEL_SE_SHIFT		(8)
1357#define LVDS_RESET_INTP_EXT			(0x1 << 7)
1358#define LVDS_VCO_VRNG_MASK			(0x7 << 4)
1359#define LVDS_VCO_VRNG_SHIFT			(4)
1360#define LVDS_PI_EN				(0x1 << 3)
1361#define LVDS_ICP_MASK				(0x7 << 0)
1362#define LVDS_ICP_SHIFT				(0)
1363
1364/* LVDS_PHY_CTRL_EXT5 */
1365#define LVDS_FREQ_OFFSET_MASK			(0x1ffff << 15)
1366#define LVDS_FREQ_OFFSET_SHIFT			(15)
1367#define LVDS_FREQ_OFFSET_VALID			(0x1 << 2)
1368#define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT	(0x1 << 1)
1369#define LVDS_FREQ_OFFSET_MODE_EN		(0x1 << 0)
1370
1371enum {
1372	PATH_PN = 0,
1373	PATH_TV,
1374	PATH_P2,
1375};
1376
1377/*
1378 * mmp path describes part of mmp path related info:
1379 * which is hiden in display driver and not exported to buffer driver
1380 */
1381struct mmphw_ctrl;
1382struct mmphw_path_plat {
1383	int id;
1384	struct mmphw_ctrl *ctrl;
1385	struct mmp_path *path;
1386	u32 path_config;
1387	u32 link_config;
1388	u32 dsi_rbswap;
1389};
1390
1391/* mmp ctrl describes mmp controller related info */
1392struct mmphw_ctrl {
1393	/* platform related, get from config */
1394	const char *name;
1395	int irq;
1396	void __iomem *reg_base;
1397	struct clk *clk;
1398
1399	/* sys info */
1400	struct device *dev;
1401
1402	/* state */
1403	int open_count;
1404	int status;
1405	struct mutex access_ok;
1406
1407	/*pathes*/
1408	int path_num;
1409	struct mmphw_path_plat path_plats[] __counted_by(path_num);
1410};
1411
1412static inline int overlay_is_vid(struct mmp_overlay *overlay)
1413{
1414	return overlay->dmafetch_id & 1;
1415}
1416
1417static inline struct mmphw_path_plat *path_to_path_plat(struct mmp_path *path)
1418{
1419	return (struct mmphw_path_plat *)path->plat_data;
1420}
1421
1422static inline struct mmphw_ctrl *path_to_ctrl(struct mmp_path *path)
1423{
1424	return path_to_path_plat(path)->ctrl;
1425}
1426
1427static inline struct mmphw_ctrl *overlay_to_ctrl(struct mmp_overlay *overlay)
1428{
1429	return path_to_ctrl(overlay->path);
1430}
1431
1432static inline void __iomem *ctrl_regs(struct mmp_path *path)
1433{
1434	return path_to_ctrl(path)->reg_base;
1435}
1436
1437/* path regs, for regs symmetrical for both pathes */
1438static inline struct lcd_regs *path_regs(struct mmp_path *path)
1439{
1440	if (path->id == PATH_PN)
1441		return (struct lcd_regs __force *)(ctrl_regs(path) + 0xc0);
1442	else if (path->id == PATH_TV)
1443		return (struct lcd_regs __force  *)ctrl_regs(path);
1444	else if (path->id == PATH_P2)
1445		return (struct lcd_regs __force *)(ctrl_regs(path) + 0x200);
1446	else {
1447		dev_err(path->dev, "path id %d invalid\n", path->id);
1448		BUG_ON(1);
1449		return NULL;
1450	}
1451}
1452
1453#ifdef CONFIG_MMP_DISP_SPI
1454extern int lcd_spi_register(struct mmphw_ctrl *ctrl);
1455#endif
1456#endif	/* _MMP_CTRL_H_ */