matroxfb_g450.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *
  4 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
  5 *
  6 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
  7 *
  8 * Portions Copyright (c) 2001 Matrox Graphics Inc.
  9 *
 10 * Version: 1.65 2002/08/14
 11 *
 12 * See matroxfb_base.c for contributors.
 13 *
 14 */
 15
 16#include <linux/export.h>
 17
 18#include "matroxfb_base.h"
 19#include "matroxfb_misc.h"
 20#include "matroxfb_DAC1064.h"
 21#include "g450_pll.h"
 22#include <linux/matroxfb.h>
 23#include <asm/div64.h>
 24
 25#include "matroxfb_g450.h"
 26
 27/* Definition of the various controls */
 28struct mctl {
 29	struct v4l2_queryctrl desc;
 30	size_t control;
 31};
 32
 33#define BLMIN	0xF3
 34#define WLMAX	0x3FF
 35
 36static const struct mctl g450_controls[] =
 37{	{ { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER,
 38	  "brightness",
 39	  0, WLMAX-BLMIN, 1, 370-BLMIN,
 40	  0,
 41	}, offsetof(struct matrox_fb_info, altout.tvo_params.brightness) },
 42	{ { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER,
 43	  "contrast",
 44	  0, 1023, 1, 127,
 45	  0,
 46	}, offsetof(struct matrox_fb_info, altout.tvo_params.contrast) },
 47	{ { V4L2_CID_SATURATION, V4L2_CTRL_TYPE_INTEGER,
 48	  "saturation",
 49	  0, 255, 1, 165,
 50	  0,
 51	}, offsetof(struct matrox_fb_info, altout.tvo_params.saturation) },
 52	{ { V4L2_CID_HUE, V4L2_CTRL_TYPE_INTEGER,
 53	  "hue",
 54	  0, 255, 1, 0,
 55	  0,
 56	}, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
 57	{ { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
 58	  "test output",
 59	  0, 1, 1, 0,
 60	  0,
 61	}, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
 62};
 63
 64#define G450CTRLS ARRAY_SIZE(g450_controls)
 65
 66/* Return: positive number: id found
 67           -EINVAL:         id not found, return failure
 68	   -ENOENT:         id not found, create fake disabled control */
 69static int get_ctrl_id(__u32 v4l2_id) {
 70	int i;
 71
 72	for (i = 0; i < G450CTRLS; i++) {
 73		if (v4l2_id < g450_controls[i].desc.id) {
 74			if (g450_controls[i].desc.id == 0x08000000) {
 75				return -EINVAL;
 76			}
 77			return -ENOENT;
 78		}
 79		if (v4l2_id == g450_controls[i].desc.id) {
 80			return i;
 81		}
 82	}
 83	return -EINVAL;
 84}
 85
 86static inline int *get_ctrl_ptr(struct matrox_fb_info *minfo, unsigned int idx)
 87{
 88	return (int*)((char*)minfo + g450_controls[idx].control);
 89}
 90
 91static void tvo_fill_defaults(struct matrox_fb_info *minfo)
 92{
 93	unsigned int i;
 94
 95	for (i = 0; i < G450CTRLS; i++) {
 96		*get_ctrl_ptr(minfo, i) = g450_controls[i].desc.default_value;
 97	}
 98}
 99
100static int cve2_get_reg(struct matrox_fb_info *minfo, int reg)
101{
102	unsigned long flags;
103	int val;
104
105	matroxfb_DAC_lock_irqsave(flags);
106	matroxfb_DAC_out(minfo, 0x87, reg);
107	val = matroxfb_DAC_in(minfo, 0x88);
108	matroxfb_DAC_unlock_irqrestore(flags);
109	return val;
110}
111
112static void cve2_set_reg(struct matrox_fb_info *minfo, int reg, int val)
113{
114	unsigned long flags;
115
116	matroxfb_DAC_lock_irqsave(flags);
117	matroxfb_DAC_out(minfo, 0x87, reg);
118	matroxfb_DAC_out(minfo, 0x88, val);
119	matroxfb_DAC_unlock_irqrestore(flags);
120}
121
122static void cve2_set_reg10(struct matrox_fb_info *minfo, int reg, int val)
123{
124	unsigned long flags;
125
126	matroxfb_DAC_lock_irqsave(flags);
127	matroxfb_DAC_out(minfo, 0x87, reg);
128	matroxfb_DAC_out(minfo, 0x88, val >> 2);
129	matroxfb_DAC_out(minfo, 0x87, reg + 1);
130	matroxfb_DAC_out(minfo, 0x88, val & 3);
131	matroxfb_DAC_unlock_irqrestore(flags);
132}
133
134static void g450_compute_bwlevel(const struct matrox_fb_info *minfo, int *bl,
135				 int *wl)
136{
137	const int b = minfo->altout.tvo_params.brightness + BLMIN;
138	const int c = minfo->altout.tvo_params.contrast;
139
140	*bl = max(b - c, BLMIN);
141	*wl = min(b + c, WLMAX);
142}
143
144static int g450_query_ctrl(void* md, struct v4l2_queryctrl *p) {
145	int i;
146
147	i = get_ctrl_id(p->id);
148	if (i >= 0) {
149		*p = g450_controls[i].desc;
150		return 0;
151	}
152	if (i == -ENOENT) {
153		static const struct v4l2_queryctrl disctrl =
154			{ .flags = V4L2_CTRL_FLAG_DISABLED };
155
156		i = p->id;
157		*p = disctrl;
158		p->id = i;
159		sprintf(p->name, "Ctrl #%08X", i);
160		return 0;
161	}
162	return -EINVAL;
163}
164
165static int g450_set_ctrl(void* md, struct v4l2_control *p) {
166	int i;
167	struct matrox_fb_info *minfo = md;
168
169	i = get_ctrl_id(p->id);
170	if (i < 0) return -EINVAL;
171
172	/*
173	 * Check if changed.
174	 */
175	if (p->value == *get_ctrl_ptr(minfo, i)) return 0;
176
177	/*
178	 * Check limits.
179	 */
180	if (p->value > g450_controls[i].desc.maximum) return -EINVAL;
181	if (p->value < g450_controls[i].desc.minimum) return -EINVAL;
182
183	/*
184	 * Store new value.
185	 */
186	*get_ctrl_ptr(minfo, i) = p->value;
187
188	switch (p->id) {
189		case V4L2_CID_BRIGHTNESS:
190		case V4L2_CID_CONTRAST:
191			{
192				int blacklevel, whitelevel;
193				g450_compute_bwlevel(minfo, &blacklevel, &whitelevel);
194				cve2_set_reg10(minfo, 0x0e, blacklevel);
195				cve2_set_reg10(minfo, 0x1e, whitelevel);
196			}
197			break;
198		case V4L2_CID_SATURATION:
199			cve2_set_reg(minfo, 0x20, p->value);
200			cve2_set_reg(minfo, 0x22, p->value);
201			break;
202		case V4L2_CID_HUE:
203			cve2_set_reg(minfo, 0x25, p->value);
204			break;
205		case MATROXFB_CID_TESTOUT:
206			{
207				unsigned char val = cve2_get_reg(minfo, 0x05);
208				if (p->value) val |=  0x02;
209				else          val &= ~0x02;
210				cve2_set_reg(minfo, 0x05, val);
211			}
212			break;
213	}
214
215
216	return 0;
217}
218
219static int g450_get_ctrl(void* md, struct v4l2_control *p) {
220	int i;
221	struct matrox_fb_info *minfo = md;
222
223	i = get_ctrl_id(p->id);
224	if (i < 0) return -EINVAL;
225	p->value = *get_ctrl_ptr(minfo, i);
226	return 0;
227}
228
229struct output_desc {
230	unsigned int	h_vis;
231	unsigned int	h_f_porch;
232	unsigned int	h_sync;
233	unsigned int	h_b_porch;
234	unsigned long long int	chromasc;
235	unsigned int	burst;
236	unsigned int	v_total;
237};
238
239static void computeRegs(struct matrox_fb_info *minfo, struct mavenregs *r,
240			struct my_timming *mt, const struct output_desc *outd)
241{
242	u_int32_t chromasc;
243	u_int32_t hlen;
244	u_int32_t hsl;
245	u_int32_t hbp;
246	u_int32_t hfp;
247	u_int32_t hvis;
248	unsigned int pixclock;
249	unsigned long long piic;
250	int mnp;
251	int over;
252
253	r->regs[0x80] = 0x03;	/* | 0x40 for SCART */
254
255	hvis = ((mt->HDisplay << 1) + 3) & ~3;
256
257	if (hvis >= 2048) {
258		hvis = 2044;
259	}
260
261	piic = 1000000000ULL * hvis;
262	do_div(piic, outd->h_vis);
263
264	dprintk(KERN_DEBUG "Want %u kHz pixclock\n", (unsigned int)piic);
265
266	mnp = matroxfb_g450_setclk(minfo, piic, M_VIDEO_PLL);
267
268	mt->mnp = mnp;
269	mt->pixclock = g450_mnp2f(minfo, mnp);
270
271	dprintk(KERN_DEBUG "MNP=%08X\n", mnp);
272
273	pixclock = 1000000000U / mt->pixclock;
274
275	dprintk(KERN_DEBUG "Got %u ps pixclock\n", pixclock);
276
277	piic = outd->chromasc;
278	do_div(piic, mt->pixclock);
279	chromasc = piic;
280
281	dprintk(KERN_DEBUG "Chroma is %08X\n", chromasc);
282
283	r->regs[0] = piic >> 24;
284	r->regs[1] = piic >> 16;
285	r->regs[2] = piic >>  8;
286	r->regs[3] = piic >>  0;
287	hbp = (((outd->h_b_porch + pixclock) / pixclock)) & ~1;
288	hfp = (((outd->h_f_porch + pixclock) / pixclock)) & ~1;
289	hsl = (((outd->h_sync + pixclock) / pixclock)) & ~1;
290	hlen = hvis + hfp + hsl + hbp;
291	over = hlen & 0x0F;
292
293	dprintk(KERN_DEBUG "WL: vis=%u, hf=%u, hs=%u, hb=%u, total=%u\n", hvis, hfp, hsl, hbp, hlen);
294
295	if (over) {
296		hfp -= over;
297		hlen -= over;
298		if (over <= 2) {
299		} else if (over < 10) {
300			hfp += 4;
301			hlen += 4;
302		} else {
303			hfp += 16;
304			hlen += 16;
305		}
306	}
307
308	/* maybe cve2 has requirement 800 < hlen < 1184 */
309	r->regs[0x08] = hsl;
310	r->regs[0x09] = (outd->burst + pixclock - 1) / pixclock;	/* burst length */
311	r->regs[0x0A] = hbp;
312	r->regs[0x2C] = hfp;
313	r->regs[0x31] = hvis / 8;
314	r->regs[0x32] = hvis & 7;
315
316	dprintk(KERN_DEBUG "PG: vis=%04X, hf=%02X, hs=%02X, hb=%02X, total=%04X\n", hvis, hfp, hsl, hbp, hlen);
317
318	r->regs[0x84] = 1;	/* x sync point */
319	r->regs[0x85] = 0;
320	hvis = hvis >> 1;
321	hlen = hlen >> 1;
322
323	dprintk(KERN_DEBUG "hlen=%u hvis=%u\n", hlen, hvis);
324
325	mt->interlaced = 1;
326
327	mt->HDisplay = hvis & ~7;
328	mt->HSyncStart = mt->HDisplay + 8;
329	mt->HSyncEnd = (hlen & ~7) - 8;
330	mt->HTotal = hlen;
331
332	{
333		int upper;
334		unsigned int vtotal;
335		unsigned int vsyncend;
336		unsigned int vdisplay;
337
338		vtotal = mt->VTotal;
339		vsyncend = mt->VSyncEnd;
340		vdisplay = mt->VDisplay;
341		if (vtotal < outd->v_total) {
342			unsigned int yovr = outd->v_total - vtotal;
343
344			vsyncend += yovr >> 1;
345		} else if (vtotal > outd->v_total) {
346			vdisplay = outd->v_total - 4;
347			vsyncend = outd->v_total;
348		}
349		upper = (outd->v_total - vsyncend) >> 1;	/* in field lines */
350		r->regs[0x17] = outd->v_total / 4;
351		r->regs[0x18] = outd->v_total & 3;
352		r->regs[0x33] = upper - 1;	/* upper blanking */
353		r->regs[0x82] = upper;		/* y sync point */
354		r->regs[0x83] = upper >> 8;
355
356		mt->VDisplay = vdisplay;
357		mt->VSyncStart = outd->v_total - 2;
358		mt->VSyncEnd = outd->v_total;
359		mt->VTotal = outd->v_total;
360	}
361}
362
363static void cve2_init_TVdata(int norm, struct mavenregs* data, const struct output_desc** outd) {
364	static const struct output_desc paloutd = {
365		.h_vis	   = 52148148,	// ps
366		.h_f_porch =  1407407,	// ps
367		.h_sync    =  4666667,	// ps
368		.h_b_porch =  5777778,	// ps
369		.chromasc  = 19042247534182ULL,	// 4433618.750 Hz
370		.burst     =  2518518,	// ps
371		.v_total   =      625,
372	};
373	static const struct output_desc ntscoutd = {
374		.h_vis     = 52888889,	// ps
375		.h_f_porch =  1333333,	// ps
376		.h_sync    =  4666667,	// ps
377		.h_b_porch =  4666667,	// ps
378		.chromasc  = 15374030659475ULL,	// 3579545.454 Hz
379		.burst     =  2418418,	// ps
380		.v_total   =      525,	// lines
381	};
382
383	static const struct mavenregs palregs = { {
384		0x2A, 0x09, 0x8A, 0xCB,	/* 00: chroma subcarrier */
385		0x00,
386		0x00,	/* test */
387		0xF9,	/* modified by code (F9 written...) */
388		0x00,	/* ? not written */
389		0x7E,	/* 08 */
390		0x44,	/* 09 */
391		0x9C,	/* 0A */
392		0x2E,	/* 0B */
393		0x21,	/* 0C */
394		0x00,	/* ? not written */
395//		0x3F, 0x03, /* 0E-0F */
396		0x3C, 0x03,
397		0x3C, 0x03, /* 10-11 */
398		0x1A,	/* 12 */
399		0x2A,	/* 13 */
400		0x1C, 0x3D, 0x14, /* 14-16 */
401		0x9C, 0x01, /* 17-18 */
402		0x00,	/* 19 */
403		0xFE,	/* 1A */
404		0x7E,	/* 1B */
405		0x60,	/* 1C */
406		0x05,	/* 1D */
407//		0x89, 0x03, /* 1E-1F */
408		0xAD, 0x03,
409//		0x72,	/* 20 */
410		0xA5,
411		0x07,	/* 21 */
412//		0x72,	/* 22 */
413		0xA5,
414		0x00,	/* 23 */
415		0x00,	/* 24 */
416		0x00,	/* 25 */
417		0x08,	/* 26 */
418		0x04,	/* 27 */
419		0x00,	/* 28 */
420		0x1A,	/* 29 */
421		0x55, 0x01, /* 2A-2B */
422		0x26,	/* 2C */
423		0x07, 0x7E, /* 2D-2E */
424		0x02, 0x54, /* 2F-30 */
425		0xB0, 0x00, /* 31-32 */
426		0x14,	/* 33 */
427		0x49,	/* 34 */
428		0x00,	/* 35 written multiple times */
429		0x00,	/* 36 not written */
430		0xA3,	/* 37 */
431		0xC8,	/* 38 */
432		0x22,	/* 39 */
433		0x02,	/* 3A */
434		0x22,	/* 3B */
435		0x3F, 0x03, /* 3C-3D */
436		0x00,	/* 3E written multiple times */
437		0x00,	/* 3F not written */
438	} };
439	static const struct mavenregs ntscregs = { {
440		0x21, 0xF0, 0x7C, 0x1F,	/* 00: chroma subcarrier */
441		0x00,
442		0x00,	/* test */
443		0xF9,	/* modified by code (F9 written...) */
444		0x00,	/* ? not written */
445		0x7E,	/* 08 */
446		0x43,	/* 09 */
447		0x7E,	/* 0A */
448		0x3D,	/* 0B */
449		0x00,	/* 0C */
450		0x00,	/* ? not written */
451		0x41, 0x00, /* 0E-0F */
452		0x3C, 0x00, /* 10-11 */
453		0x17,	/* 12 */
454		0x21,	/* 13 */
455		0x1B, 0x1B, 0x24, /* 14-16 */
456		0x83, 0x01, /* 17-18 */
457		0x00,	/* 19 */
458		0x0F,	/* 1A */
459		0x0F,	/* 1B */
460		0x60,	/* 1C */
461		0x05,	/* 1D */
462		//0x89, 0x02, /* 1E-1F */
463		0xC0, 0x02, /* 1E-1F */
464		//0x5F,	/* 20 */
465		0x9C,	/* 20 */
466		0x04,	/* 21 */
467		//0x5F,	/* 22 */
468		0x9C,	/* 22 */
469		0x01,	/* 23 */
470		0x02,	/* 24 */
471		0x00,	/* 25 */
472		0x0A,	/* 26 */
473		0x05,	/* 27 */
474		0x00,	/* 28 */
475		0x10,	/* 29 */
476		0xFF, 0x03, /* 2A-2B */
477		0x24,	/* 2C */
478		0x0F, 0x78, /* 2D-2E */
479		0x00, 0x00, /* 2F-30 */
480		0xB2, 0x04, /* 31-32 */
481		0x14,	/* 33 */
482		0x02,	/* 34 */
483		0x00,	/* 35 written multiple times */
484		0x00,	/* 36 not written */
485		0xA3,	/* 37 */
486		0xC8,	/* 38 */
487		0x15,	/* 39 */
488		0x05,	/* 3A */
489		0x3B,	/* 3B */
490		0x3C, 0x00, /* 3C-3D */
491		0x00,	/* 3E written multiple times */
492		0x00,	/* never written */
493	} };
494
495	if (norm == MATROXFB_OUTPUT_MODE_PAL) {
496		*data = palregs;
497		*outd = &paloutd;
498	} else {
499  		*data = ntscregs;
500		*outd = &ntscoutd;
501	}
502 	return;
503}
504
505#define LR(x) cve2_set_reg(minfo, (x), m->regs[(x)])
506static void cve2_init_TV(struct matrox_fb_info *minfo,
507			 const struct mavenregs *m)
508{
509	int i;
510
511	LR(0x80);
512	LR(0x82); LR(0x83);
513	LR(0x84); LR(0x85);
514
515	cve2_set_reg(minfo, 0x3E, 0x01);
516
517	for (i = 0; i < 0x3E; i++) {
518		LR(i);
519	}
520	cve2_set_reg(minfo, 0x3E, 0x00);
521}
522
523static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
524	struct matrox_fb_info *minfo = md;
525
526	dprintk(KERN_DEBUG "Computing, mode=%u\n", minfo->outputs[1].mode);
527
528	if (mt->crtc == MATROXFB_SRC_CRTC2 &&
529	    minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
530		const struct output_desc* outd;
531
532		cve2_init_TVdata(minfo->outputs[1].mode, &minfo->hw.maven, &outd);
533		{
534			int blacklevel, whitelevel;
535			g450_compute_bwlevel(minfo, &blacklevel, &whitelevel);
536			minfo->hw.maven.regs[0x0E] = blacklevel >> 2;
537			minfo->hw.maven.regs[0x0F] = blacklevel & 3;
538			minfo->hw.maven.regs[0x1E] = whitelevel >> 2;
539			minfo->hw.maven.regs[0x1F] = whitelevel & 3;
540
541			minfo->hw.maven.regs[0x20] =
542			minfo->hw.maven.regs[0x22] = minfo->altout.tvo_params.saturation;
543
544			minfo->hw.maven.regs[0x25] = minfo->altout.tvo_params.hue;
545
546			if (minfo->altout.tvo_params.testout) {
547				minfo->hw.maven.regs[0x05] |= 0x02;
548			}
549		}
550		computeRegs(minfo, &minfo->hw.maven, mt, outd);
551	} else if (mt->mnp < 0) {
552		/* We must program clocks before CRTC2, otherwise interlaced mode
553		   startup may fail */
554		mt->mnp = matroxfb_g450_setclk(minfo, mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
555		mt->pixclock = g450_mnp2f(minfo, mt->mnp);
556	}
557	dprintk(KERN_DEBUG "Pixclock = %u\n", mt->pixclock);
558	return 0;
559}
560
561static int matroxfb_g450_program(void* md) {
562	struct matrox_fb_info *minfo = md;
563
564	if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
565		cve2_init_TV(minfo, &minfo->hw.maven);
566	}
567	return 0;
568}
569
570static int matroxfb_g450_verify_mode(void* md, u_int32_t arg) {
571	switch (arg) {
572		case MATROXFB_OUTPUT_MODE_PAL:
573		case MATROXFB_OUTPUT_MODE_NTSC:
574		case MATROXFB_OUTPUT_MODE_MONITOR:
575			return 0;
576	}
577	return -EINVAL;
578}
579
580static int g450_dvi_compute(void* md, struct my_timming* mt) {
581	struct matrox_fb_info *minfo = md;
582
583	if (mt->mnp < 0) {
584		mt->mnp = matroxfb_g450_setclk(minfo, mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
585		mt->pixclock = g450_mnp2f(minfo, mt->mnp);
586	}
587	return 0;
588}
589
590static struct matrox_altout matroxfb_g450_altout = {
591	.name		= "Secondary output",
592	.compute	= matroxfb_g450_compute,
593	.program	= matroxfb_g450_program,
594	.verifymode	= matroxfb_g450_verify_mode,
595	.getqueryctrl	= g450_query_ctrl,
596	.getctrl	= g450_get_ctrl,
597	.setctrl	= g450_set_ctrl,
598};
599
600static struct matrox_altout matroxfb_g450_dvi = {
601	.name		= "DVI output",
602	.compute	= g450_dvi_compute,
603};
604
605void matroxfb_g450_connect(struct matrox_fb_info *minfo)
606{
607	if (minfo->devflags.g450dac) {
608		down_write(&minfo->altout.lock);
609		tvo_fill_defaults(minfo);
610		minfo->outputs[1].src = minfo->outputs[1].default_src;
611		minfo->outputs[1].data = minfo;
612		minfo->outputs[1].output = &matroxfb_g450_altout;
613		minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
614		minfo->outputs[2].src = minfo->outputs[2].default_src;
615		minfo->outputs[2].data = minfo;
616		minfo->outputs[2].output = &matroxfb_g450_dvi;
617		minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
618		up_write(&minfo->altout.lock);
619	}
620}
621
622void matroxfb_g450_shutdown(struct matrox_fb_info *minfo)
623{
624	if (minfo->devflags.g450dac) {
625		down_write(&minfo->altout.lock);
626		minfo->outputs[1].src = MATROXFB_SRC_NONE;
627		minfo->outputs[1].output = NULL;
628		minfo->outputs[1].data = NULL;
629		minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
630		minfo->outputs[2].src = MATROXFB_SRC_NONE;
631		minfo->outputs[2].output = NULL;
632		minfo->outputs[2].data = NULL;
633		minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
634		up_write(&minfo->altout.lock);
635	}
636}
637
638EXPORT_SYMBOL(matroxfb_g450_connect);
639EXPORT_SYMBOL(matroxfb_g450_shutdown);
640
641MODULE_AUTHOR("(c) 2000-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
642MODULE_DESCRIPTION("Matrox G450/G550 output driver");
643MODULE_LICENSE("GPL");