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lxfb_ops.c
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linux-6.19.14/drivers/video/fbdev/geode/lxfb_ops.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* Geode LX framebuffer driver 3 * 4 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc. 5 */ 6 7#include <linux/kernel.h> 8#include <linux/errno.h> 9#include <linux/fb.h> 10#include <linux/uaccess.h> 11#include <linux/delay.h> 12#include <linux/cs5535.h> 13 14#include <asm/msr.h> 15#include "lxfb.h" 16 17/* TODO 18 * Support panel scaling 19 * Add acceleration 20 * Add support for interlacing (TV out) 21 * Support compression 22 */ 23 24/* This is the complete list of PLL frequencies that we can set - 25 * we will choose the closest match to the incoming clock. 26 * freq is the frequency of the dotclock * 1000 (for example, 27 * 24823 = 24.983 Mhz). 28 * pllval is the corresponding PLL value 29*/ 30 31static const struct { 32 unsigned int pllval; 33 unsigned int freq; 34} pll_table[] = { 35 { 0x000131AC, 6231 }, 36 { 0x0001215D, 6294 }, 37 { 0x00011087, 6750 }, 38 { 0x0001216C, 7081 }, 39 { 0x0001218D, 7140 }, 40 { 0x000110C9, 7800 }, 41 { 0x00013147, 7875 }, 42 { 0x000110A7, 8258 }, 43 { 0x00012159, 8778 }, 44 { 0x00014249, 8875 }, 45 { 0x00010057, 9000 }, 46 { 0x0001219A, 9472 }, 47 { 0x00012158, 9792 }, 48 { 0x00010045, 10000 }, 49 { 0x00010089, 10791 }, 50 { 0x000110E7, 11225 }, 51 { 0x00012136, 11430 }, 52 { 0x00013207, 12375 }, 53 { 0x00012187, 12500 }, 54 { 0x00014286, 14063 }, 55 { 0x000110E5, 15016 }, 56 { 0x00014214, 16250 }, 57 { 0x00011105, 17045 }, 58 { 0x000131E4, 18563 }, 59 { 0x00013183, 18750 }, 60 { 0x00014284, 19688 }, 61 { 0x00011104, 20400 }, 62 { 0x00016363, 23625 }, 63 { 0x000031AC, 24923 }, 64 { 0x0000215D, 25175 }, 65 { 0x00001087, 27000 }, 66 { 0x0000216C, 28322 }, 67 { 0x0000218D, 28560 }, 68 { 0x000010C9, 31200 }, 69 { 0x00003147, 31500 }, 70 { 0x000010A7, 33032 }, 71 { 0x00002159, 35112 }, 72 { 0x00004249, 35500 }, 73 { 0x00000057, 36000 }, 74 { 0x0000219A, 37889 }, 75 { 0x00002158, 39168 }, 76 { 0x00000045, 40000 }, 77 { 0x00000089, 43163 }, 78 { 0x000010E7, 44900 }, 79 { 0x00002136, 45720 }, 80 { 0x00003207, 49500 }, 81 { 0x00002187, 50000 }, 82 { 0x00004286, 56250 }, 83 { 0x000010E5, 60065 }, 84 { 0x00004214, 65000 }, 85 { 0x00001105, 68179 }, 86 { 0x000031E4, 74250 }, 87 { 0x00003183, 75000 }, 88 { 0x00004284, 78750 }, 89 { 0x00001104, 81600 }, 90 { 0x00006363, 94500 }, 91 { 0x00005303, 97520 }, 92 { 0x00002183, 100187 }, 93 { 0x00002122, 101420 }, 94 { 0x00001081, 108000 }, 95 { 0x00006201, 113310 }, 96 { 0x00000041, 119650 }, 97 { 0x000041A1, 129600 }, 98 { 0x00002182, 133500 }, 99 { 0x000041B1, 135000 }, 100 { 0x00000051, 144000 }, 101 { 0x000041E1, 148500 }, 102 { 0x000062D1, 157500 }, 103 { 0x000031A1, 162000 }, 104 { 0x00000061, 169203 }, 105 { 0x00004231, 172800 }, 106 { 0x00002151, 175500 }, 107 { 0x000052E1, 189000 }, 108 { 0x00000071, 192000 }, 109 { 0x00003201, 198000 }, 110 { 0x00004291, 202500 }, 111 { 0x00001101, 204750 }, 112 { 0x00007481, 218250 }, 113 { 0x00004170, 229500 }, 114 { 0x00006210, 234000 }, 115 { 0x00003140, 251182 }, 116 { 0x00006250, 261000 }, 117 { 0x000041C0, 278400 }, 118 { 0x00005220, 280640 }, 119 { 0x00000050, 288000 }, 120 { 0x000041E0, 297000 }, 121 { 0x00002130, 320207 } 122}; 123 124 125static void lx_set_dotpll(u32 pllval) 126{ 127 u32 dotpll_lo, dotpll_hi; 128 int i; 129 130 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 131 132 if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval)) 133 return; 134 135 dotpll_hi = pllval; 136 dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX); 137 dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET; 138 139 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 140 141 /* Wait 100us for the PLL to lock */ 142 143 udelay(100); 144 145 /* Now, loop for the lock bit */ 146 147 for (i = 0; i < 1000; i++) { 148 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 149 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK) 150 break; 151 } 152 153 /* Clear the reset bit */ 154 155 dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET; 156 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 157} 158 159/* Set the clock based on the frequency specified by the current mode */ 160 161static void lx_set_clock(struct fb_info *info) 162{ 163 unsigned int diff, min, best = 0; 164 unsigned int freq, i; 165 166 freq = (unsigned int) (1000000000 / info->var.pixclock); 167 168 min = abs(pll_table[0].freq - freq); 169 170 for (i = 0; i < ARRAY_SIZE(pll_table); i++) { 171 diff = abs(pll_table[i].freq - freq); 172 if (diff < min) { 173 min = diff; 174 best = i; 175 } 176 } 177 178 lx_set_dotpll(pll_table[best].pllval & 0x00017FFF); 179} 180 181static void lx_graphics_disable(struct fb_info *info) 182{ 183 struct lxfb_par *par = info->par; 184 unsigned int val, gcfg; 185 186 /* Note: This assumes that the video is in a quitet state */ 187 188 write_vp(par, VP_A1T, 0); 189 write_vp(par, VP_A2T, 0); 190 write_vp(par, VP_A3T, 0); 191 192 /* Turn off the VGA and video enable */ 193 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE | 194 DC_GENERAL_CFG_VIDE); 195 196 write_dc(par, DC_GENERAL_CFG, val); 197 198 val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN; 199 write_vp(par, VP_VCFG, val); 200 201 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK | 202 DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS); 203 204 val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN; 205 write_dc(par, DC_GENLK_CTL, val); 206 207 val = read_dc(par, DC_CLR_KEY); 208 write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN); 209 210 /* turn off the panel */ 211 write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P); 212 213 val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN; 214 write_vp(par, VP_MISC, val); 215 216 /* Turn off the display */ 217 218 val = read_vp(par, VP_DCFG); 219 write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | 220 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN)); 221 222 gcfg = read_dc(par, DC_GENERAL_CFG); 223 gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE); 224 write_dc(par, DC_GENERAL_CFG, gcfg); 225 226 /* Turn off the TGEN */ 227 val = read_dc(par, DC_DISPLAY_CFG); 228 val &= ~DC_DISPLAY_CFG_TGEN; 229 write_dc(par, DC_DISPLAY_CFG, val); 230 231 /* Wait 1000 usecs to ensure that the TGEN is clear */ 232 udelay(1000); 233 234 /* Turn off the FIFO loader */ 235 236 gcfg &= ~DC_GENERAL_CFG_DFLE; 237 write_dc(par, DC_GENERAL_CFG, gcfg); 238 239 /* Lastly, wait for the GP to go idle */ 240 241 do { 242 val = read_gp(par, GP_BLT_STATUS); 243 } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE)); 244} 245 246static void lx_graphics_enable(struct fb_info *info) 247{ 248 struct lxfb_par *par = info->par; 249 u32 temp, config; 250 251 /* Set the video request register */ 252 write_vp(par, VP_VRR, 0); 253 254 /* Set up the polarities */ 255 256 config = read_vp(par, VP_DCFG); 257 258 config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY | 259 VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL); 260 261 config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT 262 | VP_DCFG_GV_GAM); 263 264 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 265 config |= VP_DCFG_CRT_HSYNC_POL; 266 267 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 268 config |= VP_DCFG_CRT_VSYNC_POL; 269 270 if (par->output & OUTPUT_PANEL) { 271 u32 msrlo, msrhi; 272 273 write_fp(par, FP_PT1, 0); 274 temp = FP_PT2_SCRC; 275 276 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) 277 temp |= FP_PT2_HSP; 278 279 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) 280 temp |= FP_PT2_VSP; 281 282 write_fp(par, FP_PT2, temp); 283 write_fp(par, FP_DFC, FP_DFC_BC); 284 285 msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW; 286 msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH; 287 288 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi); 289 } 290 291 if (par->output & OUTPUT_CRT) { 292 config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | 293 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN; 294 } 295 296 write_vp(par, VP_DCFG, config); 297 298 /* Turn the CRT dacs back on */ 299 300 if (par->output & OUTPUT_CRT) { 301 temp = read_vp(par, VP_MISC); 302 temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN); 303 write_vp(par, VP_MISC, temp); 304 } 305 306 /* Turn the panel on (if it isn't already) */ 307 if (par->output & OUTPUT_PANEL) 308 write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P); 309} 310 311unsigned int lx_framebuffer_size(void) 312{ 313 unsigned int val; 314 315 if (!cs5535_has_vsa2()) { 316 uint32_t hi, lo; 317 318 /* The number of pages is (PMAX - PMIN)+1 */ 319 rdmsr(MSR_GLIU_P2D_RO0, lo, hi); 320 321 /* PMAX */ 322 val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); 323 /* PMIN */ 324 val -= (lo & 0x000fffff); 325 val += 1; 326 327 /* The page size is 4k */ 328 return (val << 12); 329 } 330 331 /* The frame buffer size is reported by a VSM in VSA II */ 332 /* Virtual Register Class = 0x02 */ 333 /* VG_MEM_SIZE (1MB units) = 0x00 */ 334 335 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX); 336 outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX); 337 338 val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE; 339 return (val << 20); 340} 341 342void lx_set_mode(struct fb_info *info) 343{ 344 struct lxfb_par *par = info->par; 345 u64 msrval; 346 347 unsigned int max, dv, val, size; 348 349 unsigned int gcfg, dcfg; 350 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; 351 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; 352 353 /* Unlock the DC registers */ 354 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); 355 356 lx_graphics_disable(info); 357 358 lx_set_clock(info); 359 360 /* Set output mode */ 361 362 rdmsrq(MSR_LX_GLD_MSR_CONFIG, msrval); 363 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT; 364 365 if (par->output & OUTPUT_PANEL) { 366 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP; 367 368 if (par->output & OUTPUT_CRT) 369 msrval |= MSR_LX_GLD_MSR_CONFIG_FPC; 370 else 371 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC; 372 } else 373 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT; 374 375 wrmsrq(MSR_LX_GLD_MSR_CONFIG, msrval); 376 377 /* Clear the various buffers */ 378 /* FIXME: Adjust for panning here */ 379 380 write_dc(par, DC_FB_ST_OFFSET, 0); 381 write_dc(par, DC_CB_ST_OFFSET, 0); 382 write_dc(par, DC_CURS_ST_OFFSET, 0); 383 384 /* FIXME: Add support for interlacing */ 385 /* FIXME: Add support for scaling */ 386 387 val = read_dc(par, DC_GENLK_CTL); 388 val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN | 389 DC_GENLK_CTL_FLICK_SEL_MASK); 390 391 /* Default scaling params */ 392 393 write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000); 394 write_dc(par, DC_IRQ_FILT_CTL, 0); 395 write_dc(par, DC_GENLK_CTL, val); 396 397 /* FIXME: Support compression */ 398 399 if (info->fix.line_length > 4096) 400 dv = DC_DV_CTL_DV_LINE_SIZE_8K; 401 else if (info->fix.line_length > 2048) 402 dv = DC_DV_CTL_DV_LINE_SIZE_4K; 403 else if (info->fix.line_length > 1024) 404 dv = DC_DV_CTL_DV_LINE_SIZE_2K; 405 else 406 dv = DC_DV_CTL_DV_LINE_SIZE_1K; 407 408 max = info->fix.line_length * info->var.yres; 409 max = (max + 0x3FF) & 0xFFFFFC00; 410 411 write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN); 412 413 val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE; 414 write_dc(par, DC_DV_CTL, val | dv); 415 416 size = info->var.xres * (info->var.bits_per_pixel >> 3); 417 418 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); 419 write_dc(par, DC_LINE_SIZE, (size + 7) >> 3); 420 421 /* Set default watermark values */ 422 423 rdmsrq(MSR_LX_SPARE_MSR, msrval); 424 425 msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO 426 | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL 427 | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M 428 | MSR_LX_SPARE_MSR_WM_LPEN_OVRD); 429 msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM | 430 MSR_LX_SPARE_MSR_DIS_INIT_V_PRI; 431 wrmsrq(MSR_LX_SPARE_MSR, msrval); 432 433 gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */ 434 gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */ 435 (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT); 436 gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */ 437 438 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ 439 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ 440 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ 441 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ 442 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ 443 dcfg |= DC_DISPLAY_CFG_VISL; 444 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ 445 446 /* Set the current BPP mode */ 447 448 switch (info->var.bits_per_pixel) { 449 case 8: 450 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; 451 break; 452 453 case 16: 454 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; 455 break; 456 457 case 32: 458 case 24: 459 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; 460 break; 461 } 462 463 /* Now - set up the timings */ 464 465 hactive = info->var.xres; 466 hblankstart = hactive; 467 hsyncstart = hblankstart + info->var.right_margin; 468 hsyncend = hsyncstart + info->var.hsync_len; 469 hblankend = hsyncend + info->var.left_margin; 470 htotal = hblankend; 471 472 vactive = info->var.yres; 473 vblankstart = vactive; 474 vsyncstart = vblankstart + info->var.lower_margin; 475 vsyncend = vsyncstart + info->var.vsync_len; 476 vblankend = vsyncend + info->var.upper_margin; 477 vtotal = vblankend; 478 479 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16)); 480 write_dc(par, DC_H_BLANK_TIMING, 481 (hblankstart - 1) | ((hblankend - 1) << 16)); 482 write_dc(par, DC_H_SYNC_TIMING, 483 (hsyncstart - 1) | ((hsyncend - 1) << 16)); 484 485 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16)); 486 write_dc(par, DC_V_BLANK_TIMING, 487 (vblankstart - 1) | ((vblankend - 1) << 16)); 488 write_dc(par, DC_V_SYNC_TIMING, 489 (vsyncstart - 1) | ((vsyncend - 1) << 16)); 490 491 write_dc(par, DC_FB_ACTIVE, 492 (info->var.xres - 1) << 16 | (info->var.yres - 1)); 493 494 /* And re-enable the graphics output */ 495 lx_graphics_enable(info); 496 497 /* Write the two main configuration registers */ 498 write_dc(par, DC_DISPLAY_CFG, dcfg); 499 write_dc(par, DC_ARB_CFG, 0); 500 write_dc(par, DC_GENERAL_CFG, gcfg); 501 502 /* Lock the DC registers */ 503 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); 504} 505 506void lx_set_palette_reg(struct fb_info *info, unsigned regno, 507 unsigned red, unsigned green, unsigned blue) 508{ 509 struct lxfb_par *par = info->par; 510 int val; 511 512 /* Hardware palette is in RGB 8-8-8 format. */ 513 514 val = (red << 8) & 0xff0000; 515 val |= (green) & 0x00ff00; 516 val |= (blue >> 8) & 0x0000ff; 517 518 write_dc(par, DC_PAL_ADDRESS, regno); 519 write_dc(par, DC_PAL_DATA, val); 520} 521 522int lx_blank_display(struct fb_info *info, int blank_mode) 523{ 524 struct lxfb_par *par = info->par; 525 u32 dcfg, misc, fp_pm; 526 int blank, hsync, vsync; 527 528 /* CRT power saving modes. */ 529 switch (blank_mode) { 530 case FB_BLANK_UNBLANK: 531 blank = 0; hsync = 1; vsync = 1; 532 break; 533 case FB_BLANK_NORMAL: 534 blank = 1; hsync = 1; vsync = 1; 535 break; 536 case FB_BLANK_VSYNC_SUSPEND: 537 blank = 1; hsync = 1; vsync = 0; 538 break; 539 case FB_BLANK_HSYNC_SUSPEND: 540 blank = 1; hsync = 0; vsync = 1; 541 break; 542 case FB_BLANK_POWERDOWN: 543 blank = 1; hsync = 0; vsync = 0; 544 break; 545 default: 546 return -EINVAL; 547 } 548 549 dcfg = read_vp(par, VP_DCFG); 550 dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN | 551 VP_DCFG_CRT_EN); 552 if (!blank) 553 dcfg |= VP_DCFG_DAC_BL_EN | VP_DCFG_CRT_EN; 554 if (hsync) 555 dcfg |= VP_DCFG_HSYNC_EN; 556 if (vsync) 557 dcfg |= VP_DCFG_VSYNC_EN; 558 559 write_vp(par, VP_DCFG, dcfg); 560 561 misc = read_vp(par, VP_MISC); 562 563 if (vsync && hsync) 564 misc &= ~VP_MISC_DACPWRDN; 565 else 566 misc |= VP_MISC_DACPWRDN; 567 568 write_vp(par, VP_MISC, misc); 569 570 /* Power on/off flat panel */ 571 572 if (par->output & OUTPUT_PANEL) { 573 fp_pm = read_fp(par, FP_PM); 574 if (blank_mode == FB_BLANK_POWERDOWN) 575 fp_pm &= ~FP_PM_P; 576 else 577 fp_pm |= FP_PM_P; 578 write_fp(par, FP_PM, fp_pm); 579 } 580 581 return 0; 582} 583 584static void lx_save_regs(struct lxfb_par *par) 585{ 586 uint32_t filt; 587 int i; 588 589 /* wait for the BLT engine to stop being busy */ 590 do { 591 i = read_gp(par, GP_BLT_STATUS); 592 } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE)); 593 594 /* save MSRs */ 595 rdmsrq(MSR_LX_MSR_PADSEL, par->msr.padsel); 596 rdmsrq(MSR_GLCP_DOTPLL, par->msr.dotpll); 597 rdmsrq(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); 598 rdmsrq(MSR_LX_SPARE_MSR, par->msr.dcspare); 599 600 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); 601 602 /* save registers */ 603 memcpy(par->gp, par->gp_regs, sizeof(par->gp)); 604 memcpy(par->dc, par->dc_regs, sizeof(par->dc)); 605 memcpy(par->vp, par->vp_regs, sizeof(par->vp)); 606 memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp)); 607 608 /* save the display controller palette */ 609 write_dc(par, DC_PAL_ADDRESS, 0); 610 for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++) 611 par->dc_pal[i] = read_dc(par, DC_PAL_DATA); 612 613 /* save the video processor palette */ 614 write_vp(par, VP_PAR, 0); 615 for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++) 616 par->vp_pal[i] = read_vp(par, VP_PDR); 617 618 /* save the horizontal filter coefficients */ 619 filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL; 620 for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) { 621 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); 622 par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1); 623 par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2); 624 } 625 626 /* save the vertical filter coefficients */ 627 filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL; 628 for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) { 629 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); 630 par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1); 631 } 632 633 /* save video coeff ram */ 634 memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff)); 635} 636 637static void lx_restore_gfx_proc(struct lxfb_par *par) 638{ 639 int i; 640 641 /* a bunch of registers require GP_RASTER_MODE to be set first */ 642 write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]); 643 644 for (i = 0; i < ARRAY_SIZE(par->gp); i++) { 645 switch (i) { 646 case GP_RASTER_MODE: 647 case GP_VECTOR_MODE: 648 case GP_BLT_MODE: 649 case GP_BLT_STATUS: 650 case GP_HST_SRC: 651 /* FIXME: restore LUT data */ 652 case GP_LUT_INDEX: 653 case GP_LUT_DATA: 654 /* don't restore these registers */ 655 break; 656 657 default: 658 write_gp(par, i, par->gp[i]); 659 } 660 } 661} 662 663static void lx_restore_display_ctlr(struct lxfb_par *par) 664{ 665 uint32_t filt; 666 int i; 667 668 wrmsrq(MSR_LX_SPARE_MSR, par->msr.dcspare); 669 670 for (i = 0; i < ARRAY_SIZE(par->dc); i++) { 671 switch (i) { 672 case DC_UNLOCK: 673 /* unlock the DC; runs first */ 674 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); 675 break; 676 677 case DC_GENERAL_CFG: 678 case DC_DISPLAY_CFG: 679 /* disable all while restoring */ 680 write_dc(par, i, 0); 681 break; 682 683 case DC_DV_CTL: 684 /* set all ram to dirty */ 685 write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM); 686 break; 687 688 case DC_RSVD_1: 689 case DC_RSVD_2: 690 case DC_RSVD_3: 691 case DC_LINE_CNT: 692 case DC_PAL_ADDRESS: 693 case DC_PAL_DATA: 694 case DC_DFIFO_DIAG: 695 case DC_CFIFO_DIAG: 696 case DC_FILT_COEFF1: 697 case DC_FILT_COEFF2: 698 case DC_RSVD_4: 699 case DC_RSVD_5: 700 /* don't restore these registers */ 701 break; 702 703 default: 704 write_dc(par, i, par->dc[i]); 705 } 706 } 707 708 /* restore the palette */ 709 write_dc(par, DC_PAL_ADDRESS, 0); 710 for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++) 711 write_dc(par, DC_PAL_DATA, par->dc_pal[i]); 712 713 /* restore the horizontal filter coefficients */ 714 filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL; 715 for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) { 716 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); 717 write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]); 718 write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]); 719 } 720 721 /* restore the vertical filter coefficients */ 722 filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL; 723 for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) { 724 write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); 725 write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]); 726 } 727} 728 729static void lx_restore_video_proc(struct lxfb_par *par) 730{ 731 int i; 732 733 wrmsrq(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); 734 wrmsrq(MSR_LX_MSR_PADSEL, par->msr.padsel); 735 736 for (i = 0; i < ARRAY_SIZE(par->vp); i++) { 737 switch (i) { 738 case VP_VCFG: 739 case VP_DCFG: 740 case VP_PAR: 741 case VP_PDR: 742 case VP_CCS: 743 case VP_RSVD_0: 744 /* case VP_VDC: */ /* why should this not be restored? */ 745 case VP_RSVD_1: 746 case VP_CRC32: 747 /* don't restore these registers */ 748 break; 749 750 default: 751 write_vp(par, i, par->vp[i]); 752 } 753 } 754 755 /* restore video processor palette */ 756 write_vp(par, VP_PAR, 0); 757 for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++) 758 write_vp(par, VP_PDR, par->vp_pal[i]); 759 760 /* restore video coeff ram */ 761 memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff)); 762} 763 764static void lx_restore_regs(struct lxfb_par *par) 765{ 766 int i; 767 768 lx_set_dotpll((u32) (par->msr.dotpll >> 32)); 769 lx_restore_gfx_proc(par); 770 lx_restore_display_ctlr(par); 771 lx_restore_video_proc(par); 772 773 /* Flat Panel */ 774 for (i = 0; i < ARRAY_SIZE(par->fp); i++) { 775 switch (i) { 776 case FP_PM: 777 case FP_RSVD_0: 778 case FP_RSVD_1: 779 case FP_RSVD_2: 780 case FP_RSVD_3: 781 case FP_RSVD_4: 782 /* don't restore these registers */ 783 break; 784 785 default: 786 write_fp(par, i, par->fp[i]); 787 } 788 } 789 790 /* control the panel */ 791 if (par->fp[FP_PM] & FP_PM_P) { 792 /* power on the panel if not already power{ed,ing} on */ 793 if (!(read_fp(par, FP_PM) & 794 (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP))) 795 write_fp(par, FP_PM, par->fp[FP_PM]); 796 } else { 797 /* power down the panel if not already power{ed,ing} down */ 798 if (!(read_fp(par, FP_PM) & 799 (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN))) 800 write_fp(par, FP_PM, par->fp[FP_PM]); 801 } 802 803 /* turn everything on */ 804 write_vp(par, VP_VCFG, par->vp[VP_VCFG]); 805 write_vp(par, VP_DCFG, par->vp[VP_DCFG]); 806 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]); 807 /* do this last; it will enable the FIFO load */ 808 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]); 809 810 /* lock the door behind us */ 811 write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); 812} 813 814int lx_powerdown(struct fb_info *info) 815{ 816 struct lxfb_par *par = info->par; 817 818 if (par->powered_down) 819 return 0; 820 821 lx_save_regs(par); 822 lx_graphics_disable(info); 823 824 par->powered_down = 1; 825 return 0; 826} 827 828int lx_powerup(struct fb_info *info) 829{ 830 struct lxfb_par *par = info->par; 831 832 if (!par->powered_down) 833 return 0; 834 835 lx_restore_regs(par); 836 837 par->powered_down = 0; 838 return 0; 839}
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