display_gx.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Geode GX display controller.
  4 *
  5 *   Copyright (C) 2005 Arcom Control Systems Ltd.
  6 *
  7 *   Portions from AMD's original 2.4 driver:
  8 *     Copyright (C) 2004 Advanced Micro Devices, Inc.
  9 */
 10#include <linux/spinlock.h>
 11#include <linux/fb.h>
 12#include <linux/delay.h>
 13#include <asm/io.h>
 14#include <asm/div64.h>
 15#include <asm/delay.h>
 16#include <asm/msr.h>
 17#include <linux/cs5535.h>
 18
 19#include "gxfb.h"
 20
 21unsigned int gx_frame_buffer_size(void)
 22{
 23	unsigned int val;
 24
 25	if (!cs5535_has_vsa2()) {
 26		uint32_t hi, lo;
 27
 28		/* The number of pages is (PMAX - PMIN)+1 */
 29		rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
 30
 31		/* PMAX */
 32		val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
 33		/* PMIN */
 34		val -= (lo & 0x000fffff);
 35		val += 1;
 36
 37		/* The page size is 4k */
 38		return (val << 12);
 39	}
 40
 41	/* FB size can be obtained from the VSA II */
 42	/* Virtual register class = 0x02 */
 43	/* VG_MEM_SIZE(512Kb units) = 0x00 */
 44
 45	outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
 46	outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
 47
 48	val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFFl;
 49	return (val << 19);
 50}
 51
 52int gx_line_delta(int xres, int bpp)
 53{
 54	/* Must be a multiple of 8 bytes. */
 55	return (xres * (bpp >> 3) + 7) & ~0x7;
 56}
 57
 58void gx_set_mode(struct fb_info *info)
 59{
 60	struct gxfb_par *par = info->par;
 61	u32 gcfg, dcfg;
 62	int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
 63	int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
 64
 65	/* Unlock the display controller registers. */
 66	write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 67
 68	gcfg = read_dc(par, DC_GENERAL_CFG);
 69	dcfg = read_dc(par, DC_DISPLAY_CFG);
 70
 71	/* Disable the timing generator. */
 72	dcfg &= ~DC_DISPLAY_CFG_TGEN;
 73	write_dc(par, DC_DISPLAY_CFG, dcfg);
 74
 75	/* Wait for pending memory requests before disabling the FIFO load. */
 76	udelay(100);
 77
 78	/* Disable FIFO load and compression. */
 79	gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
 80			DC_GENERAL_CFG_DECE);
 81	write_dc(par, DC_GENERAL_CFG, gcfg);
 82
 83	/* Setup DCLK and its divisor. */
 84	gx_set_dclk_frequency(info);
 85
 86	/*
 87	 * Setup new mode.
 88	 */
 89
 90	/* Clear all unused feature bits. */
 91	gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
 92	dcfg = 0;
 93
 94	/* Set FIFO priority (default 6/5) and enable. */
 95	/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
 96	gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
 97		(5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
 98
 99	/* Framebuffer start offset. */
100	write_dc(par, DC_FB_ST_OFFSET, 0);
101
102	/* Line delta and line buffer length. */
103	write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
104	write_dc(par, DC_LINE_SIZE,
105		((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
106
107
108	/* Enable graphics and video data and unmask address lines. */
109	dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
110		DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
111
112	/* Set pixel format. */
113	switch (info->var.bits_per_pixel) {
114	case 8:
115		dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
116		break;
117	case 16:
118		dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
119		break;
120	case 32:
121		dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
122		dcfg |= DC_DISPLAY_CFG_PALB;
123		break;
124	}
125
126	/* Enable timing generator. */
127	dcfg |= DC_DISPLAY_CFG_TGEN;
128
129	/* Horizontal and vertical timings. */
130	hactive = info->var.xres;
131	hblankstart = hactive;
132	hsyncstart = hblankstart + info->var.right_margin;
133	hsyncend =  hsyncstart + info->var.hsync_len;
134	hblankend = hsyncend + info->var.left_margin;
135	htotal = hblankend;
136
137	vactive = info->var.yres;
138	vblankstart = vactive;
139	vsyncstart = vblankstart + info->var.lower_margin;
140	vsyncend =  vsyncstart + info->var.vsync_len;
141	vblankend = vsyncend + info->var.upper_margin;
142	vtotal = vblankend;
143
144	write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1)    |
145			((htotal - 1) << 16));
146	write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
147			((hblankend - 1) << 16));
148	write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1)   |
149			((hsyncend - 1) << 16));
150
151	write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1)    |
152			((vtotal - 1) << 16));
153	write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
154			((vblankend - 1) << 16));
155	write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1)   |
156			((vsyncend - 1) << 16));
157
158	/* Write final register values. */
159	write_dc(par, DC_DISPLAY_CFG, dcfg);
160	write_dc(par, DC_GENERAL_CFG, gcfg);
161
162	gx_configure_display(info);
163
164	/* Relock display controller registers */
165	write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
166}
167
168void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
169		unsigned red, unsigned green, unsigned blue)
170{
171	struct gxfb_par *par = info->par;
172	int val;
173
174	/* Hardware palette is in RGB 8-8-8 format. */
175	val  = (red   << 8) & 0xff0000;
176	val |= (green)      & 0x00ff00;
177	val |= (blue  >> 8) & 0x0000ff;
178
179	write_dc(par, DC_PAL_ADDRESS, regno);
180	write_dc(par, DC_PAL_DATA, val);
181}