hisi_acc_vfio_pci.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2021 HiSilicon Ltd. */
  3
  4#ifndef HISI_ACC_VFIO_PCI_H
  5#define HISI_ACC_VFIO_PCI_H
  6
  7#include <linux/hisi_acc_qm.h>
  8
  9#define MB_POLL_PERIOD_US		10
 10#define MB_POLL_TIMEOUT_US		1000
 11#define QM_CACHE_WB_START		0x204
 12#define QM_CACHE_WB_DONE		0x208
 13#define QM_MB_CMD_PAUSE_QM		0xe
 14#define QM_ABNORMAL_INT_STATUS		0x100008
 15#define QM_IFC_INT_STATUS		0x0028
 16#define SEC_CORE_INT_STATUS		0x301008
 17#define HPRE_HAC_INT_STATUS		0x301800
 18#define HZIP_CORE_INT_STATUS		0x3010AC
 19
 20#define QM_VFT_CFG_RDY			0x10006c
 21#define QM_VFT_CFG_OP_WR		0x100058
 22#define QM_VFT_CFG_TYPE			0x10005c
 23#define QM_VFT_CFG			0x100060
 24#define QM_VFT_CFG_OP_ENABLE		0x100054
 25#define QM_VFT_CFG_DATA_L		0x100064
 26#define QM_VFT_CFG_DATA_H		0x100068
 27
 28#define ERROR_CHECK_TIMEOUT		100
 29#define CHECK_DELAY_TIME		100
 30#define QM_RESET_WAIT_TIMEOUT  60000
 31
 32#define QM_SQC_VFT_BASE_SHIFT_V2	28
 33#define QM_SQC_VFT_BASE_MASK_V2		GENMASK(15, 0)
 34#define QM_SQC_VFT_NUM_SHIFT_V2		45
 35#define QM_SQC_VFT_NUM_MASK_V2		GENMASK(9, 0)
 36#define QM_MB_CMD_NOT_READY	0xffffffff
 37
 38/* RW regs */
 39#define QM_REGS_MAX_LEN		7
 40#define QM_REG_ADDR_OFFSET	0x0004
 41
 42#define QM_XQC_ADDR_OFFSET	32U
 43#define QM_XQC_ADDR_LOW	0x1
 44#define QM_XQC_ADDR_HIGH	0x2
 45
 46#define QM_VF_AEQ_INT_MASK	0x0004
 47#define QM_VF_EQ_INT_MASK	0x000c
 48#define QM_IFC_INT_SOURCE_V	0x0020
 49#define QM_IFC_INT_MASK		0x0024
 50#define QM_IFC_INT_SET_V	0x002c
 51#define QM_QUE_ISO_CFG_V	0x0030
 52#define QM_PAGE_SIZE		0x0034
 53
 54#define QM_EQC_VF_DW0		0X8000
 55#define QM_AEQC_VF_DW0		0X8020
 56#define QM_EQC_PF_DW0		0x1c00
 57#define QM_AEQC_PF_DW0		0x1c20
 58
 59#define ACC_DRV_MAJOR_VER 1
 60#define ACC_DRV_MINOR_VER 0
 61
 62#define ACC_DEV_MAGIC_V1	0XCDCDCDCDFEEDAACC
 63#define ACC_DEV_MAGIC_V2	0xAACCFEEDDECADEDE
 64
 65#define QM_MIG_REGION_OFFSET		0x180000
 66#define QM_MIG_REGION_SIZE		0x2000
 67
 68/**
 69 * On HW_ACC_MIG_VF_CTRL mode, the configuration domain supporting live
 70 * migration functionality is located in the latter 32KB of the VF's BAR2.
 71 * The Guest is only provided with the first 32KB of the VF's BAR2.
 72 * On HW_ACC_MIG_PF_CTRL mode, the configuration domain supporting live
 73 * migration functionality is located in the PF's BAR2, and the entire 64KB
 74 * of the VF's BAR2 is allocated to the Guest.
 75 */
 76enum hw_drv_mode {
 77	HW_ACC_MIG_VF_CTRL = 0,
 78	HW_ACC_MIG_PF_CTRL,
 79};
 80
 81struct acc_vf_data {
 82#define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
 83	/* QM match information */
 84	u64 acc_magic;
 85	u32 qp_num;
 86	u32 dev_id;
 87	u32 que_iso_cfg;
 88	u32 qp_base;
 89	u32 vf_qm_state;
 90	/* QM reserved match information */
 91	u16 major_ver;
 92	u16 minor_ver;
 93	u32 qm_rsv_state[2];
 94
 95	/* QM RW regs */
 96	u32 aeq_int_mask;
 97	u32 eq_int_mask;
 98	u32 ifc_int_source;
 99	u32 ifc_int_mask;
100	u32 ifc_int_set;
101	u32 page_size;
102
103	/* QM_EQC_DW has 7 regs */
104	u32 qm_eqc_dw[7];
105
106	/* QM_AEQC_DW has 7 regs */
107	u32 qm_aeqc_dw[7];
108
109	/* QM reserved 5 regs */
110	u32 qm_rsv_regs[5];
111	u32 padding;
112	/* QM memory init information */
113	u64 eqe_dma;
114	u64 aeqe_dma;
115	u64 sqc_dma;
116	u64 cqc_dma;
117};
118
119struct hisi_acc_vf_migration_file {
120	struct file *filp;
121	struct mutex lock;
122	bool disabled;
123
124	struct hisi_acc_vf_core_device *hisi_acc_vdev;
125	struct acc_vf_data vf_data;
126	size_t total_length;
127};
128
129struct hisi_acc_vf_core_device {
130	struct vfio_pci_core_device core_device;
131	u8 match_done;
132	bool set_reset_flag;
133	/*
134	 * io_base is only valid when dev_opened is true,
135	 * which is protected by open_mutex.
136	 */
137	bool dev_opened;
138	/* Ensure the accuracy of dev_opened operation */
139	struct mutex open_mutex;
140
141	/* For migration state */
142	struct mutex state_mutex;
143	enum vfio_device_mig_state mig_state;
144	struct pci_dev *pf_dev;
145	struct pci_dev *vf_dev;
146	struct hisi_qm *pf_qm;
147	struct hisi_qm vf_qm;
148	enum hw_drv_mode drv_mode;
149	/*
150	 * vf_qm_state represents the QM_VF_STATE register value.
151	 * It is set by Guest driver for the ACC VF dev indicating
152	 * the driver has loaded and configured the dev correctly.
153	 */
154	u32 vf_qm_state;
155	int vf_id;
156	struct hisi_acc_vf_migration_file *resuming_migf;
157	struct hisi_acc_vf_migration_file *saving_migf;
158
159	/*
160	 * It holds migration data corresponding to the last migration
161	 * and is used by the debugfs interface to report it.
162	 */
163	struct hisi_acc_vf_migration_file *debug_migf;
164};
165#endif /* HISI_ACC_VFIO_PCI_H */