octep_vdpa.h

  1/* SPDX-License-Identifier: GPL-2.0-only
  2 * Copyright (C) 2024 Marvell.
  3 */
  4#ifndef __OCTEP_VDPA_H__
  5#define __OCTEP_VDPA_H__
  6
  7#include <linux/pci.h>
  8#include <linux/pci_regs.h>
  9#include <linux/vdpa.h>
 10#include <linux/virtio_pci_modern.h>
 11#include <uapi/linux/virtio_crypto.h>
 12#include <uapi/linux/virtio_net.h>
 13#include <uapi/linux/virtio_blk.h>
 14#include <uapi/linux/virtio_config.h>
 15#include <uapi/linux/virtio_pci.h>
 16#include <uapi/linux/vdpa.h>
 17
 18#define OCTEP_VDPA_DEVID_CN106K_PF 0xb900
 19#define OCTEP_VDPA_DEVID_CN106K_VF 0xb903
 20#define OCTEP_VDPA_DEVID_CN105K_PF 0xba00
 21#define OCTEP_VDPA_DEVID_CN105K_VF 0xba03
 22#define OCTEP_VDPA_DEVID_CN103K_PF 0xbd00
 23#define OCTEP_VDPA_DEVID_CN103K_VF 0xbd03
 24
 25#define OCTEP_HW_MBOX_BAR 0
 26#define OCTEP_HW_CAPS_BAR 4
 27
 28#define OCTEP_DEV_READY_SIGNATURE 0xBABABABA
 29
 30#define OCTEP_EPF_RINFO(x) (0x000209f0 | ((x) << 25))
 31#define OCTEP_VF_MBOX_DATA(x) (0x00010210 | ((x) << 17))
 32#define OCTEP_PF_MBOX_DATA(x) (0x00022000 | ((x) << 4))
 33#define OCTEP_VF_IN_CTRL(x)        (0x00010000 | ((x) << 17))
 34#define OCTEP_VF_IN_CTRL_RPVF(val) (((val) >> 48) & 0xF)
 35
 36#define OCTEP_FW_READY_SIGNATURE0  0xFEEDFEED
 37#define OCTEP_FW_READY_SIGNATURE1  0x3355ffaa
 38#define OCTEP_MAX_CB_INTR          8
 39
 40enum octep_vdpa_dev_status {
 41	OCTEP_VDPA_DEV_STATUS_INVALID,
 42	OCTEP_VDPA_DEV_STATUS_ALLOC,
 43	OCTEP_VDPA_DEV_STATUS_WAIT_FOR_BAR_INIT,
 44	OCTEP_VDPA_DEV_STATUS_INIT,
 45	OCTEP_VDPA_DEV_STATUS_READY,
 46	OCTEP_VDPA_DEV_STATUS_UNINIT
 47};
 48
 49struct octep_vring_info {
 50	struct vdpa_callback cb;
 51	void __iomem *notify_addr;
 52	void __iomem *cb_notify_addr;
 53	phys_addr_t notify_pa;
 54};
 55
 56enum octep_pci_vndr_cfg_type {
 57	OCTEP_PCI_VNDR_CFG_TYPE_VIRTIO_ID,
 58	OCTEP_PCI_VNDR_CFG_TYPE_MAX,
 59};
 60
 61struct octep_pci_vndr_data {
 62	struct virtio_pci_vndr_data hdr;
 63	u8 id;
 64	u8 bar;
 65	union {
 66		u64 data;
 67		struct {
 68			u32 offset;
 69			u32 length;
 70		};
 71	};
 72};
 73
 74struct octep_hw {
 75	struct pci_dev *pdev;
 76	u8 __iomem *base[PCI_STD_NUM_BARS];
 77	struct virtio_pci_common_cfg __iomem *common_cfg;
 78	u8 __iomem *dev_cfg;
 79	u8 __iomem *isr;
 80	void __iomem *notify_base;
 81	phys_addr_t notify_base_pa;
 82	u32 notify_off_multiplier;
 83	u8 notify_bar;
 84	struct octep_vring_info *vqs;
 85	struct vdpa_callback config_cb;
 86	u64 features;
 87	u16 nr_vring;
 88	u32 config_size;
 89	int nb_irqs;
 90	int *irqs;
 91	u8 dev_id;
 92};
 93
 94u8 octep_hw_get_status(struct octep_hw *oct_hw);
 95void octep_hw_set_status(struct octep_hw *dev, uint8_t status);
 96void octep_hw_reset(struct octep_hw *oct_hw);
 97void octep_write_queue_select(struct octep_hw *oct_hw, u16 queue_id);
 98void octep_notify_queue(struct octep_hw *oct_hw, u16 qid);
 99void octep_read_dev_config(struct octep_hw *oct_hw, u64 offset, void *dst, int length);
100int octep_set_vq_address(struct octep_hw *oct_hw, u16 qid, u64 desc_area, u64 driver_area,
101			 u64 device_area);
102void octep_set_vq_num(struct octep_hw *oct_hw, u16 qid, u32 num);
103void octep_set_vq_ready(struct octep_hw *oct_hw, u16 qid, bool ready);
104bool octep_get_vq_ready(struct octep_hw *oct_hw, u16 qid);
105int octep_set_vq_state(struct octep_hw *oct_hw, u16 qid, const struct vdpa_vq_state *state);
106int octep_get_vq_state(struct octep_hw *oct_hw, u16 qid, struct vdpa_vq_state *state);
107u16 octep_get_vq_size(struct octep_hw *oct_hw);
108int octep_hw_caps_read(struct octep_hw *oct_hw, struct pci_dev *pdev);
109u64 octep_hw_get_dev_features(struct octep_hw *oct_hw);
110void octep_hw_set_drv_features(struct octep_hw *oct_hw, u64 features);
111u64 octep_hw_get_drv_features(struct octep_hw *oct_hw);
112int octep_verify_features(u64 features);
113
114#endif /* __OCTEP_VDPA_H__ */