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musb_core.c
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linux-6.19.14/drivers/usb/musb/musb_core.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * MUSB OTG driver core code 4 * 5 * Copyright 2005 Mentor Graphics Corporation 6 * Copyright (C) 2005-2006 by Texas Instruments 7 * Copyright (C) 2006-2007 Nokia Corporation 8 */ 9 10/* 11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 12 * 13 * This consists of a Host Controller Driver (HCD) and a peripheral 14 * controller driver implementing the "Gadget" API; OTG support is 15 * in the works. These are normal Linux-USB controller drivers which 16 * use IRQs and have no dedicated thread. 17 * 18 * This version of the driver has only been used with products from 19 * Texas Instruments. Those products integrate the Inventra logic 20 * with other DMA, IRQ, and bus modules, as well as other logic that 21 * needs to be reflected in this driver. 22 * 23 * 24 * NOTE: the original Mentor code here was pretty much a collection 25 * of mechanisms that don't seem to have been fully integrated/working 26 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 27 * Key open issues include: 28 * 29 * - Lack of host-side transaction scheduling, for all transfer types. 30 * The hardware doesn't do it; instead, software must. 31 * 32 * This is not an issue for OTG devices that don't support external 33 * hubs, but for more "normal" USB hosts it's a user issue that the 34 * "multipoint" support doesn't scale in the expected ways. That 35 * includes DaVinci EVM in a common non-OTG mode. 36 * 37 * * Control and bulk use dedicated endpoints, and there's as 38 * yet no mechanism to either (a) reclaim the hardware when 39 * peripherals are NAKing, which gets complicated with bulk 40 * endpoints, or (b) use more than a single bulk endpoint in 41 * each direction. 42 * 43 * RESULT: one device may be perceived as blocking another one. 44 * 45 * * Interrupt and isochronous will dynamically allocate endpoint 46 * hardware, but (a) there's no record keeping for bandwidth; 47 * (b) in the common case that few endpoints are available, there 48 * is no mechanism to reuse endpoints to talk to multiple devices. 49 * 50 * RESULT: At one extreme, bandwidth can be overcommitted in 51 * some hardware configurations, no faults will be reported. 52 * At the other extreme, the bandwidth capabilities which do 53 * exist tend to be severely undercommitted. You can't yet hook 54 * up both a keyboard and a mouse to an external USB hub. 55 */ 56 57/* 58 * This gets many kinds of configuration information: 59 * - Kconfig for everything user-configurable 60 * - platform_device for addressing, irq, and platform_data 61 * - platform_data is mostly for board-specific information 62 * (plus recentrly, SOC or family details) 63 * 64 * Most of the conditional compilation will (someday) vanish. 65 */ 66 67#include <linux/module.h> 68#include <linux/kernel.h> 69#include <linux/sched.h> 70#include <linux/slab.h> 71#include <linux/list.h> 72#include <linux/kobject.h> 73#include <linux/prefetch.h> 74#include <linux/platform_device.h> 75#include <linux/string_choices.h> 76#include <linux/io.h> 77#include <linux/iopoll.h> 78#include <linux/dma-mapping.h> 79#include <linux/usb.h> 80#include <linux/usb/of.h> 81 82#include "musb_core.h" 83#include "musb_trace.h" 84 85#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 86 87 88#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 89#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 90 91#define MUSB_VERSION "6.0" 92 93#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 94 95#define MUSB_DRIVER_NAME "musb-hdrc" 96const char musb_driver_name[] = MUSB_DRIVER_NAME; 97 98MODULE_DESCRIPTION(DRIVER_INFO); 99MODULE_AUTHOR(DRIVER_AUTHOR); 100MODULE_LICENSE("GPL"); 101MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 102 103 104/*-------------------------------------------------------------------------*/ 105 106static inline struct musb *dev_to_musb(struct device *dev) 107{ 108 return dev_get_drvdata(dev); 109} 110 111enum musb_mode musb_get_mode(struct device *dev) 112{ 113 enum usb_dr_mode mode; 114 115 mode = usb_get_dr_mode(dev); 116 switch (mode) { 117 case USB_DR_MODE_HOST: 118 return MUSB_HOST; 119 case USB_DR_MODE_PERIPHERAL: 120 return MUSB_PERIPHERAL; 121 case USB_DR_MODE_OTG: 122 case USB_DR_MODE_UNKNOWN: 123 default: 124 return MUSB_OTG; 125 } 126} 127EXPORT_SYMBOL_GPL(musb_get_mode); 128 129/*-------------------------------------------------------------------------*/ 130 131static int musb_ulpi_read(struct usb_phy *phy, u32 reg) 132{ 133 void __iomem *addr = phy->io_priv; 134 int i = 0; 135 u8 r; 136 u8 power; 137 int ret; 138 139 pm_runtime_get_sync(phy->io_dev); 140 141 /* Make sure the transceiver is not in low power mode */ 142 power = musb_readb(addr, MUSB_POWER); 143 power &= ~MUSB_POWER_SUSPENDM; 144 musb_writeb(addr, MUSB_POWER, power); 145 146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 148 */ 149 150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); 151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 153 154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 155 & MUSB_ULPI_REG_CMPLT)) { 156 i++; 157 if (i == 10000) { 158 ret = -ETIMEDOUT; 159 goto out; 160 } 161 162 } 163 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 164 r &= ~MUSB_ULPI_REG_CMPLT; 165 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 166 167 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 168 169out: 170 pm_runtime_put(phy->io_dev); 171 172 return ret; 173} 174 175static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg) 176{ 177 void __iomem *addr = phy->io_priv; 178 int i = 0; 179 u8 r = 0; 180 u8 power; 181 int ret = 0; 182 183 pm_runtime_get_sync(phy->io_dev); 184 185 /* Make sure the transceiver is not in low power mode */ 186 power = musb_readb(addr, MUSB_POWER); 187 power &= ~MUSB_POWER_SUSPENDM; 188 musb_writeb(addr, MUSB_POWER, power); 189 190 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); 191 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val); 192 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 193 194 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 195 & MUSB_ULPI_REG_CMPLT)) { 196 i++; 197 if (i == 10000) { 198 ret = -ETIMEDOUT; 199 goto out; 200 } 201 } 202 203 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 204 r &= ~MUSB_ULPI_REG_CMPLT; 205 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 206 207out: 208 pm_runtime_put(phy->io_dev); 209 210 return ret; 211} 212 213static struct usb_phy_io_ops musb_ulpi_access = { 214 .read = musb_ulpi_read, 215 .write = musb_ulpi_write, 216}; 217 218/*-------------------------------------------------------------------------*/ 219 220static u32 musb_default_fifo_offset(u8 epnum) 221{ 222 return 0x20 + (epnum * 4); 223} 224 225/* "flat" mapping: each endpoint has its own i/o address */ 226static void musb_flat_ep_select(void __iomem *mbase, u8 epnum) 227{ 228} 229 230static u32 musb_flat_ep_offset(u8 epnum, u16 offset) 231{ 232 return 0x100 + (0x10 * epnum) + offset; 233} 234 235/* "indexed" mapping: INDEX register controls register bank select */ 236static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum) 237{ 238 musb_writeb(mbase, MUSB_INDEX, epnum); 239} 240 241static u32 musb_indexed_ep_offset(u8 epnum, u16 offset) 242{ 243 return 0x10 + offset; 244} 245 246static u32 musb_default_busctl_offset(u8 epnum, u16 offset) 247{ 248 return 0x80 + (0x08 * epnum) + offset; 249} 250 251static u8 musb_default_readb(void __iomem *addr, u32 offset) 252{ 253 u8 data = __raw_readb(addr + offset); 254 255 trace_musb_readb(__builtin_return_address(0), addr, offset, data); 256 return data; 257} 258 259static void musb_default_writeb(void __iomem *addr, u32 offset, u8 data) 260{ 261 trace_musb_writeb(__builtin_return_address(0), addr, offset, data); 262 __raw_writeb(data, addr + offset); 263} 264 265static u16 musb_default_readw(void __iomem *addr, u32 offset) 266{ 267 u16 data = __raw_readw(addr + offset); 268 269 trace_musb_readw(__builtin_return_address(0), addr, offset, data); 270 return data; 271} 272 273static void musb_default_writew(void __iomem *addr, u32 offset, u16 data) 274{ 275 trace_musb_writew(__builtin_return_address(0), addr, offset, data); 276 __raw_writew(data, addr + offset); 277} 278 279static u16 musb_default_get_toggle(struct musb_qh *qh, int is_out) 280{ 281 void __iomem *epio = qh->hw_ep->regs; 282 u16 csr; 283 284 if (is_out) 285 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; 286 else 287 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; 288 289 return csr; 290} 291 292static u16 musb_default_set_toggle(struct musb_qh *qh, int is_out, 293 struct urb *urb) 294{ 295 u16 csr; 296 u16 toggle; 297 298 toggle = usb_gettoggle(urb->dev, qh->epnum, is_out); 299 300 if (is_out) 301 csr = toggle ? (MUSB_TXCSR_H_WR_DATATOGGLE 302 | MUSB_TXCSR_H_DATATOGGLE) 303 : MUSB_TXCSR_CLRDATATOG; 304 else 305 csr = toggle ? (MUSB_RXCSR_H_WR_DATATOGGLE 306 | MUSB_RXCSR_H_DATATOGGLE) : 0; 307 308 return csr; 309} 310 311/* 312 * Load an endpoint's FIFO 313 */ 314static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len, 315 const u8 *src) 316{ 317 struct musb *musb = hw_ep->musb; 318 void __iomem *fifo = hw_ep->fifo; 319 320 if (unlikely(len == 0)) 321 return; 322 323 prefetch((u8 *)src); 324 325 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 326 'T', hw_ep->epnum, fifo, len, src); 327 328 /* we can't assume unaligned reads work */ 329 if (likely((0x01 & (unsigned long) src) == 0)) { 330 u16 index = 0; 331 332 /* best case is 32bit-aligned source address */ 333 if ((0x02 & (unsigned long) src) == 0) { 334 if (len >= 4) { 335 iowrite32_rep(fifo, src + index, len >> 2); 336 index += len & ~0x03; 337 } 338 if (len & 0x02) { 339 __raw_writew(*(u16 *)&src[index], fifo); 340 index += 2; 341 } 342 } else { 343 if (len >= 2) { 344 iowrite16_rep(fifo, src + index, len >> 1); 345 index += len & ~0x01; 346 } 347 } 348 if (len & 0x01) 349 __raw_writeb(src[index], fifo); 350 } else { 351 /* byte aligned */ 352 iowrite8_rep(fifo, src, len); 353 } 354} 355 356/* 357 * Unload an endpoint's FIFO 358 */ 359static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 360{ 361 struct musb *musb = hw_ep->musb; 362 void __iomem *fifo = hw_ep->fifo; 363 364 if (unlikely(len == 0)) 365 return; 366 367 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 368 'R', hw_ep->epnum, fifo, len, dst); 369 370 /* we can't assume unaligned writes work */ 371 if (likely((0x01 & (unsigned long) dst) == 0)) { 372 u16 index = 0; 373 374 /* best case is 32bit-aligned destination address */ 375 if ((0x02 & (unsigned long) dst) == 0) { 376 if (len >= 4) { 377 ioread32_rep(fifo, dst, len >> 2); 378 index = len & ~0x03; 379 } 380 if (len & 0x02) { 381 *(u16 *)&dst[index] = __raw_readw(fifo); 382 index += 2; 383 } 384 } else { 385 if (len >= 2) { 386 ioread16_rep(fifo, dst, len >> 1); 387 index = len & ~0x01; 388 } 389 } 390 if (len & 0x01) 391 dst[index] = __raw_readb(fifo); 392 } else { 393 /* byte aligned */ 394 ioread8_rep(fifo, dst, len); 395 } 396} 397 398/* 399 * Old style IO functions 400 */ 401u8 (*musb_readb)(void __iomem *addr, u32 offset); 402EXPORT_SYMBOL_GPL(musb_readb); 403 404void (*musb_writeb)(void __iomem *addr, u32 offset, u8 data); 405EXPORT_SYMBOL_GPL(musb_writeb); 406 407u8 (*musb_clearb)(void __iomem *addr, u32 offset); 408EXPORT_SYMBOL_GPL(musb_clearb); 409 410u16 (*musb_readw)(void __iomem *addr, u32 offset); 411EXPORT_SYMBOL_GPL(musb_readw); 412 413void (*musb_writew)(void __iomem *addr, u32 offset, u16 data); 414EXPORT_SYMBOL_GPL(musb_writew); 415 416u16 (*musb_clearw)(void __iomem *addr, u32 offset); 417EXPORT_SYMBOL_GPL(musb_clearw); 418 419u32 musb_readl(void __iomem *addr, u32 offset) 420{ 421 u32 data = __raw_readl(addr + offset); 422 423 trace_musb_readl(__builtin_return_address(0), addr, offset, data); 424 return data; 425} 426EXPORT_SYMBOL_GPL(musb_readl); 427 428void musb_writel(void __iomem *addr, u32 offset, u32 data) 429{ 430 trace_musb_writel(__builtin_return_address(0), addr, offset, data); 431 __raw_writel(data, addr + offset); 432} 433EXPORT_SYMBOL_GPL(musb_writel); 434 435#ifndef CONFIG_MUSB_PIO_ONLY 436struct dma_controller * 437(*musb_dma_controller_create)(struct musb *musb, void __iomem *base); 438EXPORT_SYMBOL(musb_dma_controller_create); 439 440void (*musb_dma_controller_destroy)(struct dma_controller *c); 441EXPORT_SYMBOL(musb_dma_controller_destroy); 442#endif 443 444/* 445 * New style IO functions 446 */ 447void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 448{ 449 return hw_ep->musb->io.read_fifo(hw_ep, len, dst); 450} 451 452void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 453{ 454 return hw_ep->musb->io.write_fifo(hw_ep, len, src); 455} 456 457static u8 musb_read_devctl(struct musb *musb) 458{ 459 return musb_readb(musb->mregs, MUSB_DEVCTL); 460} 461 462/** 463 * musb_set_host - set and initialize host mode 464 * @musb: musb controller driver data 465 * 466 * At least some musb revisions need to enable devctl session bit in 467 * peripheral mode to switch to host mode. Initializes things to host 468 * mode and sets A_IDLE. SoC glue needs to advance state further 469 * based on phy provided VBUS state. 470 * 471 * Note that the SoC glue code may need to wait for musb to settle 472 * on enable before calling this to avoid babble. 473 */ 474int musb_set_host(struct musb *musb) 475{ 476 int error = 0; 477 u8 devctl; 478 479 if (!musb) 480 return -EINVAL; 481 482 devctl = musb_read_devctl(musb); 483 if (!(devctl & MUSB_DEVCTL_BDEVICE)) { 484 trace_musb_state(musb, devctl, "Already in host mode"); 485 goto init_data; 486 } 487 488 devctl |= MUSB_DEVCTL_SESSION; 489 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 490 491 error = readx_poll_timeout(musb_read_devctl, musb, devctl, 492 !(devctl & MUSB_DEVCTL_BDEVICE), 5000, 493 1000000); 494 if (error) { 495 dev_err(musb->controller, "%s: could not set host: %02x\n", 496 __func__, devctl); 497 498 return error; 499 } 500 501 devctl = musb_read_devctl(musb); 502 trace_musb_state(musb, devctl, "Host mode set"); 503 504init_data: 505 musb->is_active = 1; 506 musb_set_state(musb, OTG_STATE_A_IDLE); 507 MUSB_HST_MODE(musb); 508 509 return error; 510} 511EXPORT_SYMBOL_GPL(musb_set_host); 512 513/** 514 * musb_set_peripheral - set and initialize peripheral mode 515 * @musb: musb controller driver data 516 * 517 * Clears devctl session bit and initializes things for peripheral 518 * mode and sets B_IDLE. SoC glue needs to advance state further 519 * based on phy provided VBUS state. 520 */ 521int musb_set_peripheral(struct musb *musb) 522{ 523 int error = 0; 524 u8 devctl; 525 526 if (!musb) 527 return -EINVAL; 528 529 devctl = musb_read_devctl(musb); 530 if (devctl & MUSB_DEVCTL_BDEVICE) { 531 trace_musb_state(musb, devctl, "Already in peripheral mode"); 532 goto init_data; 533 } 534 535 devctl &= ~MUSB_DEVCTL_SESSION; 536 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 537 538 error = readx_poll_timeout(musb_read_devctl, musb, devctl, 539 devctl & MUSB_DEVCTL_BDEVICE, 5000, 540 1000000); 541 if (error) { 542 dev_err(musb->controller, "%s: could not set peripheral: %02x\n", 543 __func__, devctl); 544 545 return error; 546 } 547 548 devctl = musb_read_devctl(musb); 549 trace_musb_state(musb, devctl, "Peripheral mode set"); 550 551init_data: 552 musb->is_active = 0; 553 musb_set_state(musb, OTG_STATE_B_IDLE); 554 MUSB_DEV_MODE(musb); 555 556 return error; 557} 558EXPORT_SYMBOL_GPL(musb_set_peripheral); 559 560/*-------------------------------------------------------------------------*/ 561 562/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 563static const u8 musb_test_packet[53] = { 564 /* implicit SYNC then DATA0 to start */ 565 566 /* JKJKJKJK x9 */ 567 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 568 /* JJKKJJKK x8 */ 569 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 570 /* JJJJKKKK x8 */ 571 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 572 /* JJJJJJJKKKKKKK x8 */ 573 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 574 /* JJJJJJJK x8 */ 575 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 576 /* JKKKKKKK x10, JK */ 577 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 578 579 /* implicit CRC16 then EOP to end */ 580}; 581 582void musb_load_testpacket(struct musb *musb) 583{ 584 void __iomem *regs = musb->endpoints[0].regs; 585 586 musb_ep_select(musb->mregs, 0); 587 musb_write_fifo(musb->control_ep, 588 sizeof(musb_test_packet), musb_test_packet); 589 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 590} 591 592/*-------------------------------------------------------------------------*/ 593 594/* 595 * Handles OTG hnp timeouts, such as b_ase0_brst 596 */ 597static void musb_otg_timer_func(struct timer_list *t) 598{ 599 struct musb *musb = timer_container_of(musb, t, otg_timer); 600 unsigned long flags; 601 602 spin_lock_irqsave(&musb->lock, flags); 603 switch (musb_get_state(musb)) { 604 case OTG_STATE_B_WAIT_ACON: 605 musb_dbg(musb, 606 "HNP: b_wait_acon timeout; back to b_peripheral"); 607 musb_g_disconnect(musb); 608 musb_set_state(musb, OTG_STATE_B_PERIPHERAL); 609 musb->is_active = 0; 610 break; 611 case OTG_STATE_A_SUSPEND: 612 case OTG_STATE_A_WAIT_BCON: 613 musb_dbg(musb, "HNP: %s timeout", 614 musb_otg_state_string(musb)); 615 musb_platform_set_vbus(musb, 0); 616 musb_set_state(musb, OTG_STATE_A_WAIT_VFALL); 617 break; 618 default: 619 musb_dbg(musb, "HNP: Unhandled mode %s", 620 musb_otg_state_string(musb)); 621 } 622 spin_unlock_irqrestore(&musb->lock, flags); 623} 624 625/* 626 * Stops the HNP transition. Caller must take care of locking. 627 */ 628void musb_hnp_stop(struct musb *musb) 629{ 630 struct usb_hcd *hcd = musb->hcd; 631 void __iomem *mbase = musb->mregs; 632 u8 reg; 633 634 musb_dbg(musb, "HNP: stop from %s", musb_otg_state_string(musb)); 635 636 switch (musb_get_state(musb)) { 637 case OTG_STATE_A_PERIPHERAL: 638 musb_g_disconnect(musb); 639 musb_dbg(musb, "HNP: back to %s", musb_otg_state_string(musb)); 640 break; 641 case OTG_STATE_B_HOST: 642 musb_dbg(musb, "HNP: Disabling HR"); 643 if (hcd) 644 hcd->self.is_b_host = 0; 645 musb_set_state(musb, OTG_STATE_B_PERIPHERAL); 646 MUSB_DEV_MODE(musb); 647 reg = musb_readb(mbase, MUSB_POWER); 648 reg |= MUSB_POWER_SUSPENDM; 649 musb_writeb(mbase, MUSB_POWER, reg); 650 /* REVISIT: Start SESSION_REQUEST here? */ 651 break; 652 default: 653 musb_dbg(musb, "HNP: Stopping in unknown state %s", 654 musb_otg_state_string(musb)); 655 } 656 657 /* 658 * When returning to A state after HNP, avoid hub_port_rebounce(), 659 * which cause occasional OPT A "Did not receive reset after connect" 660 * errors. 661 */ 662 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 663} 664 665static void musb_recover_from_babble(struct musb *musb); 666 667static void musb_handle_intr_resume(struct musb *musb, u8 devctl) 668{ 669 musb_dbg(musb, "RESUME (%s)", musb_otg_state_string(musb)); 670 671 if (devctl & MUSB_DEVCTL_HM) { 672 switch (musb_get_state(musb)) { 673 case OTG_STATE_A_SUSPEND: 674 /* remote wakeup? */ 675 musb->port1_status |= 676 (USB_PORT_STAT_C_SUSPEND << 16) 677 | MUSB_PORT_STAT_RESUME; 678 musb->rh_timer = jiffies 679 + msecs_to_jiffies(USB_RESUME_TIMEOUT); 680 musb_set_state(musb, OTG_STATE_A_HOST); 681 musb->is_active = 1; 682 musb_host_resume_root_hub(musb); 683 schedule_delayed_work(&musb->finish_resume_work, 684 msecs_to_jiffies(USB_RESUME_TIMEOUT)); 685 break; 686 case OTG_STATE_B_WAIT_ACON: 687 musb_set_state(musb, OTG_STATE_B_PERIPHERAL); 688 musb->is_active = 1; 689 MUSB_DEV_MODE(musb); 690 break; 691 default: 692 WARNING("bogus %s RESUME (%s)\n", 693 "host", 694 musb_otg_state_string(musb)); 695 } 696 } else { 697 switch (musb_get_state(musb)) { 698 case OTG_STATE_A_SUSPEND: 699 /* possibly DISCONNECT is upcoming */ 700 musb_set_state(musb, OTG_STATE_A_HOST); 701 musb_host_resume_root_hub(musb); 702 break; 703 case OTG_STATE_B_WAIT_ACON: 704 case OTG_STATE_B_PERIPHERAL: 705 /* disconnect while suspended? we may 706 * not get a disconnect irq... 707 */ 708 if ((devctl & MUSB_DEVCTL_VBUS) 709 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 710 ) { 711 musb->int_usb |= MUSB_INTR_DISCONNECT; 712 musb->int_usb &= ~MUSB_INTR_SUSPEND; 713 break; 714 } 715 musb_g_resume(musb); 716 break; 717 case OTG_STATE_B_IDLE: 718 musb->int_usb &= ~MUSB_INTR_SUSPEND; 719 break; 720 default: 721 WARNING("bogus %s RESUME (%s)\n", 722 "peripheral", 723 musb_otg_state_string(musb)); 724 } 725 } 726} 727 728/* return IRQ_HANDLED to tell the caller to return immediately */ 729static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl) 730{ 731 void __iomem *mbase = musb->mregs; 732 733 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 734 && (devctl & MUSB_DEVCTL_BDEVICE)) { 735 musb_dbg(musb, "SessReq while on B state"); 736 return IRQ_HANDLED; 737 } 738 739 musb_dbg(musb, "SESSION_REQUEST (%s)", musb_otg_state_string(musb)); 740 741 /* IRQ arrives from ID pin sense or (later, if VBUS power 742 * is removed) SRP. responses are time critical: 743 * - turn on VBUS (with silicon-specific mechanism) 744 * - go through A_WAIT_VRISE 745 * - ... to A_WAIT_BCON. 746 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 747 */ 748 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 749 musb->ep0_stage = MUSB_EP0_START; 750 musb_set_state(musb, OTG_STATE_A_IDLE); 751 MUSB_HST_MODE(musb); 752 musb_platform_set_vbus(musb, 1); 753 754 return IRQ_NONE; 755} 756 757static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl) 758{ 759 int ignore = 0; 760 761 /* During connection as an A-Device, we may see a short 762 * current spikes causing voltage drop, because of cable 763 * and peripheral capacitance combined with vbus draw. 764 * (So: less common with truly self-powered devices, where 765 * vbus doesn't act like a power supply.) 766 * 767 * Such spikes are short; usually less than ~500 usec, max 768 * of ~2 msec. That is, they're not sustained overcurrent 769 * errors, though they're reported using VBUSERROR irqs. 770 * 771 * Workarounds: (a) hardware: use self powered devices. 772 * (b) software: ignore non-repeated VBUS errors. 773 * 774 * REVISIT: do delays from lots of DEBUG_KERNEL checks 775 * make trouble here, keeping VBUS < 4.4V ? 776 */ 777 switch (musb_get_state(musb)) { 778 case OTG_STATE_A_HOST: 779 /* recovery is dicey once we've gotten past the 780 * initial stages of enumeration, but if VBUS 781 * stayed ok at the other end of the link, and 782 * another reset is due (at least for high speed, 783 * to redo the chirp etc), it might work OK... 784 */ 785 case OTG_STATE_A_WAIT_BCON: 786 case OTG_STATE_A_WAIT_VRISE: 787 if (musb->vbuserr_retry) { 788 void __iomem *mbase = musb->mregs; 789 790 musb->vbuserr_retry--; 791 ignore = 1; 792 devctl |= MUSB_DEVCTL_SESSION; 793 musb_writeb(mbase, MUSB_DEVCTL, devctl); 794 } else { 795 musb->port1_status |= 796 USB_PORT_STAT_OVERCURRENT 797 | (USB_PORT_STAT_C_OVERCURRENT << 16); 798 } 799 break; 800 default: 801 break; 802 } 803 804 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, 805 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 806 musb_otg_state_string(musb), 807 devctl, 808 ({ char *s; 809 switch (devctl & MUSB_DEVCTL_VBUS) { 810 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 811 s = "<SessEnd"; break; 812 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 813 s = "<AValid"; break; 814 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 815 s = "<VBusValid"; break; 816 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 817 default: 818 s = "VALID"; break; 819 } s; }), 820 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 821 musb->port1_status); 822 823 /* go through A_WAIT_VFALL then start a new session */ 824 if (!ignore) 825 musb_platform_set_vbus(musb, 0); 826} 827 828static void musb_handle_intr_suspend(struct musb *musb, u8 devctl) 829{ 830 musb_dbg(musb, "SUSPEND (%s) devctl %02x", 831 musb_otg_state_string(musb), devctl); 832 833 switch (musb_get_state(musb)) { 834 case OTG_STATE_A_PERIPHERAL: 835 /* We also come here if the cable is removed, since 836 * this silicon doesn't report ID-no-longer-grounded. 837 * 838 * We depend on T(a_wait_bcon) to shut us down, and 839 * hope users don't do anything dicey during this 840 * undesired detour through A_WAIT_BCON. 841 */ 842 musb_hnp_stop(musb); 843 musb_host_resume_root_hub(musb); 844 musb_root_disconnect(musb); 845 musb_platform_try_idle(musb, jiffies 846 + msecs_to_jiffies(musb->a_wait_bcon 847 ? : OTG_TIME_A_WAIT_BCON)); 848 849 break; 850 case OTG_STATE_B_IDLE: 851 if (!musb->is_active) 852 break; 853 fallthrough; 854 case OTG_STATE_B_PERIPHERAL: 855 musb_g_suspend(musb); 856 musb->is_active = musb->g.b_hnp_enable; 857 if (musb->is_active) { 858 musb_set_state(musb, OTG_STATE_B_WAIT_ACON); 859 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst"); 860 mod_timer(&musb->otg_timer, jiffies 861 + msecs_to_jiffies( 862 OTG_TIME_B_ASE0_BRST)); 863 } 864 break; 865 case OTG_STATE_A_WAIT_BCON: 866 if (musb->a_wait_bcon != 0) 867 musb_platform_try_idle(musb, jiffies 868 + msecs_to_jiffies(musb->a_wait_bcon)); 869 break; 870 case OTG_STATE_A_HOST: 871 musb_set_state(musb, OTG_STATE_A_SUSPEND); 872 musb->is_active = musb->hcd->self.b_hnp_enable; 873 break; 874 case OTG_STATE_B_HOST: 875 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 876 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST"); 877 break; 878 default: 879 /* "should not happen" */ 880 musb->is_active = 0; 881 break; 882 } 883} 884 885static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb) 886{ 887 struct usb_hcd *hcd = musb->hcd; 888 889 musb->is_active = 1; 890 musb->ep0_stage = MUSB_EP0_START; 891 892 musb->intrtxe = musb->epmask; 893 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); 894 musb->intrrxe = musb->epmask & 0xfffe; 895 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); 896 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 897 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 898 |USB_PORT_STAT_HIGH_SPEED 899 |USB_PORT_STAT_ENABLE 900 ); 901 musb->port1_status |= USB_PORT_STAT_CONNECTION 902 |(USB_PORT_STAT_C_CONNECTION << 16); 903 904 /* high vs full speed is just a guess until after reset */ 905 if (devctl & MUSB_DEVCTL_LSDEV) 906 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 907 908 /* indicate new connection to OTG machine */ 909 switch (musb_get_state(musb)) { 910 case OTG_STATE_B_PERIPHERAL: 911 if (int_usb & MUSB_INTR_SUSPEND) { 912 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host"); 913 int_usb &= ~MUSB_INTR_SUSPEND; 914 goto b_host; 915 } else 916 musb_dbg(musb, "CONNECT as b_peripheral???"); 917 break; 918 case OTG_STATE_B_WAIT_ACON: 919 musb_dbg(musb, "HNP: CONNECT, now b_host"); 920b_host: 921 musb_set_state(musb, OTG_STATE_B_HOST); 922 if (musb->hcd) 923 musb->hcd->self.is_b_host = 1; 924 timer_delete(&musb->otg_timer); 925 break; 926 default: 927 if ((devctl & MUSB_DEVCTL_VBUS) 928 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 929 musb_set_state(musb, OTG_STATE_A_HOST); 930 if (hcd) 931 hcd->self.is_b_host = 0; 932 } 933 break; 934 } 935 936 musb_host_poke_root_hub(musb); 937 938 musb_dbg(musb, "CONNECT (%s) devctl %02x", 939 musb_otg_state_string(musb), devctl); 940} 941 942static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl) 943{ 944 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x", 945 musb_otg_state_string(musb), 946 MUSB_MODE(musb), devctl); 947 948 switch (musb_get_state(musb)) { 949 case OTG_STATE_A_HOST: 950 case OTG_STATE_A_SUSPEND: 951 musb_host_resume_root_hub(musb); 952 musb_root_disconnect(musb); 953 if (musb->a_wait_bcon != 0) 954 musb_platform_try_idle(musb, jiffies 955 + msecs_to_jiffies(musb->a_wait_bcon)); 956 break; 957 case OTG_STATE_B_HOST: 958 /* REVISIT this behaves for "real disconnect" 959 * cases; make sure the other transitions from 960 * from B_HOST act right too. The B_HOST code 961 * in hnp_stop() is currently not used... 962 */ 963 musb_root_disconnect(musb); 964 if (musb->hcd) 965 musb->hcd->self.is_b_host = 0; 966 musb_set_state(musb, OTG_STATE_B_PERIPHERAL); 967 MUSB_DEV_MODE(musb); 968 musb_g_disconnect(musb); 969 break; 970 case OTG_STATE_A_PERIPHERAL: 971 musb_hnp_stop(musb); 972 musb_root_disconnect(musb); 973 fallthrough; 974 case OTG_STATE_B_WAIT_ACON: 975 case OTG_STATE_B_PERIPHERAL: 976 case OTG_STATE_B_IDLE: 977 musb_g_disconnect(musb); 978 break; 979 default: 980 WARNING("unhandled DISCONNECT transition (%s)\n", 981 musb_otg_state_string(musb)); 982 break; 983 } 984} 985 986/* 987 * mentor saves a bit: bus reset and babble share the same irq. 988 * only host sees babble; only peripheral sees bus reset. 989 */ 990static void musb_handle_intr_reset(struct musb *musb) 991{ 992 if (is_host_active(musb)) { 993 /* 994 * When BABBLE happens what we can depends on which 995 * platform MUSB is running, because some platforms 996 * implemented proprietary means for 'recovering' from 997 * Babble conditions. One such platform is AM335x. In 998 * most cases, however, the only thing we can do is 999 * drop the session. 1000 */ 1001 dev_err(musb->controller, "Babble\n"); 1002 musb_recover_from_babble(musb); 1003 } else { 1004 musb_dbg(musb, "BUS RESET as %s", musb_otg_state_string(musb)); 1005 switch (musb_get_state(musb)) { 1006 case OTG_STATE_A_SUSPEND: 1007 musb_g_reset(musb); 1008 fallthrough; 1009 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 1010 /* never use invalid T(a_wait_bcon) */ 1011 musb_dbg(musb, "HNP: in %s, %d msec timeout", 1012 musb_otg_state_string(musb), 1013 TA_WAIT_BCON(musb)); 1014 mod_timer(&musb->otg_timer, jiffies 1015 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 1016 break; 1017 case OTG_STATE_A_PERIPHERAL: 1018 timer_delete(&musb->otg_timer); 1019 musb_g_reset(musb); 1020 break; 1021 case OTG_STATE_B_WAIT_ACON: 1022 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral", 1023 musb_otg_state_string(musb)); 1024 musb_set_state(musb, OTG_STATE_B_PERIPHERAL); 1025 musb_g_reset(musb); 1026 break; 1027 case OTG_STATE_B_IDLE: 1028 musb_set_state(musb, OTG_STATE_B_PERIPHERAL); 1029 fallthrough; 1030 case OTG_STATE_B_PERIPHERAL: 1031 musb_g_reset(musb); 1032 break; 1033 default: 1034 musb_dbg(musb, "Unhandled BUS RESET as %s", 1035 musb_otg_state_string(musb)); 1036 } 1037 } 1038} 1039 1040/* 1041 * Interrupt Service Routine to record USB "global" interrupts. 1042 * Since these do not happen often and signify things of 1043 * paramount importance, it seems OK to check them individually; 1044 * the order of the tests is specified in the manual 1045 * 1046 * @param musb instance pointer 1047 * @param int_usb register contents 1048 * @param devctl 1049 */ 1050 1051static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 1052 u8 devctl) 1053{ 1054 irqreturn_t handled = IRQ_NONE; 1055 1056 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb); 1057 1058 /* in host mode, the peripheral may issue remote wakeup. 1059 * in peripheral mode, the host may resume the link. 1060 * spurious RESUME irqs happen too, paired with SUSPEND. 1061 */ 1062 if (int_usb & MUSB_INTR_RESUME) { 1063 musb_handle_intr_resume(musb, devctl); 1064 handled = IRQ_HANDLED; 1065 } 1066 1067 /* see manual for the order of the tests */ 1068 if (int_usb & MUSB_INTR_SESSREQ) { 1069 if (musb_handle_intr_sessreq(musb, devctl)) 1070 return IRQ_HANDLED; 1071 handled = IRQ_HANDLED; 1072 } 1073 1074 if (int_usb & MUSB_INTR_VBUSERROR) { 1075 musb_handle_intr_vbuserr(musb, devctl); 1076 handled = IRQ_HANDLED; 1077 } 1078 1079 if (int_usb & MUSB_INTR_SUSPEND) { 1080 musb_handle_intr_suspend(musb, devctl); 1081 handled = IRQ_HANDLED; 1082 } 1083 1084 if (int_usb & MUSB_INTR_CONNECT) { 1085 musb_handle_intr_connect(musb, devctl, int_usb); 1086 handled = IRQ_HANDLED; 1087 } 1088 1089 if (int_usb & MUSB_INTR_DISCONNECT) { 1090 musb_handle_intr_disconnect(musb, devctl); 1091 handled = IRQ_HANDLED; 1092 } 1093 1094 if (int_usb & MUSB_INTR_RESET) { 1095 musb_handle_intr_reset(musb); 1096 handled = IRQ_HANDLED; 1097 } 1098 1099#if 0 1100/* REVISIT ... this would be for multiplexing periodic endpoints, or 1101 * supporting transfer phasing to prevent exceeding ISO bandwidth 1102 * limits of a given frame or microframe. 1103 * 1104 * It's not needed for peripheral side, which dedicates endpoints; 1105 * though it _might_ use SOF irqs for other purposes. 1106 * 1107 * And it's not currently needed for host side, which also dedicates 1108 * endpoints, relies on TX/RX interval registers, and isn't claimed 1109 * to support ISO transfers yet. 1110 */ 1111 if (int_usb & MUSB_INTR_SOF) { 1112 void __iomem *mbase = musb->mregs; 1113 struct musb_hw_ep *ep; 1114 u8 epnum; 1115 u16 frame; 1116 1117 dev_dbg(musb->controller, "START_OF_FRAME\n"); 1118 handled = IRQ_HANDLED; 1119 1120 /* start any periodic Tx transfers waiting for current frame */ 1121 frame = musb_readw(mbase, MUSB_FRAME); 1122 ep = musb->endpoints; 1123 for (epnum = 1; (epnum < musb->nr_endpoints) 1124 && (musb->epmask >= (1 << epnum)); 1125 epnum++, ep++) { 1126 /* 1127 * FIXME handle framecounter wraps (12 bits) 1128 * eliminate duplicated StartUrb logic 1129 */ 1130 if (ep->dwWaitFrame >= frame) { 1131 ep->dwWaitFrame = 0; 1132 pr_debug("SOF --> periodic TX%s on %d\n", 1133 ep->tx_channel ? " DMA" : "", 1134 epnum); 1135 if (!ep->tx_channel) 1136 musb_h_tx_start(musb, epnum); 1137 else 1138 cppi_hostdma_start(musb, epnum); 1139 } 1140 } /* end of for loop */ 1141 } 1142#endif 1143 1144 schedule_delayed_work(&musb->irq_work, 0); 1145 1146 return handled; 1147} 1148 1149/*-------------------------------------------------------------------------*/ 1150 1151static void musb_disable_interrupts(struct musb *musb) 1152{ 1153 void __iomem *mbase = musb->mregs; 1154 1155 /* disable interrupts */ 1156 musb_writeb(mbase, MUSB_INTRUSBE, 0); 1157 musb->intrtxe = 0; 1158 musb_writew(mbase, MUSB_INTRTXE, 0); 1159 musb->intrrxe = 0; 1160 musb_writew(mbase, MUSB_INTRRXE, 0); 1161 1162 /* flush pending interrupts */ 1163 musb_clearb(mbase, MUSB_INTRUSB); 1164 musb_clearw(mbase, MUSB_INTRTX); 1165 musb_clearw(mbase, MUSB_INTRRX); 1166} 1167 1168static void musb_enable_interrupts(struct musb *musb) 1169{ 1170 void __iomem *regs = musb->mregs; 1171 1172 /* Set INT enable registers, enable interrupts */ 1173 musb->intrtxe = musb->epmask; 1174 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); 1175 musb->intrrxe = musb->epmask & 0xfffe; 1176 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); 1177 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 1178 1179} 1180 1181/* 1182 * Program the HDRC to start (enable interrupts, dma, etc.). 1183 */ 1184void musb_start(struct musb *musb) 1185{ 1186 void __iomem *regs = musb->mregs; 1187 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 1188 u8 power; 1189 1190 musb_dbg(musb, "<== devctl %02x", devctl); 1191 1192 musb_enable_interrupts(musb); 1193 musb_writeb(regs, MUSB_TESTMODE, 0); 1194 1195 power = MUSB_POWER_ISOUPDATE; 1196 /* 1197 * treating UNKNOWN as unspecified maximum speed, in which case 1198 * we will default to high-speed. 1199 */ 1200 if (musb->config->maximum_speed == USB_SPEED_HIGH || 1201 musb->config->maximum_speed == USB_SPEED_UNKNOWN) 1202 power |= MUSB_POWER_HSENAB; 1203 musb_writeb(regs, MUSB_POWER, power); 1204 1205 musb->is_active = 0; 1206 devctl = musb_readb(regs, MUSB_DEVCTL); 1207 devctl &= ~MUSB_DEVCTL_SESSION; 1208 1209 /* session started after: 1210 * (a) ID-grounded irq, host mode; 1211 * (b) vbus present/connect IRQ, peripheral mode; 1212 * (c) peripheral initiates, using SRP 1213 */ 1214 if (musb->port_mode != MUSB_HOST && 1215 musb_get_state(musb) != OTG_STATE_A_WAIT_BCON && 1216 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { 1217 musb->is_active = 1; 1218 } else { 1219 devctl |= MUSB_DEVCTL_SESSION; 1220 } 1221 1222 musb_platform_enable(musb); 1223 musb_writeb(regs, MUSB_DEVCTL, devctl); 1224} 1225 1226/* 1227 * Make the HDRC stop (disable interrupts, etc.); 1228 * reversible by musb_start 1229 * called on gadget driver unregister 1230 * with controller locked, irqs blocked 1231 * acts as a NOP unless some role activated the hardware 1232 */ 1233void musb_stop(struct musb *musb) 1234{ 1235 /* stop IRQs, timers, ... */ 1236 musb_platform_disable(musb); 1237 musb_disable_interrupts(musb); 1238 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1239 1240 /* FIXME 1241 * - mark host and/or peripheral drivers unusable/inactive 1242 * - disable DMA (and enable it in HdrcStart) 1243 * - make sure we can musb_start() after musb_stop(); with 1244 * OTG mode, gadget driver module rmmod/modprobe cycles that 1245 * - ... 1246 */ 1247 musb_platform_try_idle(musb, 0); 1248} 1249 1250/*-------------------------------------------------------------------------*/ 1251 1252/* 1253 * The silicon either has hard-wired endpoint configurations, or else 1254 * "dynamic fifo" sizing. The driver has support for both, though at this 1255 * writing only the dynamic sizing is very well tested. Since we switched 1256 * away from compile-time hardware parameters, we can no longer rely on 1257 * dead code elimination to leave only the relevant one in the object file. 1258 * 1259 * We don't currently use dynamic fifo setup capability to do anything 1260 * more than selecting one of a bunch of predefined configurations. 1261 */ 1262static ushort fifo_mode; 1263 1264/* "modprobe ... fifo_mode=1" etc */ 1265module_param(fifo_mode, ushort, 0); 1266MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1267 1268/* 1269 * tables defining fifo_mode values. define more if you like. 1270 * for host side, make sure both halves of ep1 are set up. 1271 */ 1272 1273/* mode 0 - fits in 2KB */ 1274static const struct musb_fifo_cfg mode_0_cfg[] = { 1275{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1276{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1277{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1278{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1279{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1280}; 1281 1282/* mode 1 - fits in 4KB */ 1283static const struct musb_fifo_cfg mode_1_cfg[] = { 1284{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1285{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1286{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1287{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1288{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1289}; 1290 1291/* mode 2 - fits in 4KB */ 1292static const struct musb_fifo_cfg mode_2_cfg[] = { 1293{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1294{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1295{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1296{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1297{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, }, 1298{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, }, 1299}; 1300 1301/* mode 3 - fits in 4KB */ 1302static const struct musb_fifo_cfg mode_3_cfg[] = { 1303{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1304{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1305{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1306{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1307{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1308{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1309}; 1310 1311/* mode 4 - fits in 16KB */ 1312static const struct musb_fifo_cfg mode_4_cfg[] = { 1313{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1314{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1315{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1316{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1317{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1318{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1319{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1320{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1321{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1322{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1323{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1324{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1325{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1326{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1327{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1328{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1329{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1330{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1331{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1332{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1333{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1334{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1335{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1336{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1337{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1338{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1339{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1340}; 1341 1342/* mode 5 - fits in 8KB */ 1343static const struct musb_fifo_cfg mode_5_cfg[] = { 1344{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1345{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1346{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1347{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1348{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1349{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1350{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1351{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1352{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1353{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1354{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1355{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1356{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1357{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1358{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1359{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1360{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1361{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1362{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1363{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1364{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1365{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1366{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1367{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1368{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1369{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1370{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1371}; 1372 1373/* 1374 * configure a fifo; for non-shared endpoints, this may be called 1375 * once for a tx fifo and once for an rx fifo. 1376 * 1377 * returns negative errno or offset for next fifo. 1378 */ 1379static int 1380fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1381 const struct musb_fifo_cfg *cfg, u16 offset) 1382{ 1383 void __iomem *mbase = musb->mregs; 1384 int size = 0; 1385 u16 maxpacket = cfg->maxpacket; 1386 u16 c_off = offset >> 3; 1387 u8 c_size; 1388 1389 /* expect hw_ep has already been zero-initialized */ 1390 1391 size = ffs(max_t(u16, maxpacket, 8)) - 1; 1392 maxpacket = 1 << size; 1393 1394 c_size = size - 3; 1395 if (cfg->mode == BUF_DOUBLE) { 1396 if ((offset + (maxpacket << 1)) > 1397 (1 << (musb->config->ram_bits + 2))) 1398 return -EMSGSIZE; 1399 c_size |= MUSB_FIFOSZ_DPB; 1400 } else { 1401 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1402 return -EMSGSIZE; 1403 } 1404 1405 /* configure the FIFO */ 1406 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1407 1408 /* EP0 reserved endpoint for control, bidirectional; 1409 * EP1 reserved for bulk, two unidirectional halves. 1410 */ 1411 if (hw_ep->epnum == 1) 1412 musb->bulk_ep = hw_ep; 1413 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1414 switch (cfg->style) { 1415 case FIFO_TX: 1416 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); 1417 musb_writew(mbase, MUSB_TXFIFOADD, c_off); 1418 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1419 hw_ep->max_packet_sz_tx = maxpacket; 1420 break; 1421 case FIFO_RX: 1422 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size); 1423 musb_writew(mbase, MUSB_RXFIFOADD, c_off); 1424 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1425 hw_ep->max_packet_sz_rx = maxpacket; 1426 break; 1427 case FIFO_RXTX: 1428 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); 1429 musb_writew(mbase, MUSB_TXFIFOADD, c_off); 1430 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1431 hw_ep->max_packet_sz_rx = maxpacket; 1432 1433 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size); 1434 musb_writew(mbase, MUSB_RXFIFOADD, c_off); 1435 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1436 hw_ep->max_packet_sz_tx = maxpacket; 1437 1438 hw_ep->is_shared_fifo = true; 1439 break; 1440 } 1441 1442 /* NOTE rx and tx endpoint irqs aren't managed separately, 1443 * which happens to be ok 1444 */ 1445 musb->epmask |= (1 << hw_ep->epnum); 1446 1447 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1448} 1449 1450static const struct musb_fifo_cfg ep0_cfg = { 1451 .style = FIFO_RXTX, .maxpacket = 64, 1452}; 1453 1454static int ep_config_from_table(struct musb *musb) 1455{ 1456 const struct musb_fifo_cfg *cfg; 1457 unsigned i, n; 1458 int offset; 1459 struct musb_hw_ep *hw_ep = musb->endpoints; 1460 1461 if (musb->config->fifo_cfg) { 1462 cfg = musb->config->fifo_cfg; 1463 n = musb->config->fifo_cfg_size; 1464 goto done; 1465 } 1466 1467 switch (fifo_mode) { 1468 default: 1469 fifo_mode = 0; 1470 fallthrough; 1471 case 0: 1472 cfg = mode_0_cfg; 1473 n = ARRAY_SIZE(mode_0_cfg); 1474 break; 1475 case 1: 1476 cfg = mode_1_cfg; 1477 n = ARRAY_SIZE(mode_1_cfg); 1478 break; 1479 case 2: 1480 cfg = mode_2_cfg; 1481 n = ARRAY_SIZE(mode_2_cfg); 1482 break; 1483 case 3: 1484 cfg = mode_3_cfg; 1485 n = ARRAY_SIZE(mode_3_cfg); 1486 break; 1487 case 4: 1488 cfg = mode_4_cfg; 1489 n = ARRAY_SIZE(mode_4_cfg); 1490 break; 1491 case 5: 1492 cfg = mode_5_cfg; 1493 n = ARRAY_SIZE(mode_5_cfg); 1494 break; 1495 } 1496 1497 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); 1498 1499 1500done: 1501 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1502 /* assert(offset > 0) */ 1503 1504 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1505 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1506 */ 1507 1508 for (i = 0; i < n; i++) { 1509 u8 epn = cfg->hw_ep_num; 1510 1511 if (epn >= musb->config->num_eps) { 1512 pr_debug("%s: invalid ep %d\n", 1513 musb_driver_name, epn); 1514 return -EINVAL; 1515 } 1516 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1517 if (offset < 0) { 1518 pr_debug("%s: mem overrun, ep %d\n", 1519 musb_driver_name, epn); 1520 return offset; 1521 } 1522 epn++; 1523 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1524 } 1525 1526 pr_debug("%s: %d/%d max ep, %d/%d memory\n", 1527 musb_driver_name, 1528 n + 1, musb->config->num_eps * 2 - 1, 1529 offset, (1 << (musb->config->ram_bits + 2))); 1530 1531 if (!musb->bulk_ep) { 1532 pr_debug("%s: missing bulk\n", musb_driver_name); 1533 return -EINVAL; 1534 } 1535 1536 return 0; 1537} 1538 1539 1540/* 1541 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1542 * @param musb the controller 1543 */ 1544static int ep_config_from_hw(struct musb *musb) 1545{ 1546 u8 epnum = 0; 1547 struct musb_hw_ep *hw_ep; 1548 void __iomem *mbase = musb->mregs; 1549 int ret = 0; 1550 1551 musb_dbg(musb, "<== static silicon ep config"); 1552 1553 /* FIXME pick up ep0 maxpacket size */ 1554 1555 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1556 musb_ep_select(mbase, epnum); 1557 hw_ep = musb->endpoints + epnum; 1558 1559 ret = musb_read_fifosize(musb, hw_ep, epnum); 1560 if (ret < 0) 1561 break; 1562 1563 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1564 1565 /* pick an RX/TX endpoint for bulk */ 1566 if (hw_ep->max_packet_sz_tx < 512 1567 || hw_ep->max_packet_sz_rx < 512) 1568 continue; 1569 1570 /* REVISIT: this algorithm is lazy, we should at least 1571 * try to pick a double buffered endpoint. 1572 */ 1573 if (musb->bulk_ep) 1574 continue; 1575 musb->bulk_ep = hw_ep; 1576 } 1577 1578 if (!musb->bulk_ep) { 1579 pr_debug("%s: missing bulk\n", musb_driver_name); 1580 return -EINVAL; 1581 } 1582 1583 return 0; 1584} 1585 1586enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1587 1588/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1589 * configure endpoints, or take their config from silicon 1590 */ 1591static int musb_core_init(u16 musb_type, struct musb *musb) 1592{ 1593 u8 reg; 1594 char *type; 1595 char aInfo[90]; 1596 void __iomem *mbase = musb->mregs; 1597 int status = 0; 1598 int i; 1599 1600 /* log core options (read using indexed model) */ 1601 reg = musb_read_configdata(mbase); 1602 1603 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1604 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1605 strcat(aInfo, ", dyn FIFOs"); 1606 musb->dyn_fifo = true; 1607 } 1608 if (reg & MUSB_CONFIGDATA_MPRXE) { 1609 strcat(aInfo, ", bulk combine"); 1610 musb->bulk_combine = true; 1611 } 1612 if (reg & MUSB_CONFIGDATA_MPTXE) { 1613 strcat(aInfo, ", bulk split"); 1614 musb->bulk_split = true; 1615 } 1616 if (reg & MUSB_CONFIGDATA_HBRXE) { 1617 strcat(aInfo, ", HB-ISO Rx"); 1618 musb->hb_iso_rx = true; 1619 } 1620 if (reg & MUSB_CONFIGDATA_HBTXE) { 1621 strcat(aInfo, ", HB-ISO Tx"); 1622 musb->hb_iso_tx = true; 1623 } 1624 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1625 strcat(aInfo, ", SoftConn"); 1626 1627 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); 1628 1629 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1630 musb->is_multipoint = 1; 1631 type = "M"; 1632 } else { 1633 musb->is_multipoint = 0; 1634 type = ""; 1635 if (IS_ENABLED(CONFIG_USB) && 1636 !IS_ENABLED(CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB)) { 1637 pr_err("%s: kernel must disable external hubs, please fix the configuration\n", 1638 musb_driver_name); 1639 } 1640 } 1641 1642 /* log release info */ 1643 musb->hwvers = musb_readw(mbase, MUSB_HWVERS); 1644 pr_debug("%s: %sHDRC RTL version %d.%d%s\n", 1645 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers), 1646 MUSB_HWVERS_MINOR(musb->hwvers), 1647 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1648 1649 /* configure ep0 */ 1650 musb_configure_ep0(musb); 1651 1652 /* discover endpoint configuration */ 1653 musb->nr_endpoints = 1; 1654 musb->epmask = 1; 1655 1656 if (musb->dyn_fifo) 1657 status = ep_config_from_table(musb); 1658 else 1659 status = ep_config_from_hw(musb); 1660 1661 if (status < 0) 1662 return status; 1663 1664 /* finish init, and print endpoint config */ 1665 for (i = 0; i < musb->nr_endpoints; i++) { 1666 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1667 1668 hw_ep->fifo = musb->io.fifo_offset(i) + mbase; 1669#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) 1670 if (musb->ops->quirks & MUSB_IN_TUSB) { 1671 hw_ep->fifo_async = musb->async + 0x400 + 1672 musb->io.fifo_offset(i); 1673 hw_ep->fifo_sync = musb->sync + 0x400 + 1674 musb->io.fifo_offset(i); 1675 hw_ep->fifo_sync_va = 1676 musb->sync_va + 0x400 + musb->io.fifo_offset(i); 1677 1678 if (i == 0) 1679 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1680 else 1681 hw_ep->conf = mbase + 0x400 + 1682 (((i - 1) & 0xf) << 2); 1683 } 1684#endif 1685 1686 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase; 1687 hw_ep->rx_reinit = 1; 1688 hw_ep->tx_reinit = 1; 1689 1690 if (hw_ep->max_packet_sz_tx) { 1691 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", 1692 musb_driver_name, i, 1693 hw_ep->is_shared_fifo ? "shared" : "tx", 1694 hw_ep->tx_double_buffered 1695 ? "doublebuffer, " : "", 1696 hw_ep->max_packet_sz_tx); 1697 } 1698 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1699 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", 1700 musb_driver_name, i, 1701 "rx", 1702 hw_ep->rx_double_buffered 1703 ? "doublebuffer, " : "", 1704 hw_ep->max_packet_sz_rx); 1705 } 1706 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1707 musb_dbg(musb, "hw_ep %d not configured", i); 1708 } 1709 1710 return 0; 1711} 1712 1713/*-------------------------------------------------------------------------*/ 1714 1715/* 1716 * handle all the irqs defined by the HDRC core. for now we expect: other 1717 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1718 * will be assigned, and the irq will already have been acked. 1719 * 1720 * called in irq context with spinlock held, irqs blocked 1721 */ 1722irqreturn_t musb_interrupt(struct musb *musb) 1723{ 1724 irqreturn_t retval = IRQ_NONE; 1725 unsigned long status; 1726 unsigned long epnum; 1727 u8 devctl; 1728 1729 if (!musb->int_usb && !musb->int_tx && !musb->int_rx) 1730 return IRQ_NONE; 1731 1732 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1733 1734 trace_musb_isr(musb); 1735 1736 /** 1737 * According to Mentor Graphics' documentation, flowchart on page 98, 1738 * IRQ should be handled as follows: 1739 * 1740 * . Resume IRQ 1741 * . Session Request IRQ 1742 * . VBUS Error IRQ 1743 * . Suspend IRQ 1744 * . Connect IRQ 1745 * . Disconnect IRQ 1746 * . Reset/Babble IRQ 1747 * . SOF IRQ (we're not using this one) 1748 * . Endpoint 0 IRQ 1749 * . TX Endpoints 1750 * . RX Endpoints 1751 * 1752 * We will be following that flowchart in order to avoid any problems 1753 * that might arise with internal Finite State Machine. 1754 */ 1755 1756 if (musb->int_usb) 1757 retval |= musb_stage0_irq(musb, musb->int_usb, devctl); 1758 1759 if (musb->int_tx & 1) { 1760 if (is_host_active(musb)) 1761 retval |= musb_h_ep0_irq(musb); 1762 else 1763 retval |= musb_g_ep0_irq(musb); 1764 1765 /* we have just handled endpoint 0 IRQ, clear it */ 1766 musb->int_tx &= ~BIT(0); 1767 } 1768 1769 status = musb->int_tx; 1770 1771 for_each_set_bit(epnum, &status, 16) { 1772 retval = IRQ_HANDLED; 1773 if (is_host_active(musb)) 1774 musb_host_tx(musb, epnum); 1775 else 1776 musb_g_tx(musb, epnum); 1777 } 1778 1779 status = musb->int_rx; 1780 1781 for_each_set_bit(epnum, &status, 16) { 1782 retval = IRQ_HANDLED; 1783 if (is_host_active(musb)) 1784 musb_host_rx(musb, epnum); 1785 else 1786 musb_g_rx(musb, epnum); 1787 } 1788 1789 return retval; 1790} 1791EXPORT_SYMBOL_GPL(musb_interrupt); 1792 1793#ifndef CONFIG_MUSB_PIO_ONLY 1794static bool use_dma = true; 1795 1796/* "modprobe ... use_dma=0" etc */ 1797module_param(use_dma, bool, 0644); 1798MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1799 1800void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1801{ 1802 /* called with controller lock already held */ 1803 1804 if (!epnum) { 1805 if (!is_cppi_enabled(musb)) { 1806 /* endpoint 0 */ 1807 if (is_host_active(musb)) 1808 musb_h_ep0_irq(musb); 1809 else 1810 musb_g_ep0_irq(musb); 1811 } 1812 } else { 1813 /* endpoints 1..15 */ 1814 if (transmit) { 1815 if (is_host_active(musb)) 1816 musb_host_tx(musb, epnum); 1817 else 1818 musb_g_tx(musb, epnum); 1819 } else { 1820 /* receive */ 1821 if (is_host_active(musb)) 1822 musb_host_rx(musb, epnum); 1823 else 1824 musb_g_rx(musb, epnum); 1825 } 1826 } 1827} 1828EXPORT_SYMBOL_GPL(musb_dma_completion); 1829 1830#else 1831#define use_dma 0 1832#endif 1833 1834static int (*musb_phy_callback)(enum musb_vbus_id_status status); 1835 1836/* 1837 * musb_mailbox - optional phy notifier function 1838 * @status phy state change 1839 * 1840 * Optionally gets called from the USB PHY. Note that the USB PHY must be 1841 * disabled at the point the phy_callback is registered or unregistered. 1842 */ 1843int musb_mailbox(enum musb_vbus_id_status status) 1844{ 1845 if (musb_phy_callback) 1846 return musb_phy_callback(status); 1847 1848 return -ENODEV; 1849}; 1850EXPORT_SYMBOL_GPL(musb_mailbox); 1851 1852/*-------------------------------------------------------------------------*/ 1853 1854static ssize_t 1855mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1856{ 1857 struct musb *musb = dev_to_musb(dev); 1858 unsigned long flags; 1859 int ret; 1860 1861 spin_lock_irqsave(&musb->lock, flags); 1862 ret = sprintf(buf, "%s\n", musb_otg_state_string(musb)); 1863 spin_unlock_irqrestore(&musb->lock, flags); 1864 1865 return ret; 1866} 1867 1868static ssize_t 1869mode_store(struct device *dev, struct device_attribute *attr, 1870 const char *buf, size_t n) 1871{ 1872 struct musb *musb = dev_to_musb(dev); 1873 unsigned long flags; 1874 int status; 1875 1876 spin_lock_irqsave(&musb->lock, flags); 1877 if (sysfs_streq(buf, "host")) 1878 status = musb_platform_set_mode(musb, MUSB_HOST); 1879 else if (sysfs_streq(buf, "peripheral")) 1880 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1881 else if (sysfs_streq(buf, "otg")) 1882 status = musb_platform_set_mode(musb, MUSB_OTG); 1883 else 1884 status = -EINVAL; 1885 spin_unlock_irqrestore(&musb->lock, flags); 1886 1887 return (status == 0) ? n : status; 1888} 1889static DEVICE_ATTR_RW(mode); 1890 1891static ssize_t 1892vbus_store(struct device *dev, struct device_attribute *attr, 1893 const char *buf, size_t n) 1894{ 1895 struct musb *musb = dev_to_musb(dev); 1896 unsigned long flags; 1897 unsigned long val; 1898 1899 if (sscanf(buf, "%lu", &val) < 1) { 1900 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1901 return -EINVAL; 1902 } 1903 1904 spin_lock_irqsave(&musb->lock, flags); 1905 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1906 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1907 if (musb_get_state(musb) == OTG_STATE_A_WAIT_BCON) 1908 musb->is_active = 0; 1909 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1910 spin_unlock_irqrestore(&musb->lock, flags); 1911 1912 return n; 1913} 1914 1915static ssize_t 1916vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1917{ 1918 struct musb *musb = dev_to_musb(dev); 1919 unsigned long flags; 1920 unsigned long val; 1921 int vbus; 1922 u8 devctl; 1923 1924 pm_runtime_get_sync(dev); 1925 spin_lock_irqsave(&musb->lock, flags); 1926 val = musb->a_wait_bcon; 1927 vbus = musb_platform_get_vbus_status(musb); 1928 if (vbus < 0) { 1929 /* Use default MUSB method by means of DEVCTL register */ 1930 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1931 if ((devctl & MUSB_DEVCTL_VBUS) 1932 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) 1933 vbus = 1; 1934 else 1935 vbus = 0; 1936 } 1937 spin_unlock_irqrestore(&musb->lock, flags); 1938 pm_runtime_put_sync(dev); 1939 1940 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1941 str_on_off(vbus), val); 1942} 1943static DEVICE_ATTR_RW(vbus); 1944 1945/* Gadget drivers can't know that a host is connected so they might want 1946 * to start SRP, but users can. This allows userspace to trigger SRP. 1947 */ 1948static ssize_t srp_store(struct device *dev, struct device_attribute *attr, 1949 const char *buf, size_t n) 1950{ 1951 struct musb *musb = dev_to_musb(dev); 1952 unsigned short srp; 1953 1954 if (sscanf(buf, "%hu", &srp) != 1 1955 || (srp != 1)) { 1956 dev_err(dev, "SRP: Value must be 1\n"); 1957 return -EINVAL; 1958 } 1959 1960 if (srp == 1) 1961 musb_g_wakeup(musb); 1962 1963 return n; 1964} 1965static DEVICE_ATTR_WO(srp); 1966 1967static struct attribute *musb_attrs[] = { 1968 &dev_attr_mode.attr, 1969 &dev_attr_vbus.attr, 1970 &dev_attr_srp.attr, 1971 NULL 1972}; 1973ATTRIBUTE_GROUPS(musb); 1974 1975#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \ 1976 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \ 1977 MUSB_DEVCTL_SESSION) 1978#define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \ 1979 (3 << MUSB_DEVCTL_VBUS_SHIFT) | \ 1980 MUSB_DEVCTL_SESSION) 1981#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \ 1982 MUSB_DEVCTL_SESSION) 1983 1984static bool musb_state_needs_recheck(struct musb *musb, u8 devctl, 1985 const char *desc) 1986{ 1987 if (musb->quirk_retries && !musb->flush_irq_work) { 1988 trace_musb_state(musb, devctl, desc); 1989 schedule_delayed_work(&musb->irq_work, 1990 msecs_to_jiffies(1000)); 1991 musb->quirk_retries--; 1992 1993 return true; 1994 } 1995 1996 return false; 1997} 1998 1999/* 2000 * Check the musb devctl session bit to determine if we want to 2001 * allow PM runtime for the device. In general, we want to keep things 2002 * active when the session bit is set except after host disconnect. 2003 * 2004 * Only called from musb_irq_work. If this ever needs to get called 2005 * elsewhere, proper locking must be implemented for musb->session. 2006 */ 2007static void musb_pm_runtime_check_session(struct musb *musb) 2008{ 2009 u8 devctl, s; 2010 int error; 2011 2012 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2013 2014 /* Handle session status quirks first */ 2015 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV | 2016 MUSB_DEVCTL_HR; 2017 switch (devctl & ~s) { 2018 case MUSB_QUIRK_B_DISCONNECT_99: 2019 musb_state_needs_recheck(musb, devctl, 2020 "Poll devctl in case of suspend after disconnect"); 2021 break; 2022 case MUSB_QUIRK_B_INVALID_VBUS_91: 2023 if (musb_state_needs_recheck(musb, devctl, 2024 "Poll devctl on invalid vbus, assume no session")) 2025 return; 2026 fallthrough; 2027 case MUSB_QUIRK_A_DISCONNECT_19: 2028 if (musb_state_needs_recheck(musb, devctl, 2029 "Poll devctl on possible host mode disconnect")) 2030 return; 2031 if (!musb->session) 2032 break; 2033 trace_musb_state(musb, devctl, "Allow PM on possible host mode disconnect"); 2034 pm_runtime_put_autosuspend(musb->controller); 2035 musb->session = false; 2036 return; 2037 default: 2038 break; 2039 } 2040 2041 /* No need to do anything if session has not changed */ 2042 s = devctl & MUSB_DEVCTL_SESSION; 2043 if (s == musb->session) 2044 return; 2045 2046 /* Block PM or allow PM? */ 2047 if (s) { 2048 trace_musb_state(musb, devctl, "Block PM on active session"); 2049 error = pm_runtime_get_sync(musb->controller); 2050 if (error < 0) 2051 dev_err(musb->controller, "Could not enable: %i\n", 2052 error); 2053 musb->quirk_retries = 3; 2054 2055 /* 2056 * We can get a spurious MUSB_INTR_SESSREQ interrupt on start-up 2057 * in B-peripheral mode with nothing connected and the session 2058 * bit clears silently. Check status again in 3 seconds. 2059 */ 2060 if (devctl & MUSB_DEVCTL_BDEVICE) 2061 schedule_delayed_work(&musb->irq_work, 2062 msecs_to_jiffies(3000)); 2063 } else { 2064 trace_musb_state(musb, devctl, "Allow PM with no session"); 2065 pm_runtime_put_autosuspend(musb->controller); 2066 } 2067 2068 musb->session = s; 2069} 2070 2071/* Only used to provide driver mode change events */ 2072static void musb_irq_work(struct work_struct *data) 2073{ 2074 struct musb *musb = container_of(data, struct musb, irq_work.work); 2075 int error; 2076 2077 error = pm_runtime_resume_and_get(musb->controller); 2078 if (error < 0) { 2079 dev_err(musb->controller, "Could not enable: %i\n", error); 2080 2081 return; 2082 } 2083 2084 musb_pm_runtime_check_session(musb); 2085 2086 if (musb_get_state(musb) != musb->xceiv_old_state) { 2087 musb->xceiv_old_state = musb_get_state(musb); 2088 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 2089 } 2090 2091 pm_runtime_put_autosuspend(musb->controller); 2092} 2093 2094static void musb_recover_from_babble(struct musb *musb) 2095{ 2096 int ret; 2097 u8 devctl; 2098 2099 musb_disable_interrupts(musb); 2100 2101 /* 2102 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give 2103 * it some slack and wait for 10us. 2104 */ 2105 udelay(10); 2106 2107 ret = musb_platform_recover(musb); 2108 if (ret) { 2109 musb_enable_interrupts(musb); 2110 return; 2111 } 2112 2113 /* drop session bit */ 2114 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2115 devctl &= ~MUSB_DEVCTL_SESSION; 2116 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 2117 2118 /* tell usbcore about it */ 2119 musb_root_disconnect(musb); 2120 2121 /* 2122 * When a babble condition occurs, the musb controller 2123 * removes the session bit and the endpoint config is lost. 2124 */ 2125 if (musb->dyn_fifo) 2126 ret = ep_config_from_table(musb); 2127 else 2128 ret = ep_config_from_hw(musb); 2129 2130 /* restart session */ 2131 if (ret == 0) 2132 musb_start(musb); 2133} 2134 2135/* -------------------------------------------------------------------------- 2136 * Init support 2137 */ 2138 2139static struct musb *allocate_instance(struct device *dev, 2140 const struct musb_hdrc_config *config, void __iomem *mbase) 2141{ 2142 struct musb *musb; 2143 struct musb_hw_ep *ep; 2144 int epnum; 2145 int ret; 2146 2147 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); 2148 if (!musb) 2149 return NULL; 2150 2151 INIT_LIST_HEAD(&musb->control); 2152 INIT_LIST_HEAD(&musb->in_bulk); 2153 INIT_LIST_HEAD(&musb->out_bulk); 2154 INIT_LIST_HEAD(&musb->pending_list); 2155 2156 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 2157 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 2158 musb->mregs = mbase; 2159 musb->ctrl_base = mbase; 2160 musb->nIrq = -ENODEV; 2161 musb->config = config; 2162 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 2163 for (epnum = 0, ep = musb->endpoints; 2164 epnum < musb->config->num_eps; 2165 epnum++, ep++) { 2166 ep->musb = musb; 2167 ep->epnum = epnum; 2168 } 2169 2170 musb->controller = dev; 2171 2172 ret = musb_host_alloc(musb); 2173 if (ret < 0) 2174 goto err_free; 2175 2176 dev_set_drvdata(dev, musb); 2177 2178 return musb; 2179 2180err_free: 2181 return NULL; 2182} 2183 2184static void musb_free(struct musb *musb) 2185{ 2186 /* this has multiple entry modes. it handles fault cleanup after 2187 * probe(), where things may be partially set up, as well as rmmod 2188 * cleanup after everything's been de-activated. 2189 */ 2190 2191 if (musb->nIrq >= 0) { 2192 if (musb->irq_wake) 2193 disable_irq_wake(musb->nIrq); 2194 free_irq(musb->nIrq, musb); 2195 } 2196 2197 musb_host_free(musb); 2198} 2199 2200struct musb_pending_work { 2201 int (*callback)(struct musb *musb, void *data); 2202 void *data; 2203 struct list_head node; 2204}; 2205 2206#ifdef CONFIG_PM 2207/* 2208 * Called from musb_runtime_resume(), musb_resume(), and 2209 * musb_queue_resume_work(). Callers must take musb->lock. 2210 */ 2211static int musb_run_resume_work(struct musb *musb) 2212{ 2213 struct musb_pending_work *w, *_w; 2214 unsigned long flags; 2215 int error = 0; 2216 2217 spin_lock_irqsave(&musb->list_lock, flags); 2218 list_for_each_entry_safe(w, _w, &musb->pending_list, node) { 2219 if (w->callback) { 2220 error = w->callback(musb, w->data); 2221 if (error < 0) { 2222 dev_err(musb->controller, 2223 "resume callback %p failed: %i\n", 2224 w->callback, error); 2225 } 2226 } 2227 list_del(&w->node); 2228 devm_kfree(musb->controller, w); 2229 } 2230 spin_unlock_irqrestore(&musb->list_lock, flags); 2231 2232 return error; 2233} 2234#endif 2235 2236/* 2237 * Called to run work if device is active or else queue the work to happen 2238 * on resume. Caller must take musb->lock and must hold an RPM reference. 2239 * 2240 * Note that we cowardly refuse queuing work after musb PM runtime 2241 * resume is done calling musb_run_resume_work() and return -EINPROGRESS 2242 * instead. 2243 */ 2244int musb_queue_resume_work(struct musb *musb, 2245 int (*callback)(struct musb *musb, void *data), 2246 void *data) 2247{ 2248 struct musb_pending_work *w; 2249 unsigned long flags; 2250 bool is_suspended; 2251 int error; 2252 2253 if (WARN_ON(!callback)) 2254 return -EINVAL; 2255 2256 spin_lock_irqsave(&musb->list_lock, flags); 2257 is_suspended = musb->is_runtime_suspended; 2258 2259 if (is_suspended) { 2260 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC); 2261 if (!w) { 2262 error = -ENOMEM; 2263 goto out_unlock; 2264 } 2265 2266 w->callback = callback; 2267 w->data = data; 2268 2269 list_add_tail(&w->node, &musb->pending_list); 2270 error = 0; 2271 } 2272 2273out_unlock: 2274 spin_unlock_irqrestore(&musb->list_lock, flags); 2275 2276 if (!is_suspended) 2277 error = callback(musb, data); 2278 2279 return error; 2280} 2281EXPORT_SYMBOL_GPL(musb_queue_resume_work); 2282 2283static void musb_deassert_reset(struct work_struct *work) 2284{ 2285 struct musb *musb; 2286 unsigned long flags; 2287 2288 musb = container_of(work, struct musb, deassert_reset_work.work); 2289 2290 spin_lock_irqsave(&musb->lock, flags); 2291 2292 if (musb->port1_status & USB_PORT_STAT_RESET) 2293 musb_port_reset(musb, false); 2294 2295 spin_unlock_irqrestore(&musb->lock, flags); 2296} 2297 2298/* 2299 * Perform generic per-controller initialization. 2300 * 2301 * @dev: the controller (already clocked, etc) 2302 * @nIrq: IRQ number 2303 * @ctrl: virtual address of controller registers, 2304 * not yet corrected for platform-specific offsets 2305 */ 2306static int 2307musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 2308{ 2309 int status; 2310 struct musb *musb; 2311 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 2312 2313 /* The driver might handle more features than the board; OK. 2314 * Fail when the board needs a feature that's not enabled. 2315 */ 2316 if (!plat) { 2317 dev_err(dev, "no platform_data?\n"); 2318 status = -ENODEV; 2319 goto fail0; 2320 } 2321 2322 /* allocate */ 2323 musb = allocate_instance(dev, plat->config, ctrl); 2324 if (!musb) { 2325 status = -ENOMEM; 2326 goto fail0; 2327 } 2328 2329 spin_lock_init(&musb->lock); 2330 spin_lock_init(&musb->list_lock); 2331 musb->min_power = plat->min_power; 2332 musb->ops = plat->platform_ops; 2333 musb->port_mode = plat->mode; 2334 2335 /* 2336 * Initialize the default IO functions. At least omap2430 needs 2337 * these early. We initialize the platform specific IO functions 2338 * later on. 2339 */ 2340 musb_readb = musb_default_readb; 2341 musb_writeb = musb_default_writeb; 2342 musb_readw = musb_default_readw; 2343 musb_writew = musb_default_writew; 2344 2345 /* The musb_platform_init() call: 2346 * - adjusts musb->mregs 2347 * - sets the musb->isr 2348 * - may initialize an integrated transceiver 2349 * - initializes musb->xceiv, usually by otg_get_phy() 2350 * - stops powering VBUS 2351 * 2352 * There are various transceiver configurations. 2353 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 2354 * external/discrete ones in various flavors (twl4030 family, 2355 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2356 */ 2357 status = musb_platform_init(musb); 2358 if (status < 0) 2359 goto fail1; 2360 2361 if (!musb->isr) { 2362 status = -ENODEV; 2363 goto fail2; 2364 } 2365 2366 2367 /* Most devices use indexed offset or flat offset */ 2368 if (musb->ops->quirks & MUSB_INDEXED_EP) { 2369 musb->io.ep_offset = musb_indexed_ep_offset; 2370 musb->io.ep_select = musb_indexed_ep_select; 2371 } else { 2372 musb->io.ep_offset = musb_flat_ep_offset; 2373 musb->io.ep_select = musb_flat_ep_select; 2374 } 2375 2376 if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE) 2377 musb->g.quirk_avoids_skb_reserve = 1; 2378 2379 /* At least tusb6010 has its own offsets */ 2380 if (musb->ops->ep_offset) 2381 musb->io.ep_offset = musb->ops->ep_offset; 2382 if (musb->ops->ep_select) 2383 musb->io.ep_select = musb->ops->ep_select; 2384 2385 if (musb->ops->fifo_mode) 2386 fifo_mode = musb->ops->fifo_mode; 2387 else 2388 fifo_mode = 4; 2389 2390 if (musb->ops->fifo_offset) 2391 musb->io.fifo_offset = musb->ops->fifo_offset; 2392 else 2393 musb->io.fifo_offset = musb_default_fifo_offset; 2394 2395 if (musb->ops->busctl_offset) 2396 musb->io.busctl_offset = musb->ops->busctl_offset; 2397 else 2398 musb->io.busctl_offset = musb_default_busctl_offset; 2399 2400 if (musb->ops->readb) 2401 musb_readb = musb->ops->readb; 2402 if (musb->ops->writeb) 2403 musb_writeb = musb->ops->writeb; 2404 if (musb->ops->clearb) 2405 musb_clearb = musb->ops->clearb; 2406 else 2407 musb_clearb = musb_readb; 2408 2409 if (musb->ops->readw) 2410 musb_readw = musb->ops->readw; 2411 if (musb->ops->writew) 2412 musb_writew = musb->ops->writew; 2413 if (musb->ops->clearw) 2414 musb_clearw = musb->ops->clearw; 2415 else 2416 musb_clearw = musb_readw; 2417 2418#ifndef CONFIG_MUSB_PIO_ONLY 2419 if (!musb->ops->dma_init || !musb->ops->dma_exit) { 2420 dev_err(dev, "DMA controller not set\n"); 2421 status = -ENODEV; 2422 goto fail2; 2423 } 2424 musb_dma_controller_create = musb->ops->dma_init; 2425 musb_dma_controller_destroy = musb->ops->dma_exit; 2426#endif 2427 2428 if (musb->ops->read_fifo) 2429 musb->io.read_fifo = musb->ops->read_fifo; 2430 else 2431 musb->io.read_fifo = musb_default_read_fifo; 2432 2433 if (musb->ops->write_fifo) 2434 musb->io.write_fifo = musb->ops->write_fifo; 2435 else 2436 musb->io.write_fifo = musb_default_write_fifo; 2437 2438 if (musb->ops->get_toggle) 2439 musb->io.get_toggle = musb->ops->get_toggle; 2440 else 2441 musb->io.get_toggle = musb_default_get_toggle; 2442 2443 if (musb->ops->set_toggle) 2444 musb->io.set_toggle = musb->ops->set_toggle; 2445 else 2446 musb->io.set_toggle = musb_default_set_toggle; 2447 2448 if (IS_ENABLED(CONFIG_USB_PHY) && musb->xceiv && !musb->xceiv->io_ops) { 2449 musb->xceiv->io_dev = musb->controller; 2450 musb->xceiv->io_priv = musb->mregs; 2451 musb->xceiv->io_ops = &musb_ulpi_access; 2452 } 2453 2454 if (musb->ops->phy_callback) 2455 musb_phy_callback = musb->ops->phy_callback; 2456 2457 /* 2458 * We need musb_read/write functions initialized for PM. 2459 * Note that at least 2430 glue needs autosuspend delay 2460 * somewhere above 300 ms for the hardware to idle properly 2461 * after disconnecting the cable in host mode. Let's use 2462 * 500 ms for some margin. 2463 */ 2464 pm_runtime_use_autosuspend(musb->controller); 2465 pm_runtime_set_autosuspend_delay(musb->controller, 500); 2466 pm_runtime_enable(musb->controller); 2467 pm_runtime_get_sync(musb->controller); 2468 2469 status = usb_phy_init(musb->xceiv); 2470 if (status < 0) 2471 goto err_usb_phy_init; 2472 2473 if (use_dma && dev->dma_mask) { 2474 musb->dma_controller = 2475 musb_dma_controller_create(musb, musb->mregs); 2476 if (IS_ERR(musb->dma_controller)) { 2477 status = PTR_ERR(musb->dma_controller); 2478 goto fail2_5; 2479 } 2480 } 2481 2482 /* be sure interrupts are disabled before connecting ISR */ 2483 musb_platform_disable(musb); 2484 musb_disable_interrupts(musb); 2485 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2486 2487 /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */ 2488 musb_writeb(musb->mregs, MUSB_POWER, 0); 2489 2490 /* Init IRQ workqueue before request_irq */ 2491 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work); 2492 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); 2493 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); 2494 2495 /* setup musb parts of the core (especially endpoints) */ 2496 status = musb_core_init(plat->config->multipoint 2497 ? MUSB_CONTROLLER_MHDRC 2498 : MUSB_CONTROLLER_HDRC, musb); 2499 if (status < 0) 2500 goto fail3; 2501 2502 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0); 2503 2504 /* attach to the IRQ */ 2505 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) { 2506 dev_err(dev, "request_irq %d failed!\n", nIrq); 2507 status = -ENODEV; 2508 goto fail3; 2509 } 2510 musb->nIrq = nIrq; 2511 /* FIXME this handles wakeup irqs wrong */ 2512 if (enable_irq_wake(nIrq) == 0) { 2513 musb->irq_wake = 1; 2514 device_init_wakeup(dev, 1); 2515 } else { 2516 musb->irq_wake = 0; 2517 } 2518 2519 /* program PHY to use external vBus if required */ 2520 if (plat->extvbus) { 2521 u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL); 2522 busctl |= MUSB_ULPI_USE_EXTVBUS; 2523 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl); 2524 } 2525 2526 MUSB_DEV_MODE(musb); 2527 musb_set_state(musb, OTG_STATE_B_IDLE); 2528 2529 switch (musb->port_mode) { 2530 case MUSB_HOST: 2531 status = musb_host_setup(musb, plat->power); 2532 if (status < 0) 2533 goto fail3; 2534 status = musb_platform_set_mode(musb, MUSB_HOST); 2535 break; 2536 case MUSB_PERIPHERAL: 2537 status = musb_gadget_setup(musb); 2538 if (status < 0) 2539 goto fail3; 2540 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 2541 break; 2542 case MUSB_OTG: 2543 status = musb_host_setup(musb, plat->power); 2544 if (status < 0) 2545 goto fail3; 2546 status = musb_gadget_setup(musb); 2547 if (status) { 2548 musb_host_cleanup(musb); 2549 goto fail3; 2550 } 2551 status = musb_platform_set_mode(musb, MUSB_OTG); 2552 break; 2553 default: 2554 dev_err(dev, "unsupported port mode %d\n", musb->port_mode); 2555 break; 2556 } 2557 2558 if (status < 0) 2559 goto fail3; 2560 2561 musb_init_debugfs(musb); 2562 2563 musb->is_initialized = 1; 2564 pm_runtime_put_autosuspend(musb->controller); 2565 2566 return 0; 2567 2568fail3: 2569 cancel_delayed_work_sync(&musb->irq_work); 2570 cancel_delayed_work_sync(&musb->finish_resume_work); 2571 cancel_delayed_work_sync(&musb->deassert_reset_work); 2572 if (musb->dma_controller) 2573 musb_dma_controller_destroy(musb->dma_controller); 2574 2575fail2_5: 2576 usb_phy_shutdown(musb->xceiv); 2577 2578err_usb_phy_init: 2579 pm_runtime_dont_use_autosuspend(musb->controller); 2580 pm_runtime_put_sync(musb->controller); 2581 pm_runtime_disable(musb->controller); 2582 2583fail2: 2584 if (musb->irq_wake) 2585 device_init_wakeup(dev, 0); 2586 musb_platform_exit(musb); 2587 2588fail1: 2589 dev_err_probe(musb->controller, status, "%s failed\n", __func__); 2590 2591 musb_free(musb); 2592 2593fail0: 2594 2595 return status; 2596 2597} 2598 2599/*-------------------------------------------------------------------------*/ 2600 2601/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2602 * bridge to a platform device; this driver then suffices. 2603 */ 2604static int musb_probe(struct platform_device *pdev) 2605{ 2606 struct device *dev = &pdev->dev; 2607 int irq = platform_get_irq_byname(pdev, "mc"); 2608 void __iomem *base; 2609 2610 if (irq < 0) 2611 return irq; 2612 2613 base = devm_platform_ioremap_resource(pdev, 0); 2614 if (IS_ERR(base)) 2615 return PTR_ERR(base); 2616 2617 return musb_init_controller(dev, irq, base); 2618} 2619 2620static void musb_remove(struct platform_device *pdev) 2621{ 2622 struct device *dev = &pdev->dev; 2623 struct musb *musb = dev_to_musb(dev); 2624 unsigned long flags; 2625 2626 /* this gets called on rmmod. 2627 * - Host mode: host may still be active 2628 * - Peripheral mode: peripheral is deactivated (or never-activated) 2629 * - OTG mode: both roles are deactivated (or never-activated) 2630 */ 2631 musb_exit_debugfs(musb); 2632 2633 cancel_delayed_work_sync(&musb->irq_work); 2634 cancel_delayed_work_sync(&musb->finish_resume_work); 2635 cancel_delayed_work_sync(&musb->deassert_reset_work); 2636 pm_runtime_get_sync(musb->controller); 2637 musb_host_cleanup(musb); 2638 musb_gadget_cleanup(musb); 2639 2640 musb_platform_disable(musb); 2641 spin_lock_irqsave(&musb->lock, flags); 2642 musb_disable_interrupts(musb); 2643 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2644 spin_unlock_irqrestore(&musb->lock, flags); 2645 musb_platform_exit(musb); 2646 2647 pm_runtime_dont_use_autosuspend(musb->controller); 2648 pm_runtime_put_sync(musb->controller); 2649 pm_runtime_disable(musb->controller); 2650 musb_phy_callback = NULL; 2651 if (musb->dma_controller) 2652 musb_dma_controller_destroy(musb->dma_controller); 2653 usb_phy_shutdown(musb->xceiv); 2654 musb_free(musb); 2655 device_init_wakeup(dev, 0); 2656} 2657 2658#ifdef CONFIG_PM 2659 2660static void musb_save_context(struct musb *musb) 2661{ 2662 int i; 2663 void __iomem *musb_base = musb->mregs; 2664 void __iomem *epio; 2665 2666 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2667 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2668 musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL); 2669 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2670 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2671 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2672 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2673 2674 for (i = 0; i < musb->config->num_eps; ++i) { 2675 epio = musb->endpoints[i].regs; 2676 if (!epio) 2677 continue; 2678 2679 musb_writeb(musb_base, MUSB_INDEX, i); 2680 musb->context.index_regs[i].txmaxp = 2681 musb_readw(epio, MUSB_TXMAXP); 2682 musb->context.index_regs[i].txcsr = 2683 musb_readw(epio, MUSB_TXCSR); 2684 musb->context.index_regs[i].rxmaxp = 2685 musb_readw(epio, MUSB_RXMAXP); 2686 musb->context.index_regs[i].rxcsr = 2687 musb_readw(epio, MUSB_RXCSR); 2688 2689 if (musb->dyn_fifo) { 2690 musb->context.index_regs[i].txfifoadd = 2691 musb_readw(musb_base, MUSB_TXFIFOADD); 2692 musb->context.index_regs[i].rxfifoadd = 2693 musb_readw(musb_base, MUSB_RXFIFOADD); 2694 musb->context.index_regs[i].txfifosz = 2695 musb_readb(musb_base, MUSB_TXFIFOSZ); 2696 musb->context.index_regs[i].rxfifosz = 2697 musb_readb(musb_base, MUSB_RXFIFOSZ); 2698 } 2699 2700 musb->context.index_regs[i].txtype = 2701 musb_readb(epio, MUSB_TXTYPE); 2702 musb->context.index_regs[i].txinterval = 2703 musb_readb(epio, MUSB_TXINTERVAL); 2704 musb->context.index_regs[i].rxtype = 2705 musb_readb(epio, MUSB_RXTYPE); 2706 musb->context.index_regs[i].rxinterval = 2707 musb_readb(epio, MUSB_RXINTERVAL); 2708 2709 musb->context.index_regs[i].txfunaddr = 2710 musb_read_txfunaddr(musb, i); 2711 musb->context.index_regs[i].txhubaddr = 2712 musb_read_txhubaddr(musb, i); 2713 musb->context.index_regs[i].txhubport = 2714 musb_read_txhubport(musb, i); 2715 2716 musb->context.index_regs[i].rxfunaddr = 2717 musb_read_rxfunaddr(musb, i); 2718 musb->context.index_regs[i].rxhubaddr = 2719 musb_read_rxhubaddr(musb, i); 2720 musb->context.index_regs[i].rxhubport = 2721 musb_read_rxhubport(musb, i); 2722 } 2723} 2724 2725static void musb_restore_context(struct musb *musb) 2726{ 2727 int i; 2728 void __iomem *musb_base = musb->mregs; 2729 void __iomem *epio; 2730 u8 power; 2731 2732 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2733 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2734 musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl); 2735 2736 /* Don't affect SUSPENDM/RESUME bits in POWER reg */ 2737 power = musb_readb(musb_base, MUSB_POWER); 2738 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; 2739 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); 2740 power |= musb->context.power; 2741 musb_writeb(musb_base, MUSB_POWER, power); 2742 2743 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); 2744 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); 2745 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2746 if (musb->context.devctl & MUSB_DEVCTL_SESSION) 2747 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2748 2749 for (i = 0; i < musb->config->num_eps; ++i) { 2750 epio = musb->endpoints[i].regs; 2751 if (!epio) 2752 continue; 2753 2754 musb_writeb(musb_base, MUSB_INDEX, i); 2755 musb_writew(epio, MUSB_TXMAXP, 2756 musb->context.index_regs[i].txmaxp); 2757 musb_writew(epio, MUSB_TXCSR, 2758 musb->context.index_regs[i].txcsr); 2759 musb_writew(epio, MUSB_RXMAXP, 2760 musb->context.index_regs[i].rxmaxp); 2761 musb_writew(epio, MUSB_RXCSR, 2762 musb->context.index_regs[i].rxcsr); 2763 2764 if (musb->dyn_fifo) { 2765 musb_writeb(musb_base, MUSB_TXFIFOSZ, 2766 musb->context.index_regs[i].txfifosz); 2767 musb_writeb(musb_base, MUSB_RXFIFOSZ, 2768 musb->context.index_regs[i].rxfifosz); 2769 musb_writew(musb_base, MUSB_TXFIFOADD, 2770 musb->context.index_regs[i].txfifoadd); 2771 musb_writew(musb_base, MUSB_RXFIFOADD, 2772 musb->context.index_regs[i].rxfifoadd); 2773 } 2774 2775 musb_writeb(epio, MUSB_TXTYPE, 2776 musb->context.index_regs[i].txtype); 2777 musb_writeb(epio, MUSB_TXINTERVAL, 2778 musb->context.index_regs[i].txinterval); 2779 musb_writeb(epio, MUSB_RXTYPE, 2780 musb->context.index_regs[i].rxtype); 2781 musb_writeb(epio, MUSB_RXINTERVAL, 2782 2783 musb->context.index_regs[i].rxinterval); 2784 musb_write_txfunaddr(musb, i, 2785 musb->context.index_regs[i].txfunaddr); 2786 musb_write_txhubaddr(musb, i, 2787 musb->context.index_regs[i].txhubaddr); 2788 musb_write_txhubport(musb, i, 2789 musb->context.index_regs[i].txhubport); 2790 2791 musb_write_rxfunaddr(musb, i, 2792 musb->context.index_regs[i].rxfunaddr); 2793 musb_write_rxhubaddr(musb, i, 2794 musb->context.index_regs[i].rxhubaddr); 2795 musb_write_rxhubport(musb, i, 2796 musb->context.index_regs[i].rxhubport); 2797 } 2798 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2799} 2800 2801static int musb_suspend(struct device *dev) 2802{ 2803 struct musb *musb = dev_to_musb(dev); 2804 unsigned long flags; 2805 int ret; 2806 2807 ret = pm_runtime_get_sync(dev); 2808 if (ret < 0) { 2809 pm_runtime_put_noidle(dev); 2810 return ret; 2811 } 2812 2813 musb_platform_disable(musb); 2814 musb_disable_interrupts(musb); 2815 2816 musb->flush_irq_work = true; 2817 while (flush_delayed_work(&musb->irq_work)) 2818 ; 2819 musb->flush_irq_work = false; 2820 2821 if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION)) 2822 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2823 2824 WARN_ON(!list_empty(&musb->pending_list)); 2825 2826 spin_lock_irqsave(&musb->lock, flags); 2827 2828 if (is_peripheral_active(musb)) { 2829 /* FIXME force disconnect unless we know USB will wake 2830 * the system up quickly enough to respond ... 2831 */ 2832 } else if (is_host_active(musb)) { 2833 /* we know all the children are suspended; sometimes 2834 * they will even be wakeup-enabled. 2835 */ 2836 } 2837 2838 musb_save_context(musb); 2839 2840 spin_unlock_irqrestore(&musb->lock, flags); 2841 return 0; 2842} 2843 2844static int musb_resume(struct device *dev) 2845{ 2846 struct musb *musb = dev_to_musb(dev); 2847 unsigned long flags; 2848 int error; 2849 u8 devctl; 2850 u8 mask; 2851 2852 /* 2853 * For static cmos like DaVinci, register values were preserved 2854 * unless for some reason the whole soc powered down or the USB 2855 * module got reset through the PSC (vs just being disabled). 2856 * 2857 * For the DSPS glue layer though, a full register restore has to 2858 * be done. As it shouldn't harm other platforms, we do it 2859 * unconditionally. 2860 */ 2861 2862 musb_restore_context(musb); 2863 2864 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2865 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; 2866 if ((devctl & mask) != (musb->context.devctl & mask)) 2867 musb->port1_status = 0; 2868 2869 musb_enable_interrupts(musb); 2870 musb_platform_enable(musb); 2871 2872 /* session might be disabled in suspend */ 2873 if (musb->port_mode == MUSB_HOST && 2874 !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) { 2875 devctl |= MUSB_DEVCTL_SESSION; 2876 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 2877 } 2878 2879 spin_lock_irqsave(&musb->lock, flags); 2880 error = musb_run_resume_work(musb); 2881 if (error) 2882 dev_err(musb->controller, "resume work failed with %i\n", 2883 error); 2884 spin_unlock_irqrestore(&musb->lock, flags); 2885 2886 pm_runtime_put_autosuspend(dev); 2887 2888 return 0; 2889} 2890 2891static int musb_runtime_suspend(struct device *dev) 2892{ 2893 struct musb *musb = dev_to_musb(dev); 2894 2895 musb_save_context(musb); 2896 musb->is_runtime_suspended = 1; 2897 2898 return 0; 2899} 2900 2901static int musb_runtime_resume(struct device *dev) 2902{ 2903 struct musb *musb = dev_to_musb(dev); 2904 unsigned long flags; 2905 int error; 2906 2907 /* 2908 * When pm_runtime_get_sync called for the first time in driver 2909 * init, some of the structure is still not initialized which is 2910 * used in restore function. But clock needs to be 2911 * enabled before any register access, so 2912 * pm_runtime_get_sync has to be called. 2913 * Also context restore without save does not make 2914 * any sense 2915 */ 2916 if (!musb->is_initialized) 2917 return 0; 2918 2919 musb_restore_context(musb); 2920 2921 spin_lock_irqsave(&musb->lock, flags); 2922 error = musb_run_resume_work(musb); 2923 if (error) 2924 dev_err(musb->controller, "resume work failed with %i\n", 2925 error); 2926 musb->is_runtime_suspended = 0; 2927 spin_unlock_irqrestore(&musb->lock, flags); 2928 2929 return 0; 2930} 2931 2932static const struct dev_pm_ops musb_dev_pm_ops = { 2933 .suspend = musb_suspend, 2934 .resume = musb_resume, 2935 .runtime_suspend = musb_runtime_suspend, 2936 .runtime_resume = musb_runtime_resume, 2937}; 2938 2939#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2940#else 2941#define MUSB_DEV_PM_OPS NULL 2942#endif 2943 2944static struct platform_driver musb_driver = { 2945 .driver = { 2946 .name = musb_driver_name, 2947 .bus = &platform_bus_type, 2948 .pm = MUSB_DEV_PM_OPS, 2949 .dev_groups = musb_groups, 2950 }, 2951 .probe = musb_probe, 2952 .remove = musb_remove, 2953}; 2954 2955module_platform_driver(musb_driver);
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