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xhci.h
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linux-6.19.14/drivers/usb/host/xhci.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2 3/* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12#ifndef __LINUX_XHCI_HCD_H 13#define __LINUX_XHCI_HCD_H 14 15#include <linux/usb.h> 16#include <linux/timer.h> 17#include <linux/kernel.h> 18#include <linux/usb/hcd.h> 19#include <linux/io-64-nonatomic-lo-hi.h> 20#include <linux/io-64-nonatomic-hi-lo.h> 21 22/* Code sharing between pci-quirks and xhci hcd */ 23#include "xhci-ext-caps.h" 24#include "pci-quirks.h" 25 26#include "xhci-port.h" 27#include "xhci-caps.h" 28 29/* max buffer size for trace and debug messages */ 30#define XHCI_MSG_MAX 500 31 32/* xHCI PCI Configuration Registers */ 33#define XHCI_SBRN_OFFSET (0x60) 34 35/* Max number of USB devices for any host controller - limit in section 6.1 */ 36#define MAX_HC_SLOTS 256 37/* 38 * Max Number of Ports. xHCI specification section 5.3.3 39 * Valid values are in the range of 1 to 255. 40 */ 41#define MAX_HC_PORTS 127 42/* 43 * Max number of Interrupter Register Sets. xHCI specification section 5.3.3 44 * Valid values are in the range of 1 to 1024. 45 */ 46#define MAX_HC_INTRS 128 47 48/* 49 * xHCI register interface. 50 * This corresponds to the eXtensible Host Controller Interface (xHCI) 51 * Revision 0.95 specification 52 */ 53 54/** 55 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 56 * @hc_capbase: length of the capabilities register and HC version number 57 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 58 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 59 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 60 * @hcc_params: HCCPARAMS - Capability Parameters 61 * @db_off: DBOFF - Doorbell array offset 62 * @run_regs_off: RTSOFF - Runtime register space offset 63 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 64 */ 65struct xhci_cap_regs { 66 __le32 hc_capbase; 67 __le32 hcs_params1; 68 __le32 hcs_params2; 69 __le32 hcs_params3; 70 __le32 hcc_params; 71 __le32 db_off; 72 __le32 run_regs_off; 73 __le32 hcc_params2; /* xhci 1.1 */ 74 /* Reserved up to (CAPLENGTH - 0x1C) */ 75}; 76 77/* 78 * struct xhci_port_regs - Host Controller USB Port Register Set. xHCI spec 5.4.8 79 * @portsc: Port Status and Control 80 * @portpmsc: Port Power Management Status and Control 81 * @portli: Port Link Info 82 * @porthlmpc: Port Hardware LPM Control 83 */ 84struct xhci_port_regs { 85 __le32 portsc; 86 __le32 portpmsc; 87 __le32 portli; 88 __le32 porthlmpc; 89}; 90 91/** 92 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 93 * @command: USBCMD - xHC command register 94 * @status: USBSTS - xHC status register 95 * @page_size: This indicates the page size that the host controller 96 * supports. If bit n is set, the HC supports a page size 97 * of 2^(n+12), up to a 128MB page size. 98 * 4K is the minimum page size. 99 * @cmd_ring: CRP - 64-bit Command Ring Pointer 100 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 101 * @config_reg: CONFIG - Configure Register 102 * @port_regs: Port Register Sets, from 1 to MaxPorts (defined by HCSPARAMS1). 103 */ 104struct xhci_op_regs { 105 __le32 command; 106 __le32 status; 107 __le32 page_size; 108 __le32 reserved1; 109 __le32 reserved2; 110 __le32 dev_notification; 111 __le64 cmd_ring; 112 /* rsvd: offset 0x20-2F */ 113 __le32 reserved3[4]; 114 __le64 dcbaa_ptr; 115 __le32 config_reg; 116 /* rsvd: offset 0x3C-3FF */ 117 __le32 reserved4[241]; 118 struct xhci_port_regs port_regs[]; 119}; 120 121/* USBCMD - USB command - command bitmasks */ 122/* start/stop HC execution - do not write unless HC is halted*/ 123#define CMD_RUN XHCI_CMD_RUN 124/* Reset HC - resets internal HC state machine and all registers (except 125 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 126 * The xHCI driver must reinitialize the xHC after setting this bit. 127 */ 128#define CMD_RESET (1 << 1) 129/* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 130#define CMD_EIE XHCI_CMD_EIE 131/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 132#define CMD_HSEIE XHCI_CMD_HSEIE 133/* bits 4:6 are reserved (and should be preserved on writes). */ 134/* light reset (port status stays unchanged) - reset completed when this is 0 */ 135#define CMD_LRESET (1 << 7) 136/* host controller save/restore state. */ 137#define CMD_CSS (1 << 8) 138#define CMD_CRS (1 << 9) 139/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 140#define CMD_EWE XHCI_CMD_EWE 141/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 142 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 143 * '0' means the xHC can power it off if all ports are in the disconnect, 144 * disabled, or powered-off state. 145 */ 146#define CMD_PM_INDEX (1 << 11) 147/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 148#define CMD_ETE (1 << 14) 149/* bits 15:31 are reserved (and should be preserved on writes). */ 150 151#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 152#define XHCI_RESET_SHORT_USEC (250 * 1000) 153 154/* USBSTS - USB status - status bitmasks */ 155/* HC not running - set to 1 when run/stop bit is cleared. */ 156#define STS_HALT XHCI_STS_HALT 157/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 158#define STS_FATAL (1 << 2) 159/* event interrupt - clear this prior to clearing any IP flags in IR set*/ 160#define STS_EINT (1 << 3) 161/* port change detect */ 162#define STS_PORT (1 << 4) 163/* bits 5:7 reserved and zeroed */ 164/* save state status - '1' means xHC is saving state */ 165#define STS_SAVE (1 << 8) 166/* restore state status - '1' means xHC is restoring state */ 167#define STS_RESTORE (1 << 9) 168/* true: save or restore error */ 169#define STS_SRE (1 << 10) 170/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 171#define STS_CNR XHCI_STS_CNR 172/* true: internal Host Controller Error - SW needs to reset and reinitialize */ 173#define STS_HCE (1 << 12) 174/* bits 13:31 reserved and should be preserved */ 175 176/* 177 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 178 * Generate a device notification event when the HC sees a transaction with a 179 * notification type that matches a bit set in this bit field. 180 */ 181#define DEV_NOTE_MASK (0xffff) 182/* Most of the device notification types should only be used for debug. 183 * SW does need to pay attention to function wake notifications. 184 */ 185#define DEV_NOTE_FWAKE (1 << 1) 186 187/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 188/* bit 0 - Cycle bit indicates the ownership of the command ring */ 189#define CMD_RING_CYCLE (1 << 0) 190/* stop ring operation after completion of the currently executing command */ 191#define CMD_RING_PAUSE (1 << 1) 192/* stop ring immediately - abort the currently executing command */ 193#define CMD_RING_ABORT (1 << 2) 194/* true: command ring is running */ 195#define CMD_RING_RUNNING (1 << 3) 196/* bits 63:6 - Command Ring pointer */ 197#define CMD_RING_PTR_MASK GENMASK_ULL(63, 6) 198 199/* CONFIG - Configure Register - config_reg bitmasks */ 200/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 201#define MAX_DEVS(p) ((p) & 0xff) 202/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 203#define CONFIG_U3E (1 << 8) 204/* bit 9: Configuration Information Enable, xhci 1.1 */ 205#define CONFIG_CIE (1 << 9) 206/* bits 10:31 - reserved and should be preserved */ 207 208/* bits 15:0 - HCD page shift bit */ 209#define XHCI_PAGE_SIZE_MASK 0xffff 210 211/** 212 * struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2. 213 * @iman: IMAN - Interrupt Management Register. Used to enable 214 * interrupts and check for pending interrupts. 215 * @imod: IMOD - Interrupt Moderation Register. Used to throttle interrupts. 216 * @erst_size: ERSTSZ - Number of segments in the Event Ring Segment Table (ERST). 217 * @erst_base: ERSTBA - Event ring segment table base address. 218 * @erst_dequeue: ERDP - Event ring dequeue pointer. 219 * 220 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 221 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 222 * multiple segments of the same size. The HC places events on the ring and 223 * "updates the Cycle bit in the TRBs to indicate to software the current 224 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 225 * updates the dequeue pointer. 226 */ 227struct xhci_intr_reg { 228 __le32 iman; 229 __le32 imod; 230 __le32 erst_size; 231 __le32 rsvd; 232 __le64 erst_base; 233 __le64 erst_dequeue; 234}; 235 236/* iman bitmasks */ 237/* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */ 238#define IMAN_IP (1 << 0) 239/* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */ 240#define IMAN_IE (1 << 1) 241 242/* imod bitmasks */ 243/* 244 * bits 15:0 - Interrupt Moderation Interval, the minimum interval between interrupts 245 * (in 250ns intervals). The interval between interrupts will be longer if there are no 246 * events on the event ring. Default is 4000 (1 ms). 247 */ 248#define IMODI_MASK (0xffff) 249/* bits 31:16 - Interrupt Moderation Counter, used to count down the time to the next interrupt */ 250#define IMODC_MASK (0xffff << 16) 251 252/* erst_size bitmasks */ 253/* bits 15:0 - Event Ring Segment Table Size, number of ERST entries */ 254#define ERST_SIZE_MASK (0xffff) 255 256/* erst_base bitmasks */ 257/* bits 63:6 - Event Ring Segment Table Base Address Register */ 258#define ERST_BASE_ADDRESS_MASK GENMASK_ULL(63, 6) 259 260/* erst_dequeue bitmasks */ 261/* 262 * bits 2:0 - Dequeue ERST Segment Index (DESI), is the segment number (or alias) where the 263 * current dequeue pointer lies. This is an optional HW hint. 264 */ 265#define ERST_DESI_MASK (0x7) 266/* 267 * bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by 268 * a work queue (or delayed service routine)? 269 */ 270#define ERST_EHB (1 << 3) 271/* bits 63:4 - Event Ring Dequeue Pointer */ 272#define ERST_PTR_MASK GENMASK_ULL(63, 4) 273 274/** 275 * struct xhci_run_regs 276 * @microframe_index: 277 * MFINDEX - current microframe number 278 * 279 * Section 5.5 Host Controller Runtime Registers: 280 * "Software should read and write these registers using only Dword (32 bit) 281 * or larger accesses" 282 */ 283struct xhci_run_regs { 284 __le32 microframe_index; 285 __le32 rsvd[7]; 286 struct xhci_intr_reg ir_set[1024]; 287}; 288 289/** 290 * struct doorbell_array 291 * 292 * Bits 0 - 7: Endpoint target 293 * Bits 8 - 15: RsvdZ 294 * Bits 16 - 31: Stream ID 295 * 296 * Section 5.6 297 */ 298struct xhci_doorbell_array { 299 __le32 doorbell[256]; 300}; 301 302#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 303#define DB_VALUE_HOST 0x00000000 304 305#define PLT_MASK (0x03 << 6) 306#define PLT_SYM (0x00 << 6) 307#define PLT_ASYM_RX (0x02 << 6) 308#define PLT_ASYM_TX (0x03 << 6) 309 310/** 311 * struct xhci_container_ctx 312 * @type: Type of context. Used to calculated offsets to contained contexts. 313 * @size: Size of the context data 314 * @bytes: The raw context data given to HW 315 * @dma: dma address of the bytes 316 * 317 * Represents either a Device or Input context. Holds a pointer to the raw 318 * memory used for the context (bytes) and dma address of it (dma). 319 */ 320struct xhci_container_ctx { 321 unsigned type; 322#define XHCI_CTX_TYPE_DEVICE 0x1 323#define XHCI_CTX_TYPE_INPUT 0x2 324 325 int size; 326 327 u8 *bytes; 328 dma_addr_t dma; 329}; 330 331/** 332 * struct xhci_slot_ctx 333 * @dev_info: Route string, device speed, hub info, and last valid endpoint 334 * @dev_info2: Max exit latency for device number, root hub port number 335 * @tt_info: tt_info is used to construct split transaction tokens 336 * @dev_state: slot state and device address 337 * 338 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 339 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 340 * reserved at the end of the slot context for HC internal use. 341 */ 342struct xhci_slot_ctx { 343 __le32 dev_info; 344 __le32 dev_info2; 345 __le32 tt_info; 346 __le32 dev_state; 347 /* offset 0x10 to 0x1f reserved for HC internal use */ 348 __le32 reserved[4]; 349}; 350 351/* dev_info bitmasks */ 352/* Route String - 0:19 */ 353#define ROUTE_STRING_MASK (0xfffff) 354/* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 355#define DEV_SPEED (0xf << 20) 356#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 357/* bit 24 reserved */ 358/* Is this LS/FS device connected through a HS hub? - bit 25 */ 359#define DEV_MTT (0x1 << 25) 360/* Set if the device is a hub - bit 26 */ 361#define DEV_HUB (0x1 << 26) 362/* Index of the last valid endpoint context in this device context - 27:31 */ 363#define LAST_CTX_MASK (0x1f << 27) 364#define LAST_CTX(p) ((p) << 27) 365#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 366#define SLOT_FLAG (1 << 0) 367#define EP0_FLAG (1 << 1) 368 369/* dev_info2 bitmasks */ 370/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 371#define MAX_EXIT (0xffff) 372/* Root hub port number that is needed to access the USB device */ 373#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 374#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 375/* Maximum number of ports under a hub device */ 376#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 377#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 378 379/* tt_info bitmasks */ 380/* 381 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 382 * The Slot ID of the hub that isolates the high speed signaling from 383 * this low or full-speed device. '0' if attached to root hub port. 384 */ 385#define TT_SLOT (0xff) 386/* 387 * The number of the downstream facing port of the high-speed hub 388 * '0' if the device is not low or full speed. 389 */ 390#define TT_PORT (0xff << 8) 391#define TT_THINK_TIME(p) (((p) & 0x3) << 16) 392#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 393 394/* dev_state bitmasks */ 395/* USB device address - assigned by the HC */ 396#define DEV_ADDR_MASK (0xff) 397/* bits 8:26 reserved */ 398/* Slot state */ 399#define SLOT_STATE (0x1f << 27) 400#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 401 402#define SLOT_STATE_DISABLED 0 403#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 404#define SLOT_STATE_DEFAULT 1 405#define SLOT_STATE_ADDRESSED 2 406#define SLOT_STATE_CONFIGURED 3 407 408/** 409 * struct xhci_ep_ctx 410 * @ep_info: endpoint state, streams, mult, and interval information. 411 * @ep_info2: information on endpoint type, max packet size, max burst size, 412 * error count, and whether the HC will force an event for all 413 * transactions. 414 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 415 * defines one stream, this points to the endpoint transfer ring. 416 * Otherwise, it points to a stream context array, which has a 417 * ring pointer for each flow. 418 * @tx_info: 419 * Average TRB lengths for the endpoint ring and 420 * max payload within an Endpoint Service Interval Time (ESIT). 421 * 422 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 423 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 424 * reserved at the end of the endpoint context for HC internal use. 425 */ 426struct xhci_ep_ctx { 427 __le32 ep_info; 428 __le32 ep_info2; 429 __le64 deq; 430 __le32 tx_info; 431 /* offset 0x14 - 0x1f reserved for HC internal use */ 432 __le32 reserved[3]; 433}; 434 435/* ep_info bitmasks */ 436/* 437 * Endpoint State - bits 0:2 438 * 0 - disabled 439 * 1 - running 440 * 2 - halted due to halt condition - ok to manipulate endpoint ring 441 * 3 - stopped 442 * 4 - TRB error 443 * 5-7 - reserved 444 */ 445#define EP_STATE_MASK (0x7) 446#define EP_STATE_DISABLED 0 447#define EP_STATE_RUNNING 1 448#define EP_STATE_HALTED 2 449#define EP_STATE_STOPPED 3 450#define EP_STATE_ERROR 4 451#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 452 453/* Mult - Max number of burtst within an interval, in EP companion desc. */ 454#define EP_MULT(p) (((p) & 0x3) << 8) 455#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 456/* bits 10:14 are Max Primary Streams */ 457/* bit 15 is Linear Stream Array */ 458/* Interval - period between requests to an endpoint - 125u increments. */ 459#define EP_INTERVAL(p) (((p) & 0xff) << 16) 460#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 461#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 462#define EP_MAXPSTREAMS_MASK (0x1f << 10) 463#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 464#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 465/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 466#define EP_HAS_LSA (1 << 15) 467/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 468#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 469 470/* ep_info2 bitmasks */ 471/* 472 * Force Event - generate transfer events for all TRBs for this endpoint 473 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 474 */ 475#define FORCE_EVENT (0x1) 476#define ERROR_COUNT(p) (((p) & 0x3) << 1) 477#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 478#define EP_TYPE(p) ((p) << 3) 479#define ISOC_OUT_EP 1 480#define BULK_OUT_EP 2 481#define INT_OUT_EP 3 482#define CTRL_EP 4 483#define ISOC_IN_EP 5 484#define BULK_IN_EP 6 485#define INT_IN_EP 7 486/* bit 6 reserved */ 487/* bit 7 is Host Initiate Disable - for disabling stream selection */ 488#define MAX_BURST(p) (((p)&0xff) << 8) 489#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 490#define MAX_PACKET(p) (((p)&0xffff) << 16) 491#define MAX_PACKET_MASK (0xffff << 16) 492#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 493 494/* tx_info bitmasks */ 495#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 496#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 497#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 498#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 499 500/* deq bitmasks */ 501#define EP_CTX_CYCLE_MASK (1 << 0) 502/* bits 63:4 - TR Dequeue Pointer */ 503#define TR_DEQ_PTR_MASK GENMASK_ULL(63, 4) 504 505 506/** 507 * struct xhci_input_control_context 508 * Input control context; see section 6.2.5. 509 * 510 * @drop_context: set the bit of the endpoint context you want to disable 511 * @add_context: set the bit of the endpoint context you want to enable 512 */ 513struct xhci_input_control_ctx { 514 __le32 drop_flags; 515 __le32 add_flags; 516 __le32 rsvd2[6]; 517}; 518 519#define EP_IS_ADDED(ctrl_ctx, i) \ 520 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 521#define EP_IS_DROPPED(ctrl_ctx, i) \ 522 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 523 524/* Represents everything that is needed to issue a command on the command ring. 525 * It's useful to pre-allocate these for commands that cannot fail due to 526 * out-of-memory errors, like freeing streams. 527 */ 528struct xhci_command { 529 /* Input context for changing device state */ 530 struct xhci_container_ctx *in_ctx; 531 u32 status; 532 u32 comp_param; 533 int slot_id; 534 /* If completion is null, no one is waiting on this command 535 * and the structure can be freed after the command completes. 536 */ 537 struct completion *completion; 538 union xhci_trb *command_trb; 539 struct list_head cmd_list; 540 /* xHCI command response timeout in milliseconds */ 541 unsigned int timeout_ms; 542}; 543 544/* drop context bitmasks */ 545#define DROP_EP(x) (0x1 << x) 546/* add context bitmasks */ 547#define ADD_EP(x) (0x1 << x) 548 549struct xhci_stream_ctx { 550 /* 64-bit stream ring address, cycle state, and stream type */ 551 __le64 stream_ring; 552 /* offset 0x14 - 0x1f reserved for HC internal use */ 553 __le32 reserved[2]; 554}; 555 556/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 557#define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 558#define CTX_TO_SCT(p) (((p) >> 1) & 0x7) 559/* Secondary stream array type, dequeue pointer is to a transfer ring */ 560#define SCT_SEC_TR 0 561/* Primary stream array type, dequeue pointer is to a transfer ring */ 562#define SCT_PRI_TR 1 563/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 564#define SCT_SSA_8 2 565#define SCT_SSA_16 3 566#define SCT_SSA_32 4 567#define SCT_SSA_64 5 568#define SCT_SSA_128 6 569#define SCT_SSA_256 7 570 571/* Assume no secondary streams for now */ 572struct xhci_stream_info { 573 struct xhci_ring **stream_rings; 574 /* Number of streams, including stream 0 (which drivers can't use) */ 575 unsigned int num_streams; 576 /* The stream context array may be bigger than 577 * the number of streams the driver asked for 578 */ 579 struct xhci_stream_ctx *stream_ctx_array; 580 unsigned int num_stream_ctxs; 581 dma_addr_t ctx_array_dma; 582 /* For mapping physical TRB addresses to segments in stream rings */ 583 struct radix_tree_root trb_address_map; 584 struct xhci_command *free_streams_command; 585}; 586 587#define SMALL_STREAM_ARRAY_SIZE 256 588#define MEDIUM_STREAM_ARRAY_SIZE 1024 589#define GET_PORT_BW_ARRAY_SIZE 256 590 591/* Some Intel xHCI host controllers need software to keep track of the bus 592 * bandwidth. Keep track of endpoint info here. Each root port is allocated 593 * the full bus bandwidth. We must also treat TTs (including each port under a 594 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 595 * (DMI) also limits the total bandwidth (across all domains) that can be used. 596 */ 597struct xhci_bw_info { 598 /* ep_interval is zero-based */ 599 unsigned int ep_interval; 600 /* mult and num_packets are one-based */ 601 unsigned int mult; 602 unsigned int num_packets; 603 unsigned int max_packet_size; 604 unsigned int max_esit_payload; 605 unsigned int type; 606}; 607 608/* "Block" sizes in bytes the hardware uses for different device speeds. 609 * The logic in this part of the hardware limits the number of bits the hardware 610 * can use, so must represent bandwidth in a less precise manner to mimic what 611 * the scheduler hardware computes. 612 */ 613#define FS_BLOCK 1 614#define HS_BLOCK 4 615#define SS_BLOCK 16 616#define DMI_BLOCK 32 617 618/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 619 * with each byte transferred. SuperSpeed devices have an initial overhead to 620 * set up bursts. These are in blocks, see above. LS overhead has already been 621 * translated into FS blocks. 622 */ 623#define DMI_OVERHEAD 8 624#define DMI_OVERHEAD_BURST 4 625#define SS_OVERHEAD 8 626#define SS_OVERHEAD_BURST 32 627#define HS_OVERHEAD 26 628#define FS_OVERHEAD 20 629#define LS_OVERHEAD 128 630/* The TTs need to claim roughly twice as much bandwidth (94 bytes per 631 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 632 * of overhead associated with split transfers crossing microframe boundaries. 633 * 31 blocks is pure protocol overhead. 634 */ 635#define TT_HS_OVERHEAD (31 + 94) 636#define TT_DMI_OVERHEAD (25 + 12) 637 638/* Bandwidth limits in blocks */ 639#define FS_BW_LIMIT 1285 640#define TT_BW_LIMIT 1320 641#define HS_BW_LIMIT 1607 642#define SS_BW_LIMIT_IN 3906 643#define DMI_BW_LIMIT_IN 3906 644#define SS_BW_LIMIT_OUT 3906 645#define DMI_BW_LIMIT_OUT 3906 646 647/* Percentage of bus bandwidth reserved for non-periodic transfers */ 648#define FS_BW_RESERVED 10 649#define HS_BW_RESERVED 20 650#define SS_BW_RESERVED 10 651 652struct xhci_virt_ep { 653 struct xhci_virt_device *vdev; /* parent */ 654 unsigned int ep_index; 655 struct xhci_ring *ring; 656 /* Related to endpoints that are configured to use stream IDs only */ 657 struct xhci_stream_info *stream_info; 658 /* Temporary storage in case the configure endpoint command fails and we 659 * have to restore the device state to the previous state 660 */ 661 struct xhci_ring *new_ring; 662 unsigned int err_count; 663 unsigned int ep_state; 664#define SET_DEQ_PENDING (1 << 0) 665#define EP_HALTED (1 << 1) /* For stall handling */ 666#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 667/* Transitioning the endpoint to using streams, don't enqueue URBs */ 668#define EP_GETTING_STREAMS (1 << 3) 669#define EP_HAS_STREAMS (1 << 4) 670/* Transitioning the endpoint to not using streams, don't enqueue URBs */ 671#define EP_GETTING_NO_STREAMS (1 << 5) 672#define EP_HARD_CLEAR_TOGGLE (1 << 6) 673#define EP_SOFT_CLEAR_TOGGLE (1 << 7) 674/* usb_hub_clear_tt_buffer is in progress */ 675#define EP_CLEARING_TT (1 << 8) 676 /* ---- Related to URB cancellation ---- */ 677 struct list_head cancelled_td_list; 678 struct xhci_hcd *xhci; 679 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 680 * command. We'll need to update the ring's dequeue segment and dequeue 681 * pointer after the command completes. 682 */ 683 struct xhci_segment *queued_deq_seg; 684 union xhci_trb *queued_deq_ptr; 685 /* 686 * Sometimes the xHC can not process isochronous endpoint ring quickly 687 * enough, and it will miss some isoc tds on the ring and generate 688 * a Missed Service Error Event. 689 * Set skip flag when receive a Missed Service Error Event and 690 * process the missed tds on the endpoint ring. 691 */ 692 bool skip; 693 /* Bandwidth checking storage */ 694 struct xhci_bw_info bw_info; 695 struct list_head bw_endpoint_list; 696 unsigned long stop_time; 697 /* Isoch Frame ID checking storage */ 698 int next_frame_id; 699 /* Use new Isoch TRB layout needed for extended TBC support */ 700 bool use_extended_tbc; 701 /* set if this endpoint is controlled via sideband access*/ 702 struct xhci_sideband *sideband; 703}; 704 705enum xhci_overhead_type { 706 LS_OVERHEAD_TYPE = 0, 707 FS_OVERHEAD_TYPE, 708 HS_OVERHEAD_TYPE, 709}; 710 711struct xhci_interval_bw { 712 unsigned int num_packets; 713 /* Sorted by max packet size. 714 * Head of the list is the greatest max packet size. 715 */ 716 struct list_head endpoints; 717 /* How many endpoints of each speed are present. */ 718 unsigned int overhead[3]; 719}; 720 721#define XHCI_MAX_INTERVAL 16 722 723struct xhci_interval_bw_table { 724 unsigned int interval0_esit_payload; 725 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 726 /* Includes reserved bandwidth for async endpoints */ 727 unsigned int bw_used; 728 unsigned int ss_bw_in; 729 unsigned int ss_bw_out; 730}; 731 732#define EP_CTX_PER_DEV 31 733 734struct xhci_virt_device { 735 int slot_id; 736 struct usb_device *udev; 737 /* 738 * Commands to the hardware are passed an "input context" that 739 * tells the hardware what to change in its data structures. 740 * The hardware will return changes in an "output context" that 741 * software must allocate for the hardware. We need to keep 742 * track of input and output contexts separately because 743 * these commands might fail and we don't trust the hardware. 744 */ 745 struct xhci_container_ctx *out_ctx; 746 /* Used for addressing devices and configuration changes */ 747 struct xhci_container_ctx *in_ctx; 748 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 749 struct xhci_port *rhub_port; 750 struct xhci_interval_bw_table *bw_table; 751 struct xhci_tt_bw_info *tt_info; 752 /* 753 * flags for state tracking based on events and issued commands. 754 * Software can not rely on states from output contexts because of 755 * latency between events and xHC updating output context values. 756 * See xhci 1.1 section 4.8.3 for more details 757 */ 758 unsigned long flags; 759#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 760 761 /* The current max exit latency for the enabled USB3 link states. */ 762 u16 current_mel; 763 /* Used for the debugfs interfaces. */ 764 void *debugfs_private; 765 /* set if this endpoint is controlled via sideband access*/ 766 struct xhci_sideband *sideband; 767}; 768 769/* 770 * For each roothub, keep track of the bandwidth information for each periodic 771 * interval. 772 * 773 * If a high speed hub is attached to the roothub, each TT associated with that 774 * hub is a separate bandwidth domain. The interval information for the 775 * endpoints on the devices under that TT will appear in the TT structure. 776 */ 777struct xhci_root_port_bw_info { 778 struct list_head tts; 779 unsigned int num_active_tts; 780 struct xhci_interval_bw_table bw_table; 781}; 782 783struct xhci_tt_bw_info { 784 struct list_head tt_list; 785 int slot_id; 786 int ttport; 787 struct xhci_interval_bw_table bw_table; 788 int active_eps; 789}; 790 791 792/** 793 * struct xhci_device_context_array 794 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 795 */ 796struct xhci_device_context_array { 797 /* 64-bit device addresses; we only write 32-bit addresses */ 798 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 799 /* private xHCD pointers */ 800 dma_addr_t dma; 801}; 802/* 803 * TODO: change this to be dynamically sized at HC mem init time since the HC 804 * might not be able to handle the maximum number of devices possible. 805 */ 806 807 808struct xhci_transfer_event { 809 /* 64-bit buffer address, or immediate data */ 810 __le64 buffer; 811 __le32 transfer_len; 812 /* This field is interpreted differently based on the type of TRB */ 813 __le32 flags; 814}; 815 816/* Transfer event flags bitfield, also for select command completion events */ 817#define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) 818#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 819 820#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */ 821#define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16) 822 823#define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */ 824#define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 825 826/* Transfer event TRB length bit mask */ 827#define EVENT_TRB_LEN(p) ((p) & 0xffffff) 828 829/* Completion Code - only applicable for some types of TRBs */ 830#define COMP_CODE_MASK (0xff << 24) 831#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 832#define COMP_INVALID 0 833#define COMP_SUCCESS 1 834#define COMP_DATA_BUFFER_ERROR 2 835#define COMP_BABBLE_DETECTED_ERROR 3 836#define COMP_USB_TRANSACTION_ERROR 4 837#define COMP_TRB_ERROR 5 838#define COMP_STALL_ERROR 6 839#define COMP_RESOURCE_ERROR 7 840#define COMP_BANDWIDTH_ERROR 8 841#define COMP_NO_SLOTS_AVAILABLE_ERROR 9 842#define COMP_INVALID_STREAM_TYPE_ERROR 10 843#define COMP_SLOT_NOT_ENABLED_ERROR 11 844#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 845#define COMP_SHORT_PACKET 13 846#define COMP_RING_UNDERRUN 14 847#define COMP_RING_OVERRUN 15 848#define COMP_VF_EVENT_RING_FULL_ERROR 16 849#define COMP_PARAMETER_ERROR 17 850#define COMP_BANDWIDTH_OVERRUN_ERROR 18 851#define COMP_CONTEXT_STATE_ERROR 19 852#define COMP_NO_PING_RESPONSE_ERROR 20 853#define COMP_EVENT_RING_FULL_ERROR 21 854#define COMP_INCOMPATIBLE_DEVICE_ERROR 22 855#define COMP_MISSED_SERVICE_ERROR 23 856#define COMP_COMMAND_RING_STOPPED 24 857#define COMP_COMMAND_ABORTED 25 858#define COMP_STOPPED 26 859#define COMP_STOPPED_LENGTH_INVALID 27 860#define COMP_STOPPED_SHORT_PACKET 28 861#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 862#define COMP_ISOCH_BUFFER_OVERRUN 31 863#define COMP_EVENT_LOST_ERROR 32 864#define COMP_UNDEFINED_ERROR 33 865#define COMP_INVALID_STREAM_ID_ERROR 34 866#define COMP_SECONDARY_BANDWIDTH_ERROR 35 867#define COMP_SPLIT_TRANSACTION_ERROR 36 868 869static inline const char *xhci_trb_comp_code_string(u8 status) 870{ 871 switch (status) { 872 case COMP_INVALID: 873 return "Invalid"; 874 case COMP_SUCCESS: 875 return "Success"; 876 case COMP_DATA_BUFFER_ERROR: 877 return "Data Buffer Error"; 878 case COMP_BABBLE_DETECTED_ERROR: 879 return "Babble Detected"; 880 case COMP_USB_TRANSACTION_ERROR: 881 return "USB Transaction Error"; 882 case COMP_TRB_ERROR: 883 return "TRB Error"; 884 case COMP_STALL_ERROR: 885 return "Stall Error"; 886 case COMP_RESOURCE_ERROR: 887 return "Resource Error"; 888 case COMP_BANDWIDTH_ERROR: 889 return "Bandwidth Error"; 890 case COMP_NO_SLOTS_AVAILABLE_ERROR: 891 return "No Slots Available Error"; 892 case COMP_INVALID_STREAM_TYPE_ERROR: 893 return "Invalid Stream Type Error"; 894 case COMP_SLOT_NOT_ENABLED_ERROR: 895 return "Slot Not Enabled Error"; 896 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 897 return "Endpoint Not Enabled Error"; 898 case COMP_SHORT_PACKET: 899 return "Short Packet"; 900 case COMP_RING_UNDERRUN: 901 return "Ring Underrun"; 902 case COMP_RING_OVERRUN: 903 return "Ring Overrun"; 904 case COMP_VF_EVENT_RING_FULL_ERROR: 905 return "VF Event Ring Full Error"; 906 case COMP_PARAMETER_ERROR: 907 return "Parameter Error"; 908 case COMP_BANDWIDTH_OVERRUN_ERROR: 909 return "Bandwidth Overrun Error"; 910 case COMP_CONTEXT_STATE_ERROR: 911 return "Context State Error"; 912 case COMP_NO_PING_RESPONSE_ERROR: 913 return "No Ping Response Error"; 914 case COMP_EVENT_RING_FULL_ERROR: 915 return "Event Ring Full Error"; 916 case COMP_INCOMPATIBLE_DEVICE_ERROR: 917 return "Incompatible Device Error"; 918 case COMP_MISSED_SERVICE_ERROR: 919 return "Missed Service Error"; 920 case COMP_COMMAND_RING_STOPPED: 921 return "Command Ring Stopped"; 922 case COMP_COMMAND_ABORTED: 923 return "Command Aborted"; 924 case COMP_STOPPED: 925 return "Stopped"; 926 case COMP_STOPPED_LENGTH_INVALID: 927 return "Stopped - Length Invalid"; 928 case COMP_STOPPED_SHORT_PACKET: 929 return "Stopped - Short Packet"; 930 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 931 return "Max Exit Latency Too Large Error"; 932 case COMP_ISOCH_BUFFER_OVERRUN: 933 return "Isoch Buffer Overrun"; 934 case COMP_EVENT_LOST_ERROR: 935 return "Event Lost Error"; 936 case COMP_UNDEFINED_ERROR: 937 return "Undefined Error"; 938 case COMP_INVALID_STREAM_ID_ERROR: 939 return "Invalid Stream ID Error"; 940 case COMP_SECONDARY_BANDWIDTH_ERROR: 941 return "Secondary Bandwidth Error"; 942 case COMP_SPLIT_TRANSACTION_ERROR: 943 return "Split Transaction Error"; 944 default: 945 return "Unknown!!"; 946 } 947} 948 949struct xhci_link_trb { 950 /* 64-bit segment pointer*/ 951 __le64 segment_ptr; 952 __le32 intr_target; 953 __le32 control; 954}; 955 956/* control bitfields */ 957#define LINK_TOGGLE (0x1<<1) 958 959/* Command completion event TRB */ 960struct xhci_event_cmd { 961 /* Pointer to command TRB, or the value passed by the event data trb */ 962 __le64 cmd_trb; 963 __le32 status; 964 __le32 flags; 965}; 966 967/* status bitmasks */ 968#define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */ 969 970/* Address device - disable SetAddress */ 971#define TRB_BSR (1<<9) 972 973/* Configure Endpoint - Deconfigure */ 974#define TRB_DC (1<<9) 975 976/* Stop Ring - Transfer State Preserve */ 977#define TRB_TSP (1<<9) 978 979enum xhci_ep_reset_type { 980 EP_HARD_RESET, 981 EP_SOFT_RESET, 982}; 983 984/* Force Event */ 985#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 986#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 987 988/* Set Latency Tolerance Value */ 989#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 990 991/* Get Port Bandwidth */ 992#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 993 994/* Force Header */ 995#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 996#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 997 998enum xhci_setup_dev { 999 SETUP_CONTEXT_ONLY, 1000 SETUP_CONTEXT_ADDRESS, 1001}; 1002 1003/* bits 16:23 are the virtual function ID */ 1004/* bits 24:31 are the slot ID */ 1005 1006/* bits 19:16 are the dev speed */ 1007#define DEV_SPEED_FOR_TRB(p) ((p) << 16) 1008 1009/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1010#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1011#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1012#define LAST_EP_INDEX 30 1013 1014/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1015#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1016#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1017#define SCT_FOR_TRB(p) (((p) & 0x7) << 1) 1018 1019/* Link TRB specific fields */ 1020#define TRB_TC (1<<1) 1021 1022/* Port Status Change Event TRB fields */ 1023/* Port ID - bits 31:24 */ 1024#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1025 1026#define EVENT_DATA (1 << 2) 1027 1028/* Normal TRB fields */ 1029/* transfer_len bitmasks - bits 0:16 */ 1030#define TRB_LEN(p) ((p) & 0x1ffff) 1031/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1032#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1033#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1034/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1035#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1036/* Interrupter Target - which MSI-X vector to target the completion event at */ 1037#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1038#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1039 1040/* Cycle bit - indicates TRB ownership by HC or HCD */ 1041#define TRB_CYCLE (1<<0) 1042/* 1043 * Force next event data TRB to be evaluated before task switch. 1044 * Used to pass OS data back after a TD completes. 1045 */ 1046#define TRB_ENT (1<<1) 1047/* Interrupt on short packet */ 1048#define TRB_ISP (1<<2) 1049/* Set PCIe no snoop attribute */ 1050#define TRB_NO_SNOOP (1<<3) 1051/* Chain multiple TRBs into a TD */ 1052#define TRB_CHAIN (1<<4) 1053/* Interrupt on completion */ 1054#define TRB_IOC (1<<5) 1055/* The buffer pointer contains immediate data */ 1056#define TRB_IDT (1<<6) 1057/* TDs smaller than this might use IDT */ 1058#define TRB_IDT_MAX_SIZE 8 1059 1060/* Block Event Interrupt */ 1061#define TRB_BEI (1<<9) 1062 1063/* Control transfer TRB specific fields */ 1064#define TRB_DIR_IN (1<<16) 1065#define TRB_TX_TYPE(p) ((p) << 16) 1066#define TRB_DATA_OUT 2 1067#define TRB_DATA_IN 3 1068 1069/* Isochronous TRB specific fields */ 1070#define TRB_SIA (1<<31) 1071#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1072#define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff) 1073/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1074#define TRB_TBC(p) (((p) & 0x3) << 7) 1075#define GET_TBC(p) (((p) >> 7) & 0x3) 1076#define TRB_TLBPC(p) (((p) & 0xf) << 16) 1077#define GET_TLBPC(p) (((p) >> 16) & 0xf) 1078 1079/* TRB cache size for xHC with TRB cache */ 1080#define TRB_CACHE_SIZE_HS 8 1081#define TRB_CACHE_SIZE_SS 16 1082 1083struct xhci_generic_trb { 1084 __le32 field[4]; 1085}; 1086 1087union xhci_trb { 1088 struct xhci_link_trb link; 1089 struct xhci_transfer_event trans_event; 1090 struct xhci_event_cmd event_cmd; 1091 struct xhci_generic_trb generic; 1092}; 1093 1094/* TRB bit mask */ 1095#define TRB_TYPE_BITMASK (0xfc00) 1096#define TRB_TYPE(p) ((p) << 10) 1097#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1098/* TRB type IDs */ 1099/* bulk, interrupt, isoc scatter/gather, and control data stage */ 1100#define TRB_NORMAL 1 1101/* setup stage for control transfers */ 1102#define TRB_SETUP 2 1103/* data stage for control transfers */ 1104#define TRB_DATA 3 1105/* status stage for control transfers */ 1106#define TRB_STATUS 4 1107/* isoc transfers */ 1108#define TRB_ISOC 5 1109/* TRB for linking ring segments */ 1110#define TRB_LINK 6 1111#define TRB_EVENT_DATA 7 1112/* Transfer Ring No-op (not for the command ring) */ 1113#define TRB_TR_NOOP 8 1114/* Command TRBs */ 1115/* Enable Slot Command */ 1116#define TRB_ENABLE_SLOT 9 1117/* Disable Slot Command */ 1118#define TRB_DISABLE_SLOT 10 1119/* Address Device Command */ 1120#define TRB_ADDR_DEV 11 1121/* Configure Endpoint Command */ 1122#define TRB_CONFIG_EP 12 1123/* Evaluate Context Command */ 1124#define TRB_EVAL_CONTEXT 13 1125/* Reset Endpoint Command */ 1126#define TRB_RESET_EP 14 1127/* Stop Transfer Ring Command */ 1128#define TRB_STOP_RING 15 1129/* Set Transfer Ring Dequeue Pointer Command */ 1130#define TRB_SET_DEQ 16 1131/* Reset Device Command */ 1132#define TRB_RESET_DEV 17 1133/* Force Event Command (opt) */ 1134#define TRB_FORCE_EVENT 18 1135/* Negotiate Bandwidth Command (opt) */ 1136#define TRB_NEG_BANDWIDTH 19 1137/* Set Latency Tolerance Value Command (opt) */ 1138#define TRB_SET_LT 20 1139/* Get port bandwidth Command */ 1140#define TRB_GET_BW 21 1141/* Force Header Command - generate a transaction or link management packet */ 1142#define TRB_FORCE_HEADER 22 1143/* No-op Command - not for transfer rings */ 1144#define TRB_CMD_NOOP 23 1145/* TRB IDs 24-31 reserved */ 1146/* Event TRBS */ 1147/* Transfer Event */ 1148#define TRB_TRANSFER 32 1149/* Command Completion Event */ 1150#define TRB_COMPLETION 33 1151/* Port Status Change Event */ 1152#define TRB_PORT_STATUS 34 1153/* Bandwidth Request Event (opt) */ 1154#define TRB_BANDWIDTH_EVENT 35 1155/* Doorbell Event (opt) */ 1156#define TRB_DOORBELL 36 1157/* Host Controller Event */ 1158#define TRB_HC_EVENT 37 1159/* Device Notification Event - device sent function wake notification */ 1160#define TRB_DEV_NOTE 38 1161/* MFINDEX Wrap Event - microframe counter wrapped */ 1162#define TRB_MFINDEX_WRAP 39 1163/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1164#define TRB_VENDOR_DEFINED_LOW 48 1165/* Nec vendor-specific command completion event. */ 1166#define TRB_NEC_CMD_COMP 48 1167/* Get NEC firmware revision. */ 1168#define TRB_NEC_GET_FW 49 1169 1170static inline const char *xhci_trb_type_string(u8 type) 1171{ 1172 switch (type) { 1173 case TRB_NORMAL: 1174 return "Normal"; 1175 case TRB_SETUP: 1176 return "Setup Stage"; 1177 case TRB_DATA: 1178 return "Data Stage"; 1179 case TRB_STATUS: 1180 return "Status Stage"; 1181 case TRB_ISOC: 1182 return "Isoch"; 1183 case TRB_LINK: 1184 return "Link"; 1185 case TRB_EVENT_DATA: 1186 return "Event Data"; 1187 case TRB_TR_NOOP: 1188 return "No-Op"; 1189 case TRB_ENABLE_SLOT: 1190 return "Enable Slot Command"; 1191 case TRB_DISABLE_SLOT: 1192 return "Disable Slot Command"; 1193 case TRB_ADDR_DEV: 1194 return "Address Device Command"; 1195 case TRB_CONFIG_EP: 1196 return "Configure Endpoint Command"; 1197 case TRB_EVAL_CONTEXT: 1198 return "Evaluate Context Command"; 1199 case TRB_RESET_EP: 1200 return "Reset Endpoint Command"; 1201 case TRB_STOP_RING: 1202 return "Stop Ring Command"; 1203 case TRB_SET_DEQ: 1204 return "Set TR Dequeue Pointer Command"; 1205 case TRB_RESET_DEV: 1206 return "Reset Device Command"; 1207 case TRB_FORCE_EVENT: 1208 return "Force Event Command"; 1209 case TRB_NEG_BANDWIDTH: 1210 return "Negotiate Bandwidth Command"; 1211 case TRB_SET_LT: 1212 return "Set Latency Tolerance Value Command"; 1213 case TRB_GET_BW: 1214 return "Get Port Bandwidth Command"; 1215 case TRB_FORCE_HEADER: 1216 return "Force Header Command"; 1217 case TRB_CMD_NOOP: 1218 return "No-Op Command"; 1219 case TRB_TRANSFER: 1220 return "Transfer Event"; 1221 case TRB_COMPLETION: 1222 return "Command Completion Event"; 1223 case TRB_PORT_STATUS: 1224 return "Port Status Change Event"; 1225 case TRB_BANDWIDTH_EVENT: 1226 return "Bandwidth Request Event"; 1227 case TRB_DOORBELL: 1228 return "Doorbell Event"; 1229 case TRB_HC_EVENT: 1230 return "Host Controller Event"; 1231 case TRB_DEV_NOTE: 1232 return "Device Notification Event"; 1233 case TRB_MFINDEX_WRAP: 1234 return "MFINDEX Wrap Event"; 1235 case TRB_NEC_CMD_COMP: 1236 return "NEC Command Completion Event"; 1237 case TRB_NEC_GET_FW: 1238 return "NET Get Firmware Revision Command"; 1239 default: 1240 return "UNKNOWN"; 1241 } 1242} 1243 1244#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1245/* Above, but for __le32 types -- can avoid work by swapping constants: */ 1246#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1247 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1248#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1249 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1250 1251#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1252#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1253 1254/* 1255 * TRBS_PER_SEGMENT must be a multiple of 4, 1256 * since the command ring is 64-byte aligned. 1257 * It must also be greater than 16. 1258 */ 1259#define TRBS_PER_SEGMENT 256 1260/* Allow two commands + a link TRB, along with any reserved command TRBs */ 1261#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1262#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1263#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1264/* TRB buffer pointers can't cross 64KB boundaries */ 1265#define TRB_MAX_BUFF_SHIFT 16 1266#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1267/* How much data is left before the 64KB boundary? */ 1268#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1269 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1270#define MAX_SOFT_RETRY 3 1271/* 1272 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1273 * XHCI_AVOID_BEI quirk is in use. 1274 */ 1275#define AVOID_BEI_INTERVAL_MIN 8 1276#define AVOID_BEI_INTERVAL_MAX 32 1277 1278#define xhci_for_each_ring_seg(head, seg) \ 1279 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL)) 1280 1281struct xhci_segment { 1282 union xhci_trb *trbs; 1283 /* private to HCD */ 1284 struct xhci_segment *next; 1285 unsigned int num; 1286 dma_addr_t dma; 1287 /* Max packet sized bounce buffer for td-fragmant alignment */ 1288 dma_addr_t bounce_dma; 1289 void *bounce_buf; 1290 unsigned int bounce_offs; 1291 unsigned int bounce_len; 1292}; 1293 1294enum xhci_cancelled_td_status { 1295 TD_DIRTY = 0, 1296 TD_HALTED, 1297 TD_CLEARING_CACHE, 1298 TD_CLEARING_CACHE_DEFERRED, 1299 TD_CLEARED, 1300}; 1301 1302struct xhci_td { 1303 struct list_head td_list; 1304 struct list_head cancelled_td_list; 1305 int status; 1306 enum xhci_cancelled_td_status cancel_status; 1307 struct urb *urb; 1308 struct xhci_segment *start_seg; 1309 union xhci_trb *start_trb; 1310 struct xhci_segment *end_seg; 1311 union xhci_trb *end_trb; 1312 struct xhci_segment *bounce_seg; 1313 /* actual_length of the URB has already been set */ 1314 bool urb_length_set; 1315 bool error_mid_td; 1316}; 1317 1318/* 1319 * xHCI command default timeout value in milliseconds. 1320 * USB 3.2 spec, section 9.2.6.1 1321 */ 1322#define XHCI_CMD_DEFAULT_TIMEOUT 5000 1323 1324/* command descriptor */ 1325struct xhci_cd { 1326 struct xhci_command *command; 1327 union xhci_trb *cmd_trb; 1328}; 1329 1330enum xhci_ring_type { 1331 TYPE_CTRL = 0, 1332 TYPE_ISOC, 1333 TYPE_BULK, 1334 TYPE_INTR, 1335 TYPE_STREAM, 1336 TYPE_COMMAND, 1337 TYPE_EVENT, 1338}; 1339 1340static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1341{ 1342 switch (type) { 1343 case TYPE_CTRL: 1344 return "CTRL"; 1345 case TYPE_ISOC: 1346 return "ISOC"; 1347 case TYPE_BULK: 1348 return "BULK"; 1349 case TYPE_INTR: 1350 return "INTR"; 1351 case TYPE_STREAM: 1352 return "STREAM"; 1353 case TYPE_COMMAND: 1354 return "CMD"; 1355 case TYPE_EVENT: 1356 return "EVENT"; 1357 } 1358 1359 return "UNKNOWN"; 1360} 1361 1362struct xhci_ring { 1363 struct xhci_segment *first_seg; 1364 struct xhci_segment *last_seg; 1365 union xhci_trb *enqueue; 1366 struct xhci_segment *enq_seg; 1367 union xhci_trb *dequeue; 1368 struct xhci_segment *deq_seg; 1369 struct list_head td_list; 1370 /* 1371 * Write the cycle state into the TRB cycle field to give ownership of 1372 * the TRB to the host controller (if we are the producer), or to check 1373 * if we own the TRB (if we are the consumer). See section 4.9.1. 1374 */ 1375 u32 cycle_state; 1376 unsigned int stream_id; 1377 unsigned int num_segs; 1378 unsigned int num_trbs_free; /* used only by xhci DbC */ 1379 unsigned int bounce_buf_len; 1380 enum xhci_ring_type type; 1381 u32 old_trb_comp_code; 1382 struct radix_tree_root *trb_address_map; 1383}; 1384 1385struct xhci_erst_entry { 1386 /* 64-bit event ring segment address */ 1387 __le64 seg_addr; 1388 __le32 seg_size; 1389 /* Set to zero */ 1390 __le32 rsvd; 1391}; 1392 1393struct xhci_erst { 1394 struct xhci_erst_entry *entries; 1395 unsigned int num_entries; 1396 /* xhci->event_ring keeps track of segment dma addresses */ 1397 dma_addr_t erst_dma_addr; 1398}; 1399 1400struct xhci_scratchpad { 1401 u64 *sp_array; 1402 dma_addr_t sp_dma; 1403 void **sp_buffers; 1404}; 1405 1406struct urb_priv { 1407 int num_tds; 1408 int num_tds_done; 1409 struct xhci_td td[] __counted_by(num_tds); 1410}; 1411 1412/* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ 1413#define ERST_DEFAULT_SEGS 2 1414/* Poll every 60 seconds */ 1415#define POLL_TIMEOUT 60 1416/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1417#define XHCI_STOP_EP_CMD_TIMEOUT 5 1418/* XXX: Make these module parameters */ 1419 1420struct s3_save { 1421 u32 command; 1422 u32 dev_nt; 1423 u64 dcbaa_ptr; 1424 u32 config_reg; 1425}; 1426 1427/* Use for lpm */ 1428struct dev_info { 1429 u32 dev_id; 1430 struct list_head list; 1431}; 1432 1433struct xhci_bus_state { 1434 unsigned long bus_suspended; 1435 unsigned long next_statechange; 1436 1437 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1438 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1439 u32 port_c_suspend; 1440 u32 suspended_ports; 1441 u32 port_remote_wakeup; 1442 /* which ports have started to resume */ 1443 unsigned long resuming_ports; 1444}; 1445 1446struct xhci_interrupter { 1447 struct xhci_ring *event_ring; 1448 struct xhci_erst erst; 1449 struct xhci_intr_reg __iomem *ir_set; 1450 unsigned int intr_num; 1451 bool ip_autoclear; 1452 u32 isoc_bei_interval; 1453 /* For interrupter registers save and restore over suspend/resume */ 1454 u32 s3_iman; 1455 u32 s3_imod; 1456 u32 s3_erst_size; 1457 u64 s3_erst_base; 1458 u64 s3_erst_dequeue; 1459}; 1460/* 1461 * It can take up to 20 ms to transition from RExit to U0 on the 1462 * Intel Lynx Point LP xHCI host. 1463 */ 1464#define XHCI_MAX_REXIT_TIMEOUT_MS 20 1465struct xhci_port_cap { 1466 u32 *psi; /* array of protocol speed ID entries */ 1467 u8 psi_count; 1468 u8 psi_uid_count; 1469 u8 maj_rev; 1470 u8 min_rev; 1471 u32 protocol_caps; 1472}; 1473 1474struct xhci_port { 1475 struct xhci_port_regs __iomem *port_reg; 1476 int hw_portnum; 1477 int hcd_portnum; 1478 struct xhci_hub *rhub; 1479 struct xhci_port_cap *port_cap; 1480 unsigned int lpm_incapable:1; 1481 unsigned long resume_timestamp; 1482 bool rexit_active; 1483 /* Slot ID is the index of the device directly connected to the port */ 1484 int slot_id; 1485 struct completion rexit_done; 1486 struct completion u3exit_done; 1487}; 1488 1489struct xhci_hub { 1490 struct xhci_port **ports; 1491 unsigned int num_ports; 1492 struct usb_hcd *hcd; 1493 /* keep track of bus suspend info */ 1494 struct xhci_bus_state bus_state; 1495 /* supported prococol extended capabiliy values */ 1496 u8 maj_rev; 1497 u8 min_rev; 1498}; 1499 1500/* There is one xhci_hcd structure per controller */ 1501struct xhci_hcd { 1502 struct usb_hcd *main_hcd; 1503 struct usb_hcd *shared_hcd; 1504 /* glue to PCI and HCD framework */ 1505 struct xhci_cap_regs __iomem *cap_regs; 1506 struct xhci_op_regs __iomem *op_regs; 1507 struct xhci_run_regs __iomem *run_regs; 1508 struct xhci_doorbell_array __iomem *dba; 1509 1510 /* Cached register copies of read-only HC data */ 1511 __u32 hcs_params2; 1512 __u32 hcs_params3; 1513 __u32 hcc_params; 1514 __u32 hcc_params2; 1515 1516 spinlock_t lock; 1517 1518 /* packed release number */ 1519 u16 hci_version; 1520 u16 max_interrupters; 1521 u8 max_slots; 1522 u8 max_ports; 1523 /* imod_interval in ns (I * 250ns) */ 1524 u32 imod_interval; 1525 u32 page_size; 1526 /* MSI-X/MSI vectors */ 1527 int nvecs; 1528 /* optional clocks */ 1529 struct clk *clk; 1530 struct clk *reg_clk; 1531 /* optional reset controller */ 1532 struct reset_control *reset; 1533 /* data structures */ 1534 struct xhci_device_context_array *dcbaa; 1535 struct xhci_interrupter **interrupters; 1536 struct xhci_ring *cmd_ring; 1537 unsigned int cmd_ring_state; 1538#define CMD_RING_STATE_RUNNING (1 << 0) 1539#define CMD_RING_STATE_ABORTED (1 << 1) 1540#define CMD_RING_STATE_STOPPED (1 << 2) 1541 struct list_head cmd_list; 1542 unsigned int cmd_ring_reserved_trbs; 1543 struct delayed_work cmd_timer; 1544 struct completion cmd_ring_stop_completion; 1545 struct xhci_command *current_cmd; 1546 1547 /* Scratchpad */ 1548 struct xhci_scratchpad *scratchpad; 1549 1550 /* slot enabling and address device helpers */ 1551 /* these are not thread safe so use mutex */ 1552 struct mutex mutex; 1553 /* Internal mirror of the HW's dcbaa */ 1554 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1555 /* For keeping track of bandwidth domains per roothub. */ 1556 struct xhci_root_port_bw_info *rh_bw; 1557 1558 /* DMA pools */ 1559 struct dma_pool *device_pool; 1560 struct dma_pool *segment_pool; 1561 struct dma_pool *small_streams_pool; 1562 struct dma_pool *port_bw_pool; 1563 struct dma_pool *medium_streams_pool; 1564 1565 /* Host controller watchdog timer structures */ 1566 unsigned int xhc_state; 1567 unsigned long run_graceperiod; 1568 struct s3_save s3; 1569/* Host controller is dying - not responding to commands. "I'm not dead yet!" 1570 * 1571 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1572 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1573 * that sees this status (other than the timer that set it) should stop touching 1574 * hardware immediately. Interrupt handlers should return immediately when 1575 * they see this status (any time they drop and re-acquire xhci->lock). 1576 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1577 * putting the TD on the canceled list, etc. 1578 * 1579 * There are no reports of xHCI host controllers that display this issue. 1580 */ 1581#define XHCI_STATE_DYING (1 << 0) 1582#define XHCI_STATE_HALTED (1 << 1) 1583#define XHCI_STATE_REMOVING (1 << 2) 1584 unsigned long long quirks; 1585#define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1586#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1587#define XHCI_NEC_HOST BIT_ULL(2) 1588#define XHCI_AMD_PLL_FIX BIT_ULL(3) 1589#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1590/* 1591 * Certain Intel host controllers have a limit to the number of endpoint 1592 * contexts they can handle. Ideally, they would signal that they can't handle 1593 * anymore endpoint contexts by returning a Resource Error for the Configure 1594 * Endpoint command, but they don't. Instead they expect software to keep track 1595 * of the number of active endpoints for them, across configure endpoint 1596 * commands, reset device commands, disable slot commands, and address device 1597 * commands. 1598 */ 1599#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1600#define XHCI_BROKEN_MSI BIT_ULL(6) 1601#define XHCI_RESET_ON_RESUME BIT_ULL(7) 1602#define XHCI_SW_BW_CHECKING BIT_ULL(8) 1603#define XHCI_AMD_0x96_HOST BIT_ULL(9) 1604#define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ 1605#define XHCI_LPM_SUPPORT BIT_ULL(11) 1606#define XHCI_INTEL_HOST BIT_ULL(12) 1607#define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1608#define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1609#define XHCI_AVOID_BEI BIT_ULL(15) 1610#define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1611#define XHCI_SLOW_SUSPEND BIT_ULL(17) 1612#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1613/* For controllers with a broken beyond repair streams implementation */ 1614#define XHCI_BROKEN_STREAMS BIT_ULL(19) 1615#define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1616#define XHCI_MTK_HOST BIT_ULL(21) 1617#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1618#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1619#define XHCI_MISSING_CAS BIT_ULL(24) 1620/* For controller with a broken Port Disable implementation */ 1621#define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1622#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1623#define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1624#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1625#define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1626#define XHCI_SUSPEND_DELAY BIT_ULL(30) 1627#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1628#define XHCI_ZERO_64B_REGS BIT_ULL(32) 1629#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1630#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1631#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1632/* Reserved. It was XHCI_RENESAS_FW_QUIRK */ 1633#define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1634#define XHCI_DISABLE_SPARSE BIT_ULL(38) 1635#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1636#define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1637#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1638#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1639#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1640#define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1641#define XHCI_TRB_OVERFETCH BIT_ULL(45) 1642#define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1643#define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1644#define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) 1645#define XHCI_ETRON_HOST BIT_ULL(49) 1646#define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50) 1647 1648 unsigned int num_active_eps; 1649 unsigned int limit_active_eps; 1650 struct xhci_port *hw_ports; 1651 struct xhci_hub usb2_rhub; 1652 struct xhci_hub usb3_rhub; 1653 /* support xHCI 1.0 spec USB2 hardware LPM */ 1654 unsigned hw_lpm_support:1; 1655 /* Broken Suspend flag for SNPS Suspend resume issue */ 1656 unsigned broken_suspend:1; 1657 /* Indicates that omitting hcd is supported if root hub has no ports */ 1658 unsigned allow_single_roothub:1; 1659 /* cached extended protocol port capabilities */ 1660 struct xhci_port_cap *port_caps; 1661 unsigned int num_port_caps; 1662 /* Compliance Mode Recovery Data */ 1663 struct timer_list comp_mode_recovery_timer; 1664 u32 port_status_u0; 1665 u16 test_mode; 1666/* Compliance Mode Timer Triggered every 2 seconds */ 1667#define COMP_MODE_RCVRY_MSECS 2000 1668 1669 struct dentry *debugfs_root; 1670 struct dentry *debugfs_slots; 1671 struct list_head regset_list; 1672 1673 void *dbc; 1674 /* platform-specific data -- must come last */ 1675 unsigned long priv[] __aligned(sizeof(s64)); 1676}; 1677 1678/* Platform specific overrides to generic XHCI hc_driver ops */ 1679struct xhci_driver_overrides { 1680 size_t extra_priv_size; 1681 int (*reset)(struct usb_hcd *hcd); 1682 int (*start)(struct usb_hcd *hcd); 1683 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1684 struct usb_host_endpoint *ep); 1685 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1686 struct usb_host_endpoint *ep); 1687 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1688 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1689 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1690 struct usb_tt *tt, gfp_t mem_flags); 1691 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1692 u16 wIndex, char *buf, u16 wLength); 1693}; 1694 1695#define XHCI_CFC_DELAY 10 1696 1697/* convert between an HCD pointer and the corresponding EHCI_HCD */ 1698static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1699{ 1700 struct usb_hcd *primary_hcd; 1701 1702 if (usb_hcd_is_primary_hcd(hcd)) 1703 primary_hcd = hcd; 1704 else 1705 primary_hcd = hcd->primary_hcd; 1706 1707 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1708} 1709 1710static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1711{ 1712 return xhci->main_hcd; 1713} 1714 1715static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1716{ 1717 if (xhci->shared_hcd) 1718 return xhci->shared_hcd; 1719 1720 if (!xhci->usb2_rhub.num_ports) 1721 return xhci->main_hcd; 1722 1723 return NULL; 1724} 1725 1726static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1727{ 1728 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1729 1730 return hcd == xhci_get_usb3_hcd(xhci); 1731} 1732 1733static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1734{ 1735 return xhci->allow_single_roothub && 1736 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1737} 1738 1739#define xhci_dbg(xhci, fmt, args...) \ 1740 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1741#define xhci_err(xhci, fmt, args...) \ 1742 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1743#define xhci_warn(xhci, fmt, args...) \ 1744 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1745#define xhci_info(xhci, fmt, args...) \ 1746 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1747 1748/* 1749 * Registers should always be accessed with double word or quad word accesses. 1750 * 1751 * Some xHCI implementations may support 64-bit address pointers. Registers 1752 * with 64-bit address pointers should be written to with dword accesses by 1753 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1754 * xHCI implementations that do not support 64-bit address pointers will ignore 1755 * the high dword, and write order is irrelevant. 1756 */ 1757static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1758 __le64 __iomem *regs) 1759{ 1760 return lo_hi_readq(regs); 1761} 1762static inline void xhci_write_64(struct xhci_hcd *xhci, 1763 const u64 val, __le64 __iomem *regs) 1764{ 1765 lo_hi_writeq(val, regs); 1766} 1767 1768 1769/* 1770 * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set. 1771 * Other chapters and later specs say that it should only be set if the link is inside a TD 1772 * which continues from the end of one segment to the next segment. 1773 * 1774 * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set. 1775 * 1776 * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when 1777 * "resynchronizing the pipe" after a Missed Service Error. 1778 */ 1779static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type) 1780{ 1781 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || 1782 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST))); 1783} 1784 1785/* xHCI debugging */ 1786char *xhci_get_slot_state(struct xhci_hcd *xhci, 1787 struct xhci_container_ctx *ctx); 1788void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1789 const char *fmt, ...); 1790 1791/* xHCI memory management */ 1792void xhci_mem_cleanup(struct xhci_hcd *xhci); 1793int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1794void xhci_free_virt_device(struct xhci_hcd *xhci, struct xhci_virt_device *dev, int slot_id); 1795int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1796int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1797void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1798 struct usb_device *udev); 1799unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1800unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1801void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1802void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1803 struct xhci_virt_device *virt_dev, 1804 int old_active_eps); 1805void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1806void xhci_update_bw_info(struct xhci_hcd *xhci, 1807 struct xhci_container_ctx *in_ctx, 1808 struct xhci_input_control_ctx *ctrl_ctx, 1809 struct xhci_virt_device *virt_dev); 1810void xhci_endpoint_copy(struct xhci_hcd *xhci, 1811 struct xhci_container_ctx *in_ctx, 1812 struct xhci_container_ctx *out_ctx, 1813 unsigned int ep_index); 1814void xhci_slot_copy(struct xhci_hcd *xhci, 1815 struct xhci_container_ctx *in_ctx, 1816 struct xhci_container_ctx *out_ctx); 1817int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1818 struct usb_device *udev, struct usb_host_endpoint *ep, 1819 gfp_t mem_flags); 1820struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs, 1821 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1822void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1823int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1824 unsigned int num_trbs, gfp_t flags); 1825void xhci_initialize_ring_info(struct xhci_ring *ring); 1826void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1827 struct xhci_virt_device *virt_dev, 1828 unsigned int ep_index); 1829struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1830 unsigned int num_stream_ctxs, 1831 unsigned int num_streams, 1832 unsigned int max_packet, gfp_t flags); 1833void xhci_free_stream_info(struct xhci_hcd *xhci, 1834 struct xhci_stream_info *stream_info); 1835void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1836 struct xhci_ep_ctx *ep_ctx, 1837 struct xhci_stream_info *stream_info); 1838void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1839 struct xhci_virt_ep *ep); 1840void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1841 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1842struct xhci_ring *xhci_dma_to_transfer_ring( 1843 struct xhci_virt_ep *ep, 1844 u64 address); 1845struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1846 bool allocate_completion, gfp_t mem_flags); 1847struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 1848 bool allocate_completion, gfp_t mem_flags); 1849void xhci_urb_free_priv(struct urb_priv *urb_priv); 1850void xhci_free_command(struct xhci_hcd *xhci, 1851 struct xhci_command *command); 1852struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 1853 int type, gfp_t flags); 1854void xhci_free_container_ctx(struct xhci_hcd *xhci, 1855 struct xhci_container_ctx *ctx); 1856struct xhci_container_ctx *xhci_alloc_port_bw_ctx(struct xhci_hcd *xhci, 1857 gfp_t flags); 1858void xhci_free_port_bw_ctx(struct xhci_hcd *xhci, 1859 struct xhci_container_ctx *ctx); 1860struct xhci_interrupter * 1861xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs, 1862 u32 imod_interval, unsigned int intr_num); 1863void xhci_remove_secondary_interrupter(struct usb_hcd 1864 *hcd, struct xhci_interrupter *ir); 1865void xhci_skip_sec_intr_events(struct xhci_hcd *xhci, 1866 struct xhci_ring *ring, 1867 struct xhci_interrupter *ir); 1868 1869/* xHCI host controller glue */ 1870typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1871int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 1872void xhci_quiesce(struct xhci_hcd *xhci); 1873int xhci_halt(struct xhci_hcd *xhci); 1874int xhci_start(struct xhci_hcd *xhci); 1875int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 1876int xhci_run(struct usb_hcd *hcd); 1877int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1878void xhci_shutdown(struct usb_hcd *hcd); 1879void xhci_stop(struct usb_hcd *hcd); 1880void xhci_init_driver(struct hc_driver *drv, 1881 const struct xhci_driver_overrides *over); 1882int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1883 struct usb_host_endpoint *ep); 1884int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1885 struct usb_host_endpoint *ep); 1886int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1887void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1888int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1889 struct usb_tt *tt, gfp_t mem_flags); 1890int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 1891int xhci_disable_and_free_slot(struct xhci_hcd *xhci, u32 slot_id); 1892int xhci_ext_cap_init(struct xhci_hcd *xhci); 1893 1894int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1895int xhci_resume(struct xhci_hcd *xhci, bool power_lost, bool is_auto_resume); 1896 1897irqreturn_t xhci_irq(struct usb_hcd *hcd); 1898irqreturn_t xhci_msi_irq(int irq, void *hcd); 1899int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1900int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1901 struct xhci_virt_device *virt_dev, 1902 struct usb_device *hdev, 1903 struct usb_tt *tt, gfp_t mem_flags); 1904int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, 1905 u32 imod_interval); 1906int xhci_enable_interrupter(struct xhci_interrupter *ir); 1907int xhci_disable_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir); 1908 1909/* xHCI ring, segment, TRB, and TD functions */ 1910dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1911int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1912void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1913int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1914 u32 trb_type, u32 slot_id); 1915int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1916 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1917int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1918 u32 field1, u32 field2, u32 field3, u32 field4); 1919int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1920 int slot_id, unsigned int ep_index, int suspend); 1921int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1922 int slot_id, unsigned int ep_index); 1923int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1924 int slot_id, unsigned int ep_index); 1925int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1926 int slot_id, unsigned int ep_index); 1927int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1928 struct urb *urb, int slot_id, unsigned int ep_index); 1929int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1930 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1931 bool command_must_succeed); 1932int xhci_queue_get_port_bw(struct xhci_hcd *xhci, 1933 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 1934 u8 dev_speed, bool command_must_succeed); 1935int xhci_get_port_bandwidth(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, 1936 u8 dev_speed); 1937int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1938 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1939int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1940 int slot_id, unsigned int ep_index, 1941 enum xhci_ep_reset_type reset_type); 1942int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1943 u32 slot_id); 1944void xhci_handle_command_timeout(struct work_struct *work); 1945 1946void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1947 unsigned int ep_index, unsigned int stream_id); 1948void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 1949 unsigned int slot_id, 1950 unsigned int ep_index); 1951void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1952void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 1953unsigned int count_trbs(u64 addr, u64 len); 1954int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 1955 int suspend, gfp_t gfp_flags); 1956void xhci_process_cancelled_tds(struct xhci_virt_ep *ep); 1957void xhci_update_erst_dequeue(struct xhci_hcd *xhci, 1958 struct xhci_interrupter *ir, 1959 bool clear_ehb); 1960void xhci_add_interrupter(struct xhci_hcd *xhci, unsigned int intr_num); 1961int xhci_usb_endpoint_maxp(struct usb_device *udev, 1962 struct usb_host_endpoint *host_ep); 1963void xhci_portsc_writel(struct xhci_port *port, u32 val); 1964u32 xhci_portsc_readl(struct xhci_port *port); 1965 1966/* xHCI roothub code */ 1967void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 1968 u32 link_state); 1969void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 1970 u32 port_bit); 1971int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1972 char *buf, u16 wLength); 1973int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1974int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1975struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 1976enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 1977 struct xhci_port *port); 1978void xhci_hc_died(struct xhci_hcd *xhci); 1979 1980#ifdef CONFIG_PM 1981int xhci_bus_suspend(struct usb_hcd *hcd); 1982int xhci_bus_resume(struct usb_hcd *hcd); 1983unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 1984#else 1985#define xhci_bus_suspend NULL 1986#define xhci_bus_resume NULL 1987#define xhci_get_resuming_ports NULL 1988#endif /* CONFIG_PM */ 1989 1990u32 xhci_port_state_to_neutral(u32 state); 1991void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1992 1993/* xHCI contexts */ 1994struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1995struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1996struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1997 1998struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 1999 unsigned int slot_id, unsigned int ep_index, 2000 unsigned int stream_id); 2001 2002static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2003 struct urb *urb) 2004{ 2005 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2006 xhci_get_endpoint_index(&urb->ep->desc), 2007 urb->stream_id); 2008} 2009 2010/* 2011 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 2012 * them anyways as we where unable to find a device that matches the 2013 * constraints. 2014 */ 2015static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 2016{ 2017 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 2018 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 2019 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 2020 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 2021 !urb->num_sgs) 2022 return true; 2023 2024 return false; 2025} 2026 2027static inline char *xhci_slot_state_string(u32 state) 2028{ 2029 switch (state) { 2030 case SLOT_STATE_ENABLED: 2031 return "enabled/disabled"; 2032 case SLOT_STATE_DEFAULT: 2033 return "default"; 2034 case SLOT_STATE_ADDRESSED: 2035 return "addressed"; 2036 case SLOT_STATE_CONFIGURED: 2037 return "configured"; 2038 default: 2039 return "reserved"; 2040 } 2041} 2042 2043static inline const char *xhci_decode_trb(char *str, size_t size, 2044 u32 field0, u32 field1, u32 field2, u32 field3) 2045{ 2046 int type = TRB_FIELD_TO_TYPE(field3); 2047 2048 switch (type) { 2049 case TRB_LINK: 2050 snprintf(str, size, 2051 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2052 field1, field0, GET_INTR_TARGET(field2), 2053 xhci_trb_type_string(type), 2054 field3 & TRB_IOC ? 'I' : 'i', 2055 field3 & TRB_CHAIN ? 'C' : 'c', 2056 field3 & TRB_TC ? 'T' : 't', 2057 field3 & TRB_CYCLE ? 'C' : 'c'); 2058 break; 2059 case TRB_TRANSFER: 2060 case TRB_COMPLETION: 2061 case TRB_PORT_STATUS: 2062 case TRB_BANDWIDTH_EVENT: 2063 case TRB_DOORBELL: 2064 case TRB_HC_EVENT: 2065 case TRB_DEV_NOTE: 2066 case TRB_MFINDEX_WRAP: 2067 snprintf(str, size, 2068 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2069 field1, field0, 2070 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2071 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2072 TRB_TO_EP_ID(field3), 2073 xhci_trb_type_string(type), 2074 field3 & EVENT_DATA ? 'E' : 'e', 2075 field3 & TRB_CYCLE ? 'C' : 'c'); 2076 2077 break; 2078 case TRB_SETUP: 2079 snprintf(str, size, 2080 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2081 field0 & 0xff, 2082 (field0 & 0xff00) >> 8, 2083 (field0 & 0xff000000) >> 24, 2084 (field0 & 0xff0000) >> 16, 2085 (field1 & 0xff00) >> 8, 2086 field1 & 0xff, 2087 (field1 & 0xff000000) >> 16 | 2088 (field1 & 0xff0000) >> 16, 2089 TRB_LEN(field2), GET_TD_SIZE(field2), 2090 GET_INTR_TARGET(field2), 2091 xhci_trb_type_string(type), 2092 field3 & TRB_IDT ? 'I' : 'i', 2093 field3 & TRB_IOC ? 'I' : 'i', 2094 field3 & TRB_CYCLE ? 'C' : 'c'); 2095 break; 2096 case TRB_DATA: 2097 snprintf(str, size, 2098 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2099 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2100 GET_INTR_TARGET(field2), 2101 xhci_trb_type_string(type), 2102 field3 & TRB_IDT ? 'I' : 'i', 2103 field3 & TRB_IOC ? 'I' : 'i', 2104 field3 & TRB_CHAIN ? 'C' : 'c', 2105 field3 & TRB_NO_SNOOP ? 'S' : 's', 2106 field3 & TRB_ISP ? 'I' : 'i', 2107 field3 & TRB_ENT ? 'E' : 'e', 2108 field3 & TRB_CYCLE ? 'C' : 'c'); 2109 break; 2110 case TRB_STATUS: 2111 snprintf(str, size, 2112 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2113 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2114 GET_INTR_TARGET(field2), 2115 xhci_trb_type_string(type), 2116 field3 & TRB_IOC ? 'I' : 'i', 2117 field3 & TRB_CHAIN ? 'C' : 'c', 2118 field3 & TRB_ENT ? 'E' : 'e', 2119 field3 & TRB_CYCLE ? 'C' : 'c'); 2120 break; 2121 case TRB_NORMAL: 2122 case TRB_EVENT_DATA: 2123 case TRB_TR_NOOP: 2124 snprintf(str, size, 2125 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2126 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2127 GET_INTR_TARGET(field2), 2128 xhci_trb_type_string(type), 2129 field3 & TRB_BEI ? 'B' : 'b', 2130 field3 & TRB_IDT ? 'I' : 'i', 2131 field3 & TRB_IOC ? 'I' : 'i', 2132 field3 & TRB_CHAIN ? 'C' : 'c', 2133 field3 & TRB_NO_SNOOP ? 'S' : 's', 2134 field3 & TRB_ISP ? 'I' : 'i', 2135 field3 & TRB_ENT ? 'E' : 'e', 2136 field3 & TRB_CYCLE ? 'C' : 'c'); 2137 break; 2138 case TRB_ISOC: 2139 snprintf(str, size, 2140 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c", 2141 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2142 GET_INTR_TARGET(field2), 2143 xhci_trb_type_string(type), 2144 GET_TBC(field3), 2145 GET_TLBPC(field3), 2146 GET_FRAME_ID(field3), 2147 field3 & TRB_SIA ? 'S' : 's', 2148 field3 & TRB_BEI ? 'B' : 'b', 2149 field3 & TRB_IDT ? 'I' : 'i', 2150 field3 & TRB_IOC ? 'I' : 'i', 2151 field3 & TRB_CHAIN ? 'C' : 'c', 2152 field3 & TRB_NO_SNOOP ? 'S' : 's', 2153 field3 & TRB_ISP ? 'I' : 'i', 2154 field3 & TRB_ENT ? 'E' : 'e', 2155 field3 & TRB_CYCLE ? 'C' : 'c'); 2156 break; 2157 case TRB_CMD_NOOP: 2158 case TRB_ENABLE_SLOT: 2159 snprintf(str, size, 2160 "%s: flags %c", 2161 xhci_trb_type_string(type), 2162 field3 & TRB_CYCLE ? 'C' : 'c'); 2163 break; 2164 case TRB_DISABLE_SLOT: 2165 case TRB_NEG_BANDWIDTH: 2166 snprintf(str, size, 2167 "%s: slot %d flags %c", 2168 xhci_trb_type_string(type), 2169 TRB_TO_SLOT_ID(field3), 2170 field3 & TRB_CYCLE ? 'C' : 'c'); 2171 break; 2172 case TRB_ADDR_DEV: 2173 snprintf(str, size, 2174 "%s: ctx %08x%08x slot %d flags %c:%c", 2175 xhci_trb_type_string(type), 2176 field1, field0, 2177 TRB_TO_SLOT_ID(field3), 2178 field3 & TRB_BSR ? 'B' : 'b', 2179 field3 & TRB_CYCLE ? 'C' : 'c'); 2180 break; 2181 case TRB_CONFIG_EP: 2182 snprintf(str, size, 2183 "%s: ctx %08x%08x slot %d flags %c:%c", 2184 xhci_trb_type_string(type), 2185 field1, field0, 2186 TRB_TO_SLOT_ID(field3), 2187 field3 & TRB_DC ? 'D' : 'd', 2188 field3 & TRB_CYCLE ? 'C' : 'c'); 2189 break; 2190 case TRB_EVAL_CONTEXT: 2191 snprintf(str, size, 2192 "%s: ctx %08x%08x slot %d flags %c", 2193 xhci_trb_type_string(type), 2194 field1, field0, 2195 TRB_TO_SLOT_ID(field3), 2196 field3 & TRB_CYCLE ? 'C' : 'c'); 2197 break; 2198 case TRB_RESET_EP: 2199 snprintf(str, size, 2200 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2201 xhci_trb_type_string(type), 2202 field1, field0, 2203 TRB_TO_SLOT_ID(field3), 2204 TRB_TO_EP_ID(field3), 2205 field3 & TRB_TSP ? 'T' : 't', 2206 field3 & TRB_CYCLE ? 'C' : 'c'); 2207 break; 2208 case TRB_STOP_RING: 2209 snprintf(str, size, 2210 "%s: slot %d sp %d ep %d flags %c", 2211 xhci_trb_type_string(type), 2212 TRB_TO_SLOT_ID(field3), 2213 TRB_TO_SUSPEND_PORT(field3), 2214 TRB_TO_EP_ID(field3), 2215 field3 & TRB_CYCLE ? 'C' : 'c'); 2216 break; 2217 case TRB_SET_DEQ: 2218 snprintf(str, size, 2219 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2220 xhci_trb_type_string(type), 2221 field1, field0, 2222 TRB_TO_STREAM_ID(field2), 2223 TRB_TO_SLOT_ID(field3), 2224 TRB_TO_EP_ID(field3), 2225 field3 & TRB_CYCLE ? 'C' : 'c'); 2226 break; 2227 case TRB_RESET_DEV: 2228 snprintf(str, size, 2229 "%s: slot %d flags %c", 2230 xhci_trb_type_string(type), 2231 TRB_TO_SLOT_ID(field3), 2232 field3 & TRB_CYCLE ? 'C' : 'c'); 2233 break; 2234 case TRB_FORCE_EVENT: 2235 snprintf(str, size, 2236 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2237 xhci_trb_type_string(type), 2238 field1, field0, 2239 TRB_TO_VF_INTR_TARGET(field2), 2240 TRB_TO_VF_ID(field3), 2241 field3 & TRB_CYCLE ? 'C' : 'c'); 2242 break; 2243 case TRB_SET_LT: 2244 snprintf(str, size, 2245 "%s: belt %d flags %c", 2246 xhci_trb_type_string(type), 2247 TRB_TO_BELT(field3), 2248 field3 & TRB_CYCLE ? 'C' : 'c'); 2249 break; 2250 case TRB_GET_BW: 2251 snprintf(str, size, 2252 "%s: ctx %08x%08x slot %d speed %d flags %c", 2253 xhci_trb_type_string(type), 2254 field1, field0, 2255 TRB_TO_SLOT_ID(field3), 2256 TRB_TO_DEV_SPEED(field3), 2257 field3 & TRB_CYCLE ? 'C' : 'c'); 2258 break; 2259 case TRB_FORCE_HEADER: 2260 snprintf(str, size, 2261 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2262 xhci_trb_type_string(type), 2263 field2, field1, field0 & 0xffffffe0, 2264 TRB_TO_PACKET_TYPE(field0), 2265 TRB_TO_ROOTHUB_PORT(field3), 2266 field3 & TRB_CYCLE ? 'C' : 'c'); 2267 break; 2268 default: 2269 snprintf(str, size, 2270 "type '%s' -> raw %08x %08x %08x %08x", 2271 xhci_trb_type_string(type), 2272 field0, field1, field2, field3); 2273 } 2274 2275 return str; 2276} 2277 2278static inline const char *xhci_decode_ctrl_ctx(char *str, 2279 unsigned long drop, unsigned long add) 2280{ 2281 unsigned int bit; 2282 int ret = 0; 2283 2284 str[0] = '\0'; 2285 2286 if (drop) { 2287 ret = sprintf(str, "Drop:"); 2288 for_each_set_bit(bit, &drop, 32) 2289 ret += sprintf(str + ret, " %d%s", 2290 bit / 2, 2291 bit % 2 ? "in":"out"); 2292 ret += sprintf(str + ret, ", "); 2293 } 2294 2295 if (add) { 2296 ret += sprintf(str + ret, "Add:%s%s", 2297 (add & SLOT_FLAG) ? " slot":"", 2298 (add & EP0_FLAG) ? " ep0":""); 2299 add &= ~(SLOT_FLAG | EP0_FLAG); 2300 for_each_set_bit(bit, &add, 32) 2301 ret += sprintf(str + ret, " %d%s", 2302 bit / 2, 2303 bit % 2 ? "in":"out"); 2304 } 2305 return str; 2306} 2307 2308static inline const char *xhci_decode_slot_context(char *str, 2309 u32 info, u32 info2, u32 tt_info, u32 state) 2310{ 2311 u32 speed; 2312 u32 hub; 2313 u32 mtt; 2314 int ret = 0; 2315 2316 speed = info & DEV_SPEED; 2317 hub = info & DEV_HUB; 2318 mtt = info & DEV_MTT; 2319 2320 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2321 info & ROUTE_STRING_MASK, 2322 ({ char *s; 2323 switch (speed) { 2324 case SLOT_SPEED_FS: 2325 s = "full-speed"; 2326 break; 2327 case SLOT_SPEED_LS: 2328 s = "low-speed"; 2329 break; 2330 case SLOT_SPEED_HS: 2331 s = "high-speed"; 2332 break; 2333 case SLOT_SPEED_SS: 2334 s = "super-speed"; 2335 break; 2336 case SLOT_SPEED_SSP: 2337 s = "super-speed plus"; 2338 break; 2339 default: 2340 s = "UNKNOWN speed"; 2341 } s; }), 2342 mtt ? " multi-TT" : "", 2343 hub ? " Hub" : "", 2344 (info & LAST_CTX_MASK) >> 27, 2345 info2 & MAX_EXIT, 2346 DEVINFO_TO_ROOT_HUB_PORT(info2), 2347 DEVINFO_TO_MAX_PORTS(info2)); 2348 2349 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2350 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2351 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2352 state & DEV_ADDR_MASK, 2353 xhci_slot_state_string(GET_SLOT_STATE(state))); 2354 2355 return str; 2356} 2357 2358 2359static inline const char *xhci_portsc_link_state_string(u32 portsc) 2360{ 2361 switch (portsc & PORT_PLS_MASK) { 2362 case XDEV_U0: 2363 return "U0"; 2364 case XDEV_U1: 2365 return "U1"; 2366 case XDEV_U2: 2367 return "U2"; 2368 case XDEV_U3: 2369 return "U3"; 2370 case XDEV_DISABLED: 2371 return "Disabled"; 2372 case XDEV_RXDETECT: 2373 return "RxDetect"; 2374 case XDEV_INACTIVE: 2375 return "Inactive"; 2376 case XDEV_POLLING: 2377 return "Polling"; 2378 case XDEV_RECOVERY: 2379 return "Recovery"; 2380 case XDEV_HOT_RESET: 2381 return "Hot Reset"; 2382 case XDEV_COMP_MODE: 2383 return "Compliance mode"; 2384 case XDEV_TEST_MODE: 2385 return "Test mode"; 2386 case XDEV_RESUME: 2387 return "Resume"; 2388 default: 2389 break; 2390 } 2391 return "Unknown"; 2392} 2393 2394static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2395{ 2396 int ret; 2397 2398 ret = sprintf(str, "0x%08x ", portsc); 2399 2400 if (portsc == ~(u32)0) 2401 return str; 2402 2403 ret += sprintf(str + ret, "Speed=%d ", DEV_PORT_SPEED(portsc)); 2404 ret += sprintf(str + ret, "Link=%s ", xhci_portsc_link_state_string(portsc)); 2405 2406 /* RO/ROS: Read-only */ 2407 if (portsc & PORT_CONNECT) 2408 ret += sprintf(str + ret, "CCS "); 2409 if (portsc & PORT_OC) 2410 ret += sprintf(str + ret, "OCA "); /* No set for USB2 ports */ 2411 if (portsc & PORT_CAS) 2412 ret += sprintf(str + ret, "CAS "); 2413 if (portsc & PORT_DEV_REMOVE) 2414 ret += sprintf(str + ret, "DR "); 2415 2416 /* RWS; writing 1 sets the bit, writing 0 clears the bit. */ 2417 if (portsc & PORT_POWER) 2418 ret += sprintf(str + ret, "PP "); 2419 if (portsc & PORT_WKCONN_E) 2420 ret += sprintf(str + ret, "WCE "); 2421 if (portsc & PORT_WKDISC_E) 2422 ret += sprintf(str + ret, "WDE "); 2423 if (portsc & PORT_WKOC_E) 2424 ret += sprintf(str + ret, "WOE "); 2425 2426 /* RW; writing 1 sets the bit, writing 0 clears the bit */ 2427 if (portsc & PORT_LINK_STROBE) 2428 ret += sprintf(str + ret, "LWS "); /* LWS 0 write is ignored */ 2429 2430 /* RW1S; writing 1 sets the bit, writing 0 has no effect */ 2431 if (portsc & PORT_RESET) 2432 ret += sprintf(str + ret, "PR "); 2433 if (portsc & PORT_WR) 2434 ret += sprintf(str + ret, "WPR "); /* RsvdZ for USB2 ports */ 2435 2436 /* RW1CS; writing 1 clears the bit, writing 0 has no effect. */ 2437 if (portsc & PORT_PE) 2438 ret += sprintf(str + ret, "PED "); 2439 if (portsc & PORT_CSC) 2440 ret += sprintf(str + ret, "CSC "); 2441 if (portsc & PORT_PEC) 2442 ret += sprintf(str + ret, "PEC "); /* No set for USB3 ports */ 2443 if (portsc & PORT_WRC) 2444 ret += sprintf(str + ret, "WRC "); /* RsvdZ for USB2 ports */ 2445 if (portsc & PORT_OCC) 2446 ret += sprintf(str + ret, "OCC "); 2447 if (portsc & PORT_RC) 2448 ret += sprintf(str + ret, "PRC "); 2449 if (portsc & PORT_PLC) 2450 ret += sprintf(str + ret, "PLC "); 2451 if (portsc & PORT_CEC) 2452 ret += sprintf(str + ret, "CEC "); /* RsvdZ for USB2 ports */ 2453 2454 return str; 2455} 2456 2457static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2458{ 2459 int ret = 0; 2460 2461 ret = sprintf(str, " 0x%08x", usbsts); 2462 2463 if (usbsts == ~(u32)0) 2464 return str; 2465 2466 if (usbsts & STS_HALT) 2467 ret += sprintf(str + ret, " HCHalted"); 2468 if (usbsts & STS_FATAL) 2469 ret += sprintf(str + ret, " HSE"); 2470 if (usbsts & STS_EINT) 2471 ret += sprintf(str + ret, " EINT"); 2472 if (usbsts & STS_PORT) 2473 ret += sprintf(str + ret, " PCD"); 2474 if (usbsts & STS_SAVE) 2475 ret += sprintf(str + ret, " SSS"); 2476 if (usbsts & STS_RESTORE) 2477 ret += sprintf(str + ret, " RSS"); 2478 if (usbsts & STS_SRE) 2479 ret += sprintf(str + ret, " SRE"); 2480 if (usbsts & STS_CNR) 2481 ret += sprintf(str + ret, " CNR"); 2482 if (usbsts & STS_HCE) 2483 ret += sprintf(str + ret, " HCE"); 2484 2485 return str; 2486} 2487 2488static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2489{ 2490 u8 ep; 2491 u16 stream; 2492 int ret; 2493 2494 ep = (doorbell & 0xff); 2495 stream = doorbell >> 16; 2496 2497 if (slot == 0) { 2498 sprintf(str, "Command Ring %d", doorbell); 2499 return str; 2500 } 2501 ret = sprintf(str, "Slot %d ", slot); 2502 if (ep > 0 && ep < 32) 2503 ret = sprintf(str + ret, "ep%d%s", 2504 ep / 2, 2505 ep % 2 ? "in" : "out"); 2506 else if (ep == 0 || ep < 248) 2507 ret = sprintf(str + ret, "Reserved %d", ep); 2508 else 2509 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2510 if (stream) 2511 ret = sprintf(str + ret, " Stream %d", stream); 2512 2513 return str; 2514} 2515 2516static inline const char *xhci_ep_state_string(u8 state) 2517{ 2518 switch (state) { 2519 case EP_STATE_DISABLED: 2520 return "disabled"; 2521 case EP_STATE_RUNNING: 2522 return "running"; 2523 case EP_STATE_HALTED: 2524 return "halted"; 2525 case EP_STATE_STOPPED: 2526 return "stopped"; 2527 case EP_STATE_ERROR: 2528 return "error"; 2529 default: 2530 return "INVALID"; 2531 } 2532} 2533 2534static inline const char *xhci_ep_type_string(u8 type) 2535{ 2536 switch (type) { 2537 case ISOC_OUT_EP: 2538 return "Isoc OUT"; 2539 case BULK_OUT_EP: 2540 return "Bulk OUT"; 2541 case INT_OUT_EP: 2542 return "Int OUT"; 2543 case CTRL_EP: 2544 return "Ctrl"; 2545 case ISOC_IN_EP: 2546 return "Isoc IN"; 2547 case BULK_IN_EP: 2548 return "Bulk IN"; 2549 case INT_IN_EP: 2550 return "Int IN"; 2551 default: 2552 return "INVALID"; 2553 } 2554} 2555 2556static inline const char *xhci_decode_ep_context(char *str, u32 info, 2557 u32 info2, u64 deq, u32 tx_info) 2558{ 2559 int ret; 2560 2561 u32 esit; 2562 u16 maxp; 2563 u16 avg; 2564 2565 u8 max_pstr; 2566 u8 ep_state; 2567 u8 interval; 2568 u8 ep_type; 2569 u8 burst; 2570 u8 cerr; 2571 u8 mult; 2572 2573 bool lsa; 2574 bool hid; 2575 2576 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2577 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2578 2579 ep_state = info & EP_STATE_MASK; 2580 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2581 interval = CTX_TO_EP_INTERVAL(info); 2582 mult = CTX_TO_EP_MULT(info) + 1; 2583 lsa = !!(info & EP_HAS_LSA); 2584 2585 cerr = (info2 & (3 << 1)) >> 1; 2586 ep_type = CTX_TO_EP_TYPE(info2); 2587 hid = !!(info2 & (1 << 7)); 2588 burst = CTX_TO_MAX_BURST(info2); 2589 maxp = MAX_PACKET_DECODED(info2); 2590 2591 avg = EP_AVG_TRB_LENGTH(tx_info); 2592 2593 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2594 xhci_ep_state_string(ep_state), mult, 2595 max_pstr, lsa ? "LSA " : ""); 2596 2597 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2598 (1 << interval) * 125, esit, cerr); 2599 2600 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2601 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2602 burst, maxp, deq); 2603 2604 ret += sprintf(str + ret, "avg trb len %d", avg); 2605 2606 return str; 2607} 2608 2609#endif /* __LINUX_XHCI_HCD_H */
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