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xhci-tegra.c
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linux-6.19.14/drivers/usb/host/xhci-tegra.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * NVIDIA Tegra xHCI host controller driver 4 * 5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. 6 * Copyright (C) 2014 Google, Inc. 7 */ 8 9#include <linux/clk.h> 10#include <linux/delay.h> 11#include <linux/dma-mapping.h> 12#include <linux/firmware.h> 13#include <linux/interrupt.h> 14#include <linux/iopoll.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/of.h> 18#include <linux/of_irq.h> 19#include <linux/phy/phy.h> 20#include <linux/phy/tegra/xusb.h> 21#include <linux/platform_device.h> 22#include <linux/usb/ch9.h> 23#include <linux/pm.h> 24#include <linux/pm_domain.h> 25#include <linux/pm_runtime.h> 26#include <linux/regulator/consumer.h> 27#include <linux/reset.h> 28#include <linux/slab.h> 29#include <linux/string_choices.h> 30#include <linux/usb/otg.h> 31#include <linux/usb/phy.h> 32#include <linux/usb/role.h> 33#include <soc/tegra/pmc.h> 34 35#include "xhci.h" 36 37#define TEGRA_XHCI_SS_HIGH_SPEED 120000000 38#define TEGRA_XHCI_SS_LOW_SPEED 12000000 39 40/* FPCI CFG registers */ 41#define XUSB_CFG_1 0x004 42#define XUSB_IO_SPACE_EN BIT(0) 43#define XUSB_MEM_SPACE_EN BIT(1) 44#define XUSB_BUS_MASTER_EN BIT(2) 45#define XUSB_CFG_4 0x010 46#define XUSB_BASE_ADDR_SHIFT 15 47#define XUSB_BASE_ADDR_MASK 0x1ffff 48#define XUSB_CFG_7 0x01c 49#define XUSB_BASE2_ADDR_SHIFT 16 50#define XUSB_BASE2_ADDR_MASK 0xffff 51#define XUSB_CFG_16 0x040 52#define XUSB_CFG_24 0x060 53#define XUSB_CFG_AXI_CFG 0x0f8 54#define XUSB_CFG_ARU_C11_CSBRANGE 0x41c 55#define XUSB_CFG_ARU_CONTEXT 0x43c 56#define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478 57#define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c 58#define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480 59#define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484 60#define XUSB_CFG_CSB_BASE_ADDR 0x800 61 62/* FPCI mailbox registers */ 63/* XUSB_CFG_ARU_MBOX_CMD */ 64#define MBOX_DEST_FALC BIT(27) 65#define MBOX_DEST_PME BIT(28) 66#define MBOX_DEST_SMI BIT(29) 67#define MBOX_DEST_XHCI BIT(30) 68#define MBOX_INT_EN BIT(31) 69/* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */ 70#define CMD_DATA_SHIFT 0 71#define CMD_DATA_MASK 0xffffff 72#define CMD_TYPE_SHIFT 24 73#define CMD_TYPE_MASK 0xff 74/* XUSB_CFG_ARU_MBOX_OWNER */ 75#define MBOX_OWNER_NONE 0 76#define MBOX_OWNER_FW 1 77#define MBOX_OWNER_SW 2 78#define XUSB_CFG_ARU_SMI_INTR 0x428 79#define MBOX_SMI_INTR_FW_HANG BIT(1) 80#define MBOX_SMI_INTR_EN BIT(3) 81 82/* BAR2 registers */ 83#define XUSB_BAR2_ARU_MBOX_CMD 0x004 84#define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008 85#define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c 86#define XUSB_BAR2_ARU_MBOX_OWNER 0x010 87#define XUSB_BAR2_ARU_SMI_INTR 0x014 88#define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c 89#define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0 90#define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4 91#define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8 92#define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c 93#define XUSB_BAR2_ARU_FW_SCRATCH 0x1000 94#define XUSB_BAR2_CSB_BASE_ADDR 0x2000 95 96/* IPFS registers */ 97#define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 98#define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 99#define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8 100#define IPFS_XUSB_HOST_MSI_VEC0_0 0x100 101#define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140 102#define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 103#define IPFS_EN_FPCI BIT(0) 104#define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184 105#define IPFS_XUSB_HOST_INTR_MASK_0 0x188 106#define IPFS_IP_INT_MASK BIT(16) 107#define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198 108#define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c 109#define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc 110#define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc 111 112#define CSB_PAGE_SELECT_MASK 0x7fffff 113#define CSB_PAGE_SELECT_SHIFT 9 114#define CSB_PAGE_OFFSET_MASK 0x1ff 115#define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ 116 CSB_PAGE_SELECT_MASK) 117#define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) 118 119/* Falcon CSB registers */ 120#define XUSB_FALC_CPUCTL 0x100 121#define CPUCTL_STARTCPU BIT(1) 122#define CPUCTL_STATE_HALTED BIT(4) 123#define CPUCTL_STATE_STOPPED BIT(5) 124#define XUSB_FALC_BOOTVEC 0x104 125#define XUSB_FALC_DMACTL 0x10c 126#define XUSB_FALC_IMFILLRNG1 0x154 127#define IMFILLRNG1_TAG_MASK 0xffff 128#define IMFILLRNG1_TAG_LO_SHIFT 0 129#define IMFILLRNG1_TAG_HI_SHIFT 16 130#define XUSB_FALC_IMFILLCTL 0x158 131 132/* CSB ARU registers */ 133#define XUSB_CSB_ARU_SCRATCH0 0x100100 134 135/* MP CSB registers */ 136#define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 137#define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 138#define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 139#define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 140#define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 141#define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff 142#define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 143#define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff 144#define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 145#define L2IMEMOP_ACTION_SHIFT 24 146#define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) 147#define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) 148#define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18 149#define L2IMEMOP_RESULT_VLD BIT(31) 150#define XUSB_CSB_MP_APMAP 0x10181c 151#define APMAP_BOOTPATH BIT(31) 152 153#define IMEM_BLOCK_SIZE 256 154 155#define FW_IOCTL_TYPE_SHIFT 24 156#define FW_IOCTL_CFGTBL_READ 17 157 158#define WAKE_IRQ_START_INDEX 2 159 160struct tegra_xusb_fw_header { 161 __le32 boot_loadaddr_in_imem; 162 __le32 boot_codedfi_offset; 163 __le32 boot_codetag; 164 __le32 boot_codesize; 165 __le32 phys_memaddr; 166 __le16 reqphys_memsize; 167 __le16 alloc_phys_memsize; 168 __le32 rodata_img_offset; 169 __le32 rodata_section_start; 170 __le32 rodata_section_end; 171 __le32 main_fnaddr; 172 __le32 fwimg_cksum; 173 __le32 fwimg_created_time; 174 __le32 imem_resident_start; 175 __le32 imem_resident_end; 176 __le32 idirect_start; 177 __le32 idirect_end; 178 __le32 l2_imem_start; 179 __le32 l2_imem_end; 180 __le32 version_id; 181 u8 init_ddirect; 182 u8 reserved[3]; 183 __le32 phys_addr_log_buffer; 184 __le32 total_log_entries; 185 __le32 dequeue_ptr; 186 __le32 dummy_var[2]; 187 __le32 fwimg_len; 188 u8 magic[8]; 189 __le32 ss_low_power_entry_timeout; 190 u8 num_hsic_port; 191 u8 padding[139]; /* Pad to 256 bytes */ 192}; 193 194struct tegra_xusb_phy_type { 195 const char *name; 196 unsigned int num; 197}; 198 199struct tegra_xusb_mbox_regs { 200 u16 cmd; 201 u16 data_in; 202 u16 data_out; 203 u16 owner; 204 u16 smi_intr; 205}; 206 207struct tegra_xusb_context_soc { 208 struct { 209 const unsigned int *offsets; 210 unsigned int num_offsets; 211 } ipfs; 212 213 struct { 214 const unsigned int *offsets; 215 unsigned int num_offsets; 216 } fpci; 217}; 218 219struct tegra_xusb; 220struct tegra_xusb_soc_ops { 221 u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, unsigned int offset); 222 void (*mbox_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset); 223 u32 (*csb_reg_readl)(struct tegra_xusb *tegra, unsigned int offset); 224 void (*csb_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset); 225}; 226 227struct tegra_xusb_soc { 228 const char *firmware; 229 const char * const *supply_names; 230 unsigned int num_supplies; 231 const struct tegra_xusb_phy_type *phy_types; 232 unsigned int num_types; 233 unsigned int max_num_wakes; 234 const struct tegra_xusb_context_soc *context; 235 236 struct { 237 struct { 238 unsigned int offset; 239 unsigned int count; 240 } usb2, ulpi, hsic, usb3; 241 } ports; 242 243 struct tegra_xusb_mbox_regs mbox; 244 const struct tegra_xusb_soc_ops *ops; 245 246 bool scale_ss_clock; 247 bool has_ipfs; 248 bool lpm_support; 249 bool otg_reset_sspi; 250 251 bool has_bar2; 252}; 253 254struct tegra_xusb_context { 255 u32 *ipfs; 256 u32 *fpci; 257}; 258 259struct tegra_xusb { 260 struct device *dev; 261 void __iomem *regs; 262 struct usb_hcd *hcd; 263 264 struct mutex lock; 265 266 int xhci_irq; 267 int mbox_irq; 268 int padctl_irq; 269 int *wake_irqs; 270 271 void __iomem *ipfs_base; 272 void __iomem *fpci_base; 273 void __iomem *bar2_base; 274 struct resource *bar2; 275 276 const struct tegra_xusb_soc *soc; 277 278 struct regulator_bulk_data *supplies; 279 280 struct tegra_xusb_padctl *padctl; 281 282 struct clk *host_clk; 283 struct clk *falcon_clk; 284 struct clk *ss_clk; 285 struct clk *ss_src_clk; 286 struct clk *hs_src_clk; 287 struct clk *fs_src_clk; 288 struct clk *pll_u_480m; 289 struct clk *clk_m; 290 struct clk *pll_e; 291 292 struct reset_control *host_rst; 293 struct reset_control *ss_rst; 294 295 struct device *genpd_dev_host; 296 struct device *genpd_dev_ss; 297 bool use_genpd; 298 299 struct phy **phys; 300 unsigned int num_phys; 301 302 struct usb_phy **usbphy; 303 unsigned int num_usb_phys; 304 int otg_usb2_port; 305 int otg_usb3_port; 306 bool host_mode; 307 struct notifier_block id_nb; 308 struct work_struct id_work; 309 310 /* Firmware loading related */ 311 struct { 312 size_t size; 313 void *virt; 314 dma_addr_t phys; 315 } fw; 316 317 bool suspended; 318 struct tegra_xusb_context context; 319 u8 lp0_utmi_pad_mask; 320 int num_wakes; 321}; 322 323static struct hc_driver __read_mostly tegra_xhci_hc_driver; 324 325static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) 326{ 327 return readl(tegra->fpci_base + offset); 328} 329 330static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, 331 unsigned int offset) 332{ 333 writel(value, tegra->fpci_base + offset); 334} 335 336static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) 337{ 338 return readl(tegra->ipfs_base + offset); 339} 340 341static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, 342 unsigned int offset) 343{ 344 writel(value, tegra->ipfs_base + offset); 345} 346 347static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset) 348{ 349 return readl(tegra->bar2_base + offset); 350} 351 352static inline void bar2_writel(struct tegra_xusb *tegra, u32 value, 353 unsigned int offset) 354{ 355 writel(value, tegra->bar2_base + offset); 356} 357 358static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) 359{ 360 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 361 362 return ops->csb_reg_readl(tegra, offset); 363} 364 365static void csb_writel(struct tegra_xusb *tegra, u32 value, 366 unsigned int offset) 367{ 368 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 369 370 ops->csb_reg_writel(tegra, value, offset); 371} 372 373static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset) 374{ 375 u32 page = CSB_PAGE_SELECT(offset); 376 u32 ofs = CSB_PAGE_OFFSET(offset); 377 378 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 379 380 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); 381} 382 383static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value, 384 unsigned int offset) 385{ 386 u32 page = CSB_PAGE_SELECT(offset); 387 u32 ofs = CSB_PAGE_OFFSET(offset); 388 389 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 390 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); 391} 392 393static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset) 394{ 395 u32 page = CSB_PAGE_SELECT(offset); 396 u32 ofs = CSB_PAGE_OFFSET(offset); 397 398 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); 399 400 return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs); 401} 402 403static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value, 404 unsigned int offset) 405{ 406 u32 page = CSB_PAGE_SELECT(offset); 407 u32 ofs = CSB_PAGE_OFFSET(offset); 408 409 bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); 410 bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs); 411} 412 413static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, 414 unsigned long rate) 415{ 416 unsigned long new_parent_rate, old_parent_rate; 417 struct clk *clk = tegra->ss_src_clk; 418 unsigned int div; 419 int err; 420 421 if (clk_get_rate(clk) == rate) 422 return 0; 423 424 switch (rate) { 425 case TEGRA_XHCI_SS_HIGH_SPEED: 426 /* 427 * Reparent to PLLU_480M. Set divider first to avoid 428 * overclocking. 429 */ 430 old_parent_rate = clk_get_rate(clk_get_parent(clk)); 431 new_parent_rate = clk_get_rate(tegra->pll_u_480m); 432 div = new_parent_rate / rate; 433 434 err = clk_set_rate(clk, old_parent_rate / div); 435 if (err) 436 return err; 437 438 err = clk_set_parent(clk, tegra->pll_u_480m); 439 if (err) 440 return err; 441 442 /* 443 * The rate should already be correct, but set it again just 444 * to be sure. 445 */ 446 err = clk_set_rate(clk, rate); 447 if (err) 448 return err; 449 450 break; 451 452 case TEGRA_XHCI_SS_LOW_SPEED: 453 /* Reparent to CLK_M */ 454 err = clk_set_parent(clk, tegra->clk_m); 455 if (err) 456 return err; 457 458 err = clk_set_rate(clk, rate); 459 if (err) 460 return err; 461 462 break; 463 464 default: 465 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); 466 return -EINVAL; 467 } 468 469 if (clk_get_rate(clk) != rate) { 470 dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); 471 return -EINVAL; 472 } 473 474 return 0; 475} 476 477static unsigned long extract_field(u32 value, unsigned int start, 478 unsigned int count) 479{ 480 return (value >> start) & ((1 << count) - 1); 481} 482 483/* Command requests from the firmware */ 484enum tegra_xusb_mbox_cmd { 485 MBOX_CMD_MSG_ENABLED = 1, 486 MBOX_CMD_INC_FALC_CLOCK, 487 MBOX_CMD_DEC_FALC_CLOCK, 488 MBOX_CMD_INC_SSPI_CLOCK, 489 MBOX_CMD_DEC_SSPI_CLOCK, 490 MBOX_CMD_SET_BW, /* no ACK/NAK required */ 491 MBOX_CMD_SET_SS_PWR_GATING, 492 MBOX_CMD_SET_SS_PWR_UNGATING, 493 MBOX_CMD_SAVE_DFE_CTLE_CTX, 494 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ 495 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ 496 MBOX_CMD_START_HSIC_IDLE, 497 MBOX_CMD_STOP_HSIC_IDLE, 498 MBOX_CMD_DBC_WAKE_STACK, /* unused */ 499 MBOX_CMD_HSIC_PRETEND_CONNECT, 500 MBOX_CMD_RESET_SSPI, 501 MBOX_CMD_DISABLE_SS_LFPS_DETECTION, 502 MBOX_CMD_ENABLE_SS_LFPS_DETECTION, 503 504 MBOX_CMD_MAX, 505 506 /* Response message to above commands */ 507 MBOX_CMD_ACK = 128, 508 MBOX_CMD_NAK 509}; 510 511struct tegra_xusb_mbox_msg { 512 u32 cmd; 513 u32 data; 514}; 515 516static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) 517{ 518 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | 519 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; 520} 521static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, 522 u32 value) 523{ 524 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; 525 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; 526} 527 528static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) 529{ 530 switch (cmd) { 531 case MBOX_CMD_SET_BW: 532 case MBOX_CMD_ACK: 533 case MBOX_CMD_NAK: 534 return false; 535 536 default: 537 return true; 538 } 539} 540 541static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, 542 const struct tegra_xusb_mbox_msg *msg) 543{ 544 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 545 bool wait_for_idle = false; 546 u32 value; 547 548 /* 549 * Acquire the mailbox. The firmware still owns the mailbox for 550 * ACK/NAK messages. 551 */ 552 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { 553 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 554 if (value != MBOX_OWNER_NONE) { 555 dev_err(tegra->dev, "mailbox is busy\n"); 556 return -EBUSY; 557 } 558 559 ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); 560 561 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 562 if (value != MBOX_OWNER_SW) { 563 dev_err(tegra->dev, "failed to acquire mailbox\n"); 564 return -EBUSY; 565 } 566 567 wait_for_idle = true; 568 } 569 570 value = tegra_xusb_mbox_pack(msg); 571 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in); 572 573 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); 574 value |= MBOX_INT_EN | MBOX_DEST_FALC; 575 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); 576 577 if (wait_for_idle) { 578 unsigned long timeout = jiffies + msecs_to_jiffies(250); 579 580 while (time_before(jiffies, timeout)) { 581 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 582 if (value == MBOX_OWNER_NONE) 583 break; 584 585 usleep_range(10, 20); 586 } 587 588 if (time_after(jiffies, timeout)) 589 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); 590 591 if (value != MBOX_OWNER_NONE) 592 return -ETIMEDOUT; 593 } 594 595 return 0; 596} 597 598static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) 599{ 600 struct tegra_xusb *tegra = data; 601 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 602 u32 value; 603 604 /* clear mailbox interrupts */ 605 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr); 606 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr); 607 608 if (value & MBOX_SMI_INTR_FW_HANG) 609 dev_err(tegra->dev, "controller firmware hang\n"); 610 611 return IRQ_WAKE_THREAD; 612} 613 614static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, 615 const struct tegra_xusb_mbox_msg *msg) 616{ 617 struct tegra_xusb_padctl *padctl = tegra->padctl; 618 const struct tegra_xusb_soc *soc = tegra->soc; 619 struct device *dev = tegra->dev; 620 struct tegra_xusb_mbox_msg rsp; 621 unsigned long mask; 622 unsigned int port; 623 bool idle, enable; 624 int err = 0; 625 626 memset(&rsp, 0, sizeof(rsp)); 627 628 switch (msg->cmd) { 629 case MBOX_CMD_INC_FALC_CLOCK: 630 case MBOX_CMD_DEC_FALC_CLOCK: 631 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; 632 if (rsp.data != msg->data) 633 rsp.cmd = MBOX_CMD_NAK; 634 else 635 rsp.cmd = MBOX_CMD_ACK; 636 637 break; 638 639 case MBOX_CMD_INC_SSPI_CLOCK: 640 case MBOX_CMD_DEC_SSPI_CLOCK: 641 if (tegra->soc->scale_ss_clock) { 642 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); 643 if (err < 0) 644 rsp.cmd = MBOX_CMD_NAK; 645 else 646 rsp.cmd = MBOX_CMD_ACK; 647 648 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; 649 } else { 650 rsp.cmd = MBOX_CMD_ACK; 651 rsp.data = msg->data; 652 } 653 654 break; 655 656 case MBOX_CMD_SET_BW: 657 /* 658 * TODO: Request bandwidth once EMC scaling is supported. 659 * Ignore for now since ACK/NAK is not required for SET_BW 660 * messages. 661 */ 662 break; 663 664 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 665 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); 666 if (err < 0) { 667 dev_err(dev, "failed to save context for USB3#%u: %d\n", 668 msg->data, err); 669 rsp.cmd = MBOX_CMD_NAK; 670 } else { 671 rsp.cmd = MBOX_CMD_ACK; 672 } 673 674 rsp.data = msg->data; 675 break; 676 677 case MBOX_CMD_START_HSIC_IDLE: 678 case MBOX_CMD_STOP_HSIC_IDLE: 679 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) 680 idle = false; 681 else 682 idle = true; 683 684 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, 685 soc->ports.hsic.count); 686 687 for_each_set_bit(port, &mask, 32) { 688 err = tegra_xusb_padctl_hsic_set_idle(padctl, port, 689 idle); 690 if (err < 0) 691 break; 692 } 693 694 if (err < 0) { 695 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, 696 idle ? "idle" : "busy", err); 697 rsp.cmd = MBOX_CMD_NAK; 698 } else { 699 rsp.cmd = MBOX_CMD_ACK; 700 } 701 702 rsp.data = msg->data; 703 break; 704 705 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 706 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 707 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) 708 enable = false; 709 else 710 enable = true; 711 712 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, 713 soc->ports.usb3.count); 714 715 for_each_set_bit(port, &mask, soc->ports.usb3.count) { 716 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, 717 port, 718 enable); 719 if (err < 0) 720 break; 721 722 /* 723 * wait 500us for LFPS detector to be disabled before 724 * sending ACK 725 */ 726 if (!enable) 727 usleep_range(500, 1000); 728 } 729 730 if (err < 0) { 731 dev_err(dev, 732 "failed to %s LFPS detection on USB3#%u: %d\n", 733 str_enable_disable(enable), port, err); 734 rsp.cmd = MBOX_CMD_NAK; 735 } else { 736 rsp.cmd = MBOX_CMD_ACK; 737 } 738 739 rsp.data = msg->data; 740 break; 741 742 default: 743 dev_warn(dev, "unknown message: %#x\n", msg->cmd); 744 break; 745 } 746 747 if (rsp.cmd) { 748 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; 749 750 err = tegra_xusb_mbox_send(tegra, &rsp); 751 if (err < 0) 752 dev_err(dev, "failed to send %s: %d\n", cmd, err); 753 } 754} 755 756static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) 757{ 758 struct tegra_xusb *tegra = data; 759 const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; 760 struct tegra_xusb_mbox_msg msg; 761 u32 value; 762 763 mutex_lock(&tegra->lock); 764 765 if (pm_runtime_suspended(tegra->dev) || tegra->suspended) 766 goto out; 767 768 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out); 769 tegra_xusb_mbox_unpack(&msg, value); 770 771 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); 772 value &= ~MBOX_DEST_SMI; 773 ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); 774 775 /* clear mailbox owner if no ACK/NAK is required */ 776 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) 777 ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); 778 779 tegra_xusb_mbox_handle(tegra, &msg); 780 781out: 782 mutex_unlock(&tegra->lock); 783 return IRQ_HANDLED; 784} 785 786static void tegra_xusb_config(struct tegra_xusb *tegra) 787{ 788 u32 regs = tegra->hcd->rsrc_start; 789 u32 value; 790 791 if (tegra->soc->has_ipfs) { 792 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); 793 value |= IPFS_EN_FPCI; 794 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); 795 796 usleep_range(10, 20); 797 } 798 799 /* Program BAR0 space */ 800 value = fpci_readl(tegra, XUSB_CFG_4); 801 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 802 value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 803 fpci_writel(tegra, value, XUSB_CFG_4); 804 805 /* Program BAR2 space */ 806 if (tegra->bar2) { 807 value = fpci_readl(tegra, XUSB_CFG_7); 808 value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); 809 value |= tegra->bar2->start & 810 (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); 811 fpci_writel(tegra, value, XUSB_CFG_7); 812 } 813 814 usleep_range(100, 200); 815 816 /* Enable bus master */ 817 value = fpci_readl(tegra, XUSB_CFG_1); 818 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; 819 fpci_writel(tegra, value, XUSB_CFG_1); 820 821 if (tegra->soc->has_ipfs) { 822 /* Enable interrupt assertion */ 823 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); 824 value |= IPFS_IP_INT_MASK; 825 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); 826 827 /* Set hysteresis */ 828 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); 829 } 830} 831 832static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) 833{ 834 int err; 835 836 err = clk_prepare_enable(tegra->pll_e); 837 if (err < 0) 838 return err; 839 840 err = clk_prepare_enable(tegra->host_clk); 841 if (err < 0) 842 goto disable_plle; 843 844 err = clk_prepare_enable(tegra->ss_clk); 845 if (err < 0) 846 goto disable_host; 847 848 err = clk_prepare_enable(tegra->falcon_clk); 849 if (err < 0) 850 goto disable_ss; 851 852 err = clk_prepare_enable(tegra->fs_src_clk); 853 if (err < 0) 854 goto disable_falc; 855 856 err = clk_prepare_enable(tegra->hs_src_clk); 857 if (err < 0) 858 goto disable_fs_src; 859 860 if (tegra->soc->scale_ss_clock) { 861 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); 862 if (err < 0) 863 goto disable_hs_src; 864 } 865 866 return 0; 867 868disable_hs_src: 869 clk_disable_unprepare(tegra->hs_src_clk); 870disable_fs_src: 871 clk_disable_unprepare(tegra->fs_src_clk); 872disable_falc: 873 clk_disable_unprepare(tegra->falcon_clk); 874disable_ss: 875 clk_disable_unprepare(tegra->ss_clk); 876disable_host: 877 clk_disable_unprepare(tegra->host_clk); 878disable_plle: 879 clk_disable_unprepare(tegra->pll_e); 880 return err; 881} 882 883static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) 884{ 885 clk_disable_unprepare(tegra->pll_e); 886 clk_disable_unprepare(tegra->host_clk); 887 clk_disable_unprepare(tegra->ss_clk); 888 clk_disable_unprepare(tegra->falcon_clk); 889 clk_disable_unprepare(tegra->fs_src_clk); 890 clk_disable_unprepare(tegra->hs_src_clk); 891} 892 893static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) 894{ 895 unsigned int i; 896 int err; 897 898 for (i = 0; i < tegra->num_phys; i++) { 899 err = phy_init(tegra->phys[i]); 900 if (err) 901 goto disable_phy; 902 903 err = phy_power_on(tegra->phys[i]); 904 if (err) { 905 phy_exit(tegra->phys[i]); 906 goto disable_phy; 907 } 908 } 909 910 return 0; 911 912disable_phy: 913 while (i--) { 914 phy_power_off(tegra->phys[i]); 915 phy_exit(tegra->phys[i]); 916 } 917 918 return err; 919} 920 921static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) 922{ 923 unsigned int i; 924 925 for (i = 0; i < tegra->num_phys; i++) { 926 phy_power_off(tegra->phys[i]); 927 phy_exit(tegra->phys[i]); 928 } 929} 930 931#ifdef CONFIG_PM_SLEEP 932static int tegra_xusb_init_context(struct tegra_xusb *tegra) 933{ 934 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 935 936 tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets, 937 sizeof(u32), GFP_KERNEL); 938 if (!tegra->context.ipfs) 939 return -ENOMEM; 940 941 tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets, 942 sizeof(u32), GFP_KERNEL); 943 if (!tegra->context.fpci) 944 return -ENOMEM; 945 946 return 0; 947} 948#else 949static inline int tegra_xusb_init_context(struct tegra_xusb *tegra) 950{ 951 return 0; 952} 953#endif 954 955static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) 956{ 957 struct tegra_xusb_fw_header *header; 958 const struct firmware *fw; 959 int err; 960 961 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); 962 if (err < 0) { 963 dev_err(tegra->dev, "failed to request firmware: %d\n", err); 964 return err; 965 } 966 967 /* Load Falcon controller with its firmware. */ 968 header = (struct tegra_xusb_fw_header *)fw->data; 969 tegra->fw.size = le32_to_cpu(header->fwimg_len); 970 971 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, 972 &tegra->fw.phys, GFP_KERNEL); 973 if (!tegra->fw.virt) { 974 dev_err(tegra->dev, "failed to allocate memory for firmware\n"); 975 release_firmware(fw); 976 return -ENOMEM; 977 } 978 979 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 980 memcpy(tegra->fw.virt, fw->data, tegra->fw.size); 981 release_firmware(fw); 982 983 return 0; 984} 985 986static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra) 987{ 988 struct xhci_cap_regs __iomem *cap_regs; 989 struct xhci_op_regs __iomem *op_regs; 990 int ret; 991 u32 value; 992 993 cap_regs = tegra->regs; 994 op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase)); 995 996 ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000); 997 998 if (ret) 999 dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n", 1000 csb_readl(tegra, XUSB_FALC_CPUCTL)); 1001 1002 return ret; 1003} 1004 1005static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra) 1006{ 1007 unsigned int code_tag_blocks, code_size_blocks, code_blocks; 1008 struct tegra_xusb_fw_header *header; 1009 struct device *dev = tegra->dev; 1010 time64_t timestamp; 1011 u64 address; 1012 u32 value; 1013 int err; 1014 1015 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 1016 1017 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { 1018 dev_info(dev, "Firmware already loaded, Falcon state %#x\n", 1019 csb_readl(tegra, XUSB_FALC_CPUCTL)); 1020 return 0; 1021 } 1022 1023 /* Program the size of DFI into ILOAD_ATTR. */ 1024 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); 1025 1026 /* 1027 * Boot code of the firmware reads the ILOAD_BASE registers 1028 * to get to the start of the DFI in system memory. 1029 */ 1030 address = tegra->fw.phys + sizeof(*header); 1031 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); 1032 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); 1033 1034 /* Set BOOTPATH to 1 in APMAP. */ 1035 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); 1036 1037 /* Invalidate L2IMEM. */ 1038 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); 1039 1040 /* 1041 * Initiate fetch of bootcode from system memory into L2IMEM. 1042 * Program bootcode location and size in system memory. 1043 */ 1044 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), 1045 IMEM_BLOCK_SIZE); 1046 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), 1047 IMEM_BLOCK_SIZE); 1048 code_blocks = code_tag_blocks + code_size_blocks; 1049 1050 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << 1051 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | 1052 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << 1053 L2IMEMOP_SIZE_SRC_COUNT_SHIFT); 1054 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); 1055 1056 /* Trigger L2IMEM load operation. */ 1057 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, 1058 XUSB_CSB_MP_L2IMEMOP_TRIG); 1059 1060 /* Setup Falcon auto-fill. */ 1061 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); 1062 1063 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << 1064 IMFILLRNG1_TAG_LO_SHIFT) | 1065 ((code_blocks & IMFILLRNG1_TAG_MASK) << 1066 IMFILLRNG1_TAG_HI_SHIFT); 1067 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); 1068 1069 csb_writel(tegra, 0, XUSB_FALC_DMACTL); 1070 1071 /* wait for RESULT_VLD to get set */ 1072#define tegra_csb_readl(offset) csb_readl(tegra, offset) 1073 err = readx_poll_timeout(tegra_csb_readl, 1074 XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value, 1075 value & L2IMEMOP_RESULT_VLD, 100, 10000); 1076 if (err < 0) { 1077 dev_err(dev, "DMA controller not ready %#010x\n", value); 1078 return err; 1079 } 1080#undef tegra_csb_readl 1081 1082 csb_writel(tegra, le32_to_cpu(header->boot_codetag), 1083 XUSB_FALC_BOOTVEC); 1084 1085 /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ 1086 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); 1087 1088 if (tegra_xusb_wait_for_falcon(tegra)) 1089 return -EIO; 1090 1091 timestamp = le32_to_cpu(header->fwimg_created_time); 1092 1093 dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); 1094 1095 return 0; 1096} 1097 1098static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset) 1099{ 1100 /* 1101 * We only accept reading the firmware config table 1102 * The offset should not exceed the fw header structure 1103 */ 1104 if (offset >= sizeof(struct tegra_xusb_fw_header)) 1105 return 0; 1106 1107 bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset, 1108 XUSB_BAR2_ARU_FW_SCRATCH); 1109 return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0); 1110} 1111 1112static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra) 1113{ 1114 time64_t timestamp; 1115 1116 if (tegra_xusb_wait_for_falcon(tegra)) 1117 return -EIO; 1118 1119#define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32))) 1120 timestamp = tegra_xusb_read_firmware_header(tegra, offsetof_32(struct tegra_xusb_fw_header, 1121 fwimg_created_time) << 2); 1122 1123 dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); 1124 1125 return 0; 1126} 1127 1128static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) 1129{ 1130 if (!tegra->soc->firmware) 1131 return tegra_xusb_init_ifr_firmware(tegra); 1132 else 1133 return tegra_xusb_load_firmware_rom(tegra); 1134} 1135 1136static void tegra_xusb_powerdomain_remove(struct device *dev, 1137 struct tegra_xusb *tegra) 1138{ 1139 if (!tegra->use_genpd) 1140 return; 1141 1142 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss)) 1143 dev_pm_domain_detach(tegra->genpd_dev_ss, true); 1144 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host)) 1145 dev_pm_domain_detach(tegra->genpd_dev_host, true); 1146} 1147 1148static int tegra_xusb_powerdomain_init(struct device *dev, 1149 struct tegra_xusb *tegra) 1150{ 1151 int err; 1152 1153 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host"); 1154 if (IS_ERR(tegra->genpd_dev_host)) { 1155 err = PTR_ERR(tegra->genpd_dev_host); 1156 dev_err(dev, "failed to get host pm-domain: %d\n", err); 1157 return err; 1158 } 1159 1160 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss"); 1161 if (IS_ERR(tegra->genpd_dev_ss)) { 1162 err = PTR_ERR(tegra->genpd_dev_ss); 1163 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err); 1164 return err; 1165 } 1166 1167 tegra->use_genpd = true; 1168 1169 return 0; 1170} 1171 1172static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra) 1173{ 1174 struct device *dev = tegra->dev; 1175 int rc; 1176 1177 if (tegra->use_genpd) { 1178 rc = pm_runtime_resume_and_get(tegra->genpd_dev_ss); 1179 if (rc < 0) { 1180 dev_err(dev, "failed to enable XUSB SS partition\n"); 1181 return rc; 1182 } 1183 1184 rc = pm_runtime_resume_and_get(tegra->genpd_dev_host); 1185 if (rc < 0) { 1186 dev_err(dev, "failed to enable XUSB Host partition\n"); 1187 pm_runtime_put_sync(tegra->genpd_dev_ss); 1188 return rc; 1189 } 1190 } else { 1191 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 1192 tegra->ss_clk, 1193 tegra->ss_rst); 1194 if (rc < 0) { 1195 dev_err(dev, "failed to enable XUSB SS partition\n"); 1196 return rc; 1197 } 1198 1199 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 1200 tegra->host_clk, 1201 tegra->host_rst); 1202 if (rc < 0) { 1203 dev_err(dev, "failed to enable XUSB Host partition\n"); 1204 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1205 return rc; 1206 } 1207 } 1208 1209 return 0; 1210} 1211 1212static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra) 1213{ 1214 struct device *dev = tegra->dev; 1215 int rc; 1216 1217 if (tegra->use_genpd) { 1218 rc = pm_runtime_put_sync(tegra->genpd_dev_host); 1219 if (rc < 0) { 1220 dev_err(dev, "failed to disable XUSB Host partition\n"); 1221 return rc; 1222 } 1223 1224 rc = pm_runtime_put_sync(tegra->genpd_dev_ss); 1225 if (rc < 0) { 1226 dev_err(dev, "failed to disable XUSB SS partition\n"); 1227 pm_runtime_get_sync(tegra->genpd_dev_host); 1228 return rc; 1229 } 1230 } else { 1231 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1232 if (rc < 0) { 1233 dev_err(dev, "failed to disable XUSB Host partition\n"); 1234 return rc; 1235 } 1236 1237 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1238 if (rc < 0) { 1239 dev_err(dev, "failed to disable XUSB SS partition\n"); 1240 tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 1241 tegra->host_clk, 1242 tegra->host_rst); 1243 return rc; 1244 } 1245 } 1246 1247 return 0; 1248} 1249 1250static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) 1251{ 1252 struct tegra_xusb_mbox_msg msg; 1253 int err; 1254 1255 /* Enable firmware messages from controller. */ 1256 msg.cmd = MBOX_CMD_MSG_ENABLED; 1257 msg.data = 0; 1258 1259 err = tegra_xusb_mbox_send(tegra, &msg); 1260 if (err < 0) 1261 dev_err(tegra->dev, "failed to enable messages: %d\n", err); 1262 1263 return err; 1264} 1265 1266static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data) 1267{ 1268 struct tegra_xusb *tegra = data; 1269 1270 mutex_lock(&tegra->lock); 1271 1272 if (tegra->suspended) { 1273 mutex_unlock(&tegra->lock); 1274 return IRQ_HANDLED; 1275 } 1276 1277 mutex_unlock(&tegra->lock); 1278 1279 pm_runtime_resume(tegra->dev); 1280 1281 return IRQ_HANDLED; 1282} 1283 1284static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) 1285{ 1286 int err; 1287 1288 mutex_lock(&tegra->lock); 1289 err = __tegra_xusb_enable_firmware_messages(tegra); 1290 mutex_unlock(&tegra->lock); 1291 1292 return err; 1293} 1294 1295static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main, 1296 bool set) 1297{ 1298 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1299 struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd; 1300 unsigned int wait = (!main && !set) ? 1000 : 10; 1301 u16 typeReq = set ? SetPortFeature : ClearPortFeature; 1302 u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1; 1303 u32 status; 1304 u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER; 1305 u32 status_val = set ? stat_power : 0; 1306 1307 dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__, 1308 set ? "set" : "clear", main ? "HS" : "SS"); 1309 1310 hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex, 1311 NULL, 0); 1312 1313 do { 1314 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex, 1315 (char *) &status, sizeof(status)); 1316 if (status_val == (status & stat_power)) 1317 break; 1318 1319 if (!main && !set) 1320 usleep_range(600, 700); 1321 else 1322 usleep_range(10, 20); 1323 } while (--wait > 0); 1324 1325 if (status_val != (status & stat_power)) 1326 dev_info(tegra->dev, "failed to %s %s PP %d\n", 1327 set ? "set" : "clear", 1328 main ? "HS" : "SS", status); 1329} 1330 1331static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name, 1332 int port) 1333{ 1334 unsigned int i, phy_count = 0; 1335 1336 for (i = 0; i < tegra->soc->num_types; i++) { 1337 if (!strncmp(tegra->soc->phy_types[i].name, name, 1338 strlen(name))) 1339 return tegra->phys[phy_count+port]; 1340 1341 phy_count += tegra->soc->phy_types[i].num; 1342 } 1343 1344 return NULL; 1345} 1346 1347static void tegra_xhci_id_work(struct work_struct *work) 1348{ 1349 struct tegra_xusb *tegra = container_of(work, struct tegra_xusb, 1350 id_work); 1351 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1352 struct tegra_xusb_mbox_msg msg; 1353 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", 1354 tegra->otg_usb2_port); 1355 u32 status; 1356 int ret; 1357 1358 dev_dbg(tegra->dev, "host mode %s\n", str_on_off(tegra->host_mode)); 1359 1360 mutex_lock(&tegra->lock); 1361 1362 if (tegra->host_mode) 1363 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST); 1364 else 1365 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); 1366 1367 mutex_unlock(&tegra->lock); 1368 1369 tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(tegra->padctl, 1370 tegra->otg_usb2_port); 1371 1372 pm_runtime_get_sync(tegra->dev); 1373 if (tegra->host_mode) { 1374 /* switch to host mode */ 1375 if (tegra->otg_usb3_port >= 0) { 1376 if (tegra->soc->otg_reset_sspi) { 1377 /* set PP=0 */ 1378 tegra_xhci_hc_driver.hub_control( 1379 xhci->shared_hcd, GetPortStatus, 1380 0, tegra->otg_usb3_port+1, 1381 (char *) &status, sizeof(status)); 1382 if (status & USB_SS_PORT_STAT_POWER) 1383 tegra_xhci_set_port_power(tegra, false, 1384 false); 1385 1386 /* reset OTG port SSPI */ 1387 msg.cmd = MBOX_CMD_RESET_SSPI; 1388 msg.data = tegra->otg_usb3_port+1; 1389 1390 ret = tegra_xusb_mbox_send(tegra, &msg); 1391 if (ret < 0) { 1392 dev_info(tegra->dev, 1393 "failed to RESET_SSPI %d\n", 1394 ret); 1395 } 1396 } 1397 1398 tegra_xhci_set_port_power(tegra, false, true); 1399 } 1400 1401 tegra_xhci_set_port_power(tegra, true, true); 1402 1403 } else { 1404 if (tegra->otg_usb3_port >= 0) 1405 tegra_xhci_set_port_power(tegra, false, false); 1406 1407 tegra_xhci_set_port_power(tegra, true, false); 1408 } 1409 pm_runtime_put_autosuspend(tegra->dev); 1410} 1411 1412#if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP) 1413static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index) 1414{ 1415 return (tegra->usbphy[index] != NULL); 1416} 1417 1418static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index) 1419{ 1420 struct tegra_xusb_padctl *padctl = tegra->padctl; 1421 unsigned int i; 1422 int port; 1423 1424 for (i = 0; i < tegra->num_usb_phys; i++) { 1425 if (is_usb2_otg_phy(tegra, i)) { 1426 port = tegra_xusb_padctl_get_usb3_companion(padctl, i); 1427 if ((port >= 0) && (index == (unsigned int)port)) 1428 return true; 1429 } 1430 } 1431 1432 return false; 1433} 1434 1435static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index) 1436{ 1437 if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0) 1438 return true; 1439 1440 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) { 1441 if (is_usb2_otg_phy(tegra, index)) 1442 return ((index == tegra->otg_usb2_port) && tegra->host_mode); 1443 else 1444 return true; 1445 } 1446 1447 if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) { 1448 if (is_usb3_otg_phy(tegra, index)) 1449 return ((index == tegra->otg_usb3_port) && tegra->host_mode); 1450 else 1451 return true; 1452 } 1453 1454 return false; 1455} 1456#endif 1457 1458static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra, 1459 struct usb_phy *usbphy) 1460{ 1461 unsigned int i; 1462 1463 for (i = 0; i < tegra->num_usb_phys; i++) { 1464 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i]) 1465 return i; 1466 } 1467 1468 return -1; 1469} 1470 1471static int tegra_xhci_id_notify(struct notifier_block *nb, 1472 unsigned long action, void *data) 1473{ 1474 struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb, 1475 id_nb); 1476 struct usb_phy *usbphy = (struct usb_phy *)data; 1477 1478 dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event); 1479 1480 if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) || 1481 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) { 1482 dev_dbg(tegra->dev, "Same role(%d) received. Ignore", 1483 tegra->host_mode); 1484 return NOTIFY_OK; 1485 } 1486 1487 tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy); 1488 1489 tegra->host_mode = usbphy->last_event == USB_EVENT_ID; 1490 1491 schedule_work(&tegra->id_work); 1492 1493 return NOTIFY_OK; 1494} 1495 1496static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra) 1497{ 1498 unsigned int i; 1499 1500 tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys, 1501 sizeof(*tegra->usbphy), GFP_KERNEL); 1502 if (!tegra->usbphy) 1503 return -ENOMEM; 1504 1505 INIT_WORK(&tegra->id_work, tegra_xhci_id_work); 1506 tegra->id_nb.notifier_call = tegra_xhci_id_notify; 1507 tegra->otg_usb2_port = -EINVAL; 1508 tegra->otg_usb3_port = -EINVAL; 1509 1510 for (i = 0; i < tegra->num_usb_phys; i++) { 1511 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i); 1512 1513 if (!phy) 1514 continue; 1515 1516 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev, 1517 phy->dev.of_node, 1518 &tegra->id_nb); 1519 if (!IS_ERR(tegra->usbphy[i])) { 1520 dev_dbg(tegra->dev, "usbphy-%d registered", i); 1521 otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self); 1522 } else { 1523 /* 1524 * usb-phy is optional, continue if its not available. 1525 */ 1526 tegra->usbphy[i] = NULL; 1527 } 1528 } 1529 1530 return 0; 1531} 1532 1533static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra) 1534{ 1535 unsigned int i; 1536 1537 cancel_work_sync(&tegra->id_work); 1538 1539 for (i = 0; i < tegra->num_usb_phys; i++) 1540 if (tegra->usbphy[i]) 1541 otg_set_host(tegra->usbphy[i]->otg, NULL); 1542} 1543 1544static int tegra_xusb_setup_wakeup(struct platform_device *pdev, struct tegra_xusb *tegra) 1545{ 1546 unsigned int i; 1547 1548 if (tegra->soc->max_num_wakes == 0) 1549 return 0; 1550 1551 tegra->wake_irqs = devm_kcalloc(tegra->dev, 1552 tegra->soc->max_num_wakes, 1553 sizeof(*tegra->wake_irqs), GFP_KERNEL); 1554 if (!tegra->wake_irqs) 1555 return -ENOMEM; 1556 1557 /* 1558 * USB wake events are independent of each other, so it is not necessary for a platform 1559 * to utilize all wake-up events supported for a given device. The USB host can operate 1560 * even if wake-up events are not defined or fail to be configured. Therefore, we only 1561 * return critical errors, such as -ENOMEM. 1562 */ 1563 for (i = 0; i < tegra->soc->max_num_wakes; i++) { 1564 struct irq_data *data; 1565 1566 tegra->wake_irqs[i] = platform_get_irq_optional(pdev, i + WAKE_IRQ_START_INDEX); 1567 if (tegra->wake_irqs[i] < 0) 1568 break; 1569 1570 data = irq_get_irq_data(tegra->wake_irqs[i]); 1571 if (!data) { 1572 dev_warn(tegra->dev, "get wake event %d irq data fail\n", i); 1573 break; 1574 } 1575 1576 irq_set_irq_type(tegra->wake_irqs[i], irqd_get_trigger_type(data)); 1577 } 1578 1579 tegra->num_wakes = i; 1580 dev_dbg(tegra->dev, "setup %d wake events\n", tegra->num_wakes); 1581 1582 return 0; 1583} 1584 1585static int tegra_xusb_probe(struct platform_device *pdev) 1586{ 1587 struct tegra_xusb *tegra; 1588 struct device_node *np; 1589 struct resource *regs; 1590 struct xhci_hcd *xhci; 1591 unsigned int i, j, k; 1592 struct phy *phy; 1593 int err; 1594 1595 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); 1596 1597 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 1598 if (!tegra) 1599 return -ENOMEM; 1600 1601 tegra->soc = of_device_get_match_data(&pdev->dev); 1602 mutex_init(&tegra->lock); 1603 tegra->dev = &pdev->dev; 1604 1605 err = tegra_xusb_init_context(tegra); 1606 if (err < 0) 1607 return err; 1608 1609 tegra->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 1610 if (IS_ERR(tegra->regs)) 1611 return PTR_ERR(tegra->regs); 1612 1613 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1); 1614 if (IS_ERR(tegra->fpci_base)) 1615 return PTR_ERR(tegra->fpci_base); 1616 1617 if (tegra->soc->has_ipfs) { 1618 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); 1619 if (IS_ERR(tegra->ipfs_base)) 1620 return PTR_ERR(tegra->ipfs_base); 1621 } else if (tegra->soc->has_bar2) { 1622 tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &tegra->bar2); 1623 if (IS_ERR(tegra->bar2_base)) 1624 return PTR_ERR(tegra->bar2_base); 1625 } 1626 1627 tegra->xhci_irq = platform_get_irq(pdev, 0); 1628 if (tegra->xhci_irq < 0) 1629 return tegra->xhci_irq; 1630 1631 tegra->mbox_irq = platform_get_irq(pdev, 1); 1632 if (tegra->mbox_irq < 0) 1633 return tegra->mbox_irq; 1634 1635 err = tegra_xusb_setup_wakeup(pdev, tegra); 1636 if (err) 1637 return err; 1638 1639 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); 1640 if (IS_ERR(tegra->padctl)) 1641 return PTR_ERR(tegra->padctl); 1642 1643 np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0); 1644 if (!np) { 1645 err = -ENODEV; 1646 goto put_padctl; 1647 } 1648 1649 tegra->padctl_irq = of_irq_get(np, 0); 1650 if (tegra->padctl_irq == -EPROBE_DEFER) { 1651 err = tegra->padctl_irq; 1652 goto put_padctl; 1653 } else if (tegra->padctl_irq <= 0) { 1654 /* Older device-trees don't have padctrl interrupt */ 1655 tegra->padctl_irq = 0; 1656 dev_dbg(&pdev->dev, 1657 "%pOF is missing an interrupt, disabling PM support\n", np); 1658 } 1659 1660 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); 1661 if (IS_ERR(tegra->host_clk)) { 1662 err = PTR_ERR(tegra->host_clk); 1663 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); 1664 goto put_padctl; 1665 } 1666 1667 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); 1668 if (IS_ERR(tegra->falcon_clk)) { 1669 err = PTR_ERR(tegra->falcon_clk); 1670 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); 1671 goto put_padctl; 1672 } 1673 1674 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); 1675 if (IS_ERR(tegra->ss_clk)) { 1676 err = PTR_ERR(tegra->ss_clk); 1677 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); 1678 goto put_padctl; 1679 } 1680 1681 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); 1682 if (IS_ERR(tegra->ss_src_clk)) { 1683 err = PTR_ERR(tegra->ss_src_clk); 1684 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); 1685 goto put_padctl; 1686 } 1687 1688 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); 1689 if (IS_ERR(tegra->hs_src_clk)) { 1690 err = PTR_ERR(tegra->hs_src_clk); 1691 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); 1692 goto put_padctl; 1693 } 1694 1695 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); 1696 if (IS_ERR(tegra->fs_src_clk)) { 1697 err = PTR_ERR(tegra->fs_src_clk); 1698 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); 1699 goto put_padctl; 1700 } 1701 1702 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); 1703 if (IS_ERR(tegra->pll_u_480m)) { 1704 err = PTR_ERR(tegra->pll_u_480m); 1705 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); 1706 goto put_padctl; 1707 } 1708 1709 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); 1710 if (IS_ERR(tegra->clk_m)) { 1711 err = PTR_ERR(tegra->clk_m); 1712 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); 1713 goto put_padctl; 1714 } 1715 1716 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); 1717 if (IS_ERR(tegra->pll_e)) { 1718 err = PTR_ERR(tegra->pll_e); 1719 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); 1720 goto put_padctl; 1721 } 1722 1723 if (!of_property_present(pdev->dev.of_node, "power-domains")) { 1724 tegra->host_rst = devm_reset_control_get(&pdev->dev, 1725 "xusb_host"); 1726 if (IS_ERR(tegra->host_rst)) { 1727 err = PTR_ERR(tegra->host_rst); 1728 dev_err(&pdev->dev, 1729 "failed to get xusb_host reset: %d\n", err); 1730 goto put_padctl; 1731 } 1732 1733 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); 1734 if (IS_ERR(tegra->ss_rst)) { 1735 err = PTR_ERR(tegra->ss_rst); 1736 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", 1737 err); 1738 goto put_padctl; 1739 } 1740 } else { 1741 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra); 1742 if (err) 1743 goto put_powerdomains; 1744 } 1745 1746 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, 1747 sizeof(*tegra->supplies), GFP_KERNEL); 1748 if (!tegra->supplies) { 1749 err = -ENOMEM; 1750 goto put_powerdomains; 1751 } 1752 1753 regulator_bulk_set_supply_names(tegra->supplies, 1754 tegra->soc->supply_names, 1755 tegra->soc->num_supplies); 1756 1757 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, 1758 tegra->supplies); 1759 if (err) { 1760 dev_err(&pdev->dev, "failed to get regulators: %d\n", err); 1761 goto put_powerdomains; 1762 } 1763 1764 for (i = 0; i < tegra->soc->num_types; i++) { 1765 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4)) 1766 tegra->num_usb_phys = tegra->soc->phy_types[i].num; 1767 tegra->num_phys += tegra->soc->phy_types[i].num; 1768 } 1769 1770 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, 1771 sizeof(*tegra->phys), GFP_KERNEL); 1772 if (!tegra->phys) { 1773 err = -ENOMEM; 1774 goto put_powerdomains; 1775 } 1776 1777 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 1778 char prop[8]; 1779 1780 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 1781 snprintf(prop, sizeof(prop), "%s-%d", 1782 tegra->soc->phy_types[i].name, j); 1783 1784 phy = devm_phy_optional_get(&pdev->dev, prop); 1785 if (IS_ERR(phy)) { 1786 dev_err(&pdev->dev, 1787 "failed to get PHY %s: %ld\n", prop, 1788 PTR_ERR(phy)); 1789 err = PTR_ERR(phy); 1790 goto put_powerdomains; 1791 } 1792 1793 tegra->phys[k++] = phy; 1794 } 1795 } 1796 1797 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, 1798 dev_name(&pdev->dev)); 1799 if (!tegra->hcd) { 1800 err = -ENOMEM; 1801 goto put_powerdomains; 1802 } 1803 1804 tegra->hcd->skip_phy_initialization = 1; 1805 tegra->hcd->regs = tegra->regs; 1806 tegra->hcd->rsrc_start = regs->start; 1807 tegra->hcd->rsrc_len = resource_size(regs); 1808 1809 /* 1810 * This must happen after usb_create_hcd(), because usb_create_hcd() 1811 * will overwrite the drvdata of the device with the hcd it creates. 1812 */ 1813 platform_set_drvdata(pdev, tegra); 1814 1815 err = tegra_xusb_clk_enable(tegra); 1816 if (err) { 1817 dev_err(tegra->dev, "failed to enable clocks: %d\n", err); 1818 goto put_hcd; 1819 } 1820 1821 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); 1822 if (err) { 1823 dev_err(tegra->dev, "failed to enable regulators: %d\n", err); 1824 goto disable_clk; 1825 } 1826 1827 err = tegra_xusb_phy_enable(tegra); 1828 if (err < 0) { 1829 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err); 1830 goto disable_regulator; 1831 } 1832 1833 /* 1834 * The XUSB Falcon microcontroller can only address 40 bits, so set 1835 * the DMA mask accordingly. 1836 */ 1837 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40)); 1838 if (err < 0) { 1839 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 1840 goto disable_phy; 1841 } 1842 1843 if (tegra->soc->firmware) { 1844 err = tegra_xusb_request_firmware(tegra); 1845 if (err < 0) { 1846 dev_err(&pdev->dev, 1847 "failed to request firmware: %d\n", err); 1848 goto disable_phy; 1849 } 1850 } 1851 1852 err = tegra_xusb_unpowergate_partitions(tegra); 1853 if (err) 1854 goto free_firmware; 1855 1856 tegra_xusb_config(tegra); 1857 1858 err = tegra_xusb_load_firmware(tegra); 1859 if (err < 0) { 1860 dev_err(&pdev->dev, "failed to load firmware: %d\n", err); 1861 goto powergate; 1862 } 1863 1864 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); 1865 if (err < 0) { 1866 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); 1867 goto powergate; 1868 } 1869 1870 device_wakeup_enable(tegra->hcd->self.controller); 1871 1872 xhci = hcd_to_xhci(tegra->hcd); 1873 1874 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, 1875 &pdev->dev, 1876 dev_name(&pdev->dev), 1877 tegra->hcd); 1878 if (!xhci->shared_hcd) { 1879 dev_err(&pdev->dev, "failed to create shared HCD\n"); 1880 err = -ENOMEM; 1881 goto remove_usb2; 1882 } 1883 1884 if (HCC_MAX_PSA(xhci->hcc_params) >= 4) 1885 xhci->shared_hcd->can_do_streams = 1; 1886 1887 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); 1888 if (err < 0) { 1889 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); 1890 goto put_usb3; 1891 } 1892 1893 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, 1894 tegra_xusb_mbox_irq, 1895 tegra_xusb_mbox_thread, 0, 1896 dev_name(&pdev->dev), tegra); 1897 if (err < 0) { 1898 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 1899 goto remove_usb3; 1900 } 1901 1902 if (tegra->padctl_irq) { 1903 err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq, 1904 NULL, tegra_xusb_padctl_irq, 1905 IRQF_ONESHOT, dev_name(&pdev->dev), 1906 tegra); 1907 if (err < 0) { 1908 dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err); 1909 goto remove_usb3; 1910 } 1911 } 1912 1913 err = tegra_xusb_enable_firmware_messages(tegra); 1914 if (err < 0) { 1915 dev_err(&pdev->dev, "failed to enable messages: %d\n", err); 1916 goto remove_usb3; 1917 } 1918 1919 err = tegra_xusb_init_usb_phy(tegra); 1920 if (err < 0) { 1921 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err); 1922 goto remove_usb3; 1923 } 1924 1925 /* Enable wake for both USB 2.0 and USB 3.0 roothubs */ 1926 device_init_wakeup(&tegra->hcd->self.root_hub->dev, true); 1927 device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true); 1928 1929 pm_runtime_use_autosuspend(tegra->dev); 1930 pm_runtime_set_autosuspend_delay(tegra->dev, 2000); 1931 pm_runtime_mark_last_busy(tegra->dev); 1932 pm_runtime_set_active(tegra->dev); 1933 1934 if (tegra->padctl_irq) { 1935 device_init_wakeup(tegra->dev, true); 1936 pm_runtime_enable(tegra->dev); 1937 } 1938 1939 return 0; 1940 1941remove_usb3: 1942 usb_remove_hcd(xhci->shared_hcd); 1943put_usb3: 1944 usb_put_hcd(xhci->shared_hcd); 1945remove_usb2: 1946 usb_remove_hcd(tegra->hcd); 1947powergate: 1948 tegra_xusb_powergate_partitions(tegra); 1949free_firmware: 1950 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1951 tegra->fw.phys); 1952disable_phy: 1953 tegra_xusb_phy_disable(tegra); 1954disable_regulator: 1955 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 1956disable_clk: 1957 tegra_xusb_clk_disable(tegra); 1958put_hcd: 1959 usb_put_hcd(tegra->hcd); 1960put_powerdomains: 1961 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1962put_padctl: 1963 of_node_put(np); 1964 tegra_xusb_padctl_put(tegra->padctl); 1965 return err; 1966} 1967 1968static void tegra_xusb_disable(struct tegra_xusb *tegra) 1969{ 1970 tegra_xusb_powergate_partitions(tegra); 1971 tegra_xusb_powerdomain_remove(tegra->dev, tegra); 1972 tegra_xusb_phy_disable(tegra); 1973 tegra_xusb_clk_disable(tegra); 1974 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 1975} 1976 1977static void tegra_xusb_remove(struct platform_device *pdev) 1978{ 1979 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 1980 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1981 1982 tegra_xusb_deinit_usb_phy(tegra); 1983 1984 pm_runtime_get_sync(&pdev->dev); 1985 usb_remove_hcd(xhci->shared_hcd); 1986 usb_put_hcd(xhci->shared_hcd); 1987 xhci->shared_hcd = NULL; 1988 usb_remove_hcd(tegra->hcd); 1989 usb_put_hcd(tegra->hcd); 1990 1991 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1992 tegra->fw.phys); 1993 1994 if (tegra->padctl_irq) 1995 pm_runtime_disable(&pdev->dev); 1996 1997 pm_runtime_put(&pdev->dev); 1998 1999 tegra_xusb_disable(tegra); 2000 tegra_xusb_padctl_put(tegra->padctl); 2001} 2002 2003static void tegra_xusb_shutdown(struct platform_device *pdev) 2004{ 2005 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 2006 2007 pm_runtime_get_sync(&pdev->dev); 2008 disable_irq(tegra->xhci_irq); 2009 xhci_shutdown(tegra->hcd); 2010 tegra_xusb_disable(tegra); 2011} 2012 2013static bool xhci_hub_ports_suspended(struct xhci_hub *hub) 2014{ 2015 struct device *dev = hub->hcd->self.controller; 2016 bool status = true; 2017 unsigned int i; 2018 u32 value; 2019 2020 for (i = 0; i < hub->num_ports; i++) { 2021 value = xhci_portsc_readl(hub->ports[i]); 2022 if ((value & PORT_PE) == 0) 2023 continue; 2024 2025 if ((value & PORT_PLS_MASK) != XDEV_U3) { 2026 dev_info(dev, "%u-%u isn't suspended: %#010x\n", 2027 hub->hcd->self.busnum, i + 1, value); 2028 status = false; 2029 } 2030 } 2031 2032 return status; 2033} 2034 2035static int tegra_xusb_check_ports(struct tegra_xusb *tegra) 2036{ 2037 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 2038 struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state; 2039 unsigned long flags; 2040 int err = 0; 2041 2042 if (bus_state->bus_suspended) { 2043 /* xusb_hub_suspend() has just directed one or more USB2 port(s) 2044 * to U3 state, it takes 3ms to enter U3. 2045 */ 2046 usleep_range(3000, 4000); 2047 } 2048 2049 spin_lock_irqsave(&xhci->lock, flags); 2050 2051 if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) || 2052 !xhci_hub_ports_suspended(&xhci->usb3_rhub)) 2053 err = -EBUSY; 2054 2055 spin_unlock_irqrestore(&xhci->lock, flags); 2056 2057 return err; 2058} 2059 2060static void tegra_xusb_save_context(struct tegra_xusb *tegra) 2061{ 2062 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 2063 struct tegra_xusb_context *ctx = &tegra->context; 2064 unsigned int i; 2065 2066 if (soc->ipfs.num_offsets > 0) { 2067 for (i = 0; i < soc->ipfs.num_offsets; i++) 2068 ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]); 2069 } 2070 2071 if (soc->fpci.num_offsets > 0) { 2072 for (i = 0; i < soc->fpci.num_offsets; i++) 2073 ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]); 2074 } 2075} 2076 2077static void tegra_xusb_restore_context(struct tegra_xusb *tegra) 2078{ 2079 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 2080 struct tegra_xusb_context *ctx = &tegra->context; 2081 unsigned int i; 2082 2083 if (soc->fpci.num_offsets > 0) { 2084 for (i = 0; i < soc->fpci.num_offsets; i++) 2085 fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]); 2086 } 2087 2088 if (soc->ipfs.num_offsets > 0) { 2089 for (i = 0; i < soc->ipfs.num_offsets; i++) 2090 ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]); 2091 } 2092} 2093 2094static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc) 2095{ 2096 if (DEV_LOWSPEED(portsc)) 2097 return USB_SPEED_LOW; 2098 2099 if (DEV_HIGHSPEED(portsc)) 2100 return USB_SPEED_HIGH; 2101 2102 if (DEV_FULLSPEED(portsc)) 2103 return USB_SPEED_FULL; 2104 2105 if (DEV_SUPERSPEED_ANY(portsc)) 2106 return USB_SPEED_SUPER; 2107 2108 return USB_SPEED_UNKNOWN; 2109} 2110 2111static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra) 2112{ 2113 struct tegra_xusb_padctl *padctl = tegra->padctl; 2114 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 2115 enum usb_device_speed speed; 2116 struct phy *phy; 2117 unsigned int index, offset; 2118 unsigned int i, j, k; 2119 struct xhci_hub *rhub; 2120 u32 portsc; 2121 2122 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 2123 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0) 2124 rhub = &xhci->usb3_rhub; 2125 else 2126 rhub = &xhci->usb2_rhub; 2127 2128 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0) 2129 offset = tegra->soc->ports.usb2.count; 2130 else 2131 offset = 0; 2132 2133 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 2134 phy = tegra->phys[k++]; 2135 2136 if (!phy) 2137 continue; 2138 2139 index = j + offset; 2140 2141 if (index >= rhub->num_ports) 2142 continue; 2143 2144 if (!is_host_mode_phy(tegra, i, j)) 2145 continue; 2146 2147 portsc = xhci_portsc_readl(rhub->ports[index]); 2148 speed = tegra_xhci_portsc_to_speed(tegra, portsc); 2149 tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed); 2150 tegra_xusb_padctl_enable_phy_wake(padctl, phy); 2151 } 2152 } 2153} 2154 2155static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra) 2156{ 2157 struct tegra_xusb_padctl *padctl = tegra->padctl; 2158 unsigned int i; 2159 2160 for (i = 0; i < tegra->num_usb_phys; i++) { 2161 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i); 2162 2163 if (!phy) 2164 continue; 2165 2166 if (tegra_xusb_padctl_remote_wake_detected(padctl, phy)) 2167 tegra_phy_xusb_utmi_pad_power_on(phy); 2168 } 2169 2170 for (i = 0; i < tegra->num_phys; i++) { 2171 if (!tegra->phys[i]) 2172 continue; 2173 2174 if (tegra_xusb_padctl_remote_wake_detected(padctl, tegra->phys[i])) 2175 dev_dbg(tegra->dev, "%pOF remote wake detected\n", 2176 tegra->phys[i]->dev.of_node); 2177 2178 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]); 2179 } 2180} 2181 2182static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra) 2183{ 2184 struct tegra_xusb_padctl *padctl = tegra->padctl; 2185 unsigned int i; 2186 2187 for (i = 0; i < tegra->num_phys; i++) { 2188 if (!tegra->phys[i]) 2189 continue; 2190 2191 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]); 2192 } 2193} 2194 2195static void tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb *tegra) 2196{ 2197 unsigned int i, index_to_usb2; 2198 struct phy *phy; 2199 2200 for (i = 0; i < tegra->soc->num_types; i++) { 2201 if (strcmp(tegra->soc->phy_types[i].name, "usb2") == 0) 2202 index_to_usb2 = i; 2203 } 2204 2205 for (i = 0; i < tegra->num_usb_phys; i++) { 2206 if (!is_host_mode_phy(tegra, index_to_usb2, i)) 2207 continue; 2208 2209 phy = tegra_xusb_get_phy(tegra, "usb2", i); 2210 if (tegra->lp0_utmi_pad_mask & BIT(i)) 2211 tegra_phy_xusb_utmi_pad_power_on(phy); 2212 else 2213 tegra_phy_xusb_utmi_pad_power_down(phy); 2214 } 2215} 2216 2217static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool is_auto_resume) 2218{ 2219 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 2220 struct device *dev = tegra->dev; 2221 bool wakeup = is_auto_resume ? true : device_may_wakeup(dev); 2222 unsigned int i; 2223 int err; 2224 u32 usbcmd; 2225 u32 portsc; 2226 2227 dev_dbg(dev, "entering ELPG\n"); 2228 2229 usbcmd = readl(&xhci->op_regs->command); 2230 usbcmd &= ~CMD_EIE; 2231 writel(usbcmd, &xhci->op_regs->command); 2232 2233 err = tegra_xusb_check_ports(tegra); 2234 if (err < 0) { 2235 dev_err(tegra->dev, "not all ports suspended: %d\n", err); 2236 goto out; 2237 } 2238 2239 for (i = 0; i < xhci->usb2_rhub.num_ports; i++) { 2240 if (!xhci->usb2_rhub.ports[i]) 2241 continue; 2242 portsc = xhci_portsc_readl(xhci->usb2_rhub.ports[i]); 2243 tegra->lp0_utmi_pad_mask &= ~BIT(i); 2244 if (((portsc & PORT_PLS_MASK) == XDEV_U3) || ((portsc & DEV_SPEED_MASK) == XDEV_FS)) 2245 tegra->lp0_utmi_pad_mask |= BIT(i); 2246 } 2247 2248 err = xhci_suspend(xhci, wakeup); 2249 if (err < 0) { 2250 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err); 2251 goto out; 2252 } 2253 2254 tegra_xusb_save_context(tegra); 2255 2256 if (wakeup) 2257 tegra_xhci_enable_phy_sleepwalk_wake(tegra); 2258 2259 tegra_xusb_powergate_partitions(tegra); 2260 2261 for (i = 0; i < tegra->num_phys; i++) { 2262 if (!tegra->phys[i]) 2263 continue; 2264 2265 phy_power_off(tegra->phys[i]); 2266 if (!wakeup) 2267 phy_exit(tegra->phys[i]); 2268 } 2269 2270 tegra_xusb_clk_disable(tegra); 2271 2272out: 2273 if (!err) 2274 dev_dbg(tegra->dev, "entering ELPG done\n"); 2275 else { 2276 usbcmd = readl(&xhci->op_regs->command); 2277 usbcmd |= CMD_EIE; 2278 writel(usbcmd, &xhci->op_regs->command); 2279 2280 dev_dbg(tegra->dev, "entering ELPG failed\n"); 2281 pm_runtime_mark_last_busy(tegra->dev); 2282 } 2283 2284 return err; 2285} 2286 2287static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool is_auto_resume) 2288{ 2289 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 2290 struct device *dev = tegra->dev; 2291 bool wakeup = is_auto_resume ? true : device_may_wakeup(dev); 2292 unsigned int i; 2293 u32 usbcmd; 2294 int err; 2295 2296 dev_dbg(dev, "exiting ELPG\n"); 2297 pm_runtime_mark_last_busy(tegra->dev); 2298 2299 err = tegra_xusb_clk_enable(tegra); 2300 if (err < 0) { 2301 dev_err(tegra->dev, "failed to enable clocks: %d\n", err); 2302 goto out; 2303 } 2304 2305 err = tegra_xusb_unpowergate_partitions(tegra); 2306 if (err) 2307 goto disable_clks; 2308 2309 if (wakeup) 2310 tegra_xhci_disable_phy_wake(tegra); 2311 2312 for (i = 0; i < tegra->num_phys; i++) { 2313 if (!tegra->phys[i]) 2314 continue; 2315 2316 if (!wakeup) 2317 phy_init(tegra->phys[i]); 2318 2319 phy_power_on(tegra->phys[i]); 2320 } 2321 if (tegra->suspended) 2322 tegra_xhci_program_utmi_power_lp0_exit(tegra); 2323 2324 tegra_xusb_config(tegra); 2325 tegra_xusb_restore_context(tegra); 2326 2327 err = tegra_xusb_load_firmware(tegra); 2328 if (err < 0) { 2329 dev_err(tegra->dev, "failed to load firmware: %d\n", err); 2330 goto disable_phy; 2331 } 2332 2333 err = __tegra_xusb_enable_firmware_messages(tegra); 2334 if (err < 0) { 2335 dev_err(tegra->dev, "failed to enable messages: %d\n", err); 2336 goto disable_phy; 2337 } 2338 2339 if (wakeup) 2340 tegra_xhci_disable_phy_sleepwalk(tegra); 2341 2342 err = xhci_resume(xhci, false, is_auto_resume); 2343 if (err < 0) { 2344 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err); 2345 goto disable_phy; 2346 } 2347 2348 usbcmd = readl(&xhci->op_regs->command); 2349 usbcmd |= CMD_EIE; 2350 writel(usbcmd, &xhci->op_regs->command); 2351 2352 goto out; 2353 2354disable_phy: 2355 for (i = 0; i < tegra->num_phys; i++) { 2356 if (!tegra->phys[i]) 2357 continue; 2358 2359 phy_power_off(tegra->phys[i]); 2360 if (!wakeup) 2361 phy_exit(tegra->phys[i]); 2362 } 2363 tegra_xusb_powergate_partitions(tegra); 2364disable_clks: 2365 tegra_xusb_clk_disable(tegra); 2366out: 2367 if (!err) 2368 dev_dbg(dev, "exiting ELPG done\n"); 2369 else 2370 dev_dbg(dev, "exiting ELPG failed\n"); 2371 2372 return err; 2373} 2374 2375static __maybe_unused int tegra_xusb_suspend(struct device *dev) 2376{ 2377 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2378 int err; 2379 2380 synchronize_irq(tegra->mbox_irq); 2381 2382 mutex_lock(&tegra->lock); 2383 2384 if (pm_runtime_suspended(dev)) { 2385 err = tegra_xusb_exit_elpg(tegra, true); 2386 if (err < 0) 2387 goto out; 2388 } 2389 2390 err = tegra_xusb_enter_elpg(tegra, false); 2391 if (err < 0) { 2392 if (pm_runtime_suspended(dev)) { 2393 pm_runtime_disable(dev); 2394 pm_runtime_set_active(dev); 2395 pm_runtime_enable(dev); 2396 } 2397 2398 goto out; 2399 } 2400 2401out: 2402 if (!err) { 2403 tegra->suspended = true; 2404 pm_runtime_disable(dev); 2405 2406 if (device_may_wakeup(dev)) { 2407 unsigned int i; 2408 2409 if (enable_irq_wake(tegra->padctl_irq)) 2410 dev_err(dev, "failed to enable padctl wakes\n"); 2411 2412 for (i = 0; i < tegra->num_wakes; i++) 2413 enable_irq_wake(tegra->wake_irqs[i]); 2414 } 2415 } 2416 2417 mutex_unlock(&tegra->lock); 2418 2419 return err; 2420} 2421 2422static __maybe_unused int tegra_xusb_resume(struct device *dev) 2423{ 2424 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2425 int err; 2426 2427 mutex_lock(&tegra->lock); 2428 2429 if (!tegra->suspended) { 2430 mutex_unlock(&tegra->lock); 2431 return 0; 2432 } 2433 2434 err = tegra_xusb_exit_elpg(tegra, false); 2435 if (err < 0) { 2436 mutex_unlock(&tegra->lock); 2437 return err; 2438 } 2439 2440 if (device_may_wakeup(dev)) { 2441 unsigned int i; 2442 2443 if (disable_irq_wake(tegra->padctl_irq)) 2444 dev_err(dev, "failed to disable padctl wakes\n"); 2445 2446 for (i = 0; i < tegra->num_wakes; i++) 2447 disable_irq_wake(tegra->wake_irqs[i]); 2448 } 2449 tegra->suspended = false; 2450 mutex_unlock(&tegra->lock); 2451 2452 pm_runtime_set_active(dev); 2453 pm_runtime_enable(dev); 2454 2455 return 0; 2456} 2457 2458static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev) 2459{ 2460 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2461 int ret; 2462 2463 synchronize_irq(tegra->mbox_irq); 2464 mutex_lock(&tegra->lock); 2465 ret = tegra_xusb_enter_elpg(tegra, true); 2466 mutex_unlock(&tegra->lock); 2467 2468 return ret; 2469} 2470 2471static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev) 2472{ 2473 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2474 int err; 2475 2476 mutex_lock(&tegra->lock); 2477 err = tegra_xusb_exit_elpg(tegra, true); 2478 mutex_unlock(&tegra->lock); 2479 2480 return err; 2481} 2482 2483static const struct dev_pm_ops tegra_xusb_pm_ops = { 2484 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend, 2485 tegra_xusb_runtime_resume, NULL) 2486 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) 2487}; 2488 2489static const char * const tegra124_supply_names[] = { 2490 "avddio-pex", 2491 "dvddio-pex", 2492 "avdd-usb", 2493 "hvdd-usb-ss", 2494}; 2495 2496static const struct tegra_xusb_phy_type tegra124_phy_types[] = { 2497 { .name = "usb3", .num = 2, }, 2498 { .name = "usb2", .num = 3, }, 2499 { .name = "hsic", .num = 2, }, 2500}; 2501 2502static const unsigned int tegra124_xusb_context_ipfs[] = { 2503 IPFS_XUSB_HOST_MSI_BAR_SZ_0, 2504 IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0, 2505 IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0, 2506 IPFS_XUSB_HOST_MSI_VEC0_0, 2507 IPFS_XUSB_HOST_MSI_EN_VEC0_0, 2508 IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0, 2509 IPFS_XUSB_HOST_INTR_MASK_0, 2510 IPFS_XUSB_HOST_INTR_ENABLE_0, 2511 IPFS_XUSB_HOST_UFPCI_CONFIG_0, 2512 IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0, 2513 IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0, 2514}; 2515 2516static const unsigned int tegra124_xusb_context_fpci[] = { 2517 XUSB_CFG_ARU_CONTEXT_HS_PLS, 2518 XUSB_CFG_ARU_CONTEXT_FS_PLS, 2519 XUSB_CFG_ARU_CONTEXT_HSFS_SPEED, 2520 XUSB_CFG_ARU_CONTEXT_HSFS_PP, 2521 XUSB_CFG_ARU_CONTEXT, 2522 XUSB_CFG_AXI_CFG, 2523 XUSB_CFG_24, 2524 XUSB_CFG_16, 2525}; 2526 2527static const struct tegra_xusb_context_soc tegra124_xusb_context = { 2528 .ipfs = { 2529 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs), 2530 .offsets = tegra124_xusb_context_ipfs, 2531 }, 2532 .fpci = { 2533 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), 2534 .offsets = tegra124_xusb_context_fpci, 2535 }, 2536}; 2537 2538static const struct tegra_xusb_soc_ops tegra124_ops = { 2539 .mbox_reg_readl = &fpci_readl, 2540 .mbox_reg_writel = &fpci_writel, 2541 .csb_reg_readl = &fpci_csb_readl, 2542 .csb_reg_writel = &fpci_csb_writel, 2543}; 2544 2545static const struct tegra_xusb_soc tegra124_soc = { 2546 .firmware = "nvidia/tegra124/xusb.bin", 2547 .supply_names = tegra124_supply_names, 2548 .num_supplies = ARRAY_SIZE(tegra124_supply_names), 2549 .phy_types = tegra124_phy_types, 2550 .num_types = ARRAY_SIZE(tegra124_phy_types), 2551 .context = &tegra124_xusb_context, 2552 .ports = { 2553 .usb2 = { .offset = 4, .count = 4, }, 2554 .hsic = { .offset = 6, .count = 2, }, 2555 .usb3 = { .offset = 0, .count = 2, }, 2556 }, 2557 .scale_ss_clock = true, 2558 .has_ipfs = true, 2559 .otg_reset_sspi = false, 2560 .ops = &tegra124_ops, 2561 .mbox = { 2562 .cmd = 0xe4, 2563 .data_in = 0xe8, 2564 .data_out = 0xec, 2565 .owner = 0xf0, 2566 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2567 }, 2568}; 2569MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); 2570 2571static const char * const tegra210_supply_names[] = { 2572 "dvddio-pex", 2573 "hvddio-pex", 2574 "avdd-usb", 2575}; 2576 2577static const struct tegra_xusb_phy_type tegra210_phy_types[] = { 2578 { .name = "usb3", .num = 4, }, 2579 { .name = "usb2", .num = 4, }, 2580 { .name = "hsic", .num = 1, }, 2581}; 2582 2583static const struct tegra_xusb_soc tegra210_soc = { 2584 .firmware = "nvidia/tegra210/xusb.bin", 2585 .supply_names = tegra210_supply_names, 2586 .num_supplies = ARRAY_SIZE(tegra210_supply_names), 2587 .phy_types = tegra210_phy_types, 2588 .num_types = ARRAY_SIZE(tegra210_phy_types), 2589 .context = &tegra124_xusb_context, 2590 .ports = { 2591 .usb2 = { .offset = 4, .count = 4, }, 2592 .hsic = { .offset = 8, .count = 1, }, 2593 .usb3 = { .offset = 0, .count = 4, }, 2594 }, 2595 .scale_ss_clock = false, 2596 .has_ipfs = true, 2597 .otg_reset_sspi = true, 2598 .ops = &tegra124_ops, 2599 .mbox = { 2600 .cmd = 0xe4, 2601 .data_in = 0xe8, 2602 .data_out = 0xec, 2603 .owner = 0xf0, 2604 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2605 }, 2606}; 2607MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); 2608 2609static const char * const tegra186_supply_names[] = { 2610}; 2611MODULE_FIRMWARE("nvidia/tegra186/xusb.bin"); 2612 2613static const struct tegra_xusb_phy_type tegra186_phy_types[] = { 2614 { .name = "usb3", .num = 3, }, 2615 { .name = "usb2", .num = 3, }, 2616 { .name = "hsic", .num = 1, }, 2617}; 2618 2619static const struct tegra_xusb_context_soc tegra186_xusb_context = { 2620 .fpci = { 2621 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), 2622 .offsets = tegra124_xusb_context_fpci, 2623 }, 2624}; 2625 2626static const struct tegra_xusb_soc tegra186_soc = { 2627 .firmware = "nvidia/tegra186/xusb.bin", 2628 .supply_names = tegra186_supply_names, 2629 .num_supplies = ARRAY_SIZE(tegra186_supply_names), 2630 .phy_types = tegra186_phy_types, 2631 .num_types = ARRAY_SIZE(tegra186_phy_types), 2632 .context = &tegra186_xusb_context, 2633 .ports = { 2634 .usb3 = { .offset = 0, .count = 3, }, 2635 .usb2 = { .offset = 3, .count = 3, }, 2636 .hsic = { .offset = 6, .count = 1, }, 2637 }, 2638 .scale_ss_clock = false, 2639 .has_ipfs = false, 2640 .otg_reset_sspi = false, 2641 .ops = &tegra124_ops, 2642 .mbox = { 2643 .cmd = 0xe4, 2644 .data_in = 0xe8, 2645 .data_out = 0xec, 2646 .owner = 0xf0, 2647 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2648 }, 2649 .lpm_support = true, 2650}; 2651 2652static const char * const tegra194_supply_names[] = { 2653}; 2654 2655static const struct tegra_xusb_phy_type tegra194_phy_types[] = { 2656 { .name = "usb3", .num = 4, }, 2657 { .name = "usb2", .num = 4, }, 2658}; 2659 2660static const struct tegra_xusb_soc tegra194_soc = { 2661 .firmware = "nvidia/tegra194/xusb.bin", 2662 .supply_names = tegra194_supply_names, 2663 .num_supplies = ARRAY_SIZE(tegra194_supply_names), 2664 .phy_types = tegra194_phy_types, 2665 .num_types = ARRAY_SIZE(tegra194_phy_types), 2666 .context = &tegra186_xusb_context, 2667 .ports = { 2668 .usb3 = { .offset = 0, .count = 4, }, 2669 .usb2 = { .offset = 4, .count = 4, }, 2670 }, 2671 .scale_ss_clock = false, 2672 .has_ipfs = false, 2673 .otg_reset_sspi = false, 2674 .ops = &tegra124_ops, 2675 .mbox = { 2676 .cmd = 0x68, 2677 .data_in = 0x6c, 2678 .data_out = 0x70, 2679 .owner = 0x74, 2680 .smi_intr = XUSB_CFG_ARU_SMI_INTR, 2681 }, 2682 .lpm_support = true, 2683}; 2684MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); 2685 2686static const struct tegra_xusb_soc_ops tegra234_ops = { 2687 .mbox_reg_readl = &bar2_readl, 2688 .mbox_reg_writel = &bar2_writel, 2689 .csb_reg_readl = &bar2_csb_readl, 2690 .csb_reg_writel = &bar2_csb_writel, 2691}; 2692 2693static const struct tegra_xusb_soc tegra234_soc = { 2694 .supply_names = tegra194_supply_names, 2695 .num_supplies = ARRAY_SIZE(tegra194_supply_names), 2696 .phy_types = tegra194_phy_types, 2697 .num_types = ARRAY_SIZE(tegra194_phy_types), 2698 .max_num_wakes = 7, 2699 .context = &tegra186_xusb_context, 2700 .ports = { 2701 .usb3 = { .offset = 0, .count = 4, }, 2702 .usb2 = { .offset = 4, .count = 4, }, 2703 }, 2704 .scale_ss_clock = false, 2705 .has_ipfs = false, 2706 .otg_reset_sspi = false, 2707 .ops = &tegra234_ops, 2708 .mbox = { 2709 .cmd = XUSB_BAR2_ARU_MBOX_CMD, 2710 .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN, 2711 .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT, 2712 .owner = XUSB_BAR2_ARU_MBOX_OWNER, 2713 .smi_intr = XUSB_BAR2_ARU_SMI_INTR, 2714 }, 2715 .lpm_support = true, 2716 .has_bar2 = true, 2717}; 2718 2719static const struct of_device_id tegra_xusb_of_match[] = { 2720 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, 2721 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, 2722 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, 2723 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, 2724 { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc }, 2725 { }, 2726}; 2727MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); 2728 2729static struct platform_driver tegra_xusb_driver = { 2730 .probe = tegra_xusb_probe, 2731 .remove = tegra_xusb_remove, 2732 .shutdown = tegra_xusb_shutdown, 2733 .driver = { 2734 .name = "tegra-xusb", 2735 .pm = &tegra_xusb_pm_ops, 2736 .of_match_table = tegra_xusb_of_match, 2737 }, 2738}; 2739 2740static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) 2741{ 2742 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2743 2744 if (tegra && tegra->soc->lpm_support) 2745 xhci->quirks |= XHCI_LPM_SUPPORT; 2746} 2747 2748static int tegra_xhci_setup(struct usb_hcd *hcd) 2749{ 2750 return xhci_gen_setup(hcd, tegra_xhci_quirks); 2751} 2752 2753static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req, u16 value, u16 index, 2754 char *buf, u16 length) 2755{ 2756 struct tegra_xusb *tegra = dev_get_drvdata(hcd->self.controller); 2757 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2758 struct xhci_hub *rhub; 2759 struct xhci_bus_state *bus_state; 2760 int port = (index & 0xff) - 1; 2761 unsigned int i; 2762 struct xhci_port **ports; 2763 u32 portsc; 2764 int ret; 2765 struct phy *phy; 2766 2767 rhub = &xhci->usb2_rhub; 2768 bus_state = &rhub->bus_state; 2769 if (bus_state->resuming_ports && hcd->speed == HCD_USB2) { 2770 ports = rhub->ports; 2771 i = rhub->num_ports; 2772 while (i--) { 2773 if (!test_bit(i, &bus_state->resuming_ports)) 2774 continue; 2775 portsc = xhci_portsc_readl(ports[i]); 2776 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME) 2777 tegra_phy_xusb_utmi_pad_power_on( 2778 tegra_xusb_get_phy(tegra, "usb2", (int) i)); 2779 } 2780 } 2781 2782 if (hcd->speed == HCD_USB2) { 2783 phy = tegra_xusb_get_phy(tegra, "usb2", port); 2784 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) { 2785 if (!index || index > rhub->num_ports) 2786 return -EPIPE; 2787 tegra_phy_xusb_utmi_pad_power_on(phy); 2788 } 2789 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_RESET)) { 2790 if (!index || index > rhub->num_ports) 2791 return -EPIPE; 2792 ports = rhub->ports; 2793 portsc = xhci_portsc_readl(ports[port]); 2794 if (portsc & PORT_CONNECT) 2795 tegra_phy_xusb_utmi_pad_power_on(phy); 2796 } 2797 } 2798 2799 ret = xhci_hub_control(hcd, type_req, value, index, buf, length); 2800 if (ret < 0) 2801 return ret; 2802 2803 if (hcd->speed == HCD_USB2) { 2804 /* Use phy where we set previously */ 2805 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) 2806 /* We don't suspend the PAD while HNP role swap happens on the OTG port */ 2807 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable)) 2808 tegra_phy_xusb_utmi_pad_power_down(phy); 2809 2810 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_C_CONNECTION)) { 2811 ports = rhub->ports; 2812 portsc = xhci_portsc_readl(ports[port]); 2813 if (!(portsc & PORT_CONNECT)) { 2814 /* We don't suspend the PAD while HNP role swap happens on the OTG 2815 * port 2816 */ 2817 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable)) 2818 tegra_phy_xusb_utmi_pad_power_down(phy); 2819 } 2820 } 2821 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_TEST)) 2822 tegra_phy_xusb_utmi_pad_power_on(phy); 2823 } 2824 2825 return ret; 2826} 2827 2828static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { 2829 .reset = tegra_xhci_setup, 2830 .hub_control = tegra_xhci_hub_control, 2831}; 2832 2833static int __init tegra_xusb_init(void) 2834{ 2835 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); 2836 2837 return platform_driver_register(&tegra_xusb_driver); 2838} 2839module_init(tegra_xusb_init); 2840 2841static void __exit tegra_xusb_exit(void) 2842{ 2843 platform_driver_unregister(&tegra_xusb_driver); 2844} 2845module_exit(tegra_xusb_exit); 2846 2847MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 2848MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); 2849MODULE_LICENSE("GPL v2");
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