xhci-ring.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * xHCI host controller driver
   4 *
   5 * Copyright (C) 2008 Intel Corp.
   6 *
   7 * Author: Sarah Sharp
   8 * Some code borrowed from the Linux EHCI driver.
   9 */
  10
  11/*
  12 * Ring initialization rules:
  13 * 1. Each segment is initialized to zero, except for link TRBs.
  14 * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  15 *    Consumer Cycle State (CCS), depending on ring function.
  16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  17 *
  18 * Ring behavior rules:
  19 * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  20 *    least one free TRB in the ring.  This is useful if you want to turn that
  21 *    into a link TRB and expand the ring.
  22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  23 *    link TRB, then load the pointer with the address in the link TRB.  If the
  24 *    link TRB had its toggle bit set, you may need to update the ring cycle
  25 *    state (see cycle bit rules).  You may have to do this multiple times
  26 *    until you reach a non-link TRB.
  27 * 3. A ring is full if enqueue++ (for the definition of increment above)
  28 *    equals the dequeue pointer.
  29 *
  30 * Cycle bit rules:
  31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  32 *    in a link TRB, it must toggle the ring cycle state.
  33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  34 *    in a link TRB, it must toggle the ring cycle state.
  35 *
  36 * Producer rules:
  37 * 1. Check if ring is full before you enqueue.
  38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  39 *    Update enqueue pointer between each write (which may update the ring
  40 *    cycle state).
  41 * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  42 *    and endpoint rings.  If HC is the producer for the event ring,
  43 *    and it generates an interrupt according to interrupt modulation rules.
  44 *
  45 * Consumer rules:
  46 * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  47 *    the TRB is owned by the consumer.
  48 * 2. Update dequeue pointer (which may update the ring cycle state) and
  49 *    continue processing TRBs until you reach a TRB which is not owned by you.
  50 * 3. Notify the producer.  SW is the consumer for the event ring, and it
  51 *   updates event ring dequeue pointer.  HC is the consumer for the command and
  52 *   endpoint rings; it generates events on the event ring for these.
  53 */
  54
  55#include <linux/jiffies.h>
  56#include <linux/scatterlist.h>
  57#include <linux/slab.h>
  58#include <linux/string_choices.h>
  59#include <linux/dma-mapping.h>
  60#include "xhci.h"
  61#include "xhci-trace.h"
  62
  63static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
  64			 u32 field1, u32 field2,
  65			 u32 field3, u32 field4, bool command_must_succeed);
  66
  67/*
  68 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  69 * address of the TRB.
  70 */
  71dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  72		union xhci_trb *trb)
  73{
  74	unsigned long segment_offset;
  75
  76	if (!seg || !trb || trb < seg->trbs)
  77		return 0;
  78	/* offset in TRBs */
  79	segment_offset = trb - seg->trbs;
  80	if (segment_offset >= TRBS_PER_SEGMENT)
  81		return 0;
  82	return seg->dma + (segment_offset * sizeof(*trb));
  83}
  84
  85static union xhci_trb *xhci_dma_to_trb(struct xhci_segment *start_seg,
  86				       dma_addr_t dma,
  87				       struct xhci_segment **match_seg)
  88{
  89	struct xhci_segment *seg;
  90
  91	xhci_for_each_ring_seg(start_seg, seg) {
  92		if (in_range(dma, seg->dma, TRB_SEGMENT_SIZE)) {
  93			if (match_seg)
  94				*match_seg = seg;
  95			return &seg->trbs[(dma - seg->dma) / sizeof(union xhci_trb)];
  96		}
  97	}
  98
  99	return NULL;
 100}
 101
 102static bool trb_is_noop(union xhci_trb *trb)
 103{
 104	return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
 105}
 106
 107static bool trb_is_link(union xhci_trb *trb)
 108{
 109	return TRB_TYPE_LINK_LE32(trb->link.control);
 110}
 111
 112static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
 113{
 114	return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
 115}
 116
 117static bool last_trb_on_ring(struct xhci_ring *ring,
 118			struct xhci_segment *seg, union xhci_trb *trb)
 119{
 120	return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
 121}
 122
 123static bool link_trb_toggles_cycle(union xhci_trb *trb)
 124{
 125	return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 126}
 127
 128static bool last_td_in_urb(struct xhci_td *td)
 129{
 130	struct urb_priv *urb_priv = td->urb->hcpriv;
 131
 132	return urb_priv->num_tds_done == urb_priv->num_tds;
 133}
 134
 135static bool unhandled_event_trb(struct xhci_ring *ring)
 136{
 137	return ((le32_to_cpu(ring->dequeue->event_cmd.flags) & TRB_CYCLE) ==
 138		ring->cycle_state);
 139}
 140
 141static void inc_td_cnt(struct urb *urb)
 142{
 143	struct urb_priv *urb_priv = urb->hcpriv;
 144
 145	urb_priv->num_tds_done++;
 146}
 147
 148static void trb_to_noop(union xhci_trb *trb, u32 noop_type, bool unchain_links)
 149{
 150	if (trb_is_link(trb)) {
 151		if (unchain_links)
 152			trb->link.control &= cpu_to_le32(~TRB_CHAIN);
 153	} else {
 154		trb->generic.field[0] = 0;
 155		trb->generic.field[1] = 0;
 156		trb->generic.field[2] = 0;
 157		/* Preserve only the cycle bit of this TRB */
 158		trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 159		trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
 160	}
 161}
 162
 163static unsigned int trb_to_pos(struct xhci_segment *seg, union xhci_trb *trb)
 164{
 165	return seg->num * TRBS_PER_SEGMENT + (trb - seg->trbs);
 166}
 167
 168/* Updates trb to point to the next TRB in the ring, and updates seg if the next
 169 * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 170 * effect the ring dequeue or enqueue pointers.
 171 */
 172static void next_trb(struct xhci_segment **seg,
 173			union xhci_trb **trb)
 174{
 175	if (trb_is_link(*trb) || last_trb_on_seg(*seg, *trb)) {
 176		*seg = (*seg)->next;
 177		*trb = ((*seg)->trbs);
 178	} else {
 179		(*trb)++;
 180	}
 181}
 182
 183/*
 184 * See Cycle bit rules. SW is the consumer for the event ring only.
 185 */
 186void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 187{
 188	unsigned int link_trb_count = 0;
 189
 190	/* event ring doesn't have link trbs, check for last trb */
 191	if (ring->type == TYPE_EVENT) {
 192		if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
 193			ring->dequeue++;
 194			return;
 195		}
 196		if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
 197			ring->cycle_state ^= 1;
 198		ring->deq_seg = ring->deq_seg->next;
 199		ring->dequeue = ring->deq_seg->trbs;
 200
 201		trace_xhci_inc_deq(ring);
 202
 203		return;
 204	}
 205
 206	/* All other rings have link trbs */
 207	if (!trb_is_link(ring->dequeue)) {
 208		if (last_trb_on_seg(ring->deq_seg, ring->dequeue))
 209			xhci_warn(xhci, "Missing link TRB at end of segment\n");
 210		else
 211			ring->dequeue++;
 212	}
 213
 214	while (trb_is_link(ring->dequeue)) {
 215		ring->deq_seg = ring->deq_seg->next;
 216		ring->dequeue = ring->deq_seg->trbs;
 217
 218		trace_xhci_inc_deq(ring);
 219
 220		if (link_trb_count++ > ring->num_segs) {
 221			xhci_warn(xhci, "Ring is an endless link TRB loop\n");
 222			break;
 223		}
 224	}
 225	return;
 226}
 227
 228/*
 229 * If enqueue points at a link TRB, follow links until an ordinary TRB is reached.
 230 * Toggle the cycle bit of passed link TRBs and optionally chain them.
 231 */
 232static void inc_enq_past_link(struct xhci_hcd *xhci, struct xhci_ring *ring, u32 chain)
 233{
 234	unsigned int link_trb_count = 0;
 235
 236	while (trb_is_link(ring->enqueue)) {
 237
 238		/*
 239		 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 240		 * set, but other sections talk about dealing with the chain bit set. This was
 241		 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 242		 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 243		 *
 244		 * On 0.95 and some 0.96 HCs the chain bit is set once at segment initalization
 245		 * and never changed here. On all others, modify it as requested by the caller.
 246		 */
 247		if (!xhci_link_chain_quirk(xhci, ring->type)) {
 248			ring->enqueue->link.control &= cpu_to_le32(~TRB_CHAIN);
 249			ring->enqueue->link.control |= cpu_to_le32(chain);
 250		}
 251
 252		/* Give this link TRB to the hardware */
 253		wmb();
 254		ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
 255
 256		/* Toggle the cycle bit after the last ring segment. */
 257		if (link_trb_toggles_cycle(ring->enqueue))
 258			ring->cycle_state ^= 1;
 259
 260		ring->enq_seg = ring->enq_seg->next;
 261		ring->enqueue = ring->enq_seg->trbs;
 262
 263		trace_xhci_inc_enq(ring);
 264
 265		if (link_trb_count++ > ring->num_segs) {
 266			xhci_warn(xhci, "Link TRB loop at enqueue\n");
 267			break;
 268		}
 269	}
 270}
 271
 272/*
 273 * See Cycle bit rules. SW is the consumer for the event ring only.
 274 *
 275 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 276 * chain bit is set), then set the chain bit in all the following link TRBs.
 277 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 278 * have their chain bit cleared (so that each Link TRB is a separate TD).
 279 *
 280 * @more_trbs_coming:	Will you enqueue more TRBs before calling
 281 *			prepare_transfer()?
 282 */
 283static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 284			bool more_trbs_coming)
 285{
 286	u32 chain;
 287
 288	chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 289
 290	if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
 291		xhci_err(xhci, "Tried to move enqueue past ring segment\n");
 292		return;
 293	}
 294
 295	ring->enqueue++;
 296
 297	/*
 298	 * If we are in the middle of a TD or the caller plans to enqueue more
 299	 * TDs as one transfer (eg. control), traverse any link TRBs right now.
 300	 * Otherwise, enqueue can stay on a link until the next prepare_ring().
 301	 * This avoids enqueue entering deq_seg and simplifies ring expansion.
 302	 */
 303	if (trb_is_link(ring->enqueue) && (chain || more_trbs_coming))
 304		inc_enq_past_link(xhci, ring, chain);
 305}
 306
 307static bool dma_in_range(dma_addr_t dma,
 308			 struct xhci_segment *start_seg, union xhci_trb *start_trb,
 309			 struct xhci_segment *end_seg, union xhci_trb *end_trb)
 310{
 311	unsigned int pos, start, end;
 312	struct xhci_segment *pos_seg;
 313	union xhci_trb *pos_trb = xhci_dma_to_trb(start_seg, dma, &pos_seg);
 314
 315	/* Is the trb dma address even part of the whole ring? */
 316	if (!pos_trb)
 317		return false;
 318
 319	pos = trb_to_pos(pos_seg, pos_trb);
 320	start = trb_to_pos(start_seg, start_trb);
 321	end = trb_to_pos(end_seg, end_trb);
 322
 323	/* end position is smaller than start, search range wraps around */
 324	if (end < start)
 325		return !(pos > end && pos < start);
 326
 327	return (pos >= start && pos <= end);
 328}
 329
 330/* If the suspect DMA address is a TRB in this TD, this function returns true */
 331static bool trb_in_td(struct xhci_td *td, dma_addr_t suspect_dma)
 332{
 333	return dma_in_range(suspect_dma, td->start_seg, td->start_trb,
 334			    td->end_seg, td->end_trb);
 335}
 336
 337/*
 338 * Return number of free normal TRBs from enqueue to dequeue pointer on ring.
 339 * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment.
 340 * Only for transfer and command rings where driver is the producer, not for
 341 * event rings.
 342 */
 343static unsigned int xhci_num_trbs_free(struct xhci_ring *ring)
 344{
 345	struct xhci_segment *enq_seg = ring->enq_seg;
 346	union xhci_trb *enq = ring->enqueue;
 347	union xhci_trb *last_on_seg;
 348	unsigned int free = 0;
 349	int i = 0;
 350
 351	/* Ring might be empty even if enq != deq if enq is left on a link trb */
 352	if (trb_is_link(enq)) {
 353		enq_seg = enq_seg->next;
 354		enq = enq_seg->trbs;
 355	}
 356
 357	/* Empty ring, common case, don't walk the segments */
 358	if (enq == ring->dequeue)
 359		return ring->num_segs * (TRBS_PER_SEGMENT - 1);
 360
 361	do {
 362		if (ring->deq_seg == enq_seg && ring->dequeue >= enq)
 363			return free + (ring->dequeue - enq);
 364		last_on_seg = &enq_seg->trbs[TRBS_PER_SEGMENT - 1];
 365		free += last_on_seg - enq;
 366		enq_seg = enq_seg->next;
 367		enq = enq_seg->trbs;
 368	} while (i++ < ring->num_segs);
 369
 370	return free;
 371}
 372
 373/*
 374 * Check to see if there's room to enqueue num_trbs on the ring and make sure
 375 * enqueue pointer will not advance into dequeue segment. See rules above.
 376 * return number of new segments needed to ensure this.
 377 */
 378
 379static unsigned int xhci_ring_expansion_needed(struct xhci_hcd *xhci, struct xhci_ring *ring,
 380					       unsigned int num_trbs)
 381{
 382	struct xhci_segment *seg;
 383	int trbs_past_seg;
 384	int enq_used;
 385	int new_segs;
 386
 387	enq_used = ring->enqueue - ring->enq_seg->trbs;
 388
 389	/* how many trbs will be queued past the enqueue segment? */
 390	trbs_past_seg = enq_used + num_trbs - (TRBS_PER_SEGMENT - 1);
 391
 392	/*
 393	 * Consider expanding the ring already if num_trbs fills the current
 394	 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into
 395	 * the next segment. Avoids confusing full ring with special empty ring
 396	 * case below
 397	 */
 398	if (trbs_past_seg < 0)
 399		return 0;
 400
 401	/* Empty ring special case, enqueue stuck on link trb while dequeue advanced */
 402	if (trb_is_link(ring->enqueue) && ring->enq_seg->next->trbs == ring->dequeue)
 403		return 0;
 404
 405	new_segs = 1 + (trbs_past_seg / (TRBS_PER_SEGMENT - 1));
 406	seg = ring->enq_seg;
 407
 408	while (new_segs > 0) {
 409		seg = seg->next;
 410		if (seg == ring->deq_seg) {
 411			xhci_dbg(xhci, "Adding %d trbs requires expanding ring by %d segments\n",
 412				 num_trbs, new_segs);
 413			return new_segs;
 414		}
 415		new_segs--;
 416	}
 417
 418	return 0;
 419}
 420
 421/* Ring the host controller doorbell after placing a command on the ring */
 422void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 423{
 424	if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 425		return;
 426
 427	xhci_dbg(xhci, "// Ding dong!\n");
 428
 429	trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
 430
 431	writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 432	/* Flush PCI posted writes */
 433	readl(&xhci->dba->doorbell[0]);
 434}
 435
 436static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci)
 437{
 438	return mod_delayed_work(system_percpu_wq, &xhci->cmd_timer,
 439			msecs_to_jiffies(xhci->current_cmd->timeout_ms));
 440}
 441
 442static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
 443{
 444	return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
 445					cmd_list);
 446}
 447
 448/*
 449 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
 450 * If there are other commands waiting then restart the ring and kick the timer.
 451 * This must be called with command ring stopped and xhci->lock held.
 452 */
 453static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
 454					 struct xhci_command *cur_cmd)
 455{
 456	struct xhci_command *i_cmd;
 457
 458	/* Turn all aborted commands in list to no-ops, then restart */
 459	list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
 460
 461		if (i_cmd->status != COMP_COMMAND_ABORTED)
 462			continue;
 463
 464		i_cmd->status = COMP_COMMAND_RING_STOPPED;
 465
 466		xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
 467			 i_cmd->command_trb);
 468
 469		trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP, false);
 470
 471		/*
 472		 * caller waiting for completion is called when command
 473		 *  completion event is received for these no-op commands
 474		 */
 475	}
 476
 477	xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 478
 479	/* ring command ring doorbell to restart the command ring */
 480	if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
 481	    !(xhci->xhc_state & XHCI_STATE_DYING)) {
 482		xhci->current_cmd = cur_cmd;
 483		if (cur_cmd)
 484			xhci_mod_cmd_timer(xhci);
 485		xhci_ring_cmd_db(xhci);
 486	}
 487}
 488
 489/* Must be called with xhci->lock held, releases and acquires lock back */
 490static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
 491{
 492	struct xhci_segment *new_seg	= xhci->cmd_ring->deq_seg;
 493	union xhci_trb *new_deq		= xhci->cmd_ring->dequeue;
 494	u64 crcr;
 495	int ret;
 496
 497	xhci_dbg(xhci, "Abort command ring\n");
 498
 499	reinit_completion(&xhci->cmd_ring_stop_completion);
 500
 501	/*
 502	 * The control bits like command stop, abort are located in lower
 503	 * dword of the command ring control register.
 504	 * Some controllers require all 64 bits to be written to abort the ring.
 505	 * Make sure the upper dword is valid, pointing to the next command,
 506	 * avoiding corrupting the command ring pointer in case the command ring
 507	 * is stopped by the time the upper dword is written.
 508	 */
 509	next_trb(&new_seg, &new_deq);
 510	if (trb_is_link(new_deq))
 511		next_trb(&new_seg, &new_deq);
 512
 513	crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
 514	xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
 515
 516	/* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
 517	 * completion of the Command Abort operation. If CRR is not negated in 5
 518	 * seconds then driver handles it as if host died (-ENODEV).
 519	 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
 520	 * and try to recover a -ETIMEDOUT with a host controller reset.
 521	 */
 522	ret = xhci_handshake(&xhci->op_regs->cmd_ring,
 523			CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 524	if (ret < 0) {
 525		xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
 526		xhci_halt(xhci);
 527		xhci_hc_died(xhci);
 528		return ret;
 529	}
 530	/*
 531	 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
 532	 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
 533	 * but the completion event in never sent. Wait 2 secs (arbitrary
 534	 * number) to handle those cases after negation of CMD_RING_RUNNING.
 535	 */
 536	spin_unlock_irqrestore(&xhci->lock, flags);
 537	ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
 538					  msecs_to_jiffies(2000));
 539	spin_lock_irqsave(&xhci->lock, flags);
 540	if (!ret) {
 541		xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
 542		xhci_cleanup_command_queue(xhci);
 543	} else {
 544		xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
 545	}
 546	return 0;
 547}
 548
 549void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 550		unsigned int slot_id,
 551		unsigned int ep_index,
 552		unsigned int stream_id)
 553{
 554	__le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 555	struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 556	unsigned int ep_state = ep->ep_state;
 557
 558	/* Don't ring the doorbell for this endpoint if there are pending
 559	 * cancellations because we don't want to interrupt processing.
 560	 * We don't want to restart any stream rings if there's a set dequeue
 561	 * pointer command pending because the device can choose to start any
 562	 * stream once the endpoint is on the HW schedule.
 563	 */
 564	if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 565	    (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
 566		return;
 567
 568	trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
 569
 570	writel(DB_VALUE(ep_index, stream_id), db_addr);
 571	/* flush the write */
 572	readl(db_addr);
 573}
 574
 575/* Ring the doorbell for any rings with pending URBs */
 576static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 577		unsigned int slot_id,
 578		unsigned int ep_index)
 579{
 580	unsigned int stream_id;
 581	struct xhci_virt_ep *ep;
 582
 583	ep = &xhci->devs[slot_id]->eps[ep_index];
 584
 585	/* A ring has pending URBs if its TD list is not empty */
 586	if (!(ep->ep_state & EP_HAS_STREAMS)) {
 587		if (ep->ring && !(list_empty(&ep->ring->td_list)))
 588			xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 589		return;
 590	}
 591
 592	for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 593			stream_id++) {
 594		struct xhci_stream_info *stream_info = ep->stream_info;
 595		if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 596			xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 597						stream_id);
 598	}
 599}
 600
 601void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 602		unsigned int slot_id,
 603		unsigned int ep_index)
 604{
 605	ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 606}
 607
 608static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
 609					     unsigned int slot_id,
 610					     unsigned int ep_index)
 611{
 612	if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
 613		xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
 614		return NULL;
 615	}
 616	if (ep_index >= EP_CTX_PER_DEV) {
 617		xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
 618		return NULL;
 619	}
 620	if (!xhci->devs[slot_id]) {
 621		xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
 622		return NULL;
 623	}
 624
 625	return &xhci->devs[slot_id]->eps[ep_index];
 626}
 627
 628static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
 629					      struct xhci_virt_ep *ep,
 630					      unsigned int stream_id)
 631{
 632	/* common case, no streams */
 633	if (!(ep->ep_state & EP_HAS_STREAMS))
 634		return ep->ring;
 635
 636	if (!ep->stream_info)
 637		return NULL;
 638
 639	if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
 640		xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
 641			  stream_id, ep->vdev->slot_id, ep->ep_index);
 642		return NULL;
 643	}
 644
 645	return ep->stream_info->stream_rings[stream_id];
 646}
 647
 648/* Get the right ring for the given slot_id, ep_index and stream_id.
 649 * If the endpoint supports streams, boundary check the URB's stream ID.
 650 * If the endpoint doesn't support streams, return the singular endpoint ring.
 651 */
 652struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 653		unsigned int slot_id, unsigned int ep_index,
 654		unsigned int stream_id)
 655{
 656	struct xhci_virt_ep *ep;
 657
 658	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
 659	if (!ep)
 660		return NULL;
 661
 662	return xhci_virt_ep_to_ring(xhci, ep, stream_id);
 663}
 664
 665
 666/*
 667 * Get the hw dequeue pointer xHC stopped on, either directly from the
 668 * endpoint context, or if streams are in use from the stream context.
 669 * The returned hw_dequeue contains the lowest four bits with cycle state
 670 * and possbile stream context type.
 671 */
 672static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
 673			   unsigned int ep_index, unsigned int stream_id)
 674{
 675	struct xhci_ep_ctx *ep_ctx;
 676	struct xhci_stream_ctx *st_ctx;
 677	struct xhci_virt_ep *ep;
 678
 679	ep = &vdev->eps[ep_index];
 680
 681	if (ep->ep_state & EP_HAS_STREAMS) {
 682		st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
 683		return le64_to_cpu(st_ctx->stream_ring);
 684	}
 685	ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 686	return le64_to_cpu(ep_ctx->deq);
 687}
 688
 689static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
 690				unsigned int slot_id, unsigned int ep_index,
 691				unsigned int stream_id, struct xhci_td *td)
 692{
 693	struct xhci_virt_device *dev = xhci->devs[slot_id];
 694	struct xhci_virt_ep *ep = &dev->eps[ep_index];
 695	struct xhci_ring *ep_ring;
 696	struct xhci_command *cmd;
 697	struct xhci_segment *new_seg;
 698	union xhci_trb *new_deq;
 699	int new_cycle;
 700	dma_addr_t addr;
 701	u64 hw_dequeue;
 702	bool hw_dequeue_found = false;
 703	bool td_last_trb_found = false;
 704	u32 trb_sct = 0;
 705	int ret;
 706
 707	ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 708			ep_index, stream_id);
 709	if (!ep_ring) {
 710		xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
 711			  stream_id);
 712		return -ENODEV;
 713	}
 714
 715	hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id) & TR_DEQ_PTR_MASK;
 716	new_seg = ep_ring->deq_seg;
 717	new_deq = ep_ring->dequeue;
 718	new_cycle = le32_to_cpu(td->end_trb->generic.field[3]) & TRB_CYCLE;
 719
 720	/*
 721	 * Walk the ring until both the next TRB and hw_dequeue are found (don't
 722	 * move hw_dequeue back if it went forward due to a HW bug). Cycle state
 723	 * is loaded from a known good TRB, track later toggles to maintain it.
 724	 */
 725	do {
 726		if (!hw_dequeue_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 727		    == (dma_addr_t)hw_dequeue) {
 728			hw_dequeue_found = true;
 729			if (td_last_trb_found)
 730				break;
 731		}
 732		if (new_deq == td->end_trb)
 733			td_last_trb_found = true;
 734
 735		if (td_last_trb_found && trb_is_link(new_deq) &&
 736		    link_trb_toggles_cycle(new_deq))
 737			new_cycle ^= 0x1;
 738
 739		next_trb(&new_seg, &new_deq);
 740
 741		/* Search wrapped around, bail out */
 742		if (new_deq == ep->ring->dequeue) {
 743			xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 744			return -EINVAL;
 745		}
 746
 747	} while (!hw_dequeue_found || !td_last_trb_found);
 748
 749	/* Don't update the ring cycle state for the producer (us). */
 750	addr = xhci_trb_virt_to_dma(new_seg, new_deq);
 751	if (addr == 0) {
 752		xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
 753		xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
 754		return -EINVAL;
 755	}
 756
 757	if ((ep->ep_state & SET_DEQ_PENDING)) {
 758		xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
 759			  &addr);
 760		return -EBUSY;
 761	}
 762
 763	/* This function gets called from contexts where it cannot sleep */
 764	cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
 765	if (!cmd) {
 766		xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
 767		return -ENOMEM;
 768	}
 769
 770	if (stream_id)
 771		trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
 772	ret = queue_command(xhci, cmd,
 773		lower_32_bits(addr) | trb_sct | new_cycle,
 774		upper_32_bits(addr),
 775		STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
 776		EP_INDEX_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
 777	if (ret < 0) {
 778		xhci_free_command(xhci, cmd);
 779		return ret;
 780	}
 781	ep->queued_deq_seg = new_seg;
 782	ep->queued_deq_ptr = new_deq;
 783
 784	xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 785		       "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
 786
 787	/* Stop the TD queueing code from ringing the doorbell until
 788	 * this command completes.  The HC won't set the dequeue pointer
 789	 * if the ring is running, and ringing the doorbell starts the
 790	 * ring running.
 791	 */
 792	ep->ep_state |= SET_DEQ_PENDING;
 793	xhci_ring_cmd_db(xhci);
 794	return 0;
 795}
 796
 797/* flip_cycle means flip the cycle bit of all but the first and last TRB.
 798 * (The last TRB actually points to the ring enqueue pointer, which is not part
 799 * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 800 */
 801static void td_to_noop(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
 802			struct xhci_td *td, bool flip_cycle)
 803{
 804	bool unchain_links;
 805	struct xhci_segment *seg	= td->start_seg;
 806	union xhci_trb *trb		= td->start_trb;
 807
 808	/* link TRBs should now be unchained, but some old HCs expect otherwise */
 809	unchain_links = !xhci_link_chain_quirk(xhci, ep->ring ? ep->ring->type : TYPE_STREAM);
 810
 811	while (1) {
 812		trb_to_noop(trb, TRB_TR_NOOP, unchain_links);
 813
 814		/* flip cycle if asked to */
 815		if (flip_cycle && trb != td->start_trb && trb != td->end_trb)
 816			trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
 817
 818		if (trb == td->end_trb)
 819			break;
 820
 821		next_trb(&seg, &trb);
 822	}
 823}
 824
 825static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 826				     struct xhci_td *cur_td, int status)
 827{
 828	struct urb	*urb		= cur_td->urb;
 829	struct urb_priv	*urb_priv	= urb->hcpriv;
 830	struct usb_hcd	*hcd		= bus_to_hcd(urb->dev->bus);
 831
 832	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 833		xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 834		if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs	== 0) {
 835			if (xhci->quirks & XHCI_AMD_PLL_FIX)
 836				usb_amd_quirk_pll_enable();
 837		}
 838	}
 839	xhci_urb_free_priv(urb_priv);
 840	usb_hcd_unlink_urb_from_ep(hcd, urb);
 841	trace_xhci_urb_giveback(urb);
 842	usb_hcd_giveback_urb(hcd, urb, status);
 843}
 844
 845static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
 846		struct xhci_ring *ring, struct xhci_td *td)
 847{
 848	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 849	struct xhci_segment *seg = td->bounce_seg;
 850	struct urb *urb = td->urb;
 851	size_t len;
 852
 853	if (!ring || !seg || !urb)
 854		return;
 855
 856	if (usb_urb_dir_out(urb)) {
 857		dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 858				 DMA_TO_DEVICE);
 859		return;
 860	}
 861
 862	dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 863			 DMA_FROM_DEVICE);
 864	/* for in transfers we need to copy the data from bounce to sg */
 865	if (urb->num_sgs) {
 866		len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
 867					   seg->bounce_len, seg->bounce_offs);
 868		if (len != seg->bounce_len)
 869			xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
 870				  len, seg->bounce_len);
 871	} else {
 872		memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
 873		       seg->bounce_len);
 874	}
 875	seg->bounce_len = 0;
 876	seg->bounce_offs = 0;
 877}
 878
 879static void xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
 880			    struct xhci_ring *ep_ring, int status)
 881{
 882	struct urb *urb = NULL;
 883
 884	/* Clean up the endpoint's TD list */
 885	urb = td->urb;
 886
 887	/* if a bounce buffer was used to align this td then unmap it */
 888	xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
 889
 890	/* Do one last check of the actual transfer length.
 891	 * If the host controller said we transferred more data than the buffer
 892	 * length, urb->actual_length will be a very big number (since it's
 893	 * unsigned).  Play it safe and say we didn't transfer anything.
 894	 */
 895	if (urb->actual_length > urb->transfer_buffer_length) {
 896		xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
 897			  urb->transfer_buffer_length, urb->actual_length);
 898		urb->actual_length = 0;
 899		status = 0;
 900	}
 901	/* TD might be removed from td_list if we are giving back a cancelled URB */
 902	if (!list_empty(&td->td_list))
 903		list_del_init(&td->td_list);
 904	/* Giving back a cancelled URB, or if a slated TD completed anyway */
 905	if (!list_empty(&td->cancelled_td_list))
 906		list_del_init(&td->cancelled_td_list);
 907
 908	inc_td_cnt(urb);
 909	/* Giveback the urb when all the tds are completed */
 910	if (last_td_in_urb(td)) {
 911		if ((urb->actual_length != urb->transfer_buffer_length &&
 912		     (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
 913		    (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
 914			xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
 915				 urb, urb->actual_length,
 916				 urb->transfer_buffer_length, status);
 917
 918		/* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
 919		if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
 920			status = 0;
 921		xhci_giveback_urb_in_irq(xhci, td, status);
 922	}
 923}
 924
 925/* Give back previous TD and move on to the next TD. */
 926static void xhci_dequeue_td(struct xhci_hcd *xhci, struct xhci_td *td, struct xhci_ring *ring,
 927			    u32 status)
 928{
 929	ring->dequeue = td->end_trb;
 930	ring->deq_seg = td->end_seg;
 931	inc_deq(xhci, ring);
 932
 933	xhci_td_cleanup(xhci, td, ring, status);
 934}
 935
 936/* Complete the cancelled URBs we unlinked from td_list. */
 937static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
 938{
 939	struct xhci_ring *ring;
 940	struct xhci_td *td, *tmp_td;
 941
 942	list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
 943				 cancelled_td_list) {
 944
 945		ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
 946
 947		if (td->cancel_status == TD_CLEARED) {
 948			xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
 949				 __func__, td->urb);
 950			xhci_td_cleanup(ep->xhci, td, ring, td->status);
 951		} else {
 952			xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
 953				 __func__, td->urb, td->cancel_status);
 954		}
 955		if (ep->xhci->xhc_state & XHCI_STATE_DYING)
 956			return;
 957	}
 958}
 959
 960static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
 961				unsigned int ep_index, enum xhci_ep_reset_type reset_type)
 962{
 963	struct xhci_command *command;
 964	int ret = 0;
 965
 966	command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
 967	if (!command) {
 968		ret = -ENOMEM;
 969		goto done;
 970	}
 971
 972	xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
 973		 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
 974		 ep_index, slot_id);
 975
 976	ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
 977done:
 978	if (ret)
 979		xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
 980			 slot_id, ep_index, ret);
 981	return ret;
 982}
 983
 984static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
 985				struct xhci_virt_ep *ep,
 986				struct xhci_td *td,
 987				enum xhci_ep_reset_type reset_type)
 988{
 989	unsigned int slot_id = ep->vdev->slot_id;
 990	int err;
 991
 992	/*
 993	 * Avoid resetting endpoint if link is inactive. Can cause host hang.
 994	 * Device will be reset soon to recover the link so don't do anything
 995	 */
 996	if (ep->vdev->flags & VDEV_PORT_ERROR)
 997		return -ENODEV;
 998
 999	/* add td to cancelled list and let reset ep handler take care of it */
1000	if (reset_type == EP_HARD_RESET) {
1001		ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1002		if (td && list_empty(&td->cancelled_td_list)) {
1003			list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1004			td->cancel_status = TD_HALTED;
1005		}
1006	}
1007
1008	if (ep->ep_state & EP_HALTED) {
1009		xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
1010			 ep->ep_index);
1011		return 0;
1012	}
1013
1014	err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
1015	if (err)
1016		return err;
1017
1018	ep->ep_state |= EP_HALTED;
1019
1020	xhci_ring_cmd_db(xhci);
1021
1022	return 0;
1023}
1024
1025/*
1026 * Fix up the ep ring first, so HW stops executing cancelled TDs.
1027 * We have the xHCI lock, so nothing can modify this list until we drop it.
1028 * We're also in the event handler, so we can't get re-interrupted if another
1029 * Stop Endpoint command completes.
1030 *
1031 * only call this when ring is not in a running state
1032 */
1033
1034static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
1035{
1036	struct xhci_hcd		*xhci;
1037	struct xhci_td		*td = NULL;
1038	struct xhci_td		*tmp_td = NULL;
1039	struct xhci_td		*cached_td = NULL;
1040	struct xhci_ring	*ring;
1041	u64			hw_deq;
1042	unsigned int		slot_id = ep->vdev->slot_id;
1043	int			err;
1044
1045	/*
1046	 * This is not going to work if the hardware is changing its dequeue
1047	 * pointers as we look at them. Completion handler will call us later.
1048	 */
1049	if (ep->ep_state & SET_DEQ_PENDING)
1050		return 0;
1051
1052	xhci = ep->xhci;
1053
1054	list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1055		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1056			       "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
1057			       (unsigned long long)xhci_trb_virt_to_dma(
1058				       td->start_seg, td->start_trb),
1059			       td->urb->stream_id, td->urb);
1060		list_del_init(&td->td_list);
1061		ring = xhci_urb_to_transfer_ring(xhci, td->urb);
1062		if (!ring) {
1063			xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1064				  td->urb, td->urb->stream_id);
1065			continue;
1066		}
1067		/*
1068		 * If a ring stopped on the TD we need to cancel then we have to
1069		 * move the xHC endpoint ring dequeue pointer past this TD.
1070		 * Rings halted due to STALL may show hw_deq is past the stalled
1071		 * TD, but still require a set TR Deq command to flush xHC cache.
1072		 */
1073		hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
1074					 td->urb->stream_id);
1075		hw_deq &= TR_DEQ_PTR_MASK;
1076
1077		if (td->cancel_status == TD_HALTED || trb_in_td(td, hw_deq)) {
1078			switch (td->cancel_status) {
1079			case TD_CLEARED: /* TD is already no-op */
1080			case TD_CLEARING_CACHE: /* set TR deq command already queued */
1081				break;
1082			case TD_DIRTY: /* TD is cached, clear it */
1083			case TD_HALTED:
1084			case TD_CLEARING_CACHE_DEFERRED:
1085				if (cached_td) {
1086					if (cached_td->urb->stream_id != td->urb->stream_id) {
1087						/* Multiple streams case, defer move dq */
1088						xhci_dbg(xhci,
1089							 "Move dq deferred: stream %u URB %p\n",
1090							 td->urb->stream_id, td->urb);
1091						td->cancel_status = TD_CLEARING_CACHE_DEFERRED;
1092						break;
1093					}
1094
1095					/* Should never happen, but clear the TD if it does */
1096					xhci_warn(xhci,
1097						  "Found multiple active URBs %p and %p in stream %u?\n",
1098						  td->urb, cached_td->urb,
1099						  td->urb->stream_id);
1100					td_to_noop(xhci, ep, cached_td, false);
1101					cached_td->cancel_status = TD_CLEARED;
1102				}
1103				td_to_noop(xhci, ep, td, false);
1104				td->cancel_status = TD_CLEARING_CACHE;
1105				cached_td = td;
1106				break;
1107			}
1108		} else {
1109			td_to_noop(xhci, ep, td, false);
1110			td->cancel_status = TD_CLEARED;
1111		}
1112	}
1113
1114	/* If there's no need to move the dequeue pointer then we're done */
1115	if (!cached_td)
1116		return 0;
1117
1118	err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1119					cached_td->urb->stream_id,
1120					cached_td);
1121	if (err) {
1122		/* Failed to move past cached td, just set cached TDs to no-op */
1123		list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1124			/*
1125			 * Deferred TDs need to have the deq pointer set after the above command
1126			 * completes, so if that failed we just give up on all of them (and
1127			 * complain loudly since this could cause issues due to caching).
1128			 */
1129			if (td->cancel_status != TD_CLEARING_CACHE &&
1130			    td->cancel_status != TD_CLEARING_CACHE_DEFERRED)
1131				continue;
1132			xhci_warn(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1133				  td->urb);
1134			td_to_noop(xhci, ep, td, false);
1135			td->cancel_status = TD_CLEARED;
1136		}
1137	}
1138	return 0;
1139}
1140
1141/*
1142 * Erase queued TDs from transfer ring(s) and give back those the xHC didn't
1143 * stop on. If necessary, queue commands to move the xHC off cancelled TDs it
1144 * stopped on. Those will be given back later when the commands complete.
1145 *
1146 * Call under xhci->lock on a stopped endpoint.
1147 */
1148void xhci_process_cancelled_tds(struct xhci_virt_ep *ep)
1149{
1150	xhci_invalidate_cancelled_tds(ep);
1151	xhci_giveback_invalidated_tds(ep);
1152}
1153
1154/*
1155 * Returns the TD the endpoint ring halted on.
1156 * Only call for non-running rings without streams.
1157 */
1158static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1159{
1160	struct xhci_td	*td;
1161	u64		hw_deq;
1162
1163	if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1164		hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1165		hw_deq &= TR_DEQ_PTR_MASK;
1166		td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1167		if (trb_in_td(td, hw_deq))
1168			return td;
1169	}
1170	return NULL;
1171}
1172
1173/*
1174 * When we get a command completion for a Stop Endpoint Command, we need to
1175 * unlink any cancelled TDs from the ring.  There are two ways to do that:
1176 *
1177 *  1. If the HW was in the middle of processing the TD that needs to be
1178 *     cancelled, then we must move the ring's dequeue pointer past the last TRB
1179 *     in the TD with a Set Dequeue Pointer Command.
1180 *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1181 *     bit cleared) so that the HW will skip over them.
1182 */
1183static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1184				    union xhci_trb *trb, u32 comp_code)
1185{
1186	unsigned int ep_index;
1187	struct xhci_virt_ep *ep;
1188	struct xhci_ep_ctx *ep_ctx;
1189	struct xhci_td *td = NULL;
1190	enum xhci_ep_reset_type reset_type;
1191	struct xhci_command *command;
1192	int err;
1193
1194	if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1195		if (!xhci->devs[slot_id])
1196			xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1197				  slot_id);
1198		return;
1199	}
1200
1201	ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1202	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1203	if (!ep)
1204		return;
1205
1206	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1207
1208	trace_xhci_handle_cmd_stop_ep(ep_ctx);
1209
1210	if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1211	/*
1212	 * If stop endpoint command raced with a halting endpoint we need to
1213	 * reset the host side endpoint first.
1214	 * If the TD we halted on isn't cancelled the TD should be given back
1215	 * with a proper error code, and the ring dequeue moved past the TD.
1216	 * If streams case we can't find hw_deq, or the TD we halted on so do a
1217	 * soft reset.
1218	 *
1219	 * Proper error code is unknown here, it would be -EPIPE if device side
1220	 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1221	 * We use -EPROTO, if device is stalled it should return a stall error on
1222	 * next transfer, which then will return -EPIPE, and device side stall is
1223	 * noted and cleared by class driver.
1224	 */
1225		switch (GET_EP_CTX_STATE(ep_ctx)) {
1226		case EP_STATE_HALTED:
1227			xhci_dbg(xhci, "Stop ep completion raced with stall\n");
1228			/*
1229			 * If the halt happened before Stop Endpoint failed, its transfer event
1230			 * should have already been handled and Reset Endpoint should be pending.
1231			 */
1232			if (ep->ep_state & EP_HALTED)
1233				goto reset_done;
1234
1235			if (ep->ep_state & EP_HAS_STREAMS) {
1236				reset_type = EP_SOFT_RESET;
1237			} else {
1238				reset_type = EP_HARD_RESET;
1239				td = find_halted_td(ep);
1240				if (td)
1241					td->status = -EPROTO;
1242			}
1243			/* reset ep, reset handler cleans up cancelled tds */
1244			err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1245			xhci_dbg(xhci, "Stop ep completion resetting ep, status %d\n", err);
1246			if (err)
1247				break;
1248reset_done:
1249			/* Reset EP handler will clean up cancelled TDs */
1250			ep->ep_state &= ~EP_STOP_CMD_PENDING;
1251			return;
1252		case EP_STATE_STOPPED:
1253			/*
1254			 * Per xHCI 4.6.9, Stop Endpoint command on a Stopped
1255			 * EP is a Context State Error, and EP stays Stopped.
1256			 *
1257			 * But maybe it failed on Halted, and somebody ran Reset
1258			 * Endpoint later. EP state is now Stopped and EP_HALTED
1259			 * still set because Reset EP handler will run after us.
1260			 */
1261			if (ep->ep_state & EP_HALTED)
1262				break;
1263			/*
1264			 * On some HCs EP state remains Stopped for some tens of
1265			 * us to a few ms or more after a doorbell ring, and any
1266			 * new Stop Endpoint fails without aborting the restart.
1267			 * This handler may run quickly enough to still see this
1268			 * Stopped state, but it will soon change to Running.
1269			 *
1270			 * Assume this bug on unexpected Stop Endpoint failures.
1271			 * Keep retrying until the EP starts and stops again or
1272			 * up to a timeout (a defective HC may never start, or a
1273			 * driver bug may cause stopping an already stopped EP).
1274			 */
1275			if (time_is_before_jiffies(ep->stop_time + msecs_to_jiffies(100)))
1276				break;
1277			fallthrough;
1278		case EP_STATE_RUNNING:
1279			/* Race, HW handled stop ep cmd before ep was running */
1280			xhci_dbg(xhci, "Stop ep completion ctx error, ctx_state %d\n",
1281					GET_EP_CTX_STATE(ep_ctx));
1282
1283			command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1284			if (!command) {
1285				ep->ep_state &= ~EP_STOP_CMD_PENDING;
1286				return;
1287			}
1288			xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1289			xhci_ring_cmd_db(xhci);
1290
1291			return;
1292		default:
1293			break;
1294		}
1295	}
1296
1297	/* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1298	xhci_invalidate_cancelled_tds(ep);
1299	ep->ep_state &= ~EP_STOP_CMD_PENDING;
1300
1301	/* Otherwise ring the doorbell(s) to restart queued transfers */
1302	xhci_giveback_invalidated_tds(ep);
1303	ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1304}
1305
1306static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1307{
1308	struct xhci_td *cur_td;
1309	struct xhci_td *tmp;
1310
1311	list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1312		list_del_init(&cur_td->td_list);
1313
1314		if (!list_empty(&cur_td->cancelled_td_list))
1315			list_del_init(&cur_td->cancelled_td_list);
1316
1317		xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1318
1319		inc_td_cnt(cur_td->urb);
1320		if (last_td_in_urb(cur_td))
1321			xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1322	}
1323}
1324
1325static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1326		int slot_id, int ep_index)
1327{
1328	struct xhci_td *cur_td;
1329	struct xhci_td *tmp;
1330	struct xhci_virt_ep *ep;
1331	struct xhci_ring *ring;
1332
1333	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1334	if (!ep)
1335		return;
1336
1337	if ((ep->ep_state & EP_HAS_STREAMS) ||
1338			(ep->ep_state & EP_GETTING_NO_STREAMS)) {
1339		int stream_id;
1340
1341		for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1342				stream_id++) {
1343			ring = ep->stream_info->stream_rings[stream_id];
1344			if (!ring)
1345				continue;
1346
1347			xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1348					"Killing URBs for slot ID %u, ep index %u, stream %u",
1349					slot_id, ep_index, stream_id);
1350			xhci_kill_ring_urbs(xhci, ring);
1351		}
1352	} else {
1353		ring = ep->ring;
1354		if (!ring)
1355			return;
1356		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1357				"Killing URBs for slot ID %u, ep index %u",
1358				slot_id, ep_index);
1359		xhci_kill_ring_urbs(xhci, ring);
1360	}
1361
1362	list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1363			cancelled_td_list) {
1364		list_del_init(&cur_td->cancelled_td_list);
1365		inc_td_cnt(cur_td->urb);
1366
1367		if (last_td_in_urb(cur_td))
1368			xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1369	}
1370}
1371
1372/*
1373 * host controller died, register read returns 0xffffffff
1374 * Complete pending commands, mark them ABORTED.
1375 * URBs need to be given back as usb core might be waiting with device locks
1376 * held for the URBs to finish during device disconnect, blocking host remove.
1377 *
1378 * Call with xhci->lock held.
1379 * lock is relased and re-acquired while giving back urb.
1380 */
1381void xhci_hc_died(struct xhci_hcd *xhci)
1382{
1383	bool notify;
1384	int i, j;
1385
1386	if (xhci->xhc_state & XHCI_STATE_DYING)
1387		return;
1388
1389	notify = !(xhci->xhc_state & XHCI_STATE_REMOVING);
1390	if (notify)
1391		xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1392	xhci->xhc_state |= XHCI_STATE_DYING;
1393
1394	xhci_cleanup_command_queue(xhci);
1395
1396	/* return any pending urbs, remove may be waiting for them */
1397	for (i = 0; i <= xhci->max_slots; i++) {
1398		if (!xhci->devs[i])
1399			continue;
1400		for (j = 0; j < 31; j++)
1401			xhci_kill_endpoint_urbs(xhci, i, j);
1402	}
1403
1404	/* inform usb core hc died if PCI remove isn't already handling it */
1405	if (notify)
1406		usb_hc_died(xhci_to_hcd(xhci));
1407}
1408
1409/*
1410 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1411 * we need to clear the set deq pending flag in the endpoint ring state, so that
1412 * the TD queueing code can ring the doorbell again.  We also need to ring the
1413 * endpoint doorbell to restart the ring, but only if there aren't more
1414 * cancellations pending.
1415 */
1416static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1417		union xhci_trb *trb, u32 cmd_comp_code)
1418{
1419	unsigned int ep_index;
1420	unsigned int stream_id;
1421	struct xhci_ring *ep_ring;
1422	struct xhci_virt_ep *ep;
1423	struct xhci_ep_ctx *ep_ctx;
1424	struct xhci_slot_ctx *slot_ctx;
1425	struct xhci_stream_ctx *stream_ctx;
1426	struct xhci_td *td, *tmp_td;
1427
1428	ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1429	stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1430	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1431	if (!ep)
1432		return;
1433
1434	ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1435	if (!ep_ring) {
1436		xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1437				stream_id);
1438		/* XXX: Harmless??? */
1439		goto cleanup;
1440	}
1441
1442	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1443	slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1444	trace_xhci_handle_cmd_set_deq(slot_ctx);
1445	trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1446
1447	if (ep->ep_state & EP_HAS_STREAMS) {
1448		stream_ctx = &ep->stream_info->stream_ctx_array[stream_id];
1449		trace_xhci_handle_cmd_set_deq_stream(ep->stream_info, stream_id);
1450	}
1451
1452	if (cmd_comp_code != COMP_SUCCESS) {
1453		unsigned int ep_state;
1454		unsigned int slot_state;
1455
1456		switch (cmd_comp_code) {
1457		case COMP_TRB_ERROR:
1458			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1459			break;
1460		case COMP_CONTEXT_STATE_ERROR:
1461			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1462			ep_state = GET_EP_CTX_STATE(ep_ctx);
1463			slot_state = le32_to_cpu(slot_ctx->dev_state);
1464			slot_state = GET_SLOT_STATE(slot_state);
1465			xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1466					"Slot state = %u, EP state = %u",
1467					slot_state, ep_state);
1468			break;
1469		case COMP_SLOT_NOT_ENABLED_ERROR:
1470			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1471					slot_id);
1472			break;
1473		default:
1474			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1475					cmd_comp_code);
1476			break;
1477		}
1478		/* OK what do we do now?  The endpoint state is hosed, and we
1479		 * should never get to this point if the synchronization between
1480		 * queueing, and endpoint state are correct.  This might happen
1481		 * if the device gets disconnected after we've finished
1482		 * cancelling URBs, which might not be an error...
1483		 */
1484	} else {
1485		u64 deq;
1486		/* 4.6.10 deq ptr is written to the stream ctx for streams */
1487		if (ep->ep_state & EP_HAS_STREAMS) {
1488			deq = le64_to_cpu(stream_ctx->stream_ring) & TR_DEQ_PTR_MASK;
1489
1490			/*
1491			 * Cadence xHCI controllers store some endpoint state
1492			 * information within Rsvd0 fields of Stream Endpoint
1493			 * context. This field is not cleared during Set TR
1494			 * Dequeue Pointer command which causes XDMA to skip
1495			 * over transfer ring and leads to data loss on stream
1496			 * pipe.
1497			 * To fix this issue driver must clear Rsvd0 field.
1498			 */
1499			if (xhci->quirks & XHCI_CDNS_SCTX_QUIRK) {
1500				stream_ctx->reserved[0] = 0;
1501				stream_ctx->reserved[1] = 0;
1502			}
1503		} else {
1504			deq = le64_to_cpu(ep_ctx->deq) & TR_DEQ_PTR_MASK;
1505		}
1506		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1507			"Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1508		if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1509					 ep->queued_deq_ptr) == deq) {
1510			/* Update the ring's dequeue segment and dequeue pointer
1511			 * to reflect the new position.
1512			 */
1513			ep_ring->deq_seg = ep->queued_deq_seg;
1514			ep_ring->dequeue = ep->queued_deq_ptr;
1515		} else {
1516			xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1517			xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1518				  ep->queued_deq_seg, ep->queued_deq_ptr);
1519		}
1520	}
1521	/* HW cached TDs cleared from cache, give them back */
1522	list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1523				 cancelled_td_list) {
1524		ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1525		if (td->cancel_status == TD_CLEARING_CACHE) {
1526			td->cancel_status = TD_CLEARED;
1527			xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1528				 __func__, td->urb);
1529			xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1530		} else {
1531			xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1532				 __func__, td->urb, td->cancel_status);
1533		}
1534	}
1535cleanup:
1536	ep->ep_state &= ~SET_DEQ_PENDING;
1537	ep->queued_deq_seg = NULL;
1538	ep->queued_deq_ptr = NULL;
1539
1540	/* Check for deferred or newly cancelled TDs */
1541	if (!list_empty(&ep->cancelled_td_list)) {
1542		xhci_dbg(ep->xhci, "%s: Pending TDs to clear, continuing with invalidation\n",
1543			 __func__);
1544		xhci_invalidate_cancelled_tds(ep);
1545		/* Try to restart the endpoint if all is done */
1546		ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1547		/* Start giving back any TDs invalidated above */
1548		xhci_giveback_invalidated_tds(ep);
1549	} else {
1550		/* Restart any rings with pending URBs */
1551		xhci_dbg(ep->xhci, "%s: All TDs cleared, ring doorbell\n", __func__);
1552		ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1553	}
1554}
1555
1556static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1557		union xhci_trb *trb, u32 cmd_comp_code)
1558{
1559	struct xhci_virt_ep *ep;
1560	struct xhci_ep_ctx *ep_ctx;
1561	unsigned int ep_index;
1562
1563	ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1564	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1565	if (!ep)
1566		return;
1567
1568	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1569	trace_xhci_handle_cmd_reset_ep(ep_ctx);
1570
1571	/* This command will only fail if the endpoint wasn't halted,
1572	 * but we don't care.
1573	 */
1574	xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1575		"Ignoring reset ep completion code of %u", cmd_comp_code);
1576
1577	/* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1578	xhci_invalidate_cancelled_tds(ep);
1579
1580	/* Clear our internal halted state */
1581	ep->ep_state &= ~EP_HALTED;
1582
1583	xhci_giveback_invalidated_tds(ep);
1584
1585	/* if this was a soft reset, then restart */
1586	if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1587		ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1588}
1589
1590static void xhci_handle_cmd_enable_slot(int slot_id, struct xhci_command *command,
1591					u32 cmd_comp_code)
1592{
1593	if (cmd_comp_code == COMP_SUCCESS)
1594		command->slot_id = slot_id;
1595	else
1596		command->slot_id = 0;
1597}
1598
1599static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id,
1600					u32 cmd_comp_code)
1601{
1602	struct xhci_virt_device *virt_dev;
1603	struct xhci_slot_ctx *slot_ctx;
1604
1605	virt_dev = xhci->devs[slot_id];
1606	if (!virt_dev)
1607		return;
1608
1609	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1610	trace_xhci_handle_cmd_disable_slot(slot_ctx);
1611
1612	if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1613		/* Delete default control endpoint resources */
1614		xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1615	if (cmd_comp_code == COMP_SUCCESS) {
1616		xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
1617		xhci->devs[slot_id] = NULL;
1618	}
1619}
1620
1621static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id)
1622{
1623	struct xhci_virt_device *virt_dev;
1624	struct xhci_input_control_ctx *ctrl_ctx;
1625	struct xhci_ep_ctx *ep_ctx;
1626	unsigned int ep_index;
1627	u32 add_flags;
1628
1629	/*
1630	 * Configure endpoint commands can come from the USB core configuration
1631	 * or alt setting changes, or when streams were being configured.
1632	 */
1633
1634	virt_dev = xhci->devs[slot_id];
1635	if (!virt_dev)
1636		return;
1637	ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1638	if (!ctrl_ctx) {
1639		xhci_warn(xhci, "Could not get input context, bad type.\n");
1640		return;
1641	}
1642
1643	add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1644
1645	/* Input ctx add_flags are the endpoint index plus one */
1646	ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1647
1648	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1649	trace_xhci_handle_cmd_config_ep(ep_ctx);
1650
1651	return;
1652}
1653
1654static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1655{
1656	struct xhci_virt_device *vdev;
1657	struct xhci_slot_ctx *slot_ctx;
1658
1659	vdev = xhci->devs[slot_id];
1660	if (!vdev)
1661		return;
1662	slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1663	trace_xhci_handle_cmd_addr_dev(slot_ctx);
1664}
1665
1666static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1667{
1668	struct xhci_virt_device *vdev;
1669	struct xhci_slot_ctx *slot_ctx;
1670
1671	vdev = xhci->devs[slot_id];
1672	if (!vdev) {
1673		xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1674			  slot_id);
1675		return;
1676	}
1677	slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1678	trace_xhci_handle_cmd_reset_dev(slot_ctx);
1679
1680	xhci_dbg(xhci, "Completed reset device command.\n");
1681}
1682
1683static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1684		struct xhci_event_cmd *event)
1685{
1686	if (!(xhci->quirks & XHCI_NEC_HOST)) {
1687		xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1688		return;
1689	}
1690	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1691			"NEC firmware version %2x.%02x",
1692			NEC_FW_MAJOR(le32_to_cpu(event->status)),
1693			NEC_FW_MINOR(le32_to_cpu(event->status)));
1694}
1695
1696static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 comp_code, u32 comp_param)
1697{
1698	list_del(&cmd->cmd_list);
1699
1700	if (cmd->completion) {
1701		cmd->status = comp_code;
1702		cmd->comp_param = comp_param;
1703		complete(cmd->completion);
1704	} else {
1705		kfree(cmd);
1706	}
1707}
1708
1709void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1710{
1711	struct xhci_command *cur_cmd, *tmp_cmd;
1712	xhci->current_cmd = NULL;
1713	list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1714		xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED, 0);
1715}
1716
1717void xhci_handle_command_timeout(struct work_struct *work)
1718{
1719	struct xhci_hcd	*xhci;
1720	unsigned long	flags;
1721	char		str[XHCI_MSG_MAX];
1722	u64		hw_ring_state;
1723	u32		cmd_field3;
1724	u32		usbsts;
1725
1726	xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1727
1728	spin_lock_irqsave(&xhci->lock, flags);
1729
1730	/*
1731	 * If timeout work is pending, or current_cmd is NULL, it means we
1732	 * raced with command completion. Command is handled so just return.
1733	 */
1734	if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1735		spin_unlock_irqrestore(&xhci->lock, flags);
1736		return;
1737	}
1738
1739	cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1740	usbsts = readl(&xhci->op_regs->status);
1741	xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1742
1743	/* Bail out and tear down xhci if a stop endpoint command failed */
1744	if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1745		struct xhci_virt_ep	*ep;
1746
1747		xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1748
1749		ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1750				      TRB_TO_EP_INDEX(cmd_field3));
1751		if (ep)
1752			ep->ep_state &= ~EP_STOP_CMD_PENDING;
1753
1754		xhci_halt(xhci);
1755		xhci_hc_died(xhci);
1756		goto time_out_completed;
1757	}
1758
1759	/* mark this command to be cancelled */
1760	xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1761
1762	/* Make sure command ring is running before aborting it */
1763	hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1764	if (hw_ring_state == ~(u64)0) {
1765		xhci_hc_died(xhci);
1766		goto time_out_completed;
1767	}
1768
1769	if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1770	    (hw_ring_state & CMD_RING_RUNNING))  {
1771		/* Prevent new doorbell, and start command abort */
1772		xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1773		xhci_dbg(xhci, "Command timeout\n");
1774		xhci_abort_cmd_ring(xhci, flags);
1775		goto time_out_completed;
1776	}
1777
1778	/* host removed. Bail out */
1779	if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1780		xhci_dbg(xhci, "host removed, ring start fail?\n");
1781		xhci_cleanup_command_queue(xhci);
1782
1783		goto time_out_completed;
1784	}
1785
1786	/* command timeout on stopped ring, ring can't be aborted */
1787	xhci_dbg(xhci, "Command timeout on stopped ring\n");
1788	xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1789
1790time_out_completed:
1791	spin_unlock_irqrestore(&xhci->lock, flags);
1792	return;
1793}
1794
1795static void handle_cmd_completion(struct xhci_hcd *xhci,
1796		struct xhci_event_cmd *event)
1797{
1798	unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1799	u32 status = le32_to_cpu(event->status);
1800	u64 cmd_dma;
1801	dma_addr_t cmd_dequeue_dma;
1802	u32 cmd_comp_code;
1803	union xhci_trb *cmd_trb;
1804	struct xhci_command *cmd;
1805	u32 cmd_type;
1806
1807	if (slot_id >= MAX_HC_SLOTS) {
1808		xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1809		return;
1810	}
1811
1812	cmd_dma = le64_to_cpu(event->cmd_trb);
1813	cmd_trb = xhci->cmd_ring->dequeue;
1814
1815	trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic, cmd_dma);
1816
1817	cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1818
1819	/* If CMD ring stopped we own the trbs between enqueue and dequeue */
1820	if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1821		complete_all(&xhci->cmd_ring_stop_completion);
1822		return;
1823	}
1824
1825	cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1826			cmd_trb);
1827	/*
1828	 * Check whether the completion event is for our internal kept
1829	 * command.
1830	 */
1831	if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1832		xhci_warn(xhci,
1833			  "ERROR mismatched command completion event\n");
1834		return;
1835	}
1836
1837	cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1838
1839	cancel_delayed_work(&xhci->cmd_timer);
1840
1841	if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1842		xhci_err(xhci,
1843			 "Command completion event does not match command\n");
1844		return;
1845	}
1846
1847	/*
1848	 * Host aborted the command ring, check if the current command was
1849	 * supposed to be aborted, otherwise continue normally.
1850	 * The command ring is stopped now, but the xHC will issue a Command
1851	 * Ring Stopped event which will cause us to restart it.
1852	 */
1853	if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1854		xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1855		if (cmd->status == COMP_COMMAND_ABORTED) {
1856			if (xhci->current_cmd == cmd)
1857				xhci->current_cmd = NULL;
1858			goto event_handled;
1859		}
1860	}
1861
1862	cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1863	switch (cmd_type) {
1864	case TRB_ENABLE_SLOT:
1865		xhci_handle_cmd_enable_slot(slot_id, cmd, cmd_comp_code);
1866		break;
1867	case TRB_DISABLE_SLOT:
1868		xhci_handle_cmd_disable_slot(xhci, slot_id, cmd_comp_code);
1869		break;
1870	case TRB_CONFIG_EP:
1871		if (!cmd->completion)
1872			xhci_handle_cmd_config_ep(xhci, slot_id);
1873		break;
1874	case TRB_EVAL_CONTEXT:
1875		break;
1876	case TRB_ADDR_DEV:
1877		xhci_handle_cmd_addr_dev(xhci, slot_id);
1878		break;
1879	case TRB_STOP_RING:
1880		WARN_ON(slot_id != TRB_TO_SLOT_ID(
1881				le32_to_cpu(cmd_trb->generic.field[3])));
1882		if (!cmd->completion)
1883			xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1884						cmd_comp_code);
1885		break;
1886	case TRB_SET_DEQ:
1887		WARN_ON(slot_id != TRB_TO_SLOT_ID(
1888				le32_to_cpu(cmd_trb->generic.field[3])));
1889		xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1890		break;
1891	case TRB_CMD_NOOP:
1892		/* Is this an aborted command turned to NO-OP? */
1893		if (cmd->status == COMP_COMMAND_RING_STOPPED)
1894			cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1895		break;
1896	case TRB_RESET_EP:
1897		WARN_ON(slot_id != TRB_TO_SLOT_ID(
1898				le32_to_cpu(cmd_trb->generic.field[3])));
1899		xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1900		break;
1901	case TRB_RESET_DEV:
1902		/* SLOT_ID field in reset device cmd completion event TRB is 0.
1903		 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1904		 */
1905		slot_id = TRB_TO_SLOT_ID(
1906				le32_to_cpu(cmd_trb->generic.field[3]));
1907		xhci_handle_cmd_reset_dev(xhci, slot_id);
1908		break;
1909	case TRB_NEC_GET_FW:
1910		xhci_handle_cmd_nec_get_fw(xhci, event);
1911		break;
1912	case TRB_GET_BW:
1913		break;
1914	default:
1915		/* Skip over unknown commands on the event ring */
1916		xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1917		break;
1918	}
1919
1920	/* restart timer if this wasn't the last command */
1921	if (!list_is_singular(&xhci->cmd_list)) {
1922		xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1923						struct xhci_command, cmd_list);
1924		xhci_mod_cmd_timer(xhci);
1925	} else if (xhci->current_cmd == cmd) {
1926		xhci->current_cmd = NULL;
1927	}
1928
1929event_handled:
1930	xhci_complete_del_and_free_cmd(cmd, cmd_comp_code, COMP_PARAM(status));
1931
1932	inc_deq(xhci, xhci->cmd_ring);
1933}
1934
1935static void handle_vendor_event(struct xhci_hcd *xhci,
1936				union xhci_trb *event, u32 trb_type)
1937{
1938	xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1939	if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1940		handle_cmd_completion(xhci, &event->event_cmd);
1941}
1942
1943static void handle_device_notification(struct xhci_hcd *xhci,
1944		union xhci_trb *event)
1945{
1946	u32 slot_id;
1947	struct usb_device *udev;
1948
1949	slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1950	if (!xhci->devs[slot_id]) {
1951		xhci_warn(xhci, "Device Notification event for "
1952				"unused slot %u\n", slot_id);
1953		return;
1954	}
1955
1956	xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1957			slot_id);
1958	udev = xhci->devs[slot_id]->udev;
1959	if (udev && udev->parent)
1960		usb_wakeup_notification(udev->parent, udev->portnum);
1961}
1962
1963/*
1964 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1965 * Controller.
1966 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1967 * If a connection to a USB 1 device is followed by another connection
1968 * to a USB 2 device.
1969 *
1970 * Reset the PHY after the USB device is disconnected if device speed
1971 * is less than HCD_USB3.
1972 * Retry the reset sequence max of 4 times checking the PLL lock status.
1973 *
1974 */
1975static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1976{
1977	struct usb_hcd *hcd = xhci_to_hcd(xhci);
1978	u32 pll_lock_check;
1979	u32 retry_count = 4;
1980
1981	do {
1982		/* Assert PHY reset */
1983		writel(0x6F, hcd->regs + 0x1048);
1984		udelay(10);
1985		/* De-assert the PHY reset */
1986		writel(0x7F, hcd->regs + 0x1048);
1987		udelay(200);
1988		pll_lock_check = readl(hcd->regs + 0x1070);
1989	} while (!(pll_lock_check & 0x1) && --retry_count);
1990}
1991
1992static void handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event)
1993{
1994	struct xhci_virt_device *vdev = NULL;
1995	struct usb_hcd *hcd;
1996	u32 port_id;
1997	u32 portsc, cmd_reg;
1998	unsigned int hcd_portnum;
1999	struct xhci_bus_state *bus_state;
2000	bool bogus_port_status = false;
2001	struct xhci_port *port;
2002
2003	/* Port status change events always have a successful completion code */
2004	if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
2005		xhci_warn(xhci,
2006			  "WARN: xHC returned failed port status event\n");
2007
2008	port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
2009
2010	if ((port_id <= 0) || (port_id > xhci->max_ports)) {
2011		xhci_warn(xhci, "Port change event with invalid port ID %d\n",
2012			  port_id);
2013		return;
2014	}
2015
2016	port = &xhci->hw_ports[port_id - 1];
2017	if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
2018		xhci_warn(xhci, "Port change event, no port for port ID %u\n",
2019			  port_id);
2020		bogus_port_status = true;
2021		goto cleanup;
2022	}
2023
2024	if (port->slot_id)
2025		vdev = xhci->devs[port->slot_id];
2026
2027	/* We might get interrupts after shared_hcd is removed */
2028	if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
2029		xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
2030		bogus_port_status = true;
2031		goto cleanup;
2032	}
2033
2034	hcd = port->rhub->hcd;
2035	bus_state = &port->rhub->bus_state;
2036	hcd_portnum = port->hcd_portnum;
2037	portsc = xhci_portsc_readl(port);
2038
2039	xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
2040		 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
2041
2042	trace_xhci_handle_port_status(port, portsc);
2043
2044	if (hcd->state == HC_STATE_SUSPENDED) {
2045		xhci_dbg(xhci, "resume root hub\n");
2046		usb_hcd_resume_root_hub(hcd);
2047	}
2048
2049	if (vdev && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
2050		if (!(portsc & PORT_RESET))
2051			vdev->flags |= VDEV_PORT_ERROR;
2052	} else if (vdev && portsc & PORT_RC) {
2053		vdev->flags &= ~VDEV_PORT_ERROR;
2054	}
2055
2056	if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
2057		xhci_dbg(xhci, "port resume event for port %d\n", port_id);
2058
2059		cmd_reg = readl(&xhci->op_regs->command);
2060		if (!(cmd_reg & CMD_RUN)) {
2061			xhci_warn(xhci, "xHC is not running.\n");
2062			goto cleanup;
2063		}
2064
2065		if (DEV_SUPERSPEED_ANY(portsc)) {
2066			xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
2067			/* Set a flag to say the port signaled remote wakeup,
2068			 * so we can tell the difference between the end of
2069			 * device and host initiated resume.
2070			 */
2071			bus_state->port_remote_wakeup |= 1 << hcd_portnum;
2072			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2073			usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
2074			xhci_set_link_state(xhci, port, XDEV_U0);
2075			/* Need to wait until the next link state change
2076			 * indicates the device is actually in U0.
2077			 */
2078			bogus_port_status = true;
2079			goto cleanup;
2080		} else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
2081			xhci_dbg(xhci, "resume HS port %d\n", port_id);
2082			port->resume_timestamp = jiffies +
2083				msecs_to_jiffies(USB_RESUME_TIMEOUT);
2084			set_bit(hcd_portnum, &bus_state->resuming_ports);
2085			/* Do the rest in GetPortStatus after resume time delay.
2086			 * Avoid polling roothub status before that so that a
2087			 * usb device auto-resume latency around ~40ms.
2088			 */
2089			set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2090			mod_timer(&hcd->rh_timer,
2091				  port->resume_timestamp);
2092			usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
2093			bogus_port_status = true;
2094		}
2095	}
2096
2097	if ((portsc & PORT_PLC) &&
2098	    DEV_SUPERSPEED_ANY(portsc) &&
2099	    ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
2100	     (portsc & PORT_PLS_MASK) == XDEV_U1 ||
2101	     (portsc & PORT_PLS_MASK) == XDEV_U2)) {
2102		xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
2103		complete(&port->u3exit_done);
2104		/* We've just brought the device into U0/1/2 through either the
2105		 * Resume state after a device remote wakeup, or through the
2106		 * U3Exit state after a host-initiated resume.  If it's a device
2107		 * initiated remote wake, don't pass up the link state change,
2108		 * so the roothub behavior is consistent with external
2109		 * USB 3.0 hub behavior.
2110		 */
2111		if (vdev)
2112			xhci_ring_device(xhci, port->slot_id);
2113		if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
2114			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2115			usb_wakeup_notification(hcd->self.root_hub,
2116					hcd_portnum + 1);
2117			bogus_port_status = true;
2118			goto cleanup;
2119		}
2120	}
2121
2122	/*
2123	 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
2124	 * RExit to a disconnect state).  If so, let the driver know it's
2125	 * out of the RExit state.
2126	 */
2127	if (hcd->speed < HCD_USB3 && port->rexit_active) {
2128		complete(&port->rexit_done);
2129		port->rexit_active = false;
2130		bogus_port_status = true;
2131		goto cleanup;
2132	}
2133
2134	if (hcd->speed < HCD_USB3) {
2135		xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2136		if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
2137		    (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
2138			xhci_cavium_reset_phy_quirk(xhci);
2139	}
2140
2141cleanup:
2142
2143	/* Don't make the USB core poll the roothub if we got a bad port status
2144	 * change event.  Besides, at that point we can't tell which roothub
2145	 * (USB 2.0 or USB 3.0) to kick.
2146	 */
2147	if (bogus_port_status)
2148		return;
2149
2150	/*
2151	 * xHCI port-status-change events occur when the "or" of all the
2152	 * status-change bits in the portsc register changes from 0 to 1.
2153	 * New status changes won't cause an event if any other change
2154	 * bits are still set.  When an event occurs, switch over to
2155	 * polling to avoid losing status changes.
2156	 */
2157	xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2158		 __func__, hcd->self.busnum);
2159	set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2160	spin_unlock(&xhci->lock);
2161	/* Pass this up to the core */
2162	usb_hcd_poll_rh_status(hcd);
2163	spin_lock(&xhci->lock);
2164}
2165
2166static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2167		struct xhci_virt_ep *ep)
2168{
2169	/*
2170	 * As part of low/full-speed endpoint-halt processing
2171	 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2172	 */
2173	if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2174	    (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2175	    !(ep->ep_state & EP_CLEARING_TT)) {
2176		ep->ep_state |= EP_CLEARING_TT;
2177		td->urb->ep->hcpriv = td->urb->dev;
2178		if (usb_hub_clear_tt_buffer(td->urb))
2179			ep->ep_state &= ~EP_CLEARING_TT;
2180	}
2181}
2182
2183/*
2184 * Check if xhci internal endpoint state has gone to a "halt" state due to an
2185 * error or stall, including default control pipe protocol stall.
2186 * The internal halt needs to be cleared with a reset endpoint command.
2187 *
2188 * External device side is also halted in functional stall cases. Class driver
2189 * will clear the device halt with a CLEAR_FEATURE(ENDPOINT_HALT) request later.
2190 */
2191static bool xhci_halted_host_endpoint(struct xhci_hcd *xhci, struct xhci_ep_ctx *ep_ctx,
2192				      unsigned int comp_code)
2193{
2194	int ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
2195
2196	switch (comp_code) {
2197	case COMP_STALL_ERROR:
2198		/* on xHCI this always halts, including protocol stall */
2199		return true;
2200	case COMP_BABBLE_DETECTED_ERROR:
2201		/*
2202		 * The 0.95 spec says a babbling control endpoint is not halted.
2203		 * The 0.96 spec says it is. Some HW claims to be 0.95
2204		 * compliant, but it halts the control endpoint anyway.
2205		 * Check endpoint context if endpoint is halted.
2206		 */
2207		if (xhci->hci_version <= 0x95 && ep_type == CTRL_EP)
2208			return GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED;
2209
2210		fallthrough;
2211	case COMP_USB_TRANSACTION_ERROR:
2212	case COMP_SPLIT_TRANSACTION_ERROR:
2213		/* these errors halt all non-isochronous endpoints */
2214		return ep_type != ISOC_IN_EP && ep_type != ISOC_OUT_EP;
2215	}
2216
2217	return false;
2218}
2219
2220int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2221{
2222	if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2223		/* Vendor defined "informational" completion code,
2224		 * treat as not-an-error.
2225		 */
2226		xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2227				trb_comp_code);
2228		xhci_dbg(xhci, "Treating code as success.\n");
2229		return 1;
2230	}
2231	return 0;
2232}
2233
2234static void finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2235		      struct xhci_ring *ep_ring, struct xhci_td *td,
2236		      u32 trb_comp_code)
2237{
2238	struct xhci_ep_ctx *ep_ctx;
2239
2240	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2241
2242	switch (trb_comp_code) {
2243	case COMP_STOPPED_LENGTH_INVALID:
2244	case COMP_STOPPED_SHORT_PACKET:
2245	case COMP_STOPPED:
2246		/*
2247		 * The "Stop Endpoint" completion will take care of any
2248		 * stopped TDs. A stopped TD may be restarted, so don't update
2249		 * the ring dequeue pointer or take this TD off any lists yet.
2250		 */
2251		return;
2252	}
2253
2254	if (xhci_halted_host_endpoint(xhci, ep_ctx, trb_comp_code)) {
2255		/*
2256		 * xhci internal endpoint state will go to a "halt" state for
2257		 * any stall, including default control pipe protocol stall.
2258		 * To clear the host side halt we need to issue a reset endpoint
2259		 * command, followed by a set dequeue command to move past the
2260		 * TD.
2261		 * Class drivers clear the device side halt from a functional
2262		 * stall later. Hub TT buffer should only be cleared for FS/LS
2263		 * devices behind HS hubs for functional stalls.
2264		 */
2265		if (!(ep->ep_index == 0 && trb_comp_code == COMP_STALL_ERROR))
2266			xhci_clear_hub_tt_buffer(xhci, td, ep);
2267
2268		xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2269
2270		return; /* xhci_handle_halted_endpoint marked td cancelled */
2271	}
2272
2273	xhci_dequeue_td(xhci, td, ep_ring, td->status);
2274}
2275
2276/* sum trb lengths from the first trb up to stop_trb, _excluding_ stop_trb */
2277static u32 sum_trb_lengths(struct xhci_td *td, union xhci_trb *stop_trb)
2278{
2279	u32 sum;
2280	union xhci_trb *trb = td->start_trb;
2281	struct xhci_segment *seg = td->start_seg;
2282
2283	for (sum = 0; trb != stop_trb; next_trb(&seg, &trb)) {
2284		if (!trb_is_noop(trb) && !trb_is_link(trb))
2285			sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2286	}
2287	return sum;
2288}
2289
2290/*
2291 * Process control tds, update urb status and actual_length.
2292 */
2293static void process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2294			    struct xhci_ring *ep_ring,  struct xhci_td *td,
2295			    union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2296{
2297	struct xhci_ep_ctx *ep_ctx;
2298	u32 trb_comp_code;
2299	u32 remaining, requested;
2300	u32 trb_type;
2301
2302	trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2303	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2304	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2305	requested = td->urb->transfer_buffer_length;
2306	remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2307
2308	switch (trb_comp_code) {
2309	case COMP_SUCCESS:
2310		if (trb_type != TRB_STATUS) {
2311			xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2312				  (trb_type == TRB_DATA) ? "data" : "setup");
2313			td->status = -ESHUTDOWN;
2314			break;
2315		}
2316		td->status = 0;
2317		break;
2318	case COMP_SHORT_PACKET:
2319		td->status = 0;
2320		break;
2321	case COMP_STOPPED_SHORT_PACKET:
2322		if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2323			td->urb->actual_length = remaining;
2324		else
2325			xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2326		goto finish_td;
2327	case COMP_STOPPED:
2328		switch (trb_type) {
2329		case TRB_SETUP:
2330			td->urb->actual_length = 0;
2331			goto finish_td;
2332		case TRB_DATA:
2333		case TRB_NORMAL:
2334			td->urb->actual_length = requested - remaining;
2335			goto finish_td;
2336		case TRB_STATUS:
2337			td->urb->actual_length = requested;
2338			goto finish_td;
2339		default:
2340			xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2341				  trb_type);
2342			goto finish_td;
2343		}
2344	case COMP_STOPPED_LENGTH_INVALID:
2345		goto finish_td;
2346	default:
2347		if (!xhci_halted_host_endpoint(xhci, ep_ctx, trb_comp_code))
2348			break;
2349		xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2350			 trb_comp_code, ep->ep_index);
2351		fallthrough;
2352	case COMP_STALL_ERROR:
2353		/* Did we transfer part of the data (middle) phase? */
2354		if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2355			td->urb->actual_length = requested - remaining;
2356		else if (!td->urb_length_set)
2357			td->urb->actual_length = 0;
2358		goto finish_td;
2359	}
2360
2361	/* stopped at setup stage, no data transferred */
2362	if (trb_type == TRB_SETUP)
2363		goto finish_td;
2364
2365	/*
2366	 * if on data stage then update the actual_length of the URB and flag it
2367	 * as set, so it won't be overwritten in the event for the last TRB.
2368	 */
2369	if (trb_type == TRB_DATA ||
2370		trb_type == TRB_NORMAL) {
2371		td->urb_length_set = true;
2372		td->urb->actual_length = requested - remaining;
2373		xhci_dbg(xhci, "Waiting for status stage event\n");
2374		return;
2375	}
2376
2377	/* at status stage */
2378	if (!td->urb_length_set)
2379		td->urb->actual_length = requested;
2380
2381finish_td:
2382	finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2383}
2384
2385/*
2386 * Process isochronous tds, update urb packet status and actual_length.
2387 */
2388static void process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2389			    struct xhci_ring *ep_ring, struct xhci_td *td,
2390			    union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2391{
2392	struct urb_priv *urb_priv;
2393	int idx;
2394	struct usb_iso_packet_descriptor *frame;
2395	u32 trb_comp_code;
2396	bool sum_trbs_for_length = false;
2397	u32 remaining, requested, ep_trb_len;
2398	int short_framestatus;
2399
2400	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2401	urb_priv = td->urb->hcpriv;
2402	idx = urb_priv->num_tds_done;
2403	frame = &td->urb->iso_frame_desc[idx];
2404	requested = frame->length;
2405	remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2406	ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2407	short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2408		-EREMOTEIO : 0;
2409
2410	/* handle completion code */
2411	switch (trb_comp_code) {
2412	case COMP_SUCCESS:
2413		/* Don't overwrite status if TD had an error, see xHCI 4.9.1 */
2414		if (td->error_mid_td)
2415			break;
2416		if (remaining) {
2417			frame->status = short_framestatus;
2418			sum_trbs_for_length = true;
2419			break;
2420		}
2421		frame->status = 0;
2422		break;
2423	case COMP_SHORT_PACKET:
2424		frame->status = short_framestatus;
2425		sum_trbs_for_length = true;
2426		break;
2427	case COMP_BANDWIDTH_OVERRUN_ERROR:
2428		frame->status = -ECOMM;
2429		break;
2430	case COMP_BABBLE_DETECTED_ERROR:
2431		sum_trbs_for_length = true;
2432		fallthrough;
2433	case COMP_ISOCH_BUFFER_OVERRUN:
2434		frame->status = -EOVERFLOW;
2435		if (ep_trb != td->end_trb)
2436			td->error_mid_td = true;
2437		break;
2438	case COMP_MISSED_SERVICE_ERROR:
2439		frame->status = -EXDEV;
2440		sum_trbs_for_length = true;
2441		if (ep_trb != td->end_trb)
2442			td->error_mid_td = true;
2443		break;
2444	case COMP_INCOMPATIBLE_DEVICE_ERROR:
2445	case COMP_STALL_ERROR:
2446		frame->status = -EPROTO;
2447		break;
2448	case COMP_USB_TRANSACTION_ERROR:
2449		frame->status = -EPROTO;
2450		sum_trbs_for_length = true;
2451		if (ep_trb != td->end_trb)
2452			td->error_mid_td = true;
2453		break;
2454	case COMP_STOPPED:
2455		sum_trbs_for_length = true;
2456		break;
2457	case COMP_STOPPED_SHORT_PACKET:
2458		/* field normally containing residue now contains transferred */
2459		frame->status = short_framestatus;
2460		requested = remaining;
2461		break;
2462	case COMP_STOPPED_LENGTH_INVALID:
2463		/* exclude stopped trb with invalid length from length sum */
2464		sum_trbs_for_length = true;
2465		ep_trb_len = 0;
2466		remaining = 0;
2467		break;
2468	default:
2469		sum_trbs_for_length = true;
2470		frame->status = -1;
2471		break;
2472	}
2473
2474	if (td->urb_length_set)
2475		goto finish_td;
2476
2477	if (sum_trbs_for_length)
2478		frame->actual_length = sum_trb_lengths(td, ep_trb) +
2479			ep_trb_len - remaining;
2480	else
2481		frame->actual_length = requested;
2482
2483	td->urb->actual_length += frame->actual_length;
2484
2485finish_td:
2486	/* Don't give back TD yet if we encountered an error mid TD */
2487	if (td->error_mid_td && ep_trb != td->end_trb) {
2488		xhci_dbg(xhci, "Error mid isoc TD, wait for final completion event\n");
2489		td->urb_length_set = true;
2490		return;
2491	}
2492	finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2493}
2494
2495static void skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2496			 struct xhci_virt_ep *ep, int status)
2497{
2498	struct urb_priv *urb_priv;
2499	struct usb_iso_packet_descriptor *frame;
2500	int idx;
2501
2502	urb_priv = td->urb->hcpriv;
2503	idx = urb_priv->num_tds_done;
2504	frame = &td->urb->iso_frame_desc[idx];
2505
2506	/* The transfer is partly done. */
2507	frame->status = -EXDEV;
2508
2509	/* calc actual length */
2510	frame->actual_length = 0;
2511
2512	xhci_dequeue_td(xhci, td, ep->ring, status);
2513}
2514
2515/*
2516 * Process bulk and interrupt tds, update urb status and actual_length.
2517 */
2518static void process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2519				 struct xhci_ring *ep_ring, struct xhci_td *td,
2520				 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2521{
2522	struct xhci_slot_ctx *slot_ctx;
2523	u32 trb_comp_code;
2524	u32 remaining, requested, ep_trb_len;
2525
2526	slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2527	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2528	remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2529	ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2530	requested = td->urb->transfer_buffer_length;
2531
2532	switch (trb_comp_code) {
2533	case COMP_SUCCESS:
2534		ep->err_count = 0;
2535		/* handle success with untransferred data as short packet */
2536		if (ep_trb != td->end_trb || remaining) {
2537			xhci_warn(xhci, "WARN Successful completion on short TX\n");
2538			xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2539				 td->urb->ep->desc.bEndpointAddress,
2540				 requested, remaining);
2541		}
2542		td->status = 0;
2543		break;
2544	case COMP_SHORT_PACKET:
2545		td->status = 0;
2546		break;
2547	case COMP_STOPPED_SHORT_PACKET:
2548		td->urb->actual_length = remaining;
2549		goto finish_td;
2550	case COMP_STOPPED_LENGTH_INVALID:
2551		/* stopped on ep trb with invalid length, exclude it */
2552		td->urb->actual_length = sum_trb_lengths(td, ep_trb);
2553		goto finish_td;
2554	case COMP_USB_TRANSACTION_ERROR:
2555		if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2556		    (ep->err_count++ > MAX_SOFT_RETRY) ||
2557		    le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2558			break;
2559
2560		td->status = 0;
2561
2562		xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2563		return;
2564	default:
2565		/* do nothing */
2566		break;
2567	}
2568
2569	if (ep_trb == td->end_trb)
2570		td->urb->actual_length = requested - remaining;
2571	else
2572		td->urb->actual_length =
2573			sum_trb_lengths(td, ep_trb) +
2574			ep_trb_len - remaining;
2575finish_td:
2576	if (remaining > requested) {
2577		xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2578			  remaining);
2579		td->urb->actual_length = 0;
2580	}
2581
2582	finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2583}
2584
2585/* Transfer events which don't point to a transfer TRB, see xhci 4.17.4 */
2586static int handle_transferless_tx_event(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2587					u32 trb_comp_code)
2588{
2589	switch (trb_comp_code) {
2590	case COMP_STALL_ERROR:
2591	case COMP_USB_TRANSACTION_ERROR:
2592	case COMP_INVALID_STREAM_TYPE_ERROR:
2593	case COMP_INVALID_STREAM_ID_ERROR:
2594		xhci_dbg(xhci, "Stream transaction error ep %u no id\n", ep->ep_index);
2595		if (ep->err_count++ > MAX_SOFT_RETRY)
2596			xhci_handle_halted_endpoint(xhci, ep, NULL, EP_HARD_RESET);
2597		else
2598			xhci_handle_halted_endpoint(xhci, ep, NULL, EP_SOFT_RESET);
2599		break;
2600	case COMP_RING_UNDERRUN:
2601	case COMP_RING_OVERRUN:
2602	case COMP_STOPPED_LENGTH_INVALID:
2603		break;
2604	default:
2605		xhci_err(xhci, "Transfer event %u for unknown stream ring slot %u ep %u\n",
2606			 trb_comp_code, ep->vdev->slot_id, ep->ep_index);
2607		return -ENODEV;
2608	}
2609	return 0;
2610}
2611
2612static bool xhci_spurious_success_tx_event(struct xhci_hcd *xhci,
2613					   struct xhci_ring *ring)
2614{
2615	switch (ring->old_trb_comp_code) {
2616	case COMP_SHORT_PACKET:
2617		return xhci->quirks & XHCI_SPURIOUS_SUCCESS;
2618	case COMP_USB_TRANSACTION_ERROR:
2619	case COMP_BABBLE_DETECTED_ERROR:
2620	case COMP_ISOCH_BUFFER_OVERRUN:
2621		return xhci->quirks & XHCI_ETRON_HOST &&
2622			ring->type == TYPE_ISOC;
2623	default:
2624		return false;
2625	}
2626}
2627
2628/*
2629 * If this function returns an error condition, it means it got a Transfer
2630 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2631 * At this point, the host controller is probably hosed and should be reset.
2632 */
2633static int handle_tx_event(struct xhci_hcd *xhci,
2634			   struct xhci_interrupter *ir,
2635			   struct xhci_transfer_event *event)
2636{
2637	struct xhci_virt_ep *ep;
2638	struct xhci_ring *ep_ring;
2639	unsigned int slot_id;
2640	int ep_index;
2641	struct xhci_td *td = NULL;
2642	dma_addr_t ep_trb_dma;
2643	union xhci_trb *ep_trb;
2644	int status = -EINPROGRESS;
2645	struct xhci_ep_ctx *ep_ctx;
2646	u32 trb_comp_code;
2647	bool ring_xrun_event = false;
2648
2649	slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2650	ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2651	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2652	ep_trb_dma = le64_to_cpu(event->buffer);
2653
2654	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2655	if (!ep) {
2656		xhci_err(xhci, "ERROR Invalid Transfer event\n");
2657		goto err_out;
2658	}
2659
2660	ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2661	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2662
2663	if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2664		xhci_err(xhci,
2665			 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2666			  slot_id, ep_index);
2667		goto err_out;
2668	}
2669
2670	if (!ep_ring)
2671		return handle_transferless_tx_event(xhci, ep, trb_comp_code);
2672
2673	/* find the transfer trb this events points to */
2674	ep_trb = xhci_dma_to_trb(ep_ring->deq_seg, ep_trb_dma, NULL);
2675
2676	/* Look for common error cases */
2677	switch (trb_comp_code) {
2678	/* Skip codes that require special handling depending on
2679	 * transfer type
2680	 */
2681	case COMP_SUCCESS:
2682		if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2683			trb_comp_code = COMP_SHORT_PACKET;
2684			xhci_dbg(xhci, "Successful completion on short TX for slot %u ep %u with last td comp code %d\n",
2685				 slot_id, ep_index, ep_ring->old_trb_comp_code);
2686		}
2687		break;
2688	case COMP_SHORT_PACKET:
2689		break;
2690	/* Completion codes for endpoint stopped state */
2691	case COMP_STOPPED:
2692		xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2693			 slot_id, ep_index);
2694		break;
2695	case COMP_STOPPED_LENGTH_INVALID:
2696		xhci_dbg(xhci,
2697			 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2698			 slot_id, ep_index);
2699		break;
2700	case COMP_STOPPED_SHORT_PACKET:
2701		xhci_dbg(xhci,
2702			 "Stopped with short packet transfer detected for slot %u ep %u\n",
2703			 slot_id, ep_index);
2704		break;
2705	/* Completion codes for endpoint halted state */
2706	case COMP_STALL_ERROR:
2707		xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2708			 ep_index);
2709		status = -EPIPE;
2710		break;
2711	case COMP_SPLIT_TRANSACTION_ERROR:
2712		xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2713			 slot_id, ep_index);
2714		status = -EPROTO;
2715		break;
2716	case COMP_USB_TRANSACTION_ERROR:
2717		xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2718			 slot_id, ep_index);
2719		status = -EPROTO;
2720		break;
2721	case COMP_BABBLE_DETECTED_ERROR:
2722		xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2723			 slot_id, ep_index);
2724		status = -EOVERFLOW;
2725		break;
2726	/* Completion codes for endpoint error state */
2727	case COMP_TRB_ERROR:
2728		xhci_warn(xhci,
2729			  "WARN: TRB error for slot %u ep %u on endpoint\n",
2730			  slot_id, ep_index);
2731		status = -EILSEQ;
2732		break;
2733	/* completion codes not indicating endpoint state change */
2734	case COMP_DATA_BUFFER_ERROR:
2735		xhci_warn(xhci,
2736			  "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2737			  slot_id, ep_index);
2738		status = -ENOSR;
2739		break;
2740	case COMP_BANDWIDTH_OVERRUN_ERROR:
2741		xhci_warn(xhci,
2742			  "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2743			  slot_id, ep_index);
2744		break;
2745	case COMP_ISOCH_BUFFER_OVERRUN:
2746		xhci_warn(xhci,
2747			  "WARN: buffer overrun event for slot %u ep %u on endpoint",
2748			  slot_id, ep_index);
2749		break;
2750	case COMP_RING_UNDERRUN:
2751		/*
2752		 * When the Isoch ring is empty, the xHC will generate
2753		 * a Ring Overrun Event for IN Isoch endpoint or Ring
2754		 * Underrun Event for OUT Isoch endpoint.
2755		 */
2756		xhci_dbg(xhci, "Underrun event on slot %u ep %u\n", slot_id, ep_index);
2757		ring_xrun_event = true;
2758		break;
2759	case COMP_RING_OVERRUN:
2760		xhci_dbg(xhci, "Overrun event on slot %u ep %u\n", slot_id, ep_index);
2761		ring_xrun_event = true;
2762		break;
2763	case COMP_MISSED_SERVICE_ERROR:
2764		/*
2765		 * When encounter missed service error, one or more isoc tds
2766		 * may be missed by xHC.
2767		 * Set skip flag of the ep_ring; Complete the missed tds as
2768		 * short transfer when process the ep_ring next time.
2769		 */
2770		ep->skip = true;
2771		xhci_dbg(xhci,
2772			 "Miss service interval error for slot %u ep %u, set skip flag%s\n",
2773			 slot_id, ep_index, ep_trb_dma ? ", skip now" : "");
2774		break;
2775	case COMP_NO_PING_RESPONSE_ERROR:
2776		ep->skip = true;
2777		xhci_dbg(xhci,
2778			 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2779			 slot_id, ep_index);
2780		return 0;
2781
2782	case COMP_INCOMPATIBLE_DEVICE_ERROR:
2783		/* needs disable slot command to recover */
2784		xhci_warn(xhci,
2785			  "WARN: detect an incompatible device for slot %u ep %u",
2786			  slot_id, ep_index);
2787		status = -EPROTO;
2788		break;
2789	default:
2790		if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2791			status = 0;
2792			break;
2793		}
2794		xhci_warn(xhci,
2795			  "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2796			  trb_comp_code, slot_id, ep_index);
2797		if (ep->skip)
2798			break;
2799		return 0;
2800	}
2801
2802	/*
2803	 * xhci 4.10.2 states isoc endpoints should continue
2804	 * processing the next TD if there was an error mid TD.
2805	 * So host like NEC don't generate an event for the last
2806	 * isoc TRB even if the IOC flag is set.
2807	 * xhci 4.9.1 states that if there are errors in mult-TRB
2808	 * TDs xHC should generate an error for that TRB, and if xHC
2809	 * proceeds to the next TD it should genete an event for
2810	 * any TRB with IOC flag on the way. Other host follow this.
2811	 *
2812	 * We wait for the final IOC event, but if we get an event
2813	 * anywhere outside this TD, just give it back already.
2814	 */
2815	td = list_first_entry_or_null(&ep_ring->td_list, struct xhci_td, td_list);
2816
2817	if (td && td->error_mid_td && !trb_in_td(td, ep_trb_dma)) {
2818		xhci_dbg(xhci, "Missing TD completion event after mid TD error\n");
2819		xhci_dequeue_td(xhci, td, ep_ring, td->status);
2820	}
2821
2822	/* If the TRB pointer is NULL, missed TDs will be skipped on the next event */
2823	if (trb_comp_code == COMP_MISSED_SERVICE_ERROR && !ep_trb_dma)
2824		return 0;
2825
2826	if (list_empty(&ep_ring->td_list)) {
2827		/*
2828		 * Don't print wanings if ring is empty due to a stopped endpoint generating an
2829		 * extra completion event if the device was suspended. Or, a event for the last TRB
2830		 * of a short TD we already got a short event for. The short TD is already removed
2831		 * from the TD list.
2832		 */
2833		if (trb_comp_code != COMP_STOPPED &&
2834		    trb_comp_code != COMP_STOPPED_LENGTH_INVALID &&
2835		    !ring_xrun_event &&
2836		    !xhci_spurious_success_tx_event(xhci, ep_ring)) {
2837			xhci_warn(xhci, "Event TRB for slot %u ep %u with no TDs queued\n",
2838				  slot_id, ep_index);
2839		}
2840
2841		ep->skip = false;
2842		goto check_endpoint_halted;
2843	}
2844
2845	do {
2846		td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2847				      td_list);
2848
2849		/* Is this TRB not part of the currently executing TD? */
2850		if (!trb_in_td(td, ep_trb_dma)) {
2851
2852			if (ep->skip && usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2853				/* this event is unlikely to match any TD, don't skip them all */
2854				if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID)
2855					return 0;
2856
2857				skip_isoc_td(xhci, td, ep, status);
2858
2859				if (!list_empty(&ep_ring->td_list)) {
2860					if (ring_xrun_event) {
2861						/*
2862						 * If we are here, we are on xHCI 1.0 host with no
2863						 * idea how many TDs were missed or where the xrun
2864						 * occurred. New TDs may have been added after the
2865						 * xrun, so skip only one TD to be safe.
2866						 */
2867						xhci_dbg(xhci, "Skipped one TD for slot %u ep %u",
2868								slot_id, ep_index);
2869						return 0;
2870					}
2871					continue;
2872				}
2873
2874				xhci_dbg(xhci, "All TDs skipped for slot %u ep %u. Clear skip flag.\n",
2875					 slot_id, ep_index);
2876				ep->skip = false;
2877				td = NULL;
2878				goto check_endpoint_halted;
2879			}
2880
2881			/* TD was queued after xrun, maybe xrun was on a link, don't panic yet */
2882			if (ring_xrun_event)
2883				return 0;
2884
2885			/*
2886			 * Skip the Force Stopped Event. The 'ep_trb' of FSE is not in the current
2887			 * TD pointed by 'ep_ring->dequeue' because that the hardware dequeue
2888			 * pointer still at the previous TRB of the current TD. The previous TRB
2889			 * maybe a Link TD or the last TRB of the previous TD. The command
2890			 * completion handle will take care the rest.
2891			 */
2892			if (trb_comp_code == COMP_STOPPED ||
2893			    trb_comp_code == COMP_STOPPED_LENGTH_INVALID) {
2894				return 0;
2895			}
2896
2897			/*
2898			 * Some hosts give a spurious success event after a short
2899			 * transfer or error on last TRB. Ignore it.
2900			 */
2901			if (xhci_spurious_success_tx_event(xhci, ep_ring)) {
2902				xhci_dbg(xhci, "Spurious event dma %pad, comp_code %u after %u\n",
2903					 &ep_trb_dma, trb_comp_code, ep_ring->old_trb_comp_code);
2904				ep_ring->old_trb_comp_code = 0;
2905				return 0;
2906			}
2907
2908			/* HC is busted, give up! */
2909			goto debug_finding_td;
2910		}
2911
2912		if (ep->skip) {
2913			xhci_dbg(xhci,
2914				 "Found td. Clear skip flag for slot %u ep %u.\n",
2915				 slot_id, ep_index);
2916			ep->skip = false;
2917		}
2918
2919	/*
2920	 * If ep->skip is set, it means there are missed tds on the
2921	 * endpoint ring need to take care of.
2922	 * Process them as short transfer until reach the td pointed by
2923	 * the event.
2924	 */
2925	} while (ep->skip);
2926
2927	ep_ring->old_trb_comp_code = trb_comp_code;
2928
2929	/* Get out if a TD was queued at enqueue after the xrun occurred */
2930	if (ring_xrun_event)
2931		return 0;
2932
2933	trace_xhci_handle_transfer(ep_ring, (struct xhci_generic_trb *) ep_trb, ep_trb_dma);
2934
2935	/*
2936	 * No-op TRB could trigger interrupts in a case where a URB was killed
2937	 * and a STALL_ERROR happens right after the endpoint ring stopped.
2938	 * Reset the halted endpoint. Otherwise, the endpoint remains stalled
2939	 * indefinitely.
2940	 */
2941
2942	if (trb_is_noop(ep_trb))
2943		goto check_endpoint_halted;
2944
2945	td->status = status;
2946
2947	/* update the urb's actual_length and give back to the core */
2948	if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2949		process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2950	else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2951		process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2952	else
2953		process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2954	return 0;
2955
2956check_endpoint_halted:
2957	if (xhci_halted_host_endpoint(xhci, ep_ctx, trb_comp_code))
2958		xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2959
2960	return 0;
2961
2962debug_finding_td:
2963	xhci_err(xhci, "Event dma %pad for ep %d status %d not part of TD at %016llx - %016llx\n",
2964		 &ep_trb_dma, ep_index, trb_comp_code,
2965		 (unsigned long long)xhci_trb_virt_to_dma(td->start_seg, td->start_trb),
2966		 (unsigned long long)xhci_trb_virt_to_dma(td->end_seg, td->end_trb));
2967
2968	return -ESHUTDOWN;
2969
2970err_out:
2971	xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2972		 (unsigned long long) xhci_trb_virt_to_dma(
2973			 ir->event_ring->deq_seg,
2974			 ir->event_ring->dequeue),
2975		 lower_32_bits(le64_to_cpu(event->buffer)),
2976		 upper_32_bits(le64_to_cpu(event->buffer)),
2977		 le32_to_cpu(event->transfer_len),
2978		 le32_to_cpu(event->flags));
2979	return -ENODEV;
2980}
2981
2982/*
2983 * This function handles one OS-owned event on the event ring. It may drop
2984 * xhci->lock between event processing (e.g. to pass up port status changes).
2985 */
2986static int xhci_handle_event_trb(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
2987				 union xhci_trb *event)
2988{
2989	u32 trb_type;
2990
2991	trace_xhci_handle_event(ir->event_ring, &event->generic,
2992				xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
2993						     ir->event_ring->dequeue));
2994
2995	/*
2996	 * Barrier between reading the TRB_CYCLE (valid) flag before, and any
2997	 * speculative reads of the event's flags/data below.
2998	 */
2999	rmb();
3000	trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
3001	/* FIXME: Handle more event types. */
3002
3003	switch (trb_type) {
3004	case TRB_COMPLETION:
3005		handle_cmd_completion(xhci, &event->event_cmd);
3006		break;
3007	case TRB_PORT_STATUS:
3008		handle_port_status(xhci, event);
3009		break;
3010	case TRB_TRANSFER:
3011		handle_tx_event(xhci, ir, &event->trans_event);
3012		break;
3013	case TRB_DEV_NOTE:
3014		handle_device_notification(xhci, event);
3015		break;
3016	default:
3017		if (trb_type >= TRB_VENDOR_DEFINED_LOW)
3018			handle_vendor_event(xhci, event, trb_type);
3019		else
3020			xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
3021	}
3022	/* Any of the above functions may drop and re-acquire the lock, so check
3023	 * to make sure a watchdog timer didn't mark the host as non-responsive.
3024	 */
3025	if (xhci->xhc_state & XHCI_STATE_DYING) {
3026		xhci_dbg(xhci, "xHCI host dying, returning from event handler.\n");
3027		return -ENODEV;
3028	}
3029
3030	return 0;
3031}
3032
3033/*
3034 * Update Event Ring Dequeue Pointer:
3035 * - When all events have finished
3036 * - To avoid "Event Ring Full Error" condition
3037 */
3038void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
3039			      struct xhci_interrupter *ir,
3040			      bool clear_ehb)
3041{
3042	u64 temp_64;
3043	dma_addr_t deq;
3044
3045	temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3046	deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
3047				   ir->event_ring->dequeue);
3048	if (deq == 0)
3049		xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
3050	/*
3051	 * Per 4.9.4, Software writes to the ERDP register shall always advance
3052	 * the Event Ring Dequeue Pointer value.
3053	 */
3054	if ((temp_64 & ERST_PTR_MASK) == (deq & ERST_PTR_MASK) && !clear_ehb)
3055		return;
3056
3057	/* Update HC event ring dequeue pointer */
3058	temp_64 = ir->event_ring->deq_seg->num & ERST_DESI_MASK;
3059	temp_64 |= deq & ERST_PTR_MASK;
3060
3061	/* Clear the event handler busy flag (RW1C) */
3062	if (clear_ehb)
3063		temp_64 |= ERST_EHB;
3064	xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue);
3065}
3066
3067/* Clear the interrupt pending bit for a specific interrupter. */
3068static void xhci_clear_interrupt_pending(struct xhci_interrupter *ir)
3069{
3070	if (!ir->ip_autoclear) {
3071		u32 iman;
3072
3073		iman = readl(&ir->ir_set->iman);
3074		iman |= IMAN_IP;
3075		writel(iman, &ir->ir_set->iman);
3076
3077		/* Read operation to guarantee the write has been flushed from posted buffers */
3078		readl(&ir->ir_set->iman);
3079	}
3080}
3081
3082/*
3083 * Handle all OS-owned events on an interrupter event ring. It may drop
3084 * and reaquire xhci->lock between event processing.
3085 */
3086static int xhci_handle_events(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
3087			      bool skip_events)
3088{
3089	int event_loop = 0;
3090	int err = 0;
3091	u64 temp;
3092
3093	xhci_clear_interrupt_pending(ir);
3094
3095	/* Event ring hasn't been allocated yet. */
3096	if (!ir->event_ring || !ir->event_ring->dequeue) {
3097		xhci_err(xhci, "ERROR interrupter event ring not ready\n");
3098		return -ENOMEM;
3099	}
3100
3101	if (xhci->xhc_state & XHCI_STATE_DYING ||
3102	    xhci->xhc_state & XHCI_STATE_HALTED) {
3103		xhci_dbg(xhci, "xHCI dying, ignoring interrupt. Shouldn't IRQs be disabled?\n");
3104
3105		/* Clear the event handler busy flag (RW1C) */
3106		temp = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3107		xhci_write_64(xhci, temp | ERST_EHB, &ir->ir_set->erst_dequeue);
3108		return -ENODEV;
3109	}
3110
3111	/* Process all OS owned event TRBs on this event ring */
3112	while (unhandled_event_trb(ir->event_ring)) {
3113		if (!skip_events)
3114			err = xhci_handle_event_trb(xhci, ir, ir->event_ring->dequeue);
3115
3116		/*
3117		 * If half a segment of events have been handled in one go then
3118		 * update ERDP, and force isoc trbs to interrupt more often
3119		 */
3120		if (event_loop++ > TRBS_PER_SEGMENT / 2) {
3121			xhci_update_erst_dequeue(xhci, ir, false);
3122
3123			if (ir->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3124				ir->isoc_bei_interval = ir->isoc_bei_interval / 2;
3125
3126			event_loop = 0;
3127		}
3128
3129		/* Update SW event ring dequeue pointer */
3130		inc_deq(xhci, ir->event_ring);
3131
3132		if (err)
3133			break;
3134	}
3135
3136	xhci_update_erst_dequeue(xhci, ir, true);
3137
3138	return 0;
3139}
3140
3141/*
3142 * Move the event ring dequeue pointer to skip events kept in the secondary
3143 * event ring.  This is used to ensure that pending events in the ring are
3144 * acknowledged, so the xHCI HCD can properly enter suspend/resume.  The
3145 * secondary ring is typically maintained by an external component.
3146 */
3147void xhci_skip_sec_intr_events(struct xhci_hcd *xhci,
3148			       struct xhci_ring *ring,	struct xhci_interrupter *ir)
3149{
3150	union xhci_trb *current_trb;
3151	u64 erdp_reg;
3152	dma_addr_t deq;
3153
3154	/* disable irq, ack pending interrupt and ack all pending events */
3155	xhci_disable_interrupter(xhci, ir);
3156
3157	/* last acked event trb is in erdp reg  */
3158	erdp_reg = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3159	deq = (dma_addr_t)(erdp_reg & ERST_PTR_MASK);
3160	if (!deq) {
3161		xhci_err(xhci, "event ring handling not required\n");
3162		return;
3163	}
3164
3165	current_trb = ir->event_ring->dequeue;
3166	/* read cycle state of the last acked trb to find out CCS */
3167	ring->cycle_state = le32_to_cpu(current_trb->event_cmd.flags) & TRB_CYCLE;
3168
3169	xhci_handle_events(xhci, ir, true);
3170}
3171
3172/*
3173 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3174 * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
3175 * indicators of an event TRB error, but we check the status *first* to be safe.
3176 */
3177irqreturn_t xhci_irq(struct usb_hcd *hcd)
3178{
3179	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3180	irqreturn_t ret = IRQ_HANDLED;
3181	u32 status;
3182
3183	spin_lock(&xhci->lock);
3184	/* Check if the xHC generated the interrupt, or the irq is shared */
3185	status = readl(&xhci->op_regs->status);
3186	if (status == ~(u32)0) {
3187		xhci_hc_died(xhci);
3188		goto out;
3189	}
3190
3191	if (!(status & STS_EINT)) {
3192		ret = IRQ_NONE;
3193		goto out;
3194	}
3195
3196	if (status & STS_HCE) {
3197		xhci_warn(xhci, "WARNING: Host Controller Error\n");
3198		xhci_halt(xhci);
3199		goto out;
3200	}
3201
3202	if (status & STS_FATAL) {
3203		xhci_warn(xhci, "WARNING: Host System Error\n");
3204		xhci_halt(xhci);
3205		goto out;
3206	}
3207
3208	/*
3209	 * Clear the op reg interrupt status first,
3210	 * so we can receive interrupts from other MSI-X interrupters.
3211	 * Write 1 to clear the interrupt status.
3212	 */
3213	status |= STS_EINT;
3214	writel(status, &xhci->op_regs->status);
3215
3216	/* This is the handler of the primary interrupter */
3217	xhci_handle_events(xhci, xhci->interrupters[0], false);
3218out:
3219	spin_unlock(&xhci->lock);
3220
3221	return ret;
3222}
3223
3224irqreturn_t xhci_msi_irq(int irq, void *hcd)
3225{
3226	return xhci_irq(hcd);
3227}
3228EXPORT_SYMBOL_GPL(xhci_msi_irq);
3229
3230/****		Endpoint Ring Operations	****/
3231
3232/*
3233 * Generic function for queueing a TRB on a ring.
3234 * The caller must have checked to make sure there's room on the ring.
3235 *
3236 * @more_trbs_coming:	Will you enqueue more TRBs before calling
3237 *			prepare_transfer()?
3238 */
3239static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3240		bool more_trbs_coming,
3241		u32 field1, u32 field2, u32 field3, u32 field4)
3242{
3243	struct xhci_generic_trb *trb;
3244
3245	trb = &ring->enqueue->generic;
3246	trb->field[0] = cpu_to_le32(field1);
3247	trb->field[1] = cpu_to_le32(field2);
3248	trb->field[2] = cpu_to_le32(field3);
3249	/* make sure TRB is fully written before giving it to the controller */
3250	wmb();
3251	trb->field[3] = cpu_to_le32(field4);
3252
3253	trace_xhci_queue_trb(ring, trb,
3254			     xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue));
3255
3256	inc_enq(xhci, ring, more_trbs_coming);
3257}
3258
3259/*
3260 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3261 * expand ring if it start to be full.
3262 */
3263static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3264		u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3265{
3266	unsigned int new_segs = 0;
3267
3268	/* Make sure the endpoint has been added to xHC schedule */
3269	switch (ep_state) {
3270	case EP_STATE_DISABLED:
3271		/*
3272		 * USB core changed config/interfaces without notifying us,
3273		 * or hardware is reporting the wrong state.
3274		 */
3275		xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3276		return -ENOENT;
3277	case EP_STATE_ERROR:
3278		xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3279		/* FIXME event handling code for error needs to clear it */
3280		/* XXX not sure if this should be -ENOENT or not */
3281		return -EINVAL;
3282	case EP_STATE_HALTED:
3283		xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3284		break;
3285	case EP_STATE_STOPPED:
3286	case EP_STATE_RUNNING:
3287		break;
3288	default:
3289		xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3290		/*
3291		 * FIXME issue Configure Endpoint command to try to get the HC
3292		 * back into a known state.
3293		 */
3294		return -EINVAL;
3295	}
3296
3297	if (ep_ring != xhci->cmd_ring) {
3298		new_segs = xhci_ring_expansion_needed(xhci, ep_ring, num_trbs);
3299	} else if (xhci_num_trbs_free(ep_ring) <= num_trbs) {
3300		xhci_err(xhci, "Do not support expand command ring\n");
3301		return -ENOMEM;
3302	}
3303
3304	if (new_segs) {
3305		xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3306				"ERROR no room on ep ring, try ring expansion");
3307		if (xhci_ring_expansion(xhci, ep_ring, new_segs, mem_flags)) {
3308			xhci_err(xhci, "Ring expansion failed\n");
3309			return -ENOMEM;
3310		}
3311	}
3312
3313	/* Ensure that new TRBs won't overwrite a link */
3314	if (trb_is_link(ep_ring->enqueue))
3315		inc_enq_past_link(xhci, ep_ring, 0);
3316
3317	if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3318		xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3319		return -EINVAL;
3320	}
3321
3322	return 0;
3323}
3324
3325static int prepare_transfer(struct xhci_hcd *xhci,
3326		struct xhci_virt_device *xdev,
3327		unsigned int ep_index,
3328		unsigned int stream_id,
3329		unsigned int num_trbs,
3330		struct urb *urb,
3331		unsigned int td_index,
3332		gfp_t mem_flags)
3333{
3334	int ret;
3335	struct urb_priv *urb_priv;
3336	struct xhci_td	*td;
3337	struct xhci_ring *ep_ring;
3338	struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3339
3340	ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3341					      stream_id);
3342	if (!ep_ring) {
3343		xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3344				stream_id);
3345		return -EINVAL;
3346	}
3347
3348	ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3349			   num_trbs, mem_flags);
3350	if (ret)
3351		return ret;
3352
3353	urb_priv = urb->hcpriv;
3354	td = &urb_priv->td[td_index];
3355
3356	INIT_LIST_HEAD(&td->td_list);
3357	INIT_LIST_HEAD(&td->cancelled_td_list);
3358
3359	if (td_index == 0) {
3360		ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3361		if (unlikely(ret))
3362			return ret;
3363	}
3364
3365	td->urb = urb;
3366	/* Add this TD to the tail of the endpoint ring's TD list */
3367	list_add_tail(&td->td_list, &ep_ring->td_list);
3368	td->start_seg = ep_ring->enq_seg;
3369	td->start_trb = ep_ring->enqueue;
3370
3371	return 0;
3372}
3373
3374unsigned int count_trbs(u64 addr, u64 len)
3375{
3376	unsigned int num_trbs;
3377
3378	num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3379			TRB_MAX_BUFF_SIZE);
3380	if (num_trbs == 0)
3381		num_trbs++;
3382
3383	return num_trbs;
3384}
3385
3386static inline unsigned int count_trbs_needed(struct urb *urb)
3387{
3388	return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3389}
3390
3391static unsigned int count_sg_trbs_needed(struct urb *urb)
3392{
3393	struct scatterlist *sg;
3394	unsigned int i, len, full_len, num_trbs = 0;
3395
3396	full_len = urb->transfer_buffer_length;
3397
3398	for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3399		len = sg_dma_len(sg);
3400		num_trbs += count_trbs(sg_dma_address(sg), len);
3401		len = min_t(unsigned int, len, full_len);
3402		full_len -= len;
3403		if (full_len == 0)
3404			break;
3405	}
3406
3407	return num_trbs;
3408}
3409
3410static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3411{
3412	u64 addr, len;
3413
3414	addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3415	len = urb->iso_frame_desc[i].length;
3416
3417	return count_trbs(addr, len);
3418}
3419
3420static void check_trb_math(struct urb *urb, int running_total)
3421{
3422	if (unlikely(running_total != urb->transfer_buffer_length))
3423		dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3424				"queued %#x (%d), asked for %#x (%d)\n",
3425				__func__,
3426				urb->ep->desc.bEndpointAddress,
3427				running_total, running_total,
3428				urb->transfer_buffer_length,
3429				urb->transfer_buffer_length);
3430}
3431
3432static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3433		unsigned int ep_index, unsigned int stream_id, int start_cycle,
3434		struct xhci_generic_trb *start_trb)
3435{
3436	/*
3437	 * Pass all the TRBs to the hardware at once and make sure this write
3438	 * isn't reordered.
3439	 */
3440	wmb();
3441	if (start_cycle)
3442		start_trb->field[3] |= cpu_to_le32(start_cycle);
3443	else
3444		start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3445	xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3446}
3447
3448static void check_interval(struct urb *urb, struct xhci_ep_ctx *ep_ctx)
3449{
3450	int xhci_interval;
3451	int ep_interval;
3452
3453	xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3454	ep_interval = urb->interval;
3455
3456	/* Convert to microframes */
3457	if (urb->dev->speed == USB_SPEED_LOW ||
3458			urb->dev->speed == USB_SPEED_FULL)
3459		ep_interval *= 8;
3460
3461	/* FIXME change this to a warning and a suggestion to use the new API
3462	 * to set the polling interval (once the API is added).
3463	 */
3464	if (xhci_interval != ep_interval) {
3465		dev_dbg_ratelimited(&urb->dev->dev,
3466				"Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3467				ep_interval, str_plural(ep_interval),
3468				xhci_interval, str_plural(xhci_interval));
3469		urb->interval = xhci_interval;
3470		/* Convert back to frames for LS/FS devices */
3471		if (urb->dev->speed == USB_SPEED_LOW ||
3472				urb->dev->speed == USB_SPEED_FULL)
3473			urb->interval /= 8;
3474	}
3475}
3476
3477/*
3478 * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3479 * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3480 * (comprised of sg list entries) can take several service intervals to
3481 * transmit.
3482 */
3483int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3484		struct urb *urb, int slot_id, unsigned int ep_index)
3485{
3486	struct xhci_ep_ctx *ep_ctx;
3487
3488	ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3489	check_interval(urb, ep_ctx);
3490
3491	return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3492}
3493
3494/*
3495 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3496 * packets remaining in the TD (*not* including this TRB).
3497 *
3498 * Total TD packet count = total_packet_count =
3499 *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3500 *
3501 * Packets transferred up to and including this TRB = packets_transferred =
3502 *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3503 *
3504 * TD size = total_packet_count - packets_transferred
3505 *
3506 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3507 * including this TRB, right shifted by 10
3508 *
3509 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3510 * This is taken care of in the TRB_TD_SIZE() macro
3511 *
3512 * The last TRB in a TD must have the TD size set to zero.
3513 */
3514static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3515			      int trb_buff_len, unsigned int td_total_len,
3516			      struct urb *urb, bool more_trbs_coming)
3517{
3518	u32 maxp, total_packet_count;
3519
3520	/* MTK xHCI 0.96 contains some features from 1.0 */
3521	if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3522		return ((td_total_len - transferred) >> 10);
3523
3524	/* One TRB with a zero-length data packet. */
3525	if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3526	    trb_buff_len == td_total_len)
3527		return 0;
3528
3529	/* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3530	if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3531		trb_buff_len = 0;
3532
3533	maxp = xhci_usb_endpoint_maxp(urb->dev, urb->ep);
3534	total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3535
3536	/* Queueing functions don't count the current TRB into transferred */
3537	return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3538}
3539
3540
3541static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3542			 u32 *trb_buff_len, struct xhci_segment *seg)
3543{
3544	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
3545	unsigned int unalign;
3546	unsigned int max_pkt;
3547	u32 new_buff_len;
3548	size_t len;
3549
3550	max_pkt = xhci_usb_endpoint_maxp(urb->dev, urb->ep);
3551	unalign = (enqd_len + *trb_buff_len) % max_pkt;
3552
3553	/* we got lucky, last normal TRB data on segment is packet aligned */
3554	if (unalign == 0)
3555		return 0;
3556
3557	xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3558		 unalign, *trb_buff_len);
3559
3560	/* is the last nornal TRB alignable by splitting it */
3561	if (*trb_buff_len > unalign) {
3562		*trb_buff_len -= unalign;
3563		xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3564		return 0;
3565	}
3566
3567	/*
3568	 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3569	 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3570	 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3571	 */
3572	new_buff_len = max_pkt - (enqd_len % max_pkt);
3573
3574	if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3575		new_buff_len = (urb->transfer_buffer_length - enqd_len);
3576
3577	/* create a max max_pkt sized bounce buffer pointed to by last trb */
3578	if (usb_urb_dir_out(urb)) {
3579		if (urb->num_sgs) {
3580			len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3581						 seg->bounce_buf, new_buff_len, enqd_len);
3582			if (len != new_buff_len)
3583				xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3584					  len, new_buff_len);
3585		} else {
3586			memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3587		}
3588
3589		seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3590						 max_pkt, DMA_TO_DEVICE);
3591	} else {
3592		seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3593						 max_pkt, DMA_FROM_DEVICE);
3594	}
3595
3596	if (dma_mapping_error(dev, seg->bounce_dma)) {
3597		/* try without aligning. Some host controllers survive */
3598		xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3599		return 0;
3600	}
3601	*trb_buff_len = new_buff_len;
3602	seg->bounce_len = new_buff_len;
3603	seg->bounce_offs = enqd_len;
3604
3605	xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3606
3607	return 1;
3608}
3609
3610/* This is very similar to what ehci-q.c qtd_fill() does */
3611int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3612		struct urb *urb, int slot_id, unsigned int ep_index)
3613{
3614	struct xhci_ring *ring;
3615	struct urb_priv *urb_priv;
3616	struct xhci_td *td;
3617	struct xhci_generic_trb *start_trb;
3618	struct scatterlist *sg = NULL;
3619	bool more_trbs_coming = true;
3620	bool need_zero_pkt = false;
3621	bool first_trb = true;
3622	unsigned int num_trbs;
3623	unsigned int start_cycle, num_sgs = 0;
3624	unsigned int enqd_len, block_len, trb_buff_len, full_len;
3625	int sent_len, ret;
3626	u32 field, length_field, remainder;
3627	u64 addr, send_addr;
3628
3629	ring = xhci_urb_to_transfer_ring(xhci, urb);
3630	if (!ring)
3631		return -EINVAL;
3632
3633	full_len = urb->transfer_buffer_length;
3634	/* If we have scatter/gather list, we use it. */
3635	if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3636		num_sgs = urb->num_mapped_sgs;
3637		sg = urb->sg;
3638		addr = (u64) sg_dma_address(sg);
3639		block_len = sg_dma_len(sg);
3640		num_trbs = count_sg_trbs_needed(urb);
3641	} else {
3642		num_trbs = count_trbs_needed(urb);
3643		addr = (u64) urb->transfer_dma;
3644		block_len = full_len;
3645	}
3646	ret = prepare_transfer(xhci, xhci->devs[slot_id],
3647			ep_index, urb->stream_id,
3648			num_trbs, urb, 0, mem_flags);
3649	if (unlikely(ret < 0))
3650		return ret;
3651
3652	urb_priv = urb->hcpriv;
3653
3654	/* Deal with URB_ZERO_PACKET - need one more td/trb */
3655	if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3656		need_zero_pkt = true;
3657
3658	td = &urb_priv->td[0];
3659
3660	/*
3661	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3662	 * until we've finished creating all the other TRBs.  The ring's cycle
3663	 * state may change as we enqueue the other TRBs, so save it too.
3664	 */
3665	start_trb = &ring->enqueue->generic;
3666	start_cycle = ring->cycle_state;
3667	send_addr = addr;
3668
3669	/* Queue the TRBs, even if they are zero-length */
3670	for (enqd_len = 0; first_trb || enqd_len < full_len;
3671			enqd_len += trb_buff_len) {
3672		field = TRB_TYPE(TRB_NORMAL);
3673
3674		/* TRB buffer should not cross 64KB boundaries */
3675		trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3676		trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3677
3678		if (enqd_len + trb_buff_len > full_len)
3679			trb_buff_len = full_len - enqd_len;
3680
3681		/* Don't change the cycle bit of the first TRB until later */
3682		if (first_trb) {
3683			first_trb = false;
3684			if (start_cycle == 0)
3685				field |= TRB_CYCLE;
3686		} else
3687			field |= ring->cycle_state;
3688
3689		/* Chain all the TRBs together; clear the chain bit in the last
3690		 * TRB to indicate it's the last TRB in the chain.
3691		 */
3692		if (enqd_len + trb_buff_len < full_len) {
3693			field |= TRB_CHAIN;
3694			if (trb_is_link(ring->enqueue + 1)) {
3695				if (xhci_align_td(xhci, urb, enqd_len,
3696						  &trb_buff_len,
3697						  ring->enq_seg)) {
3698					send_addr = ring->enq_seg->bounce_dma;
3699					/* assuming TD won't span 2 segs */
3700					td->bounce_seg = ring->enq_seg;
3701				}
3702			}
3703		}
3704		if (enqd_len + trb_buff_len >= full_len) {
3705			field &= ~TRB_CHAIN;
3706			field |= TRB_IOC;
3707			more_trbs_coming = false;
3708			td->end_trb = ring->enqueue;
3709			td->end_seg = ring->enq_seg;
3710			if (xhci_urb_suitable_for_idt(urb)) {
3711				memcpy(&send_addr, urb->transfer_buffer,
3712				       trb_buff_len);
3713				le64_to_cpus(&send_addr);
3714				field |= TRB_IDT;
3715			}
3716		}
3717
3718		/* Only set interrupt on short packet for IN endpoints */
3719		if (usb_urb_dir_in(urb))
3720			field |= TRB_ISP;
3721
3722		/* Set the TRB length, TD size, and interrupter fields. */
3723		remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3724					      full_len, urb, more_trbs_coming);
3725
3726		length_field = TRB_LEN(trb_buff_len) |
3727			TRB_TD_SIZE(remainder) |
3728			TRB_INTR_TARGET(0);
3729
3730		queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3731				lower_32_bits(send_addr),
3732				upper_32_bits(send_addr),
3733				length_field,
3734				field);
3735		addr += trb_buff_len;
3736		sent_len = trb_buff_len;
3737
3738		while (sg && sent_len >= block_len) {
3739			/* New sg entry */
3740			--num_sgs;
3741			sent_len -= block_len;
3742			sg = sg_next(sg);
3743			if (num_sgs != 0 && sg) {
3744				block_len = sg_dma_len(sg);
3745				addr = (u64) sg_dma_address(sg);
3746				addr += sent_len;
3747			}
3748		}
3749		block_len -= sent_len;
3750		send_addr = addr;
3751	}
3752
3753	if (need_zero_pkt) {
3754		ret = prepare_transfer(xhci, xhci->devs[slot_id],
3755				       ep_index, urb->stream_id,
3756				       1, urb, 1, mem_flags);
3757		urb_priv->td[1].end_trb = ring->enqueue;
3758		urb_priv->td[1].end_seg = ring->enq_seg;
3759		field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3760		queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3761	}
3762
3763	check_trb_math(urb, enqd_len);
3764	giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3765			start_cycle, start_trb);
3766	return 0;
3767}
3768
3769/* Caller must have locked xhci->lock */
3770int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3771		struct urb *urb, int slot_id, unsigned int ep_index)
3772{
3773	struct xhci_ring *ep_ring;
3774	int num_trbs;
3775	int ret;
3776	struct usb_ctrlrequest *setup;
3777	struct xhci_generic_trb *start_trb;
3778	int start_cycle;
3779	u32 field;
3780	struct urb_priv *urb_priv;
3781	struct xhci_td *td;
3782
3783	ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3784	if (!ep_ring)
3785		return -EINVAL;
3786
3787	/*
3788	 * Need to copy setup packet into setup TRB, so we can't use the setup
3789	 * DMA address.
3790	 */
3791	if (!urb->setup_packet)
3792		return -EINVAL;
3793
3794	if ((xhci->quirks & XHCI_ETRON_HOST) &&
3795	    urb->dev->speed >= USB_SPEED_SUPER) {
3796		/*
3797		 * If next available TRB is the Link TRB in the ring segment then
3798		 * enqueue a No Op TRB, this can prevent the Setup and Data Stage
3799		 * TRB to be breaked by the Link TRB.
3800		 */
3801		if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue + 1)) {
3802			field = TRB_TYPE(TRB_TR_NOOP) | ep_ring->cycle_state;
3803			queue_trb(xhci, ep_ring, false, 0, 0,
3804					TRB_INTR_TARGET(0), field);
3805		}
3806	}
3807
3808	/* 1 TRB for setup, 1 for status */
3809	num_trbs = 2;
3810	/*
3811	 * Don't need to check if we need additional event data and normal TRBs,
3812	 * since data in control transfers will never get bigger than 16MB
3813	 * XXX: can we get a buffer that crosses 64KB boundaries?
3814	 */
3815	if (urb->transfer_buffer_length > 0)
3816		num_trbs++;
3817	ret = prepare_transfer(xhci, xhci->devs[slot_id],
3818			ep_index, urb->stream_id,
3819			num_trbs, urb, 0, mem_flags);
3820	if (ret < 0)
3821		return ret;
3822
3823	urb_priv = urb->hcpriv;
3824	td = &urb_priv->td[0];
3825
3826	/*
3827	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3828	 * until we've finished creating all the other TRBs.  The ring's cycle
3829	 * state may change as we enqueue the other TRBs, so save it too.
3830	 */
3831	start_trb = &ep_ring->enqueue->generic;
3832	start_cycle = ep_ring->cycle_state;
3833
3834	/* Queue setup TRB - see section 6.4.1.2.1 */
3835	/* FIXME better way to translate setup_packet into two u32 fields? */
3836	setup = (struct usb_ctrlrequest *) urb->setup_packet;
3837	field = 0;
3838	field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3839	if (start_cycle == 0)
3840		field |= 0x1;
3841
3842	/* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3843	if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3844		if (urb->transfer_buffer_length > 0) {
3845			if (setup->bRequestType & USB_DIR_IN)
3846				field |= TRB_TX_TYPE(TRB_DATA_IN);
3847			else
3848				field |= TRB_TX_TYPE(TRB_DATA_OUT);
3849		}
3850	}
3851
3852	queue_trb(xhci, ep_ring, true,
3853		  setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3854		  le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3855		  TRB_LEN(8) | TRB_INTR_TARGET(0),
3856		  /* Immediate data in pointer */
3857		  field);
3858
3859	/* If there's data, queue data TRBs */
3860	/* Only set interrupt on short packet for IN endpoints */
3861	if (usb_urb_dir_in(urb))
3862		field = TRB_ISP | TRB_TYPE(TRB_DATA);
3863	else
3864		field = TRB_TYPE(TRB_DATA);
3865
3866	if (urb->transfer_buffer_length > 0) {
3867		u32 length_field, remainder;
3868		u64 addr;
3869
3870		if (xhci_urb_suitable_for_idt(urb)) {
3871			memcpy(&addr, urb->transfer_buffer,
3872			       urb->transfer_buffer_length);
3873			le64_to_cpus(&addr);
3874			field |= TRB_IDT;
3875		} else {
3876			addr = (u64) urb->transfer_dma;
3877		}
3878
3879		remainder = xhci_td_remainder(xhci, 0,
3880				urb->transfer_buffer_length,
3881				urb->transfer_buffer_length,
3882				urb, 1);
3883		length_field = TRB_LEN(urb->transfer_buffer_length) |
3884				TRB_TD_SIZE(remainder) |
3885				TRB_INTR_TARGET(0);
3886		if (setup->bRequestType & USB_DIR_IN)
3887			field |= TRB_DIR_IN;
3888		queue_trb(xhci, ep_ring, true,
3889				lower_32_bits(addr),
3890				upper_32_bits(addr),
3891				length_field,
3892				field | ep_ring->cycle_state);
3893	}
3894
3895	/* Save the DMA address of the last TRB in the TD */
3896	td->end_trb = ep_ring->enqueue;
3897	td->end_seg = ep_ring->enq_seg;
3898
3899	/* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3900	/* If the device sent data, the status stage is an OUT transfer */
3901	if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3902		field = 0;
3903	else
3904		field = TRB_DIR_IN;
3905	queue_trb(xhci, ep_ring, false,
3906			0,
3907			0,
3908			TRB_INTR_TARGET(0),
3909			/* Event on completion */
3910			field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3911
3912	giveback_first_trb(xhci, slot_id, ep_index, 0,
3913			start_cycle, start_trb);
3914	return 0;
3915}
3916
3917/*
3918 * The transfer burst count field of the isochronous TRB defines the number of
3919 * bursts that are required to move all packets in this TD.  Only SuperSpeed
3920 * devices can burst up to bMaxBurst number of packets per service interval.
3921 * This field is zero based, meaning a value of zero in the field means one
3922 * burst.  Basically, for everything but SuperSpeed devices, this field will be
3923 * zero.  Only xHCI 1.0 host controllers support this field.
3924 */
3925static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3926		struct urb *urb, unsigned int total_packet_count)
3927{
3928	unsigned int max_burst;
3929
3930	if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3931		return 0;
3932
3933	max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3934	return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3935}
3936
3937/*
3938 * Returns the number of packets in the last "burst" of packets.  This field is
3939 * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3940 * the last burst packet count is equal to the total number of packets in the
3941 * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3942 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3943 * contain 1 to (bMaxBurst + 1) packets.
3944 */
3945static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3946		struct urb *urb, unsigned int total_packet_count)
3947{
3948	unsigned int max_burst;
3949	unsigned int residue;
3950
3951	if (xhci->hci_version < 0x100)
3952		return 0;
3953
3954	if (urb->dev->speed >= USB_SPEED_SUPER) {
3955		/* bMaxBurst is zero based: 0 means 1 packet per burst */
3956		max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3957		residue = total_packet_count % (max_burst + 1);
3958		/* If residue is zero, the last burst contains (max_burst + 1)
3959		 * number of packets, but the TLBPC field is zero-based.
3960		 */
3961		if (residue == 0)
3962			return max_burst;
3963		return residue - 1;
3964	}
3965	if (total_packet_count == 0)
3966		return 0;
3967	return total_packet_count - 1;
3968}
3969
3970/* Returns the Isochronous Scheduling Threshold in Microframes. 1 Frame is 8 Microframes. */
3971static int xhci_ist_microframes(struct xhci_hcd *xhci)
3972{
3973	int ist = HCS_IST_VALUE(xhci->hcs_params2);
3974
3975	if (xhci->hcs_params2 & HCS_IST_UNIT)
3976		ist *= 8;
3977	return ist;
3978}
3979
3980/*
3981 * Calculates Frame ID field of the isochronous TRB identifies the
3982 * target frame that the Interval associated with this Isochronous
3983 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3984 *
3985 * Returns actual frame id on success, negative value on error.
3986 */
3987static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3988		struct urb *urb, int index)
3989{
3990	int start_frame, ist, ret = 0;
3991	int start_frame_id, end_frame_id, current_frame_id;
3992
3993	if (urb->dev->speed == USB_SPEED_LOW ||
3994			urb->dev->speed == USB_SPEED_FULL)
3995		start_frame = urb->start_frame + index * urb->interval;
3996	else
3997		start_frame = (urb->start_frame + index * urb->interval) >> 3;
3998
3999	ist = xhci_ist_microframes(xhci);
4000
4001	/* Software shall not schedule an Isoch TD with a Frame ID value that
4002	 * is less than the Start Frame ID or greater than the End Frame ID,
4003	 * where:
4004	 *
4005	 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
4006	 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
4007	 *
4008	 * Both the End Frame ID and Start Frame ID values are calculated
4009	 * in microframes. When software determines the valid Frame ID value;
4010	 * The End Frame ID value should be rounded down to the nearest Frame
4011	 * boundary, and the Start Frame ID value should be rounded up to the
4012	 * nearest Frame boundary.
4013	 */
4014	current_frame_id = readl(&xhci->run_regs->microframe_index);
4015	start_frame_id = roundup(current_frame_id + ist + 1, 8);
4016	end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
4017
4018	start_frame &= 0x7ff;
4019	start_frame_id = (start_frame_id >> 3) & 0x7ff;
4020	end_frame_id = (end_frame_id >> 3) & 0x7ff;
4021
4022	if (start_frame_id < end_frame_id) {
4023		if (start_frame > end_frame_id ||
4024				start_frame < start_frame_id)
4025			ret = -EINVAL;
4026	} else if (start_frame_id > end_frame_id) {
4027		if ((start_frame > end_frame_id &&
4028				start_frame < start_frame_id))
4029			ret = -EINVAL;
4030	} else {
4031			ret = -EINVAL;
4032	}
4033
4034	if (index == 0) {
4035		if (ret == -EINVAL || start_frame == start_frame_id) {
4036			start_frame = start_frame_id + 1;
4037			if (urb->dev->speed == USB_SPEED_LOW ||
4038					urb->dev->speed == USB_SPEED_FULL)
4039				urb->start_frame = start_frame;
4040			else
4041				urb->start_frame = start_frame << 3;
4042			ret = 0;
4043		}
4044	}
4045
4046	if (ret) {
4047		xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4048				start_frame, current_frame_id, index,
4049				start_frame_id, end_frame_id);
4050		xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
4051		return ret;
4052	}
4053
4054	return start_frame;
4055}
4056
4057/* Check if we should generate event interrupt for a TD in an isoc URB */
4058static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i,
4059				 struct xhci_interrupter *ir)
4060{
4061	if (xhci->hci_version < 0x100)
4062		return false;
4063	/* always generate an event interrupt for the last TD */
4064	if (i == num_tds - 1)
4065		return false;
4066	/*
4067	 * If AVOID_BEI is set the host handles full event rings poorly,
4068	 * generate an event at least every 8th TD to clear the event ring
4069	 */
4070	if (i && ir->isoc_bei_interval && xhci->quirks & XHCI_AVOID_BEI)
4071		return !!(i % ir->isoc_bei_interval);
4072
4073	return true;
4074}
4075
4076/* This is for isoc transfer */
4077static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
4078		struct urb *urb, int slot_id, unsigned int ep_index)
4079{
4080	struct xhci_interrupter *ir;
4081	struct xhci_ring *ep_ring;
4082	struct urb_priv *urb_priv;
4083	struct xhci_td *td;
4084	int num_tds, trbs_per_td;
4085	struct xhci_generic_trb *start_trb;
4086	bool first_trb;
4087	int start_cycle;
4088	u32 field, length_field;
4089	int running_total, trb_buff_len, td_len, td_remain_len, ret;
4090	u64 start_addr, addr;
4091	int i, j;
4092	bool more_trbs_coming;
4093	struct xhci_virt_ep *xep;
4094	int frame_id;
4095
4096	xep = &xhci->devs[slot_id]->eps[ep_index];
4097	ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
4098	ir = xhci->interrupters[0];
4099
4100	num_tds = urb->number_of_packets;
4101	if (num_tds < 1) {
4102		xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4103		return -EINVAL;
4104	}
4105	start_addr = (u64) urb->transfer_dma;
4106	start_trb = &ep_ring->enqueue->generic;
4107	start_cycle = ep_ring->cycle_state;
4108
4109	urb_priv = urb->hcpriv;
4110	/* Queue the TRBs for each TD, even if they are zero-length */
4111	for (i = 0; i < num_tds; i++) {
4112		unsigned int total_pkt_count, max_pkt;
4113		unsigned int burst_count, last_burst_pkt_count;
4114		u32 sia_frame_id;
4115
4116		first_trb = true;
4117		running_total = 0;
4118		addr = start_addr + urb->iso_frame_desc[i].offset;
4119		td_len = urb->iso_frame_desc[i].length;
4120		td_remain_len = td_len;
4121		max_pkt = xhci_usb_endpoint_maxp(urb->dev, urb->ep);
4122		total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4123
4124		/* A zero-length transfer still involves at least one packet. */
4125		if (total_pkt_count == 0)
4126			total_pkt_count++;
4127		burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4128		last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4129							urb, total_pkt_count);
4130
4131		trbs_per_td = count_isoc_trbs_needed(urb, i);
4132
4133		ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4134				urb->stream_id, trbs_per_td, urb, i, mem_flags);
4135		if (ret < 0) {
4136			if (i == 0)
4137				return ret;
4138			goto cleanup;
4139		}
4140		td = &urb_priv->td[i];
4141		/* use SIA as default, if frame id is used overwrite it */
4142		sia_frame_id = TRB_SIA;
4143		if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4144		    (xhci->hcc_params & HCC_CFC)) {
4145			frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4146			if (frame_id >= 0)
4147				sia_frame_id = TRB_FRAME_ID(frame_id);
4148		}
4149		/*
4150		 * Set isoc specific data for the first TRB in a TD.
4151		 * Prevent HW from getting the TRBs by keeping the cycle state
4152		 * inverted in the first TDs isoc TRB.
4153		 */
4154		field = TRB_TYPE(TRB_ISOC) |
4155			TRB_TLBPC(last_burst_pkt_count) |
4156			sia_frame_id |
4157			(i ? ep_ring->cycle_state : !start_cycle);
4158
4159		/* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4160		if (!xep->use_extended_tbc)
4161			field |= TRB_TBC(burst_count);
4162
4163		/* fill the rest of the TRB fields, and remaining normal TRBs */
4164		for (j = 0; j < trbs_per_td; j++) {
4165			u32 remainder = 0;
4166
4167			/* only first TRB is isoc, overwrite otherwise */
4168			if (!first_trb)
4169				field = TRB_TYPE(TRB_NORMAL) |
4170					ep_ring->cycle_state;
4171
4172			/* Only set interrupt on short packet for IN EPs */
4173			if (usb_urb_dir_in(urb))
4174				field |= TRB_ISP;
4175
4176			/* Set the chain bit for all except the last TRB  */
4177			if (j < trbs_per_td - 1) {
4178				more_trbs_coming = true;
4179				field |= TRB_CHAIN;
4180			} else {
4181				more_trbs_coming = false;
4182				td->end_trb = ep_ring->enqueue;
4183				td->end_seg = ep_ring->enq_seg;
4184				field |= TRB_IOC;
4185				if (trb_block_event_intr(xhci, num_tds, i, ir))
4186					field |= TRB_BEI;
4187			}
4188			/* Calculate TRB length */
4189			trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4190			if (trb_buff_len > td_remain_len)
4191				trb_buff_len = td_remain_len;
4192
4193			/* Set the TRB length, TD size, & interrupter fields. */
4194			remainder = xhci_td_remainder(xhci, running_total,
4195						   trb_buff_len, td_len,
4196						   urb, more_trbs_coming);
4197
4198			length_field = TRB_LEN(trb_buff_len) |
4199				TRB_INTR_TARGET(0);
4200
4201			/* xhci 1.1 with ETE uses TD Size field for TBC */
4202			if (first_trb && xep->use_extended_tbc)
4203				length_field |= TRB_TD_SIZE_TBC(burst_count);
4204			else
4205				length_field |= TRB_TD_SIZE(remainder);
4206			first_trb = false;
4207
4208			queue_trb(xhci, ep_ring, more_trbs_coming,
4209				lower_32_bits(addr),
4210				upper_32_bits(addr),
4211				length_field,
4212				field);
4213			running_total += trb_buff_len;
4214
4215			addr += trb_buff_len;
4216			td_remain_len -= trb_buff_len;
4217		}
4218
4219		/* Check TD length */
4220		if (running_total != td_len) {
4221			xhci_err(xhci, "ISOC TD length unmatch\n");
4222			ret = -EINVAL;
4223			goto cleanup;
4224		}
4225	}
4226
4227	/* store the next frame id */
4228	if (xhci->hcc_params & HCC_CFC)
4229		xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4230
4231	if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4232		if (xhci->quirks & XHCI_AMD_PLL_FIX)
4233			usb_amd_quirk_pll_disable();
4234	}
4235	xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4236
4237	giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4238			start_cycle, start_trb);
4239	return 0;
4240cleanup:
4241	/* Clean up a partially enqueued isoc transfer. */
4242
4243	for (i--; i >= 0; i--)
4244		list_del_init(&urb_priv->td[i].td_list);
4245
4246	/* Use the first TD as a temporary variable to turn the TDs we've queued
4247	 * into No-ops with a software-owned cycle bit. That way the hardware
4248	 * won't accidentally start executing bogus TDs when we partially
4249	 * overwrite them.  td->start_trb and td->start_seg are already set.
4250	 */
4251	urb_priv->td[0].end_trb = ep_ring->enqueue;
4252	/* Every TRB except the first & last will have its cycle bit flipped. */
4253	td_to_noop(xhci, xep, &urb_priv->td[0], true);
4254
4255	/* Reset the ring enqueue back to the first TRB and its cycle bit. */
4256	ep_ring->enqueue = urb_priv->td[0].start_trb;
4257	ep_ring->enq_seg = urb_priv->td[0].start_seg;
4258	ep_ring->cycle_state = start_cycle;
4259	usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4260	return ret;
4261}
4262
4263/*
4264 * Check transfer ring to guarantee there is enough room for the urb.
4265 * Update ISO URB start_frame and interval.
4266 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4267 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4268 * Contiguous Frame ID is not supported by HC.
4269 */
4270int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4271		struct urb *urb, int slot_id, unsigned int ep_index)
4272{
4273	struct xhci_virt_device *xdev;
4274	struct xhci_ring *ep_ring;
4275	struct xhci_ep_ctx *ep_ctx;
4276	int start_frame;
4277	int num_tds, num_trbs, i;
4278	int ret;
4279	struct xhci_virt_ep *xep;
4280	int ist;
4281
4282	xdev = xhci->devs[slot_id];
4283	xep = &xhci->devs[slot_id]->eps[ep_index];
4284	ep_ring = xdev->eps[ep_index].ring;
4285	ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4286
4287	num_trbs = 0;
4288	num_tds = urb->number_of_packets;
4289	for (i = 0; i < num_tds; i++)
4290		num_trbs += count_isoc_trbs_needed(urb, i);
4291
4292	/* Check the ring to guarantee there is enough room for the whole urb.
4293	 * Do not insert any td of the urb to the ring if the check failed.
4294	 */
4295	ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4296			   num_trbs, mem_flags);
4297	if (ret)
4298		return ret;
4299
4300	/*
4301	 * Check interval value. This should be done before we start to
4302	 * calculate the start frame value.
4303	 */
4304	check_interval(urb, ep_ctx);
4305
4306	/* Calculate the start frame and put it in urb->start_frame. */
4307	if ((xhci->hcc_params & HCC_CFC) && !list_empty(&ep_ring->td_list)) {
4308		if (GET_EP_CTX_STATE(ep_ctx) ==	EP_STATE_RUNNING) {
4309			urb->start_frame = xep->next_frame_id;
4310			goto skip_start_over;
4311		}
4312	}
4313
4314	start_frame = readl(&xhci->run_regs->microframe_index);
4315	start_frame &= 0x3fff;
4316	/*
4317	 * Round up to the next frame and consider the time before trb really
4318	 * gets scheduled by hardare.
4319	 */
4320	ist = xhci_ist_microframes(xhci);
4321	start_frame += ist + XHCI_CFC_DELAY;
4322	start_frame = roundup(start_frame, 8);
4323
4324	/*
4325	 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4326	 * is greate than 8 microframes.
4327	 */
4328	if (urb->dev->speed == USB_SPEED_LOW ||
4329			urb->dev->speed == USB_SPEED_FULL) {
4330		start_frame = roundup(start_frame, urb->interval << 3);
4331		urb->start_frame = start_frame >> 3;
4332	} else {
4333		start_frame = roundup(start_frame, urb->interval);
4334		urb->start_frame = start_frame;
4335	}
4336
4337skip_start_over:
4338
4339	return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4340}
4341
4342/****		Command Ring Operations		****/
4343
4344/* Generic function for queueing a command TRB on the command ring.
4345 * Check to make sure there's room on the command ring for one command TRB.
4346 * Also check that there's room reserved for commands that must not fail.
4347 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4348 * then only check for the number of reserved spots.
4349 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4350 * because the command event handler may want to resubmit a failed command.
4351 */
4352static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4353			 u32 field1, u32 field2,
4354			 u32 field3, u32 field4, bool command_must_succeed)
4355{
4356	int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4357	int ret;
4358
4359	if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4360		(xhci->xhc_state & XHCI_STATE_HALTED)) {
4361		xhci_dbg(xhci, "xHCI dying or halted, can't queue_command. state: 0x%x\n",
4362			 xhci->xhc_state);
4363		return -ESHUTDOWN;
4364	}
4365
4366	if (!command_must_succeed)
4367		reserved_trbs++;
4368
4369	ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4370			reserved_trbs, GFP_ATOMIC);
4371	if (ret < 0) {
4372		xhci_err(xhci, "ERR: No room for command on command ring\n");
4373		if (command_must_succeed)
4374			xhci_err(xhci, "ERR: Reserved TRB counting for "
4375					"unfailable commands failed.\n");
4376		return ret;
4377	}
4378
4379	cmd->command_trb = xhci->cmd_ring->enqueue;
4380
4381	/* if there are no other commands queued we start the timeout timer */
4382	if (list_empty(&xhci->cmd_list)) {
4383		xhci->current_cmd = cmd;
4384		xhci_mod_cmd_timer(xhci);
4385	}
4386
4387	list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4388
4389	queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4390			field4 | xhci->cmd_ring->cycle_state);
4391	return 0;
4392}
4393
4394/* Queue a slot enable or disable request on the command ring */
4395int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4396		u32 trb_type, u32 slot_id)
4397{
4398	return queue_command(xhci, cmd, 0, 0, 0,
4399			TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4400}
4401
4402/* Queue an address device command TRB */
4403int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4404		dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4405{
4406	return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4407			upper_32_bits(in_ctx_ptr), 0,
4408			TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4409			| (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4410}
4411
4412int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4413		u32 field1, u32 field2, u32 field3, u32 field4)
4414{
4415	return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4416}
4417
4418/* Queue a reset device command TRB */
4419int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4420		u32 slot_id)
4421{
4422	return queue_command(xhci, cmd, 0, 0, 0,
4423			TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4424			false);
4425}
4426
4427/* Queue a configure endpoint command TRB */
4428int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4429		struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4430		u32 slot_id, bool command_must_succeed)
4431{
4432	return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4433			upper_32_bits(in_ctx_ptr), 0,
4434			TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4435			command_must_succeed);
4436}
4437
4438/* Queue a get root hub port bandwidth command TRB */
4439int xhci_queue_get_port_bw(struct xhci_hcd *xhci,
4440		struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4441		u8 dev_speed, bool command_must_succeed)
4442{
4443	return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4444		upper_32_bits(in_ctx_ptr), 0,
4445		TRB_TYPE(TRB_GET_BW) | DEV_SPEED_FOR_TRB(dev_speed),
4446		command_must_succeed);
4447}
4448
4449/* Queue an evaluate context command TRB */
4450int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4451		dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4452{
4453	return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4454			upper_32_bits(in_ctx_ptr), 0,
4455			TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4456			command_must_succeed);
4457}
4458
4459/*
4460 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4461 * activity on an endpoint that is about to be suspended.
4462 */
4463int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4464			     int slot_id, unsigned int ep_index, int suspend)
4465{
4466	u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4467	u32 trb_ep_index = EP_INDEX_FOR_TRB(ep_index);
4468	u32 type = TRB_TYPE(TRB_STOP_RING);
4469	u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4470
4471	return queue_command(xhci, cmd, 0, 0, 0,
4472			trb_slot_id | trb_ep_index | type | trb_suspend, false);
4473}
4474
4475int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4476			int slot_id, unsigned int ep_index,
4477			enum xhci_ep_reset_type reset_type)
4478{
4479	u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4480	u32 trb_ep_index = EP_INDEX_FOR_TRB(ep_index);
4481	u32 type = TRB_TYPE(TRB_RESET_EP);
4482
4483	if (reset_type == EP_SOFT_RESET)
4484		type |= TRB_TSP;
4485
4486	return queue_command(xhci, cmd, 0, 0, 0,
4487			trb_slot_id | trb_ep_index | type, false);
4488}