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xhci-pci.c
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linux-6.19.14/drivers/usb/host/xhci-pci.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * xHCI host controller driver PCI Bus Glue. 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11#include <linux/pci.h> 12#include <linux/slab.h> 13#include <linux/module.h> 14#include <linux/acpi.h> 15#include <linux/reset.h> 16#include <linux/suspend.h> 17 18#include "xhci.h" 19#include "xhci-trace.h" 20#include "xhci-pci.h" 21 22#define SSIC_PORT_NUM 2 23#define SSIC_PORT_CFG2 0x880c 24#define SSIC_PORT_CFG2_OFFSET 0x30 25#define PROG_DONE (1 << 30) 26#define SSIC_PORT_UNUSED (1 << 31) 27#define SPARSE_DISABLE_BIT 17 28#define SPARSE_CNTL_ENABLE 0xC12C 29 30/* Device for a quirk */ 31#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 32#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 34#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 35#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 36 37#define PCI_VENDOR_ID_ETRON 0x1b6f 38#define PCI_DEVICE_ID_ETRON_EJ168 0x7023 39#define PCI_DEVICE_ID_ETRON_EJ188 0x7052 40 41#define PCI_DEVICE_ID_VIA_VL805 0x3483 42 43#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 44#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 45#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 46#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 47#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f 48#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f 49#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 50#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 51#define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 52#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 53#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 54#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 55#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed 56#define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af 57#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed 58#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed 59 60#define PCI_VENDOR_ID_PHYTIUM 0x1db7 61#define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27 62 63/* Thunderbolt */ 64#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 65#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 66#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 67#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 68#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db 69#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 70#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 71#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec 72#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 73 74#define PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI 0x13ed 75#define PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI 0x13ee 76#define PCI_DEVICE_ID_AMD_STARSHIP_XHCI 0x148c 77#define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI 0x15d4 78#define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI 0x15d5 79#define PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI 0x15e0 80#define PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI 0x15e1 81#define PCI_DEVICE_ID_AMD_RAVEN2_XHCI 0x15e5 82#define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 83#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 84#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 85#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb 86#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc 87 88#define PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI 0x7316 89 90#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 91#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 92#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 93#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 94#define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042 95#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 96 97static const char hcd_name[] = "xhci_hcd"; 98 99static struct hc_driver __read_mostly xhci_pci_hc_driver; 100 101static int xhci_pci_setup(struct usb_hcd *hcd); 102static int xhci_pci_run(struct usb_hcd *hcd); 103static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 104 struct usb_tt *tt, gfp_t mem_flags); 105 106static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { 107 .reset = xhci_pci_setup, 108 .start = xhci_pci_run, 109 .update_hub_device = xhci_pci_update_hub_device, 110}; 111 112/* 113 * Primary Legacy and MSI IRQ are synced in suspend_common(). 114 * All MSI-X IRQs and secondary MSI IRQs should be synced here. 115 */ 116static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) 117{ 118 struct usb_hcd *hcd = xhci_to_hcd(xhci); 119 120 if (hcd->msix_enabled) { 121 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 122 123 /* for now, the driver only supports one primary interrupter */ 124 synchronize_irq(pci_irq_vector(pdev, 0)); 125 } 126} 127 128/* Legacy IRQ is freed by usb_remove_hcd() or usb_hcd_pci_shutdown() */ 129static void xhci_cleanup_msix(struct xhci_hcd *xhci) 130{ 131 struct usb_hcd *hcd = xhci_to_hcd(xhci); 132 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 133 134 if (hcd->irq > 0) 135 return; 136 137 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); 138 pci_free_irq_vectors(pdev); 139 hcd->msix_enabled = 0; 140} 141 142/* Try enabling MSI-X with MSI and legacy IRQ as fallback */ 143static int xhci_try_enable_msi(struct usb_hcd *hcd) 144{ 145 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 146 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 147 int ret; 148 149 /* 150 * Some Fresco Logic host controllers advertise MSI, but fail to 151 * generate interrupts. Don't even try to enable MSI. 152 */ 153 if (xhci->quirks & XHCI_BROKEN_MSI) 154 goto legacy_irq; 155 156 /* unregister the legacy interrupt */ 157 if (hcd->irq) 158 free_irq(hcd->irq, hcd); 159 hcd->irq = 0; 160 161 /* 162 * Calculate number of MSI/MSI-X vectors supported. 163 * - max_interrupters: the max number of interrupts requested, capped to xhci HCSPARAMS1. 164 * - num_online_cpus: one vector per CPUs core, with at least one overall. 165 */ 166 xhci->nvecs = min(num_online_cpus() + 1, xhci->max_interrupters); 167 168 /* TODO: Check with MSI Soc for sysdev */ 169 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs, 170 PCI_IRQ_MSIX | PCI_IRQ_MSI); 171 if (xhci->nvecs < 0) { 172 xhci_dbg_trace(xhci, trace_xhci_dbg_init, 173 "failed to allocate IRQ vectors"); 174 goto legacy_irq; 175 } 176 177 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd", 178 xhci_to_hcd(xhci)); 179 if (ret) 180 goto free_irq_vectors; 181 182 hcd->msi_enabled = 1; 183 hcd->msix_enabled = pdev->msix_enabled; 184 return 0; 185 186free_irq_vectors: 187 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt", 188 pdev->msix_enabled ? "MSI-X" : "MSI"); 189 pci_free_irq_vectors(pdev); 190 191legacy_irq: 192 if (!pdev->irq) { 193 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); 194 return -EINVAL; 195 } 196 197 if (!strlen(hcd->irq_descr)) 198 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", 199 hcd->driver->description, hcd->self.busnum); 200 201 /* fall back to legacy interrupt */ 202 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd); 203 if (ret) { 204 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); 205 return ret; 206 } 207 hcd->irq = pdev->irq; 208 return 0; 209} 210 211static int xhci_pci_run(struct usb_hcd *hcd) 212{ 213 int ret; 214 215 if (usb_hcd_is_primary_hcd(hcd)) { 216 ret = xhci_try_enable_msi(hcd); 217 if (ret) 218 return ret; 219 } 220 221 return xhci_run(hcd); 222} 223 224static void xhci_pci_stop(struct usb_hcd *hcd) 225{ 226 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 227 228 xhci_stop(hcd); 229 230 if (usb_hcd_is_primary_hcd(hcd)) 231 xhci_cleanup_msix(xhci); 232} 233 234/* called after powerup, by probe or system-pm "wakeup" */ 235static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) 236{ 237 /* 238 * TODO: Implement finding debug ports later. 239 * TODO: see if there are any quirks that need to be added to handle 240 * new extended capabilities. 241 */ 242 243 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 244 if (!pci_set_mwi(pdev)) 245 xhci_dbg(xhci, "MWI active\n"); 246 247 xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); 248 return 0; 249} 250 251static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 252{ 253 struct pci_dev *pdev = to_pci_dev(dev); 254 255 /* Look for vendor-specific quirks */ 256 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 257 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || 258 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { 259 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 260 pdev->revision == 0x0) { 261 xhci->quirks |= XHCI_RESET_EP_QUIRK; 262 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 263 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); 264 } 265 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && 266 pdev->revision == 0x4) { 267 xhci->quirks |= XHCI_SLOW_SUSPEND; 268 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 269 "QUIRK: Fresco Logic xHC revision %u" 270 "must be suspended extra slowly", 271 pdev->revision); 272 } 273 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) 274 xhci->quirks |= XHCI_BROKEN_STREAMS; 275 /* Fresco Logic confirms: all revisions of this chip do not 276 * support MSI, even though some of them claim to in their PCI 277 * capabilities. 278 */ 279 xhci->quirks |= XHCI_BROKEN_MSI; 280 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 281 "QUIRK: Fresco Logic revision %u " 282 "has broken MSI implementation", 283 pdev->revision); 284 } 285 286 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && 287 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) 288 xhci->quirks |= XHCI_BROKEN_STREAMS; 289 290 if (pdev->vendor == PCI_VENDOR_ID_NEC) 291 xhci->quirks |= XHCI_NEC_HOST; 292 293 if (pdev->vendor == PCI_VENDOR_ID_AMD && 294 (pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI || 295 pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI || 296 pdev->device == PCI_DEVICE_ID_AMD_STARSHIP_XHCI || 297 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI || 298 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI || 299 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI || 300 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI || 301 pdev->device == PCI_DEVICE_ID_AMD_RAVEN2_XHCI)) 302 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9; 303 304 if (pdev->vendor == PCI_VENDOR_ID_ATI && 305 pdev->device == PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI) 306 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9; 307 308 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) 309 xhci->quirks |= XHCI_AMD_0x96_HOST; 310 311 /* AMD PLL quirk */ 312 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) 313 xhci->quirks |= XHCI_AMD_PLL_FIX; 314 315 if (pdev->vendor == PCI_VENDOR_ID_AMD && 316 (pdev->device == 0x145c || 317 pdev->device == 0x15e0 || 318 pdev->device == 0x15e1 || 319 pdev->device == 0x43bb)) 320 xhci->quirks |= XHCI_SUSPEND_DELAY; 321 322 if (pdev->vendor == PCI_VENDOR_ID_AMD && 323 (pdev->device == 0x15e0 || pdev->device == 0x15e1)) 324 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; 325 326 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { 327 xhci->quirks |= XHCI_DISABLE_SPARSE; 328 xhci->quirks |= XHCI_RESET_ON_RESUME; 329 } 330 331 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) 332 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 333 334 if ((pdev->vendor == PCI_VENDOR_ID_AMD) && 335 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || 336 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || 337 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 338 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 339 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 340 341 if (pdev->vendor == PCI_VENDOR_ID_AMD && 342 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 343 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; 344 345 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 346 xhci->quirks |= XHCI_LPM_SUPPORT; 347 xhci->quirks |= XHCI_INTEL_HOST; 348 xhci->quirks |= XHCI_AVOID_BEI; 349 } 350 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 351 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 352 xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 353 xhci->limit_active_eps = 64; 354 xhci->quirks |= XHCI_SW_BW_CHECKING; 355 /* 356 * PPT desktop boards DH77EB and DH77DF will power back on after 357 * a few seconds of being shutdown. The fix for this is to 358 * switch the ports from xHCI to EHCI on shutdown. We can't use 359 * DMI information to find those particular boards (since each 360 * vendor will change the board name), so we have to key off all 361 * PPT chipsets. 362 */ 363 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 364 } 365 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 366 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || 367 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { 368 xhci->quirks |= XHCI_SPURIOUS_REBOOT; 369 xhci->quirks |= XHCI_SPURIOUS_WAKEUP; 370 } 371 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 372 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 373 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 374 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 375 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || 376 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || 377 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 378 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || 379 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { 380 xhci->quirks |= XHCI_PME_STUCK_QUIRK; 381 } 382 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 383 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) 384 xhci->quirks |= XHCI_SSIC_PORT_UNUSED; 385 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 386 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 387 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 388 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) 389 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; 390 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 391 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || 392 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || 393 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || 394 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || 395 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) 396 xhci->quirks |= XHCI_MISSING_CAS; 397 398 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 399 (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI || 400 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || 401 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) 402 xhci->quirks |= XHCI_RESET_TO_DEFAULT; 403 404 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 405 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || 406 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || 407 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || 408 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || 409 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || 410 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || 411 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || 412 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || 413 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || 414 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || 415 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) 416 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 417 418 if (pdev->vendor == PCI_VENDOR_ID_ETRON && 419 (pdev->device == PCI_DEVICE_ID_ETRON_EJ168 || 420 pdev->device == PCI_DEVICE_ID_ETRON_EJ188)) { 421 xhci->quirks |= XHCI_ETRON_HOST; 422 xhci->quirks |= XHCI_RESET_ON_RESUME; 423 xhci->quirks |= XHCI_BROKEN_STREAMS; 424 xhci->quirks |= XHCI_NO_SOFT_RETRY; 425 } 426 427 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 428 pdev->device == 0x0014) { 429 xhci->quirks |= XHCI_ZERO_64B_REGS; 430 } 431 if (pdev->vendor == PCI_VENDOR_ID_RENESAS && 432 pdev->device == 0x0015) { 433 xhci->quirks |= XHCI_RESET_ON_RESUME; 434 xhci->quirks |= XHCI_ZERO_64B_REGS; 435 } 436 if (pdev->vendor == PCI_VENDOR_ID_VIA) 437 xhci->quirks |= XHCI_RESET_ON_RESUME; 438 439 if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM && 440 pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI) 441 xhci->quirks |= XHCI_RESET_ON_RESUME; 442 443 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ 444 if (pdev->vendor == PCI_VENDOR_ID_VIA && 445 pdev->device == 0x3432) 446 xhci->quirks |= XHCI_BROKEN_STREAMS; 447 448 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) { 449 xhci->quirks |= XHCI_LPM_SUPPORT; 450 xhci->quirks |= XHCI_TRB_OVERFETCH; 451 } 452 453 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 454 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { 455 /* 456 * try to tame the ASMedia 1042 controller which reports 0.96 457 * but appears to behave more like 1.0 458 */ 459 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 460 xhci->quirks |= XHCI_BROKEN_STREAMS; 461 } 462 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 463 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { 464 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 465 } 466 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 467 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || 468 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || 469 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) 470 xhci->quirks |= XHCI_NO_64BIT_SUPPORT; 471 472 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 473 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) 474 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; 475 476 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 477 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI) 478 xhci->quirks |= XHCI_RESET_ON_RESUME; 479 480 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) 481 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; 482 483 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || 484 pdev->vendor == PCI_VENDOR_ID_CAVIUM) && 485 pdev->device == 0x9026) 486 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; 487 488 if (pdev->vendor == PCI_VENDOR_ID_AMD && 489 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || 490 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) 491 xhci->quirks |= XHCI_NO_SOFT_RETRY; 492 493 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { 494 xhci->quirks |= XHCI_ZHAOXIN_HOST; 495 xhci->quirks |= XHCI_LPM_SUPPORT; 496 497 if (pdev->device == 0x9202) { 498 xhci->quirks |= XHCI_RESET_ON_RESUME; 499 xhci->quirks |= XHCI_TRB_OVERFETCH; 500 } 501 502 if (pdev->device == 0x9203) 503 xhci->quirks |= XHCI_TRB_OVERFETCH; 504 } 505 506 if (pdev->vendor == PCI_VENDOR_ID_CDNS && 507 pdev->device == PCI_DEVICE_ID_CDNS_USBSSP) 508 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; 509 510 /* xHC spec requires PCI devices to support D3hot and D3cold */ 511 if (xhci->hci_version >= 0x120) 512 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; 513 514 if (xhci->quirks & XHCI_RESET_ON_RESUME) 515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 516 "QUIRK: Resetting on resume"); 517} 518 519#ifdef CONFIG_ACPI 520static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) 521{ 522 static const guid_t intel_dsm_guid = 523 GUID_INIT(0xac340cb7, 0xe901, 0x45bf, 524 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); 525 union acpi_object *obj; 526 527 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, 528 NULL); 529 ACPI_FREE(obj); 530} 531 532static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) 533{ 534 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 535 struct xhci_hub *rhub = &xhci->usb3_rhub; 536 int ret; 537 int i; 538 539 /* This is not the usb3 roothub we are looking for */ 540 if (hcd != rhub->hcd) 541 return; 542 543 if (hdev->maxchild > rhub->num_ports) { 544 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); 545 return; 546 } 547 548 for (i = 0; i < hdev->maxchild; i++) { 549 ret = usb_acpi_port_lpm_incapable(hdev, i); 550 551 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); 552 553 if (ret >= 0) { 554 rhub->ports[i]->lpm_incapable = ret; 555 continue; 556 } 557 } 558} 559 560#else 561static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } 562static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } 563#endif /* CONFIG_ACPI */ 564 565/* called during probe() after chip reset completes */ 566static int xhci_pci_setup(struct usb_hcd *hcd) 567{ 568 struct xhci_hcd *xhci; 569 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 570 int retval; 571 u8 sbrn; 572 573 xhci = hcd_to_xhci(hcd); 574 575 /* imod_interval is the interrupt moderation value in nanoseconds. */ 576 xhci->imod_interval = 40000; 577 578 retval = xhci_gen_setup(hcd, xhci_pci_quirks); 579 if (retval) 580 return retval; 581 582 if (!usb_hcd_is_primary_hcd(hcd)) 583 return 0; 584 585 xhci->allow_single_roothub = 1; 586 587 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 588 xhci_pme_acpi_rtd3_enable(pdev); 589 590 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &sbrn); 591 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int)sbrn); 592 593 /* Find any debug ports */ 594 return xhci_pci_reinit(xhci, pdev); 595} 596 597static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 598 struct usb_tt *tt, gfp_t mem_flags) 599{ 600 /* Check if acpi claims some USB3 roothub ports are lpm incapable */ 601 if (!hdev->parent) 602 xhci_find_lpm_incapable_ports(hcd, hdev); 603 604 return xhci_update_hub_device(hcd, hdev, tt, mem_flags); 605} 606 607/* 608 * We need to register our own PCI probe function (instead of the USB core's 609 * function) in order to create a second roothub under xHCI. 610 */ 611int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id) 612{ 613 int retval; 614 struct xhci_hcd *xhci; 615 struct usb_hcd *hcd, *usb3_hcd; 616 struct reset_control *reset; 617 618 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 619 if (IS_ERR(reset)) 620 return PTR_ERR(reset); 621 reset_control_reset(reset); 622 623 /* Prevent runtime suspending between USB-2 and USB-3 initialization */ 624 pm_runtime_get_noresume(&dev->dev); 625 626 /* Register the USB 2.0 roothub. 627 * FIXME: USB core must know to register the USB 2.0 roothub first. 628 * This is sort of silly, because we could just set the HCD driver flags 629 * to say USB 2.0, but I'm not sure what the implications would be in 630 * the other parts of the HCD code. 631 */ 632 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver); 633 634 if (retval) 635 goto put_runtime_pm; 636 637 /* USB 2.0 roothub is stored in the PCI device now. */ 638 hcd = dev_get_drvdata(&dev->dev); 639 xhci = hcd_to_xhci(hcd); 640 xhci->reset = reset; 641 642 if (!xhci_has_one_roothub(xhci)) { 643 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, 644 pci_name(dev), hcd); 645 if (!xhci->shared_hcd) { 646 retval = -ENOMEM; 647 goto dealloc_usb2_hcd; 648 } 649 650 retval = xhci_ext_cap_init(xhci); 651 if (retval) 652 goto put_usb3_hcd; 653 654 retval = usb_add_hcd(xhci->shared_hcd, dev->irq, IRQF_SHARED); 655 if (retval) 656 goto put_usb3_hcd; 657 } else { 658 retval = xhci_ext_cap_init(xhci); 659 if (retval) 660 goto dealloc_usb2_hcd; 661 } 662 663 usb3_hcd = xhci_get_usb3_hcd(xhci); 664 if (usb3_hcd && !(xhci->quirks & XHCI_BROKEN_STREAMS) && HCC_MAX_PSA(xhci->hcc_params) >= 4) 665 usb3_hcd->can_do_streams = 1; 666 667 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ 668 pm_runtime_put_noidle(&dev->dev); 669 670 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 671 pm_runtime_get(&dev->dev); 672 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 673 pm_runtime_allow(&dev->dev); 674 675 dma_set_max_seg_size(&dev->dev, UINT_MAX); 676 677 if (device_property_read_bool(&dev->dev, "ti,pwron-active-high")) 678 pci_clear_and_set_config_dword(dev, 0xE0, 0, 1 << 22); 679 680 return 0; 681 682put_usb3_hcd: 683 usb_put_hcd(xhci->shared_hcd); 684dealloc_usb2_hcd: 685 usb_hcd_pci_remove(dev); 686put_runtime_pm: 687 pm_runtime_put_noidle(&dev->dev); 688 return retval; 689} 690EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, "xhci"); 691 692/* handled by xhci-pci-renesas if enabled */ 693static const struct pci_device_id pci_ids_renesas[] = { 694 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) }, 695 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) }, 696 { /* end: all zeroes */ } 697}; 698 699static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 700{ 701 if (IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) && 702 pci_match_id(pci_ids_renesas, dev)) 703 return -ENODEV; 704 705 return xhci_pci_common_probe(dev, id); 706} 707 708void xhci_pci_remove(struct pci_dev *dev) 709{ 710 struct xhci_hcd *xhci; 711 bool set_power_d3; 712 713 xhci = hcd_to_xhci(pci_get_drvdata(dev)); 714 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; 715 716 xhci->xhc_state |= XHCI_STATE_REMOVING; 717 718 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) 719 pm_runtime_put(&dev->dev); 720 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) 721 pm_runtime_forbid(&dev->dev); 722 723 if (xhci->shared_hcd) { 724 usb_remove_hcd(xhci->shared_hcd); 725 usb_put_hcd(xhci->shared_hcd); 726 xhci->shared_hcd = NULL; 727 } 728 729 usb_hcd_pci_remove(dev); 730 731 /* Workaround for spurious wakeups at shutdown with HSW */ 732 if (set_power_d3) 733 pci_set_power_state(dev, PCI_D3hot); 734} 735EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, "xhci"); 736 737/* 738 * In some Intel xHCI controllers, in order to get D3 working, 739 * through a vendor specific SSIC CONFIG register at offset 0x883c, 740 * SSIC PORT need to be marked as "unused" before putting xHCI 741 * into D3. After D3 exit, the SSIC port need to be marked as "used". 742 * Without this change, xHCI might not enter D3 state. 743 */ 744static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) 745{ 746 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 747 u32 val; 748 void __iomem *reg; 749 int i; 750 751 for (i = 0; i < SSIC_PORT_NUM; i++) { 752 reg = (void __iomem *) xhci->cap_regs + 753 SSIC_PORT_CFG2 + 754 i * SSIC_PORT_CFG2_OFFSET; 755 756 /* Notify SSIC that SSIC profile programming is not done. */ 757 val = readl(reg) & ~PROG_DONE; 758 writel(val, reg); 759 760 /* Mark SSIC port as unused(suspend) or used(resume) */ 761 val = readl(reg); 762 if (suspend) 763 val |= SSIC_PORT_UNUSED; 764 else 765 val &= ~SSIC_PORT_UNUSED; 766 writel(val, reg); 767 768 /* Notify SSIC that SSIC profile programming is done */ 769 val = readl(reg) | PROG_DONE; 770 writel(val, reg); 771 readl(reg); 772 } 773} 774 775/* 776 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear 777 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 778 */ 779static void xhci_pme_quirk(struct usb_hcd *hcd) 780{ 781 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 782 void __iomem *reg; 783 u32 val; 784 785 reg = (void __iomem *) xhci->cap_regs + 0x80a4; 786 val = readl(reg); 787 writel(val | BIT(28), reg); 788 readl(reg); 789} 790 791static void xhci_sparse_control_quirk(struct usb_hcd *hcd) 792{ 793 u32 reg; 794 795 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); 796 reg &= ~BIT(SPARSE_DISABLE_BIT); 797 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); 798} 799 800static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 801{ 802 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 803 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 804 int ret; 805 806 /* 807 * Systems with the TI redriver that loses port status change events 808 * need to have the registers polled during D3, so avoid D3cold. 809 */ 810 if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 811 pci_d3cold_disable(pdev); 812 813#ifdef CONFIG_SUSPEND 814 /* d3cold is broken, but only when s2idle is used */ 815 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && 816 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) 817 pci_d3cold_disable(pdev); 818#endif 819 820 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 821 xhci_pme_quirk(hcd); 822 823 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 824 xhci_ssic_port_unused_quirk(hcd, true); 825 826 if (xhci->quirks & XHCI_DISABLE_SPARSE) 827 xhci_sparse_control_quirk(hcd); 828 829 ret = xhci_suspend(xhci, do_wakeup); 830 831 /* synchronize irq when using MSI-X */ 832 xhci_msix_sync_irqs(xhci); 833 834 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) 835 xhci_ssic_port_unused_quirk(hcd, false); 836 837 return ret; 838} 839 840static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) 841{ 842 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 843 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 844 bool power_lost = msg.event == PM_EVENT_RESTORE; 845 bool is_auto_resume = msg.event == PM_EVENT_AUTO_RESUME; 846 847 reset_control_reset(xhci->reset); 848 849 /* The BIOS on systems with the Intel Panther Point chipset may or may 850 * not support xHCI natively. That means that during system resume, it 851 * may switch the ports back to EHCI so that users can use their 852 * keyboard to select a kernel from GRUB after resume from hibernate. 853 * 854 * The BIOS is supposed to remember whether the OS had xHCI ports 855 * enabled before resume, and switch the ports back to xHCI when the 856 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 857 * writers. 858 * 859 * Unconditionally switch the ports back to xHCI after a system resume. 860 * It should not matter whether the EHCI or xHCI controller is 861 * resumed first. It's enough to do the switchover in xHCI because 862 * USB core won't notice anything as the hub driver doesn't start 863 * running again until after all the devices (including both EHCI and 864 * xHCI host controllers) have been resumed. 865 */ 866 867 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 868 usb_enable_intel_xhci_ports(pdev); 869 870 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) 871 xhci_ssic_port_unused_quirk(hcd, false); 872 873 if (xhci->quirks & XHCI_PME_STUCK_QUIRK) 874 xhci_pme_quirk(hcd); 875 876 return xhci_resume(xhci, power_lost, is_auto_resume); 877} 878 879static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) 880{ 881 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 882 struct xhci_port *port; 883 struct usb_device *udev; 884 u32 portsc; 885 int i; 886 887 /* 888 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that 889 * cause significant boot delay if usb ports are in suspended U3 state 890 * during boot. Some USB devices survive in U3 state over S4 hibernate 891 * 892 * Disable ports that are in U3 if remote wake is not enabled for either 893 * host controller or connected device 894 */ 895 896 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) 897 return 0; 898 899 for (i = 0; i < xhci->max_ports; i++) { 900 port = &xhci->hw_ports[i]; 901 portsc = xhci_portsc_readl(port); 902 903 if ((portsc & PORT_PLS_MASK) != XDEV_U3) 904 continue; 905 906 if (!port->slot_id || !xhci->devs[port->slot_id]) { 907 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", 908 port->slot_id, port->rhub->hcd->self.busnum, 909 port->hcd_portnum + 1); 910 continue; 911 } 912 913 udev = xhci->devs[port->slot_id]->udev; 914 915 /* if wakeup is enabled then don't disable the port */ 916 if (udev->do_remote_wakeup && do_wakeup) 917 continue; 918 919 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", 920 port->rhub->hcd->self.busnum, port->hcd_portnum + 1); 921 portsc = xhci_port_state_to_neutral(portsc); 922 xhci_portsc_writel(port, portsc | PORT_PE); 923 } 924 925 return 0; 926} 927 928static void xhci_pci_shutdown(struct usb_hcd *hcd) 929{ 930 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 931 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 932 933 xhci_shutdown(hcd); 934 xhci_cleanup_msix(xhci); 935 936 /* Yet another workaround for spurious wakeups at shutdown with HSW */ 937 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) 938 pci_set_power_state(pdev, PCI_D3hot); 939} 940 941/*-------------------------------------------------------------------------*/ 942 943/* PCI driver selection metadata; PCI hotplugging uses this */ 944static const struct pci_device_id pci_ids[] = { 945 /* handle any USB 3.0 xHCI controller */ 946 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), 947 }, 948 { /* end: all zeroes */ } 949}; 950MODULE_DEVICE_TABLE(pci, pci_ids); 951 952/* pci driver glue; this is a "new style" PCI driver module */ 953static struct pci_driver xhci_pci_driver = { 954 .name = hcd_name, 955 .id_table = pci_ids, 956 957 .probe = xhci_pci_probe, 958 .remove = xhci_pci_remove, 959 /* suspend and resume implemented later */ 960 961 .shutdown = usb_hcd_pci_shutdown, 962 .driver = { 963 .pm = pm_ptr(&usb_hcd_pci_pm_ops), 964 }, 965}; 966 967static int __init xhci_pci_init(void) 968{ 969 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); 970 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); 971 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); 972 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); 973 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); 974 xhci_pci_hc_driver.stop = xhci_pci_stop; 975 return pci_register_driver(&xhci_pci_driver); 976} 977module_init(xhci_pci_init); 978 979static void __exit xhci_pci_exit(void) 980{ 981 pci_unregister_driver(&xhci_pci_driver); 982} 983module_exit(xhci_pci_exit); 984 985MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); 986MODULE_LICENSE("GPL");
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