xhci-mem.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * xHCI host controller driver
   4 *
   5 * Copyright (C) 2008 Intel Corp.
   6 *
   7 * Author: Sarah Sharp
   8 * Some code borrowed from the Linux EHCI driver.
   9 */
  10
  11#include <linux/usb.h>
  12#include <linux/overflow.h>
  13#include <linux/pci.h>
  14#include <linux/slab.h>
  15#include <linux/dmapool.h>
  16#include <linux/dma-mapping.h>
  17
  18#include "xhci.h"
  19#include "xhci-trace.h"
  20#include "xhci-debugfs.h"
  21
  22/*
  23 * Allocates a generic ring segment from the ring pool, sets the dma address,
  24 * initializes the segment to zero, and sets the private next pointer to NULL.
  25 *
  26 * Section 4.11.1.1:
  27 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  28 */
  29static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
  30					       unsigned int max_packet,
  31					       unsigned int num,
  32					       gfp_t flags)
  33{
  34	struct xhci_segment *seg;
  35	dma_addr_t	dma;
  36	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
  37
  38	seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev));
  39	if (!seg)
  40		return NULL;
  41
  42	seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma);
  43	if (!seg->trbs) {
  44		kfree(seg);
  45		return NULL;
  46	}
  47
  48	if (max_packet) {
  49		seg->bounce_buf = kzalloc_node(max_packet, flags,
  50					dev_to_node(dev));
  51		if (!seg->bounce_buf) {
  52			dma_pool_free(xhci->segment_pool, seg->trbs, dma);
  53			kfree(seg);
  54			return NULL;
  55		}
  56	}
  57	seg->num = num;
  58	seg->dma = dma;
  59	seg->next = NULL;
  60
  61	return seg;
  62}
  63
  64static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  65{
  66	if (seg->trbs) {
  67		dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  68		seg->trbs = NULL;
  69	}
  70	kfree(seg->bounce_buf);
  71	kfree(seg);
  72}
  73
  74static void xhci_ring_segments_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
  75{
  76	struct xhci_segment *seg, *next;
  77
  78	ring->last_seg->next = NULL;
  79	seg = ring->first_seg;
  80
  81	while (seg) {
  82		next = seg->next;
  83		xhci_segment_free(xhci, seg);
  84		seg = next;
  85	}
  86}
  87
  88/*
  89 * Only for transfer and command rings where driver is the producer, not for
  90 * event rings.
  91 *
  92 * Change the last TRB in the segment to be a Link TRB which points to the
  93 * DMA address of the next segment.  The caller needs to set any Link TRB
  94 * related flags, such as End TRB, Toggle Cycle, and no snoop.
  95 */
  96static void xhci_set_link_trb(struct xhci_segment *seg, bool chain_links)
  97{
  98	union xhci_trb *trb;
  99	u32 val;
 100
 101	if (!seg || !seg->next)
 102		return;
 103
 104	trb = &seg->trbs[TRBS_PER_SEGMENT - 1];
 105
 106	/* Set the last TRB in the segment to have a TRB type ID of Link TRB */
 107	val = le32_to_cpu(trb->link.control);
 108	val &= ~TRB_TYPE_BITMASK;
 109	val |= TRB_TYPE(TRB_LINK);
 110	if (chain_links)
 111		val |= TRB_CHAIN;
 112	trb->link.control = cpu_to_le32(val);
 113	trb->link.segment_ptr = cpu_to_le64(seg->next->dma);
 114}
 115
 116static void xhci_initialize_ring_segments(struct xhci_hcd *xhci, struct xhci_ring *ring)
 117{
 118	struct xhci_segment *seg;
 119	bool chain_links;
 120
 121	if (ring->type == TYPE_EVENT)
 122		return;
 123
 124	chain_links = xhci_link_chain_quirk(xhci, ring->type);
 125	xhci_for_each_ring_seg(ring->first_seg, seg)
 126		xhci_set_link_trb(seg, chain_links);
 127
 128	/* See section 4.9.2.1 and 6.4.4.1 */
 129	ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= cpu_to_le32(LINK_TOGGLE);
 130}
 131
 132/*
 133 * Link the src ring segments to the dst ring.
 134 * Set Toggle Cycle for the new ring if needed.
 135 */
 136static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *src, struct xhci_ring *dst)
 137{
 138	struct xhci_segment *seg;
 139	bool chain_links;
 140
 141	if (!src || !dst)
 142		return;
 143
 144	/* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
 145	if (dst->cycle_state == 0) {
 146		xhci_for_each_ring_seg(src->first_seg, seg) {
 147			for (int i = 0; i < TRBS_PER_SEGMENT; i++)
 148				seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
 149		}
 150	}
 151
 152	src->last_seg->next = dst->enq_seg->next;
 153	dst->enq_seg->next = src->first_seg;
 154	if (dst->type != TYPE_EVENT) {
 155		chain_links = xhci_link_chain_quirk(xhci, dst->type);
 156		xhci_set_link_trb(dst->enq_seg, chain_links);
 157		xhci_set_link_trb(src->last_seg, chain_links);
 158	}
 159	dst->num_segs += src->num_segs;
 160
 161	if (dst->enq_seg == dst->last_seg) {
 162		if (dst->type != TYPE_EVENT)
 163			dst->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
 164				&= ~cpu_to_le32(LINK_TOGGLE);
 165
 166		dst->last_seg = src->last_seg;
 167	} else if (dst->type != TYPE_EVENT) {
 168		src->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control &= ~cpu_to_le32(LINK_TOGGLE);
 169	}
 170
 171	for (seg = dst->enq_seg; seg != dst->last_seg; seg = seg->next)
 172		seg->next->num = seg->num + 1;
 173}
 174
 175/*
 176 * We need a radix tree for mapping physical addresses of TRBs to which stream
 177 * ID they belong to.  We need to do this because the host controller won't tell
 178 * us which stream ring the TRB came from.  We could store the stream ID in an
 179 * event data TRB, but that doesn't help us for the cancellation case, since the
 180 * endpoint may stop before it reaches that event data TRB.
 181 *
 182 * The radix tree maps the upper portion of the TRB DMA address to a ring
 183 * segment that has the same upper portion of DMA addresses.  For example, say I
 184 * have segments of size 1KB, that are always 1KB aligned.  A segment may
 185 * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 186 * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 187 * pass the radix tree a key to get the right stream ID:
 188 *
 189 *	0x10c90fff >> 10 = 0x43243
 190 *	0x10c912c0 >> 10 = 0x43244
 191 *	0x10c91400 >> 10 = 0x43245
 192 *
 193 * Obviously, only those TRBs with DMA addresses that are within the segment
 194 * will make the radix tree return the stream ID for that ring.
 195 *
 196 * Caveats for the radix tree:
 197 *
 198 * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 199 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 200 * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 201 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 202 * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 203 * extended systems (where the DMA address can be bigger than 32-bits),
 204 * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 205 */
 206static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
 207		struct xhci_ring *ring,
 208		struct xhci_segment *seg,
 209		gfp_t mem_flags)
 210{
 211	unsigned long key;
 212	int ret;
 213
 214	key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
 215	/* Skip any segments that were already added. */
 216	if (radix_tree_lookup(trb_address_map, key))
 217		return 0;
 218
 219	ret = radix_tree_maybe_preload(mem_flags);
 220	if (ret)
 221		return ret;
 222	ret = radix_tree_insert(trb_address_map,
 223			key, ring);
 224	radix_tree_preload_end();
 225	return ret;
 226}
 227
 228static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
 229		struct xhci_segment *seg)
 230{
 231	unsigned long key;
 232
 233	key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
 234	if (radix_tree_lookup(trb_address_map, key))
 235		radix_tree_delete(trb_address_map, key);
 236}
 237
 238static int xhci_update_stream_segment_mapping(
 239		struct radix_tree_root *trb_address_map,
 240		struct xhci_ring *ring,
 241		struct xhci_segment *first_seg,
 242		gfp_t mem_flags)
 243{
 244	struct xhci_segment *seg;
 245	struct xhci_segment *failed_seg;
 246	int ret;
 247
 248	if (WARN_ON_ONCE(trb_address_map == NULL))
 249		return 0;
 250
 251	xhci_for_each_ring_seg(first_seg, seg) {
 252		ret = xhci_insert_segment_mapping(trb_address_map,
 253				ring, seg, mem_flags);
 254		if (ret)
 255			goto remove_streams;
 256	}
 257
 258	return 0;
 259
 260remove_streams:
 261	failed_seg = seg;
 262	xhci_for_each_ring_seg(first_seg, seg) {
 263		xhci_remove_segment_mapping(trb_address_map, seg);
 264		if (seg == failed_seg)
 265			return ret;
 266	}
 267
 268	return ret;
 269}
 270
 271static void xhci_remove_stream_mapping(struct xhci_ring *ring)
 272{
 273	struct xhci_segment *seg;
 274
 275	if (WARN_ON_ONCE(ring->trb_address_map == NULL))
 276		return;
 277
 278	xhci_for_each_ring_seg(ring->first_seg, seg)
 279		xhci_remove_segment_mapping(ring->trb_address_map, seg);
 280}
 281
 282static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
 283{
 284	return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
 285			ring->first_seg, mem_flags);
 286}
 287
 288/* XXX: Do we need the hcd structure in all these functions? */
 289void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 290{
 291	if (!ring)
 292		return;
 293
 294	trace_xhci_ring_free(ring);
 295
 296	if (ring->first_seg) {
 297		if (ring->type == TYPE_STREAM)
 298			xhci_remove_stream_mapping(ring);
 299		xhci_ring_segments_free(xhci, ring);
 300	}
 301
 302	kfree(ring);
 303}
 304
 305void xhci_initialize_ring_info(struct xhci_ring *ring)
 306{
 307	/* The ring is empty, so the enqueue pointer == dequeue pointer */
 308	ring->enqueue = ring->first_seg->trbs;
 309	ring->enq_seg = ring->first_seg;
 310	ring->dequeue = ring->enqueue;
 311	ring->deq_seg = ring->first_seg;
 312	/* The ring is initialized to 0. The producer must write 1 to the cycle
 313	 * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 314	 * compare CCS to the cycle bit to check ownership, so CCS = 1.
 315	 *
 316	 * New rings are initialized with cycle state equal to 1; if we are
 317	 * handling ring expansion, set the cycle state equal to the old ring.
 318	 */
 319	ring->cycle_state = 1;
 320
 321	/*
 322	 * Each segment has a link TRB, and leave an extra TRB for SW
 323	 * accounting purpose
 324	 */
 325	ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 326}
 327EXPORT_SYMBOL_GPL(xhci_initialize_ring_info);
 328
 329/* Allocate segments and link them for a ring */
 330static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, gfp_t flags)
 331{
 332	struct xhci_segment *prev;
 333	unsigned int num = 0;
 334
 335	prev = xhci_segment_alloc(xhci, ring->bounce_buf_len, num, flags);
 336	if (!prev)
 337		return -ENOMEM;
 338	num++;
 339
 340	ring->first_seg = prev;
 341	while (num < ring->num_segs) {
 342		struct xhci_segment	*next;
 343
 344		next = xhci_segment_alloc(xhci, ring->bounce_buf_len, num, flags);
 345		if (!next)
 346			goto free_segments;
 347
 348		prev->next = next;
 349		prev = next;
 350		num++;
 351	}
 352	ring->last_seg = prev;
 353
 354	ring->last_seg->next = ring->first_seg;
 355	return 0;
 356
 357free_segments:
 358	ring->last_seg = prev;
 359	xhci_ring_segments_free(xhci, ring);
 360	return -ENOMEM;
 361}
 362
 363/*
 364 * Create a new ring with zero or more segments.
 365 *
 366 * Link each segment together into a ring.
 367 * Set the end flag and the cycle toggle bit on the last segment.
 368 * See section 4.9.1 and figures 15 and 16.
 369 */
 370struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs,
 371				  enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
 372{
 373	struct xhci_ring	*ring;
 374	int ret;
 375	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 376
 377	ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev));
 378	if (!ring)
 379		return NULL;
 380
 381	ring->num_segs = num_segs;
 382	ring->bounce_buf_len = max_packet;
 383	INIT_LIST_HEAD(&ring->td_list);
 384	ring->type = type;
 385	if (num_segs == 0)
 386		return ring;
 387
 388	ret = xhci_alloc_segments_for_ring(xhci, ring, flags);
 389	if (ret)
 390		goto fail;
 391
 392	xhci_initialize_ring_segments(xhci, ring);
 393	xhci_initialize_ring_info(ring);
 394	trace_xhci_ring_alloc(ring);
 395	return ring;
 396
 397fail:
 398	kfree(ring);
 399	return NULL;
 400}
 401
 402void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
 403		struct xhci_virt_device *virt_dev,
 404		unsigned int ep_index)
 405{
 406	xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 407	virt_dev->eps[ep_index].ring = NULL;
 408}
 409
 410/*
 411 * Expand an existing ring.
 412 * Allocate a new ring which has same segment numbers and link the two rings.
 413 */
 414int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
 415				unsigned int num_new_segs, gfp_t flags)
 416{
 417	struct xhci_ring new_ring;
 418	int ret;
 419
 420	if (num_new_segs == 0)
 421		return 0;
 422
 423	new_ring.num_segs = num_new_segs;
 424	new_ring.bounce_buf_len = ring->bounce_buf_len;
 425	new_ring.type = ring->type;
 426	ret = xhci_alloc_segments_for_ring(xhci, &new_ring, flags);
 427	if (ret)
 428		return -ENOMEM;
 429
 430	xhci_initialize_ring_segments(xhci, &new_ring);
 431
 432	if (ring->type == TYPE_STREAM) {
 433		ret = xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
 434							 new_ring.first_seg, flags);
 435		if (ret)
 436			goto free_segments;
 437	}
 438
 439	xhci_link_rings(xhci, &new_ring, ring);
 440	trace_xhci_ring_expansion(ring);
 441	xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
 442			"ring expansion succeed, now has %d segments",
 443			ring->num_segs);
 444
 445	return 0;
 446
 447free_segments:
 448	xhci_ring_segments_free(xhci, &new_ring);
 449	return ret;
 450}
 451
 452struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 453						    int type, gfp_t flags)
 454{
 455	struct xhci_container_ctx *ctx;
 456	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 457
 458	if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
 459		return NULL;
 460
 461	ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
 462	if (!ctx)
 463		return NULL;
 464
 465	ctx->type = type;
 466	ctx->size = xhci->hcc_params & HCC_64BYTE_CONTEXT ? 2048 : 1024;
 467	if (type == XHCI_CTX_TYPE_INPUT)
 468		ctx->size += CTX_SIZE(xhci->hcc_params);
 469
 470	ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma);
 471	if (!ctx->bytes) {
 472		kfree(ctx);
 473		return NULL;
 474	}
 475	return ctx;
 476}
 477
 478void xhci_free_container_ctx(struct xhci_hcd *xhci,
 479			     struct xhci_container_ctx *ctx)
 480{
 481	if (!ctx)
 482		return;
 483	dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 484	kfree(ctx);
 485}
 486
 487struct xhci_container_ctx *xhci_alloc_port_bw_ctx(struct xhci_hcd *xhci,
 488						  gfp_t flags)
 489{
 490	struct xhci_container_ctx *ctx;
 491	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 492
 493	ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
 494	if (!ctx)
 495		return NULL;
 496
 497	ctx->size = GET_PORT_BW_ARRAY_SIZE;
 498
 499	ctx->bytes = dma_pool_zalloc(xhci->port_bw_pool, flags, &ctx->dma);
 500	if (!ctx->bytes) {
 501		kfree(ctx);
 502		return NULL;
 503	}
 504	return ctx;
 505}
 506
 507void xhci_free_port_bw_ctx(struct xhci_hcd *xhci,
 508			     struct xhci_container_ctx *ctx)
 509{
 510	if (!ctx)
 511		return;
 512	dma_pool_free(xhci->port_bw_pool, ctx->bytes, ctx->dma);
 513	kfree(ctx);
 514}
 515
 516struct xhci_input_control_ctx *xhci_get_input_control_ctx(
 517					      struct xhci_container_ctx *ctx)
 518{
 519	if (ctx->type != XHCI_CTX_TYPE_INPUT)
 520		return NULL;
 521
 522	return (struct xhci_input_control_ctx *)ctx->bytes;
 523}
 524
 525struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 526					struct xhci_container_ctx *ctx)
 527{
 528	if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 529		return (struct xhci_slot_ctx *)ctx->bytes;
 530
 531	return (struct xhci_slot_ctx *)
 532		(ctx->bytes + CTX_SIZE(xhci->hcc_params));
 533}
 534
 535struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 536				    struct xhci_container_ctx *ctx,
 537				    unsigned int ep_index)
 538{
 539	/* increment ep index by offset of start of ep ctx array */
 540	ep_index++;
 541	if (ctx->type == XHCI_CTX_TYPE_INPUT)
 542		ep_index++;
 543
 544	return (struct xhci_ep_ctx *)
 545		(ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 546}
 547EXPORT_SYMBOL_GPL(xhci_get_ep_ctx);
 548
 549/***************** Streams structures manipulation *************************/
 550
 551static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 552		unsigned int num_stream_ctxs,
 553		struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 554{
 555	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 556	size_t size = array_size(sizeof(struct xhci_stream_ctx), num_stream_ctxs);
 557
 558	if (size > MEDIUM_STREAM_ARRAY_SIZE)
 559		dma_free_coherent(dev, size, stream_ctx, dma);
 560	else if (size > SMALL_STREAM_ARRAY_SIZE)
 561		dma_pool_free(xhci->medium_streams_pool, stream_ctx, dma);
 562	else
 563		dma_pool_free(xhci->small_streams_pool, stream_ctx, dma);
 564}
 565
 566/*
 567 * The stream context array for each endpoint with bulk streams enabled can
 568 * vary in size, based on:
 569 *  - how many streams the endpoint supports,
 570 *  - the maximum primary stream array size the host controller supports,
 571 *  - and how many streams the device driver asks for.
 572 *
 573 * The stream context array must be a power of 2, and can be as small as
 574 * 64 bytes or as large as 1MB.
 575 */
 576static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 577		unsigned int num_stream_ctxs, dma_addr_t *dma,
 578		gfp_t mem_flags)
 579{
 580	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 581	size_t size = array_size(sizeof(struct xhci_stream_ctx), num_stream_ctxs);
 582
 583	if (size > MEDIUM_STREAM_ARRAY_SIZE)
 584		return dma_alloc_coherent(dev, size, dma, mem_flags);
 585	if (size > SMALL_STREAM_ARRAY_SIZE)
 586		return dma_pool_zalloc(xhci->medium_streams_pool, mem_flags, dma);
 587	else
 588		return dma_pool_zalloc(xhci->small_streams_pool, mem_flags, dma);
 589}
 590
 591struct xhci_ring *xhci_dma_to_transfer_ring(
 592		struct xhci_virt_ep *ep,
 593		u64 address)
 594{
 595	if (ep->ep_state & EP_HAS_STREAMS)
 596		return radix_tree_lookup(&ep->stream_info->trb_address_map,
 597				address >> TRB_SEGMENT_SHIFT);
 598	return ep->ring;
 599}
 600
 601/*
 602 * Change an endpoint's internal structure so it supports stream IDs.  The
 603 * number of requested streams includes stream 0, which cannot be used by device
 604 * drivers.
 605 *
 606 * The number of stream contexts in the stream context array may be bigger than
 607 * the number of streams the driver wants to use.  This is because the number of
 608 * stream context array entries must be a power of two.
 609 */
 610struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 611		unsigned int num_stream_ctxs,
 612		unsigned int num_streams,
 613		unsigned int max_packet, gfp_t mem_flags)
 614{
 615	struct xhci_stream_info *stream_info;
 616	u32 cur_stream;
 617	struct xhci_ring *cur_ring;
 618	u64 addr;
 619	int ret;
 620	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 621
 622	xhci_dbg(xhci, "Allocating %u streams and %u stream context array entries.\n",
 623			num_streams, num_stream_ctxs);
 624	if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 625		xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 626		return NULL;
 627	}
 628	xhci->cmd_ring_reserved_trbs++;
 629
 630	stream_info = kzalloc_node(sizeof(*stream_info), mem_flags,
 631			dev_to_node(dev));
 632	if (!stream_info)
 633		goto cleanup_trbs;
 634
 635	stream_info->num_streams = num_streams;
 636	stream_info->num_stream_ctxs = num_stream_ctxs;
 637
 638	/* Initialize the array of virtual pointers to stream rings. */
 639	stream_info->stream_rings = kcalloc_node(
 640			num_streams, sizeof(struct xhci_ring *), mem_flags,
 641			dev_to_node(dev));
 642	if (!stream_info->stream_rings)
 643		goto cleanup_info;
 644
 645	/* Initialize the array of DMA addresses for stream rings for the HW. */
 646	stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 647			num_stream_ctxs, &stream_info->ctx_array_dma,
 648			mem_flags);
 649	if (!stream_info->stream_ctx_array)
 650		goto cleanup_ring_array;
 651
 652	/* Allocate everything needed to free the stream rings later */
 653	stream_info->free_streams_command =
 654		xhci_alloc_command_with_ctx(xhci, true, mem_flags);
 655	if (!stream_info->free_streams_command)
 656		goto cleanup_ctx;
 657
 658	INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 659
 660	/* Allocate rings for all the streams that the driver will use,
 661	 * and add their segment DMA addresses to the radix tree.
 662	 * Stream 0 is reserved.
 663	 */
 664
 665	for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 666		stream_info->stream_rings[cur_stream] =
 667			xhci_ring_alloc(xhci, 2, TYPE_STREAM, max_packet, mem_flags);
 668		cur_ring = stream_info->stream_rings[cur_stream];
 669		if (!cur_ring)
 670			goto cleanup_rings;
 671		cur_ring->stream_id = cur_stream;
 672		cur_ring->trb_address_map = &stream_info->trb_address_map;
 673		/* Set deq ptr, cycle bit, and stream context type */
 674		addr = cur_ring->first_seg->dma |
 675			SCT_FOR_CTX(SCT_PRI_TR) |
 676			cur_ring->cycle_state;
 677		stream_info->stream_ctx_array[cur_stream].stream_ring =
 678			cpu_to_le64(addr);
 679		xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", cur_stream, addr);
 680
 681		ret = xhci_update_stream_mapping(cur_ring, mem_flags);
 682
 683		trace_xhci_alloc_stream_info_ctx(stream_info, cur_stream);
 684		if (ret) {
 685			xhci_ring_free(xhci, cur_ring);
 686			stream_info->stream_rings[cur_stream] = NULL;
 687			goto cleanup_rings;
 688		}
 689	}
 690	/* Leave the other unused stream ring pointers in the stream context
 691	 * array initialized to zero.  This will cause the xHC to give us an
 692	 * error if the device asks for a stream ID we don't have setup (if it
 693	 * was any other way, the host controller would assume the ring is
 694	 * "empty" and wait forever for data to be queued to that stream ID).
 695	 */
 696
 697	return stream_info;
 698
 699cleanup_rings:
 700	for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 701		cur_ring = stream_info->stream_rings[cur_stream];
 702		if (cur_ring) {
 703			xhci_ring_free(xhci, cur_ring);
 704			stream_info->stream_rings[cur_stream] = NULL;
 705		}
 706	}
 707	xhci_free_command(xhci, stream_info->free_streams_command);
 708cleanup_ctx:
 709	xhci_free_stream_ctx(xhci,
 710		stream_info->num_stream_ctxs,
 711		stream_info->stream_ctx_array,
 712		stream_info->ctx_array_dma);
 713cleanup_ring_array:
 714	kfree(stream_info->stream_rings);
 715cleanup_info:
 716	kfree(stream_info);
 717cleanup_trbs:
 718	xhci->cmd_ring_reserved_trbs--;
 719	return NULL;
 720}
 721/*
 722 * Sets the MaxPStreams field and the Linear Stream Array field.
 723 * Sets the dequeue pointer to the stream context array.
 724 */
 725void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 726		struct xhci_ep_ctx *ep_ctx,
 727		struct xhci_stream_info *stream_info)
 728{
 729	u32 max_primary_streams;
 730	/* MaxPStreams is the number of stream context array entries, not the
 731	 * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 732	 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 733	 */
 734	max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 735	xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
 736			"Setting number of stream ctx array entries to %u",
 737			1 << (max_primary_streams + 1));
 738	ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 739	ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 740				       | EP_HAS_LSA);
 741	ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 742}
 743
 744/*
 745 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 746 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 747 * not at the beginning of the ring).
 748 */
 749void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
 750		struct xhci_virt_ep *ep)
 751{
 752	dma_addr_t addr;
 753	ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 754	addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 755	ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 756}
 757
 758/* Frees all stream contexts associated with the endpoint,
 759 *
 760 * Caller should fix the endpoint context streams fields.
 761 */
 762void xhci_free_stream_info(struct xhci_hcd *xhci,
 763		struct xhci_stream_info *stream_info)
 764{
 765	int cur_stream;
 766	struct xhci_ring *cur_ring;
 767
 768	if (!stream_info)
 769		return;
 770
 771	for (cur_stream = 1; cur_stream < stream_info->num_streams;
 772			cur_stream++) {
 773		cur_ring = stream_info->stream_rings[cur_stream];
 774		if (cur_ring) {
 775			xhci_ring_free(xhci, cur_ring);
 776			stream_info->stream_rings[cur_stream] = NULL;
 777		}
 778	}
 779	xhci_free_command(xhci, stream_info->free_streams_command);
 780	xhci->cmd_ring_reserved_trbs--;
 781	if (stream_info->stream_ctx_array)
 782		xhci_free_stream_ctx(xhci,
 783				stream_info->num_stream_ctxs,
 784				stream_info->stream_ctx_array,
 785				stream_info->ctx_array_dma);
 786
 787	kfree(stream_info->stream_rings);
 788	kfree(stream_info);
 789}
 790
 791
 792/***************** Device context manipulation *************************/
 793
 794static void xhci_free_tt_info(struct xhci_hcd *xhci,
 795		struct xhci_virt_device *virt_dev,
 796		int slot_id)
 797{
 798	struct list_head *tt_list_head;
 799	struct xhci_tt_bw_info *tt_info, *next;
 800	bool slot_found = false;
 801
 802	/* If the device never made it past the Set Address stage,
 803	 * it may not have the root hub port pointer set correctly.
 804	 */
 805	if (!virt_dev->rhub_port) {
 806		xhci_dbg(xhci, "Bad rhub port.\n");
 807		return;
 808	}
 809
 810	tt_list_head = &(xhci->rh_bw[virt_dev->rhub_port->hw_portnum].tts);
 811	list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 812		/* Multi-TT hubs will have more than one entry */
 813		if (tt_info->slot_id == slot_id) {
 814			slot_found = true;
 815			list_del(&tt_info->tt_list);
 816			kfree(tt_info);
 817		} else if (slot_found) {
 818			break;
 819		}
 820	}
 821}
 822
 823int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 824		struct xhci_virt_device *virt_dev,
 825		struct usb_device *hdev,
 826		struct usb_tt *tt, gfp_t mem_flags)
 827{
 828	struct xhci_tt_bw_info		*tt_info;
 829	unsigned int			num_ports;
 830	int				i, j;
 831	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 832
 833	if (!tt->multi)
 834		num_ports = 1;
 835	else
 836		num_ports = hdev->maxchild;
 837
 838	for (i = 0; i < num_ports; i++, tt_info++) {
 839		struct xhci_interval_bw_table *bw_table;
 840
 841		tt_info = kzalloc_node(sizeof(*tt_info), mem_flags,
 842				dev_to_node(dev));
 843		if (!tt_info)
 844			goto free_tts;
 845		INIT_LIST_HEAD(&tt_info->tt_list);
 846		list_add(&tt_info->tt_list,
 847				&xhci->rh_bw[virt_dev->rhub_port->hw_portnum].tts);
 848		tt_info->slot_id = virt_dev->udev->slot_id;
 849		if (tt->multi)
 850			tt_info->ttport = i+1;
 851		bw_table = &tt_info->bw_table;
 852		for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 853			INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 854	}
 855	return 0;
 856
 857free_tts:
 858	xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 859	return -ENOMEM;
 860}
 861
 862
 863/* All the xhci_tds in the ring's TD list should be freed at this point.
 864 * Should be called with xhci->lock held if there is any chance the TT lists
 865 * will be manipulated by the configure endpoint, allocate device, or update
 866 * hub functions while this function is removing the TT entries from the list.
 867 */
 868void xhci_free_virt_device(struct xhci_hcd *xhci, struct xhci_virt_device *dev,
 869		int slot_id)
 870{
 871	int i;
 872	int old_active_eps = 0;
 873
 874	/* Slot ID 0 is reserved */
 875	if (slot_id == 0 || !dev)
 876		return;
 877
 878	/* If device ctx array still points to _this_ device, clear it */
 879	if (dev->out_ctx &&
 880	    xhci->dcbaa->dev_context_ptrs[slot_id] == cpu_to_le64(dev->out_ctx->dma))
 881		xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 882
 883	trace_xhci_free_virt_device(dev);
 884
 885	if (dev->tt_info)
 886		old_active_eps = dev->tt_info->active_eps;
 887
 888	for (i = 0; i < 31; i++) {
 889		if (dev->eps[i].ring)
 890			xhci_ring_free(xhci, dev->eps[i].ring);
 891		if (dev->eps[i].stream_info)
 892			xhci_free_stream_info(xhci,
 893					dev->eps[i].stream_info);
 894		/*
 895		 * Endpoints are normally deleted from the bandwidth list when
 896		 * endpoints are dropped, before device is freed.
 897		 * If host is dying or being removed then endpoints aren't
 898		 * dropped cleanly, so delete the endpoint from list here.
 899		 * Only applicable for hosts with software bandwidth checking.
 900		 */
 901
 902		if (!list_empty(&dev->eps[i].bw_endpoint_list)) {
 903			list_del_init(&dev->eps[i].bw_endpoint_list);
 904			xhci_dbg(xhci, "Slot %u endpoint %u not removed from BW list!\n",
 905				 slot_id, i);
 906		}
 907	}
 908	/* If this is a hub, free the TT(s) from the TT list */
 909	xhci_free_tt_info(xhci, dev, slot_id);
 910	/* If necessary, update the number of active TTs on this root port */
 911	xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 912
 913	if (dev->in_ctx)
 914		xhci_free_container_ctx(xhci, dev->in_ctx);
 915	if (dev->out_ctx)
 916		xhci_free_container_ctx(xhci, dev->out_ctx);
 917
 918	if (dev->udev && dev->udev->slot_id)
 919		dev->udev->slot_id = 0;
 920	if (dev->rhub_port && dev->rhub_port->slot_id == slot_id)
 921		dev->rhub_port->slot_id = 0;
 922	if (xhci->devs[slot_id] == dev)
 923		xhci->devs[slot_id] = NULL;
 924	kfree(dev);
 925}
 926
 927/*
 928 * Free a virt_device structure.
 929 * If the virt_device added a tt_info (a hub) and has children pointing to
 930 * that tt_info, then free the child first. Recursive.
 931 * We can't rely on udev at this point to find child-parent relationships.
 932 */
 933static void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
 934{
 935	struct xhci_virt_device *vdev;
 936	struct list_head *tt_list_head;
 937	struct xhci_tt_bw_info *tt_info, *next;
 938	int i;
 939
 940	vdev = xhci->devs[slot_id];
 941	if (!vdev)
 942		return;
 943
 944	if (!vdev->rhub_port) {
 945		xhci_dbg(xhci, "Bad rhub port.\n");
 946		goto out;
 947	}
 948
 949	tt_list_head = &(xhci->rh_bw[vdev->rhub_port->hw_portnum].tts);
 950	list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 951		/* is this a hub device that added a tt_info to the tts list */
 952		if (tt_info->slot_id == slot_id) {
 953			/* are any devices using this tt_info? */
 954			for (i = 1; i < xhci->max_slots; i++) {
 955				vdev = xhci->devs[i];
 956				if (vdev && (vdev->tt_info == tt_info))
 957					xhci_free_virt_devices_depth_first(
 958						xhci, i);
 959			}
 960		}
 961	}
 962out:
 963	/* we are now at a leaf device */
 964	xhci_debugfs_remove_slot(xhci, slot_id);
 965	xhci_free_virt_device(xhci, xhci->devs[slot_id], slot_id);
 966}
 967
 968int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 969		struct usb_device *udev, gfp_t flags)
 970{
 971	struct xhci_virt_device *dev;
 972	int i;
 973
 974	/* Slot ID 0 is reserved */
 975	if (slot_id == 0 || xhci->devs[slot_id]) {
 976		xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 977		return 0;
 978	}
 979
 980	dev = kzalloc(sizeof(*dev), flags);
 981	if (!dev)
 982		return 0;
 983
 984	dev->slot_id = slot_id;
 985
 986	/* Allocate the (output) device context that will be used in the HC. */
 987	dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 988	if (!dev->out_ctx)
 989		goto fail;
 990
 991	xhci_dbg(xhci, "Slot %d output ctx = 0x%pad (dma)\n", slot_id, &dev->out_ctx->dma);
 992
 993	/* Allocate the (input) device context for address device command */
 994	dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 995	if (!dev->in_ctx)
 996		goto fail;
 997
 998	xhci_dbg(xhci, "Slot %d input ctx = 0x%pad (dma)\n", slot_id, &dev->in_ctx->dma);
 999
1000	/* Initialize the cancellation and bandwidth list for each ep */
1001	for (i = 0; i < 31; i++) {
1002		dev->eps[i].ep_index = i;
1003		dev->eps[i].vdev = dev;
1004		dev->eps[i].xhci = xhci;
1005		INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1006		INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1007	}
1008
1009	/* Allocate endpoint 0 ring */
1010	dev->eps[0].ring = xhci_ring_alloc(xhci, 2, TYPE_CTRL, 0, flags);
1011	if (!dev->eps[0].ring)
1012		goto fail;
1013
1014	dev->udev = udev;
1015
1016	/* Point to output device context in dcbaa. */
1017	xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1018	xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1019		 slot_id,
1020		 &xhci->dcbaa->dev_context_ptrs[slot_id],
1021		 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1022
1023	trace_xhci_alloc_virt_device(dev);
1024
1025	xhci->devs[slot_id] = dev;
1026
1027	return 1;
1028fail:
1029
1030	if (dev->in_ctx)
1031		xhci_free_container_ctx(xhci, dev->in_ctx);
1032	if (dev->out_ctx)
1033		xhci_free_container_ctx(xhci, dev->out_ctx);
1034	kfree(dev);
1035
1036	return 0;
1037}
1038
1039void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1040		struct usb_device *udev)
1041{
1042	struct xhci_virt_device *virt_dev;
1043	struct xhci_ep_ctx	*ep0_ctx;
1044	struct xhci_ring	*ep_ring;
1045
1046	virt_dev = xhci->devs[udev->slot_id];
1047	ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1048	ep_ring = virt_dev->eps[0].ring;
1049	/*
1050	 * FIXME we don't keep track of the dequeue pointer very well after a
1051	 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1052	 * host to our enqueue pointer.  This should only be called after a
1053	 * configured device has reset, so all control transfers should have
1054	 * been completed or cancelled before the reset.
1055	 */
1056	ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1057							ep_ring->enqueue)
1058				   | ep_ring->cycle_state);
1059}
1060
1061/*
1062 * The xHCI roothub may have ports of differing speeds in any order in the port
1063 * status registers.
1064 *
1065 * The xHCI hardware wants to know the roothub port that the USB device
1066 * is attached to (or the roothub port its ancestor hub is attached to).  All we
1067 * know is the index of that port under either the USB 2.0 or the USB 3.0
1068 * roothub, but that doesn't give us the real index into the HW port status
1069 * registers.
1070 */
1071static struct xhci_port *xhci_find_rhub_port(struct xhci_hcd *xhci, struct usb_device *udev)
1072{
1073	struct usb_device *top_dev;
1074	struct xhci_hub *rhub;
1075	struct usb_hcd *hcd;
1076
1077	if (udev->speed >= USB_SPEED_SUPER)
1078		hcd = xhci_get_usb3_hcd(xhci);
1079	else
1080		hcd = xhci->main_hcd;
1081
1082	for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1083			top_dev = top_dev->parent)
1084		/* Found device below root hub */;
1085
1086	rhub = xhci_get_rhub(hcd);
1087	return rhub->ports[top_dev->portnum - 1];
1088}
1089
1090/* Setup an xHCI virtual device for a Set Address command */
1091int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1092{
1093	struct xhci_virt_device *dev;
1094	struct xhci_ep_ctx	*ep0_ctx;
1095	struct xhci_slot_ctx    *slot_ctx;
1096	u32			max_packets;
1097
1098	dev = xhci->devs[udev->slot_id];
1099	/* Slot ID 0 is reserved */
1100	if (udev->slot_id == 0 || !dev) {
1101		xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1102				udev->slot_id);
1103		return -EINVAL;
1104	}
1105	ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1106	slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1107
1108	/* 3) Only the control endpoint is valid - one endpoint context */
1109	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1110	switch (udev->speed) {
1111	case USB_SPEED_SUPER_PLUS:
1112		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1113		max_packets = MAX_PACKET(512);
1114		break;
1115	case USB_SPEED_SUPER:
1116		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1117		max_packets = MAX_PACKET(512);
1118		break;
1119	case USB_SPEED_HIGH:
1120		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1121		max_packets = MAX_PACKET(64);
1122		break;
1123	/* USB core guesses at a 64-byte max packet first for FS devices */
1124	case USB_SPEED_FULL:
1125		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1126		max_packets = MAX_PACKET(64);
1127		break;
1128	case USB_SPEED_LOW:
1129		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1130		max_packets = MAX_PACKET(8);
1131		break;
1132	default:
1133		/* Speed was set earlier, this shouldn't happen. */
1134		return -EINVAL;
1135	}
1136	/* Find the root hub port this device is under */
1137	dev->rhub_port = xhci_find_rhub_port(xhci, udev);
1138	if (!dev->rhub_port)
1139		return -EINVAL;
1140	/* Slot ID is set to the device directly below the root hub */
1141	if (!udev->parent->parent)
1142		dev->rhub_port->slot_id = udev->slot_id;
1143	slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(dev->rhub_port->hw_portnum + 1));
1144	xhci_dbg(xhci, "Slot ID %d: HW portnum %d, hcd portnum %d\n",
1145		 udev->slot_id, dev->rhub_port->hw_portnum, dev->rhub_port->hcd_portnum);
1146
1147	/* Find the right bandwidth table that this device will be a part of.
1148	 * If this is a full speed device attached directly to a root port (or a
1149	 * decendent of one), it counts as a primary bandwidth domain, not a
1150	 * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1151	 * will never be created for the HS root hub.
1152	 */
1153	if (!udev->tt || !udev->tt->hub->parent) {
1154		dev->bw_table = &xhci->rh_bw[dev->rhub_port->hw_portnum].bw_table;
1155	} else {
1156		struct xhci_root_port_bw_info *rh_bw;
1157		struct xhci_tt_bw_info *tt_bw;
1158
1159		rh_bw = &xhci->rh_bw[dev->rhub_port->hw_portnum];
1160		/* Find the right TT. */
1161		list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1162			if (tt_bw->slot_id != udev->tt->hub->slot_id)
1163				continue;
1164
1165			if (!dev->udev->tt->multi ||
1166					(udev->tt->multi &&
1167					 tt_bw->ttport == dev->udev->ttport)) {
1168				dev->bw_table = &tt_bw->bw_table;
1169				dev->tt_info = tt_bw;
1170				break;
1171			}
1172		}
1173		if (!dev->tt_info)
1174			xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1175	}
1176
1177	/* Is this a LS/FS device under an external HS hub? */
1178	if (udev->tt && udev->tt->hub->parent) {
1179		slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1180						(udev->ttport << 8));
1181		if (udev->tt->multi)
1182			slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1183	}
1184	xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1185	xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1186
1187	/* Step 4 - ring already allocated */
1188	/* Step 5 */
1189	ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1190
1191	/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1192	ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1193					 max_packets);
1194
1195	ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1196				   dev->eps[0].ring->cycle_state);
1197
1198	ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(8));
1199
1200	trace_xhci_setup_addressable_virt_device(dev);
1201
1202	/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1203
1204	return 0;
1205}
1206
1207/*
1208 * Convert interval expressed as 2^(bInterval - 1) == interval into
1209 * straight exponent value 2^n == interval.
1210 *
1211 */
1212static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1213		struct usb_host_endpoint *ep)
1214{
1215	unsigned int interval;
1216
1217	interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1218	if (interval != ep->desc.bInterval - 1)
1219		dev_warn(&udev->dev,
1220			 "ep %#x - rounding interval to %d %sframes\n",
1221			 ep->desc.bEndpointAddress,
1222			 1 << interval,
1223			 udev->speed == USB_SPEED_FULL ? "" : "micro");
1224
1225	if (udev->speed == USB_SPEED_FULL) {
1226		/*
1227		 * Full speed isoc endpoints specify interval in frames,
1228		 * not microframes. We are using microframes everywhere,
1229		 * so adjust accordingly.
1230		 */
1231		interval += 3;	/* 1 frame = 2^3 uframes */
1232	}
1233
1234	return interval;
1235}
1236
1237/*
1238 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1239 * microframes, rounded down to nearest power of 2.
1240 */
1241static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1242		struct usb_host_endpoint *ep, unsigned int desc_interval,
1243		unsigned int min_exponent, unsigned int max_exponent)
1244{
1245	unsigned int interval;
1246
1247	interval = fls(desc_interval) - 1;
1248	interval = clamp_val(interval, min_exponent, max_exponent);
1249	if ((1 << interval) != desc_interval)
1250		dev_dbg(&udev->dev,
1251			 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1252			 ep->desc.bEndpointAddress,
1253			 1 << interval,
1254			 desc_interval);
1255
1256	return interval;
1257}
1258
1259static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1260		struct usb_host_endpoint *ep)
1261{
1262	if (ep->desc.bInterval == 0)
1263		return 0;
1264	return xhci_microframes_to_exponent(udev, ep,
1265			ep->desc.bInterval, 0, 15);
1266}
1267
1268
1269static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1270		struct usb_host_endpoint *ep)
1271{
1272	return xhci_microframes_to_exponent(udev, ep,
1273			ep->desc.bInterval * 8, 3, 10);
1274}
1275
1276/* Return the polling or NAK interval.
1277 *
1278 * The polling interval is expressed in "microframes".  If xHCI's Interval field
1279 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1280 *
1281 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1282 * is set to 0.
1283 */
1284static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1285		struct usb_host_endpoint *ep)
1286{
1287	unsigned int interval = 0;
1288
1289	switch (udev->speed) {
1290	case USB_SPEED_HIGH:
1291		/* Max NAK rate */
1292		if (usb_endpoint_xfer_control(&ep->desc) ||
1293		    usb_endpoint_xfer_bulk(&ep->desc)) {
1294			interval = xhci_parse_microframe_interval(udev, ep);
1295			break;
1296		}
1297		fallthrough;	/* SS and HS isoc/int have same decoding */
1298
1299	case USB_SPEED_SUPER_PLUS:
1300	case USB_SPEED_SUPER:
1301		if (usb_endpoint_xfer_int(&ep->desc) ||
1302		    usb_endpoint_xfer_isoc(&ep->desc)) {
1303			interval = xhci_parse_exponent_interval(udev, ep);
1304		}
1305		break;
1306
1307	case USB_SPEED_FULL:
1308		if (usb_endpoint_xfer_isoc(&ep->desc)) {
1309			interval = xhci_parse_exponent_interval(udev, ep);
1310			break;
1311		}
1312		/*
1313		 * Fall through for interrupt endpoint interval decoding
1314		 * since it uses the same rules as low speed interrupt
1315		 * endpoints.
1316		 */
1317		fallthrough;
1318
1319	case USB_SPEED_LOW:
1320		if (usb_endpoint_xfer_int(&ep->desc) ||
1321		    usb_endpoint_xfer_isoc(&ep->desc)) {
1322
1323			interval = xhci_parse_frame_interval(udev, ep);
1324		}
1325		break;
1326
1327	default:
1328		BUG();
1329	}
1330	return interval;
1331}
1332
1333/*
1334 * xHCs without LEC use the "Mult" field in the endpoint context for SuperSpeed
1335 * isoc eps, and High speed isoc eps that support bandwidth doubling. Standard
1336 * High speed endpoint descriptors can define "the number of additional
1337 * transaction opportunities per microframe", but that goes in the Max Burst
1338 * endpoint context field.
1339 */
1340static u32 xhci_get_endpoint_mult(struct xhci_hcd *xhci,
1341				  struct usb_device *udev,
1342				  struct usb_host_endpoint *ep)
1343{
1344	bool lec;
1345
1346	/* xHCI 1.1 with LEC set does not use mult field, except intel eUSB2 */
1347	lec = xhci->hci_version > 0x100 && (xhci->hcc_params2 & HCC2_LEC);
1348
1349	/* eUSB2 double isoc bw devices are the only USB2 devices using mult */
1350	if (usb_endpoint_is_hs_isoc_double(udev, ep) &&
1351	    (!lec || xhci->quirks & XHCI_INTEL_HOST))
1352		return 1;
1353
1354	/* SuperSpeed isoc transfers on hosts without LEC uses mult field */
1355	if (udev->speed >= USB_SPEED_SUPER &&
1356	    usb_endpoint_xfer_isoc(&ep->desc) && !lec)
1357		return ep->ss_ep_comp.bmAttributes;
1358
1359	return 0;
1360}
1361
1362static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1363				       struct usb_host_endpoint *ep)
1364{
1365	/* Super speed and Plus have max burst in ep companion desc */
1366	if (udev->speed >= USB_SPEED_SUPER)
1367		return ep->ss_ep_comp.bMaxBurst;
1368
1369	if (udev->speed == USB_SPEED_HIGH &&
1370	    (usb_endpoint_xfer_isoc(&ep->desc) ||
1371	     usb_endpoint_xfer_int(&ep->desc))) {
1372		/*
1373		 * USB 2 Isochronous Double IN Bandwidth ECN uses fixed burst
1374		 * size and max packets bits 12:11 are invalid.
1375		 */
1376		if (usb_endpoint_is_hs_isoc_double(udev, ep))
1377			return 2;
1378
1379		return usb_endpoint_maxp_mult(&ep->desc) - 1;
1380	}
1381
1382	return 0;
1383}
1384
1385static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1386{
1387	int in;
1388
1389	in = usb_endpoint_dir_in(&ep->desc);
1390
1391	switch (usb_endpoint_type(&ep->desc)) {
1392	case USB_ENDPOINT_XFER_CONTROL:
1393		return CTRL_EP;
1394	case USB_ENDPOINT_XFER_BULK:
1395		return in ? BULK_IN_EP : BULK_OUT_EP;
1396	case USB_ENDPOINT_XFER_ISOC:
1397		return in ? ISOC_IN_EP : ISOC_OUT_EP;
1398	case USB_ENDPOINT_XFER_INT:
1399		return in ? INT_IN_EP : INT_OUT_EP;
1400	}
1401	return 0;
1402}
1403
1404/* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1405 * Drivers will have to call usb_alloc_streams() to do that.
1406 */
1407int xhci_endpoint_init(struct xhci_hcd *xhci,
1408		struct xhci_virt_device *virt_dev,
1409		struct usb_device *udev,
1410		struct usb_host_endpoint *ep,
1411		gfp_t mem_flags)
1412{
1413	unsigned int ep_index;
1414	struct xhci_ep_ctx *ep_ctx;
1415	struct xhci_ring *ep_ring;
1416	unsigned int max_packet;
1417	enum xhci_ring_type ring_type;
1418	u32 max_esit_payload;
1419	u32 endpoint_type;
1420	unsigned int max_burst;
1421	unsigned int interval;
1422	unsigned int mult;
1423	unsigned int avg_trb_len;
1424	unsigned int err_count = 0;
1425
1426	ep_index = xhci_get_endpoint_index(&ep->desc);
1427	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1428
1429	endpoint_type = xhci_get_endpoint_type(ep);
1430	if (!endpoint_type)
1431		return -EINVAL;
1432
1433	ring_type = usb_endpoint_type(&ep->desc);
1434
1435	/* Ensure host supports double isoc bandwidth for eUSB2 devices */
1436	if (usb_endpoint_is_hs_isoc_double(udev, ep) && !(xhci->hcc_params2 & HCC2_EUSB2_DIC))	{
1437		dev_dbg(&udev->dev, "Double Isoc Bandwidth not supported by xhci\n");
1438		return -EINVAL;
1439	}
1440
1441	/*
1442	 * Get values to fill the endpoint context, mostly from ep descriptor.
1443	 * The average TRB buffer lengt for bulk endpoints is unclear as we
1444	 * have no clue on scatter gather list entry size. For Isoc and Int,
1445	 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1446	 */
1447	max_esit_payload = usb_endpoint_max_periodic_payload(udev, ep);
1448	interval = xhci_get_endpoint_interval(udev, ep);
1449
1450	/* Periodic endpoint bInterval limit quirk */
1451	if (usb_endpoint_xfer_int(&ep->desc) ||
1452	    usb_endpoint_xfer_isoc(&ep->desc)) {
1453		if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_9) &&
1454		    interval >= 9) {
1455			interval = 8;
1456		}
1457		if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
1458		    udev->speed >= USB_SPEED_HIGH &&
1459		    interval >= 7) {
1460			interval = 6;
1461		}
1462	}
1463
1464	mult = xhci_get_endpoint_mult(xhci, udev, ep);
1465	max_packet = xhci_usb_endpoint_maxp(udev, ep);
1466	max_burst = xhci_get_endpoint_max_burst(udev, ep);
1467	avg_trb_len = max_esit_payload;
1468
1469	/* FIXME dig Mult and streams info out of ep companion desc */
1470
1471	/* Allow 3 retries for everything but isoc, set CErr = 3 */
1472	if (!usb_endpoint_xfer_isoc(&ep->desc))
1473		err_count = 3;
1474	/* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */
1475	if (usb_endpoint_xfer_bulk(&ep->desc)) {
1476		if (udev->speed == USB_SPEED_HIGH)
1477			max_packet = 512;
1478		if (udev->speed == USB_SPEED_FULL) {
1479			max_packet = rounddown_pow_of_two(max_packet);
1480			max_packet = clamp_val(max_packet, 8, 64);
1481		}
1482	}
1483	/* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1484	if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
1485		avg_trb_len = 8;
1486
1487	/* Set up the endpoint ring */
1488	virt_dev->eps[ep_index].new_ring =
1489		xhci_ring_alloc(xhci, 2, ring_type, max_packet, mem_flags);
1490	if (!virt_dev->eps[ep_index].new_ring)
1491		return -ENOMEM;
1492
1493	virt_dev->eps[ep_index].skip = false;
1494	ep_ring = virt_dev->eps[ep_index].new_ring;
1495
1496	/* Fill the endpoint context */
1497	ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
1498				      EP_INTERVAL(interval) |
1499				      EP_MULT(mult));
1500	ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1501				       MAX_PACKET(max_packet) |
1502				       MAX_BURST(max_burst) |
1503				       ERROR_COUNT(err_count));
1504	ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1505				  ep_ring->cycle_state);
1506
1507	ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1508				      EP_AVG_TRB_LENGTH(avg_trb_len));
1509
1510	return 0;
1511}
1512
1513void xhci_endpoint_zero(struct xhci_hcd *xhci,
1514		struct xhci_virt_device *virt_dev,
1515		struct usb_host_endpoint *ep)
1516{
1517	unsigned int ep_index;
1518	struct xhci_ep_ctx *ep_ctx;
1519
1520	ep_index = xhci_get_endpoint_index(&ep->desc);
1521	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1522
1523	ep_ctx->ep_info = 0;
1524	ep_ctx->ep_info2 = 0;
1525	ep_ctx->deq = 0;
1526	ep_ctx->tx_info = 0;
1527	/* Don't free the endpoint ring until the set interface or configuration
1528	 * request succeeds.
1529	 */
1530}
1531
1532void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1533{
1534	bw_info->ep_interval = 0;
1535	bw_info->mult = 0;
1536	bw_info->num_packets = 0;
1537	bw_info->max_packet_size = 0;
1538	bw_info->type = 0;
1539	bw_info->max_esit_payload = 0;
1540}
1541
1542void xhci_update_bw_info(struct xhci_hcd *xhci,
1543		struct xhci_container_ctx *in_ctx,
1544		struct xhci_input_control_ctx *ctrl_ctx,
1545		struct xhci_virt_device *virt_dev)
1546{
1547	struct xhci_bw_info *bw_info;
1548	struct xhci_ep_ctx *ep_ctx;
1549	unsigned int ep_type;
1550	int i;
1551
1552	for (i = 1; i < 31; i++) {
1553		bw_info = &virt_dev->eps[i].bw_info;
1554
1555		/* We can't tell what endpoint type is being dropped, but
1556		 * unconditionally clearing the bandwidth info for non-periodic
1557		 * endpoints should be harmless because the info will never be
1558		 * set in the first place.
1559		 */
1560		if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1561			/* Dropped endpoint */
1562			xhci_clear_endpoint_bw_info(bw_info);
1563			continue;
1564		}
1565
1566		if (EP_IS_ADDED(ctrl_ctx, i)) {
1567			ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1568			ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1569
1570			/* Ignore non-periodic endpoints */
1571			if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1572					ep_type != ISOC_IN_EP &&
1573					ep_type != INT_IN_EP)
1574				continue;
1575
1576			/* Added or changed endpoint */
1577			bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1578					le32_to_cpu(ep_ctx->ep_info));
1579			/* Number of packets and mult are zero-based in the
1580			 * input context, but we want one-based for the
1581			 * interval table.
1582			 */
1583			bw_info->mult = CTX_TO_EP_MULT(
1584					le32_to_cpu(ep_ctx->ep_info)) + 1;
1585			bw_info->num_packets = CTX_TO_MAX_BURST(
1586					le32_to_cpu(ep_ctx->ep_info2)) + 1;
1587			bw_info->max_packet_size = MAX_PACKET_DECODED(
1588					le32_to_cpu(ep_ctx->ep_info2));
1589			bw_info->type = ep_type;
1590			bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1591					le32_to_cpu(ep_ctx->tx_info));
1592		}
1593	}
1594}
1595
1596/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1597 * Useful when you want to change one particular aspect of the endpoint and then
1598 * issue a configure endpoint command.
1599 */
1600void xhci_endpoint_copy(struct xhci_hcd *xhci,
1601		struct xhci_container_ctx *in_ctx,
1602		struct xhci_container_ctx *out_ctx,
1603		unsigned int ep_index)
1604{
1605	struct xhci_ep_ctx *out_ep_ctx;
1606	struct xhci_ep_ctx *in_ep_ctx;
1607
1608	out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1609	in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1610
1611	in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1612	in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1613	in_ep_ctx->deq = out_ep_ctx->deq;
1614	in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1615	if (xhci->quirks & XHCI_MTK_HOST) {
1616		in_ep_ctx->reserved[0] = out_ep_ctx->reserved[0];
1617		in_ep_ctx->reserved[1] = out_ep_ctx->reserved[1];
1618	}
1619}
1620
1621/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1622 * Useful when you want to change one particular aspect of the endpoint and then
1623 * issue a configure endpoint command.  Only the context entries field matters,
1624 * but we'll copy the whole thing anyway.
1625 */
1626void xhci_slot_copy(struct xhci_hcd *xhci,
1627		struct xhci_container_ctx *in_ctx,
1628		struct xhci_container_ctx *out_ctx)
1629{
1630	struct xhci_slot_ctx *in_slot_ctx;
1631	struct xhci_slot_ctx *out_slot_ctx;
1632
1633	in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1634	out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1635
1636	in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1637	in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1638	in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1639	in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1640}
1641
1642/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1643static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1644{
1645	int i;
1646	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1647	int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1648
1649	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1650			"Allocating %d scratchpad buffers", num_sp);
1651
1652	if (!num_sp)
1653		return 0;
1654
1655	xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags,
1656				dev_to_node(dev));
1657	if (!xhci->scratchpad)
1658		goto fail_sp;
1659
1660	xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1661				     array_size(sizeof(u64), num_sp),
1662				     &xhci->scratchpad->sp_dma, flags);
1663	if (!xhci->scratchpad->sp_array)
1664		goto fail_sp2;
1665
1666	xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *),
1667					flags, dev_to_node(dev));
1668	if (!xhci->scratchpad->sp_buffers)
1669		goto fail_sp3;
1670
1671	xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1672	for (i = 0; i < num_sp; i++) {
1673		dma_addr_t dma;
1674		void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1675					       flags);
1676		if (!buf)
1677			goto fail_sp4;
1678
1679		xhci->scratchpad->sp_array[i] = dma;
1680		xhci->scratchpad->sp_buffers[i] = buf;
1681	}
1682
1683	return 0;
1684
1685 fail_sp4:
1686	while (i--)
1687		dma_free_coherent(dev, xhci->page_size,
1688				    xhci->scratchpad->sp_buffers[i],
1689				    xhci->scratchpad->sp_array[i]);
1690
1691	kfree(xhci->scratchpad->sp_buffers);
1692
1693 fail_sp3:
1694	dma_free_coherent(dev, array_size(sizeof(u64), num_sp),
1695			    xhci->scratchpad->sp_array,
1696			    xhci->scratchpad->sp_dma);
1697
1698 fail_sp2:
1699	kfree(xhci->scratchpad);
1700	xhci->scratchpad = NULL;
1701
1702 fail_sp:
1703	return -ENOMEM;
1704}
1705
1706static void scratchpad_free(struct xhci_hcd *xhci)
1707{
1708	int num_sp;
1709	int i;
1710	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1711
1712	if (!xhci->scratchpad)
1713		return;
1714
1715	num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1716
1717	for (i = 0; i < num_sp; i++) {
1718		dma_free_coherent(dev, xhci->page_size,
1719				    xhci->scratchpad->sp_buffers[i],
1720				    xhci->scratchpad->sp_array[i]);
1721	}
1722	kfree(xhci->scratchpad->sp_buffers);
1723	dma_free_coherent(dev, array_size(sizeof(u64), num_sp),
1724			    xhci->scratchpad->sp_array,
1725			    xhci->scratchpad->sp_dma);
1726	kfree(xhci->scratchpad);
1727	xhci->scratchpad = NULL;
1728}
1729
1730struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1731		bool allocate_completion, gfp_t mem_flags)
1732{
1733	struct xhci_command *command;
1734	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1735
1736	command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev));
1737	if (!command)
1738		return NULL;
1739
1740	if (allocate_completion) {
1741		command->completion =
1742			kzalloc_node(sizeof(struct completion), mem_flags,
1743				dev_to_node(dev));
1744		if (!command->completion) {
1745			kfree(command);
1746			return NULL;
1747		}
1748		init_completion(command->completion);
1749	}
1750
1751	command->status = 0;
1752	/* set default timeout to 5000 ms */
1753	command->timeout_ms = XHCI_CMD_DEFAULT_TIMEOUT;
1754	INIT_LIST_HEAD(&command->cmd_list);
1755	return command;
1756}
1757
1758struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1759		bool allocate_completion, gfp_t mem_flags)
1760{
1761	struct xhci_command *command;
1762
1763	command = xhci_alloc_command(xhci, allocate_completion, mem_flags);
1764	if (!command)
1765		return NULL;
1766
1767	command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1768						   mem_flags);
1769	if (!command->in_ctx) {
1770		kfree(command->completion);
1771		kfree(command);
1772		return NULL;
1773	}
1774	return command;
1775}
1776
1777void xhci_urb_free_priv(struct urb_priv *urb_priv)
1778{
1779	kfree(urb_priv);
1780}
1781
1782void xhci_free_command(struct xhci_hcd *xhci,
1783		struct xhci_command *command)
1784{
1785	xhci_free_container_ctx(xhci,
1786			command->in_ctx);
1787	kfree(command->completion);
1788	kfree(command);
1789}
1790
1791static int xhci_alloc_erst(struct xhci_hcd *xhci,
1792		    struct xhci_ring *evt_ring,
1793		    struct xhci_erst *erst,
1794		    gfp_t flags)
1795{
1796	size_t size;
1797	unsigned int val;
1798	struct xhci_segment *seg;
1799	struct xhci_erst_entry *entry;
1800
1801	size = array_size(sizeof(struct xhci_erst_entry), evt_ring->num_segs);
1802	erst->entries = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
1803					   size, &erst->erst_dma_addr, flags);
1804	if (!erst->entries)
1805		return -ENOMEM;
1806
1807	erst->num_entries = evt_ring->num_segs;
1808
1809	seg = evt_ring->first_seg;
1810	for (val = 0; val < evt_ring->num_segs; val++) {
1811		entry = &erst->entries[val];
1812		entry->seg_addr = cpu_to_le64(seg->dma);
1813		entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
1814		entry->rsvd = 0;
1815		seg = seg->next;
1816	}
1817
1818	return 0;
1819}
1820
1821static void
1822xhci_remove_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
1823{
1824	u32 tmp;
1825
1826	if (!ir)
1827		return;
1828
1829	/*
1830	 * Clean out interrupter registers except ERSTBA. Clearing either the
1831	 * low or high 32 bits of ERSTBA immediately causes the controller to
1832	 * dereference the partially cleared 64 bit address, causing IOMMU error.
1833	 */
1834	if (ir->ir_set) {
1835		tmp = readl(&ir->ir_set->erst_size);
1836		tmp &= ~ERST_SIZE_MASK;
1837		writel(tmp, &ir->ir_set->erst_size);
1838
1839		xhci_update_erst_dequeue(xhci, ir, true);
1840	}
1841}
1842
1843static void
1844xhci_free_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
1845{
1846	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1847	size_t erst_size;
1848
1849	if (!ir)
1850		return;
1851
1852	erst_size = array_size(sizeof(struct xhci_erst_entry), ir->erst.num_entries);
1853	if (ir->erst.entries)
1854		dma_free_coherent(dev, erst_size,
1855				  ir->erst.entries,
1856				  ir->erst.erst_dma_addr);
1857	ir->erst.entries = NULL;
1858
1859	/* free interrupter event ring */
1860	if (ir->event_ring)
1861		xhci_ring_free(xhci, ir->event_ring);
1862
1863	ir->event_ring = NULL;
1864
1865	kfree(ir);
1866}
1867
1868void xhci_remove_secondary_interrupter(struct usb_hcd *hcd, struct xhci_interrupter *ir)
1869{
1870	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1871	unsigned int intr_num;
1872
1873	spin_lock_irq(&xhci->lock);
1874
1875	/* interrupter 0 is primary interrupter, don't touch it */
1876	if (!ir || !ir->intr_num || ir->intr_num >= xhci->max_interrupters) {
1877		xhci_dbg(xhci, "Invalid secondary interrupter, can't remove\n");
1878		spin_unlock_irq(&xhci->lock);
1879		return;
1880	}
1881
1882	/*
1883	 * Cleanup secondary interrupter to ensure there are no pending events.
1884	 * This also updates event ring dequeue pointer back to the start.
1885	 */
1886	xhci_skip_sec_intr_events(xhci, ir->event_ring, ir);
1887	intr_num = ir->intr_num;
1888
1889	xhci_remove_interrupter(xhci, ir);
1890	xhci->interrupters[intr_num] = NULL;
1891
1892	spin_unlock_irq(&xhci->lock);
1893
1894	xhci_free_interrupter(xhci, ir);
1895}
1896EXPORT_SYMBOL_GPL(xhci_remove_secondary_interrupter);
1897
1898void xhci_mem_cleanup(struct xhci_hcd *xhci)
1899{
1900	struct device	*dev = xhci_to_hcd(xhci)->self.sysdev;
1901	int i, j;
1902
1903	cancel_delayed_work_sync(&xhci->cmd_timer);
1904
1905	for (i = 0; xhci->interrupters && i < xhci->max_interrupters; i++) {
1906		if (xhci->interrupters[i]) {
1907			xhci_remove_interrupter(xhci, xhci->interrupters[i]);
1908			xhci_free_interrupter(xhci, xhci->interrupters[i]);
1909			xhci->interrupters[i] = NULL;
1910		}
1911	}
1912	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed interrupters");
1913
1914	if (xhci->cmd_ring)
1915		xhci_ring_free(xhci, xhci->cmd_ring);
1916	xhci->cmd_ring = NULL;
1917	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1918	xhci_cleanup_command_queue(xhci);
1919
1920	for (i = 0; i < xhci->max_ports && xhci->rh_bw; i++) {
1921		struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1922		for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1923			struct list_head *ep = &bwt->interval_bw[j].endpoints;
1924			while (!list_empty(ep))
1925				list_del_init(ep->next);
1926		}
1927	}
1928
1929	for (i = xhci->max_slots; i > 0; i--)
1930		xhci_free_virt_devices_depth_first(xhci, i);
1931
1932	dma_pool_destroy(xhci->segment_pool);
1933	xhci->segment_pool = NULL;
1934	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1935
1936	dma_pool_destroy(xhci->device_pool);
1937	xhci->device_pool = NULL;
1938	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1939
1940	dma_pool_destroy(xhci->small_streams_pool);
1941	xhci->small_streams_pool = NULL;
1942	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1943			"Freed small stream array pool");
1944
1945	dma_pool_destroy(xhci->port_bw_pool);
1946	xhci->port_bw_pool = NULL;
1947	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1948			"Freed xhci port bw array pool");
1949
1950	dma_pool_destroy(xhci->medium_streams_pool);
1951	xhci->medium_streams_pool = NULL;
1952	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1953			"Freed medium stream array pool");
1954
1955	if (xhci->dcbaa)
1956		dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1957				xhci->dcbaa, xhci->dcbaa->dma);
1958	xhci->dcbaa = NULL;
1959
1960	scratchpad_free(xhci);
1961
1962	if (!xhci->rh_bw)
1963		goto no_bw;
1964
1965	for (i = 0; i < xhci->max_ports; i++) {
1966		struct xhci_tt_bw_info *tt, *n;
1967		list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1968			list_del(&tt->tt_list);
1969			kfree(tt);
1970		}
1971	}
1972
1973no_bw:
1974	xhci->cmd_ring_reserved_trbs = 0;
1975	xhci->usb2_rhub.num_ports = 0;
1976	xhci->usb3_rhub.num_ports = 0;
1977	xhci->num_active_eps = 0;
1978	kfree(xhci->usb2_rhub.ports);
1979	kfree(xhci->usb3_rhub.ports);
1980	kfree(xhci->hw_ports);
1981	kfree(xhci->rh_bw);
1982	for (i = 0; i < xhci->num_port_caps; i++)
1983		kfree(xhci->port_caps[i].psi);
1984	kfree(xhci->port_caps);
1985	kfree(xhci->interrupters);
1986	xhci->num_port_caps = 0;
1987
1988	xhci->usb2_rhub.ports = NULL;
1989	xhci->usb3_rhub.ports = NULL;
1990	xhci->hw_ports = NULL;
1991	xhci->rh_bw = NULL;
1992	xhci->port_caps = NULL;
1993	xhci->interrupters = NULL;
1994
1995	xhci->page_size = 0;
1996	xhci->usb2_rhub.bus_state.bus_suspended = 0;
1997	xhci->usb3_rhub.bus_state.bus_suspended = 0;
1998}
1999
2000static void xhci_set_hc_event_deq(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
2001{
2002	dma_addr_t deq;
2003
2004	deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
2005			ir->event_ring->dequeue);
2006	if (!deq)
2007		xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr.\n");
2008	/* Update HC event ring dequeue pointer */
2009	/* Don't clear the EHB bit (which is RW1C) because
2010	 * there might be more events to service.
2011	 */
2012	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2013		       "// Write event ring dequeue pointer, preserving EHB bit");
2014	xhci_write_64(xhci, deq & ERST_PTR_MASK, &ir->ir_set->erst_dequeue);
2015}
2016
2017static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2018		__le32 __iomem *addr, int max_caps)
2019{
2020	u32 temp, port_offset, port_count;
2021	int i;
2022	u8 major_revision, minor_revision, tmp_minor_revision;
2023	struct xhci_hub *rhub;
2024	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2025	struct xhci_port_cap *port_cap;
2026
2027	temp = readl(addr);
2028	major_revision = XHCI_EXT_PORT_MAJOR(temp);
2029	minor_revision = XHCI_EXT_PORT_MINOR(temp);
2030
2031	if (major_revision == 0x03) {
2032		rhub = &xhci->usb3_rhub;
2033		/*
2034		 * Some hosts incorrectly use sub-minor version for minor
2035		 * version (i.e. 0x02 instead of 0x20 for bcdUSB 0x320 and 0x01
2036		 * for bcdUSB 0x310). Since there is no USB release with sub
2037		 * minor version 0x301 to 0x309, we can assume that they are
2038		 * incorrect and fix it here.
2039		 */
2040		if (minor_revision > 0x00 && minor_revision < 0x10)
2041			minor_revision <<= 4;
2042		/*
2043		 * Some zhaoxin's xHCI controller that follow usb3.1 spec
2044		 * but only support Gen1.
2045		 */
2046		if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
2047			tmp_minor_revision = minor_revision;
2048			minor_revision = 0;
2049		}
2050
2051	} else if (major_revision <= 0x02) {
2052		rhub = &xhci->usb2_rhub;
2053	} else {
2054		xhci_warn(xhci, "Ignoring unknown port speed, Ext Cap %p, revision = 0x%x\n",
2055				addr, major_revision);
2056		/* Ignoring port protocol we can't understand. FIXME */
2057		return;
2058	}
2059
2060	/* Port offset and count in the third dword, see section 7.2 */
2061	temp = readl(addr + 2);
2062	port_offset = XHCI_EXT_PORT_OFF(temp);
2063	port_count = XHCI_EXT_PORT_COUNT(temp);
2064	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2065		       "Ext Cap %p, port offset = %u, count = %u, revision = 0x%x",
2066		       addr, port_offset, port_count, major_revision);
2067	/* Port count includes the current port offset */
2068	if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2069		/* WTF? "Valid values are ‘1’ to MaxPorts" */
2070		return;
2071
2072	port_cap = &xhci->port_caps[xhci->num_port_caps++];
2073	if (xhci->num_port_caps > max_caps)
2074		return;
2075
2076	port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
2077
2078	if (port_cap->psi_count) {
2079		port_cap->psi = kcalloc_node(port_cap->psi_count,
2080					     sizeof(*port_cap->psi),
2081					     GFP_KERNEL, dev_to_node(dev));
2082		if (!port_cap->psi)
2083			port_cap->psi_count = 0;
2084
2085		port_cap->psi_uid_count++;
2086		for (i = 0; i < port_cap->psi_count; i++) {
2087			port_cap->psi[i] = readl(addr + 4 + i);
2088
2089			/* count unique ID values, two consecutive entries can
2090			 * have the same ID if link is assymetric
2091			 */
2092			if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) !=
2093				  XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
2094				port_cap->psi_uid_count++;
2095
2096			if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
2097			    major_revision == 0x03 &&
2098			    XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
2099				minor_revision = tmp_minor_revision;
2100
2101			xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2102				  XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
2103				  XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
2104				  XHCI_EXT_PORT_PLT(port_cap->psi[i]),
2105				  XHCI_EXT_PORT_PFD(port_cap->psi[i]),
2106				  XHCI_EXT_PORT_LP(port_cap->psi[i]),
2107				  XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
2108		}
2109	}
2110
2111	rhub->maj_rev = major_revision;
2112
2113	if (rhub->min_rev < minor_revision)
2114		rhub->min_rev = minor_revision;
2115
2116	port_cap->maj_rev = major_revision;
2117	port_cap->min_rev = minor_revision;
2118	port_cap->protocol_caps = temp;
2119
2120	if ((xhci->hci_version >= 0x100) && (major_revision != 0x03) &&
2121		 (temp & XHCI_HLC)) {
2122		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2123			       "xHCI 1.0: support USB2 hardware lpm");
2124		xhci->hw_lpm_support = 1;
2125	}
2126
2127	port_offset--;
2128	for (i = port_offset; i < (port_offset + port_count); i++) {
2129		struct xhci_port *hw_port = &xhci->hw_ports[i];
2130		/* Duplicate entry.  Ignore the port if the revisions differ. */
2131		if (hw_port->rhub) {
2132			xhci_warn(xhci, "Duplicate port entry, Ext Cap %p, port %u\n", addr, i);
2133			xhci_warn(xhci, "Port was marked as USB %u, duplicated as USB %u\n",
2134					hw_port->rhub->maj_rev, major_revision);
2135			/* Only adjust the roothub port counts if we haven't
2136			 * found a similar duplicate.
2137			 */
2138			if (hw_port->rhub != rhub &&
2139				 hw_port->hcd_portnum != DUPLICATE_ENTRY) {
2140				hw_port->rhub->num_ports--;
2141				hw_port->hcd_portnum = DUPLICATE_ENTRY;
2142			}
2143			continue;
2144		}
2145		hw_port->rhub = rhub;
2146		hw_port->port_cap = port_cap;
2147		rhub->num_ports++;
2148	}
2149	/* FIXME: Should we disable ports not in the Extended Capabilities? */
2150}
2151
2152static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
2153					struct xhci_hub *rhub, gfp_t flags)
2154{
2155	int port_index = 0;
2156	int i;
2157	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2158
2159	if (!rhub->num_ports)
2160		return;
2161	rhub->ports = kcalloc_node(rhub->num_ports, sizeof(*rhub->ports),
2162			flags, dev_to_node(dev));
2163	if (!rhub->ports)
2164		return;
2165
2166	for (i = 0; i < xhci->max_ports; i++) {
2167		if (xhci->hw_ports[i].rhub != rhub ||
2168		    xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
2169			continue;
2170		xhci->hw_ports[i].hcd_portnum = port_index;
2171		rhub->ports[port_index] = &xhci->hw_ports[i];
2172		port_index++;
2173		if (port_index == rhub->num_ports)
2174			break;
2175	}
2176}
2177
2178/*
2179 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2180 * specify what speeds each port is supposed to be.  We can't count on the port
2181 * speed bits in the PORTSC register being correct until a device is connected,
2182 * but we need to set up the two fake roothubs with the correct number of USB
2183 * 3.0 and USB 2.0 ports at host controller initialization time.
2184 */
2185static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2186{
2187	void __iomem *base;
2188	u32 offset;
2189	int i, j;
2190	int cap_count = 0;
2191	u32 cap_start;
2192	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2193
2194	xhci->hw_ports = kcalloc_node(xhci->max_ports, sizeof(*xhci->hw_ports),
2195				      flags, dev_to_node(dev));
2196	if (!xhci->hw_ports)
2197		return -ENOMEM;
2198
2199	for (i = 0; i < xhci->max_ports; i++) {
2200		xhci->hw_ports[i].port_reg = &xhci->op_regs->port_regs[i];
2201		xhci->hw_ports[i].hw_portnum = i;
2202
2203		init_completion(&xhci->hw_ports[i].rexit_done);
2204		init_completion(&xhci->hw_ports[i].u3exit_done);
2205	}
2206
2207	xhci->rh_bw = kcalloc_node(xhci->max_ports, sizeof(*xhci->rh_bw), flags, dev_to_node(dev));
2208	if (!xhci->rh_bw)
2209		return -ENOMEM;
2210	for (i = 0; i < xhci->max_ports; i++) {
2211		struct xhci_interval_bw_table *bw_table;
2212
2213		INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2214		bw_table = &xhci->rh_bw[i].bw_table;
2215		for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2216			INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2217	}
2218	base = &xhci->cap_regs->hc_capbase;
2219
2220	cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL);
2221	if (!cap_start) {
2222		xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2223		return -ENODEV;
2224	}
2225
2226	offset = cap_start;
2227	/* count extended protocol capability entries for later caching */
2228	while (offset) {
2229		cap_count++;
2230		offset = xhci_find_next_ext_cap(base, offset,
2231						      XHCI_EXT_CAPS_PROTOCOL);
2232	}
2233
2234	xhci->port_caps = kcalloc_node(cap_count, sizeof(*xhci->port_caps),
2235				flags, dev_to_node(dev));
2236	if (!xhci->port_caps)
2237		return -ENOMEM;
2238
2239	offset = cap_start;
2240
2241	while (offset) {
2242		xhci_add_in_port(xhci, xhci->max_ports, base + offset, cap_count);
2243		if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports == xhci->max_ports)
2244			break;
2245		offset = xhci_find_next_ext_cap(base, offset,
2246						XHCI_EXT_CAPS_PROTOCOL);
2247	}
2248	if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) {
2249		xhci_warn(xhci, "No ports on the roothubs?\n");
2250		return -ENODEV;
2251	}
2252	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2253		       "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2254		       xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports);
2255
2256	/* Place limits on the number of roothub ports so that the hub
2257	 * descriptors aren't longer than the USB core will allocate.
2258	 */
2259	if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) {
2260		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2261				"Limiting USB 3.0 roothub ports to %u.",
2262				USB_SS_MAXPORTS);
2263		xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS;
2264	}
2265	if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) {
2266		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2267				"Limiting USB 2.0 roothub ports to %u.",
2268				USB_MAXCHILDREN);
2269		xhci->usb2_rhub.num_ports = USB_MAXCHILDREN;
2270	}
2271
2272	if (!xhci->usb2_rhub.num_ports)
2273		xhci_info(xhci, "USB2 root hub has no ports\n");
2274
2275	if (!xhci->usb3_rhub.num_ports)
2276		xhci_info(xhci, "USB3 root hub has no ports\n");
2277
2278	xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags);
2279	xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags);
2280
2281	return 0;
2282}
2283
2284static struct xhci_interrupter *
2285xhci_alloc_interrupter(struct xhci_hcd *xhci, unsigned int segs, gfp_t flags)
2286{
2287	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2288	struct xhci_interrupter *ir;
2289	unsigned int max_segs;
2290	int ret;
2291
2292	if (!segs)
2293		segs = ERST_DEFAULT_SEGS;
2294
2295	max_segs = BIT(HCS_ERST_MAX(xhci->hcs_params2));
2296	segs = min(segs, max_segs);
2297
2298	ir = kzalloc_node(sizeof(*ir), flags, dev_to_node(dev));
2299	if (!ir)
2300		return NULL;
2301
2302	ir->event_ring = xhci_ring_alloc(xhci, segs, TYPE_EVENT, 0, flags);
2303	if (!ir->event_ring) {
2304		xhci_warn(xhci, "Failed to allocate interrupter event ring\n");
2305		kfree(ir);
2306		return NULL;
2307	}
2308
2309	ret = xhci_alloc_erst(xhci, ir->event_ring, &ir->erst, flags);
2310	if (ret) {
2311		xhci_warn(xhci, "Failed to allocate interrupter erst\n");
2312		xhci_ring_free(xhci, ir->event_ring);
2313		kfree(ir);
2314		return NULL;
2315	}
2316
2317	return ir;
2318}
2319
2320void xhci_add_interrupter(struct xhci_hcd *xhci, unsigned int intr_num)
2321{
2322	struct xhci_interrupter *ir;
2323	u64 erst_base;
2324	u32 erst_size;
2325
2326	ir = xhci->interrupters[intr_num];
2327	ir->intr_num = intr_num;
2328	ir->ir_set = &xhci->run_regs->ir_set[intr_num];
2329
2330	/* set ERST count with the number of entries in the segment table */
2331	erst_size = readl(&ir->ir_set->erst_size);
2332	erst_size &= ~ERST_SIZE_MASK;
2333	erst_size |= ir->event_ring->num_segs;
2334	writel(erst_size, &ir->ir_set->erst_size);
2335
2336	erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
2337	erst_base &= ~ERST_BASE_ADDRESS_MASK;
2338	erst_base |= ir->erst.erst_dma_addr & ERST_BASE_ADDRESS_MASK;
2339	if (xhci->quirks & XHCI_WRITE_64_HI_LO)
2340		hi_lo_writeq(erst_base, &ir->ir_set->erst_base);
2341	else
2342		xhci_write_64(xhci, erst_base, &ir->ir_set->erst_base);
2343
2344	/* Set the event ring dequeue address of this interrupter */
2345	xhci_set_hc_event_deq(xhci, ir);
2346}
2347
2348struct xhci_interrupter *
2349xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs,
2350				  u32 imod_interval, unsigned int intr_num)
2351{
2352	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2353	struct xhci_interrupter *ir;
2354	unsigned int i;
2355	int err = -ENOSPC;
2356
2357	if (!xhci->interrupters || xhci->max_interrupters <= 1 ||
2358	    intr_num >= xhci->max_interrupters)
2359		return NULL;
2360
2361	ir = xhci_alloc_interrupter(xhci, segs, GFP_KERNEL);
2362	if (!ir)
2363		return NULL;
2364
2365	spin_lock_irq(&xhci->lock);
2366	if (!intr_num) {
2367		/* Find available secondary interrupter, interrupter 0 is reserved for primary */
2368		for (i = 1; i < xhci->max_interrupters; i++) {
2369			if (!xhci->interrupters[i]) {
2370				xhci->interrupters[i] = ir;
2371				xhci_add_interrupter(xhci, i);
2372				err = 0;
2373				break;
2374			}
2375		}
2376	} else {
2377		if (!xhci->interrupters[intr_num]) {
2378			xhci->interrupters[intr_num] = ir;
2379			xhci_add_interrupter(xhci, intr_num);
2380			err = 0;
2381		}
2382	}
2383	spin_unlock_irq(&xhci->lock);
2384
2385	if (err) {
2386		xhci_warn(xhci, "Failed to add secondary interrupter, max interrupters %d\n",
2387			  xhci->max_interrupters);
2388		xhci_free_interrupter(xhci, ir);
2389		return NULL;
2390	}
2391
2392	xhci_set_interrupter_moderation(ir, imod_interval);
2393
2394	xhci_dbg(xhci, "Add secondary interrupter %d, max interrupters %d\n",
2395		 ir->intr_num, xhci->max_interrupters);
2396
2397	return ir;
2398}
2399EXPORT_SYMBOL_GPL(xhci_create_secondary_interrupter);
2400
2401int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2402{
2403	struct device	*dev = xhci_to_hcd(xhci)->self.sysdev;
2404	dma_addr_t	dma;
2405
2406	/*
2407	 * xHCI section 5.4.6 - Device Context array must be
2408	 * "physically contiguous and 64-byte (cache line) aligned".
2409	 */
2410	xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, flags);
2411	if (!xhci->dcbaa)
2412		goto fail;
2413
2414	xhci->dcbaa->dma = dma;
2415	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2416		       "Device context base array address = 0x%pad (DMA), %p (virt)",
2417		       &xhci->dcbaa->dma, xhci->dcbaa);
2418
2419	/*
2420	 * Initialize the ring segment pool.  The ring must be a contiguous
2421	 * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2422	 * however, the command ring segment needs 64-byte aligned segments
2423	 * and our use of dma addresses in the trb_address_map radix tree needs
2424	 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2425	 */
2426	if (xhci->quirks & XHCI_TRB_OVERFETCH)
2427		/* Buggy HC prefetches beyond segment bounds - allocate dummy space at the end */
2428		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2429				TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, xhci->page_size * 2);
2430	else
2431		xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2432				TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2433	if (!xhci->segment_pool)
2434		goto fail;
2435
2436	/* See Table 46 and Note on Figure 55 */
2437	xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, 2112, 64,
2438					    xhci->page_size);
2439	if (!xhci->device_pool)
2440		goto fail;
2441
2442	/*
2443	 * Linear stream context arrays don't have any boundary restrictions,
2444	 * and only need to be 16-byte aligned.
2445	 */
2446	xhci->small_streams_pool = dma_pool_create("xHCI 256 byte stream ctx arrays",
2447						   dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2448	if (!xhci->small_streams_pool)
2449		goto fail;
2450
2451	/*
2452	 * Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE will be
2453	 * allocated with dma_alloc_coherent().
2454	 */
2455
2456	xhci->medium_streams_pool = dma_pool_create("xHCI 1KB stream ctx arrays",
2457						    dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2458	if (!xhci->medium_streams_pool)
2459		goto fail;
2460
2461	/*
2462	 * refer to xhci rev1_2 protocol 5.3.3 max ports is 255.
2463	 * refer to xhci rev1_2 protocol 6.4.3.14 port bandwidth buffer need
2464	 * to be 16-byte aligned.
2465	 */
2466	xhci->port_bw_pool = dma_pool_create("xHCI 256 port bw ctx arrays",
2467					     dev, GET_PORT_BW_ARRAY_SIZE, 16, 0);
2468	if (!xhci->port_bw_pool)
2469		goto fail;
2470
2471	/* Set up the command ring to have one segments for now. */
2472	xhci->cmd_ring = xhci_ring_alloc(xhci, 1, TYPE_COMMAND, 0, flags);
2473	if (!xhci->cmd_ring)
2474		goto fail;
2475
2476	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Allocated command ring at %p", xhci->cmd_ring);
2477	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%pad",
2478		       &xhci->cmd_ring->first_seg->dma);
2479
2480	/*
2481	 * Reserve one command ring TRB for disabling LPM.
2482	 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2483	 * disabling LPM, we only need to reserve one TRB for all devices.
2484	 */
2485	xhci->cmd_ring_reserved_trbs++;
2486
2487	/* Allocate and set up primary interrupter 0 with an event ring. */
2488	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Allocating primary event ring");
2489	xhci->interrupters = kcalloc_node(xhci->max_interrupters, sizeof(*xhci->interrupters),
2490					  flags, dev_to_node(dev));
2491	if (!xhci->interrupters)
2492		goto fail;
2493
2494	xhci->interrupters[0] = xhci_alloc_interrupter(xhci, 0, flags);
2495	if (!xhci->interrupters[0])
2496		goto fail;
2497
2498	if (scratchpad_alloc(xhci, flags))
2499		goto fail;
2500
2501	if (xhci_setup_port_arrays(xhci, flags))
2502		goto fail;
2503
2504	return 0;
2505
2506fail:
2507	xhci_halt(xhci);
2508	xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
2509	xhci_mem_cleanup(xhci);
2510	return -ENOMEM;
2511}