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oxu210hp-hcd.c
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linux-6.19.14/drivers/usb/host/oxu210hp-hcd.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it> 4 * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it> 5 * 6 * This code is *strongly* based on EHCI-HCD code by David Brownell since 7 * the chip is a quasi-EHCI compatible. 8 */ 9 10#include <linux/module.h> 11#include <linux/pci.h> 12#include <linux/dmapool.h> 13#include <linux/kernel.h> 14#include <linux/delay.h> 15#include <linux/ioport.h> 16#include <linux/sched.h> 17#include <linux/slab.h> 18#include <linux/string_choices.h> 19#include <linux/errno.h> 20#include <linux/timer.h> 21#include <linux/list.h> 22#include <linux/interrupt.h> 23#include <linux/usb.h> 24#include <linux/usb/hcd.h> 25#include <linux/moduleparam.h> 26#include <linux/dma-mapping.h> 27#include <linux/io.h> 28#include <linux/iopoll.h> 29 30#include <asm/irq.h> 31#include <linux/unaligned.h> 32 33#include <linux/irq.h> 34#include <linux/platform_device.h> 35 36#define DRIVER_VERSION "0.0.50" 37 38#define OXU_DEVICEID 0x00 39 #define OXU_REV_MASK 0xffff0000 40 #define OXU_REV_SHIFT 16 41 #define OXU_REV_2100 0x2100 42 #define OXU_BO_SHIFT 8 43 #define OXU_BO_MASK (0x3 << OXU_BO_SHIFT) 44 #define OXU_MAJ_REV_SHIFT 4 45 #define OXU_MAJ_REV_MASK (0xf << OXU_MAJ_REV_SHIFT) 46 #define OXU_MIN_REV_SHIFT 0 47 #define OXU_MIN_REV_MASK (0xf << OXU_MIN_REV_SHIFT) 48#define OXU_HOSTIFCONFIG 0x04 49#define OXU_SOFTRESET 0x08 50 #define OXU_SRESET (1 << 0) 51 52#define OXU_PIOBURSTREADCTRL 0x0C 53 54#define OXU_CHIPIRQSTATUS 0x10 55#define OXU_CHIPIRQEN_SET 0x14 56#define OXU_CHIPIRQEN_CLR 0x18 57 #define OXU_USBSPHLPWUI 0x00000080 58 #define OXU_USBOTGLPWUI 0x00000040 59 #define OXU_USBSPHI 0x00000002 60 #define OXU_USBOTGI 0x00000001 61 62#define OXU_CLKCTRL_SET 0x1C 63 #define OXU_SYSCLKEN 0x00000008 64 #define OXU_USBSPHCLKEN 0x00000002 65 #define OXU_USBOTGCLKEN 0x00000001 66 67#define OXU_ASO 0x68 68 #define OXU_SPHPOEN 0x00000100 69 #define OXU_OVRCCURPUPDEN 0x00000800 70 #define OXU_ASO_OP (1 << 10) 71 #define OXU_COMPARATOR 0x000004000 72 73#define OXU_USBMODE 0x1A8 74 #define OXU_VBPS 0x00000020 75 #define OXU_ES_LITTLE 0x00000000 76 #define OXU_CM_HOST_ONLY 0x00000003 77 78/* 79 * Proper EHCI structs & defines 80 */ 81 82/* Magic numbers that can affect system performance */ 83#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 84#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 85#define EHCI_TUNE_RL_TT 0 86#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 87#define EHCI_TUNE_MULT_TT 1 88#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 89 90struct oxu_hcd; 91 92/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 93 94/* Section 2.2 Host Controller Capability Registers */ 95struct ehci_caps { 96 /* these fields are specified as 8 and 16 bit registers, 97 * but some hosts can't perform 8 or 16 bit PCI accesses. 98 */ 99 u32 hc_capbase; 100#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 101#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 102 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 103#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 104#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 105#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 106#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 107#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 108#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 109#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 110 111 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 112#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 113#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 114#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 115#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 116#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 117#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 118 u8 portroute[8]; /* nibbles for routing - offset 0xC */ 119} __packed; 120 121 122/* Section 2.3 Host Controller Operational Registers */ 123struct ehci_regs { 124 /* USBCMD: offset 0x00 */ 125 u32 command; 126/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 127#define CMD_PARK (1<<11) /* enable "park" on async qh */ 128#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 129#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 130#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 131#define CMD_ASE (1<<5) /* async schedule enable */ 132#define CMD_PSE (1<<4) /* periodic schedule enable */ 133/* 3:2 is periodic frame list size */ 134#define CMD_RESET (1<<1) /* reset HC not bus */ 135#define CMD_RUN (1<<0) /* start/stop HC */ 136 137 /* USBSTS: offset 0x04 */ 138 u32 status; 139#define STS_ASS (1<<15) /* Async Schedule Status */ 140#define STS_PSS (1<<14) /* Periodic Schedule Status */ 141#define STS_RECL (1<<13) /* Reclamation */ 142#define STS_HALT (1<<12) /* Not running (any reason) */ 143/* some bits reserved */ 144 /* these STS_* flags are also intr_enable bits (USBINTR) */ 145#define STS_IAA (1<<5) /* Interrupted on async advance */ 146#define STS_FATAL (1<<4) /* such as some PCI access errors */ 147#define STS_FLR (1<<3) /* frame list rolled over */ 148#define STS_PCD (1<<2) /* port change detect */ 149#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 150#define STS_INT (1<<0) /* "normal" completion (short, ...) */ 151 152#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 153 154 /* USBINTR: offset 0x08 */ 155 u32 intr_enable; 156 157 /* FRINDEX: offset 0x0C */ 158 u32 frame_index; /* current microframe number */ 159 /* CTRLDSSEGMENT: offset 0x10 */ 160 u32 segment; /* address bits 63:32 if needed */ 161 /* PERIODICLISTBASE: offset 0x14 */ 162 u32 frame_list; /* points to periodic list */ 163 /* ASYNCLISTADDR: offset 0x18 */ 164 u32 async_next; /* address of next async queue head */ 165 166 u32 reserved[9]; 167 168 /* CONFIGFLAG: offset 0x40 */ 169 u32 configured_flag; 170#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 171 172 /* PORTSC: offset 0x44 */ 173 u32 port_status[]; /* up to N_PORTS */ 174/* 31:23 reserved */ 175#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 176#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 177#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 178/* 19:16 for port testing */ 179#define PORT_LED_OFF (0<<14) 180#define PORT_LED_AMBER (1<<14) 181#define PORT_LED_GREEN (2<<14) 182#define PORT_LED_MASK (3<<14) 183#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 184#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 185#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ 186/* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 187/* 9 reserved */ 188#define PORT_RESET (1<<8) /* reset port */ 189#define PORT_SUSPEND (1<<7) /* suspend port */ 190#define PORT_RESUME (1<<6) /* resume it */ 191#define PORT_OCC (1<<5) /* over current change */ 192#define PORT_OC (1<<4) /* over current active */ 193#define PORT_PEC (1<<3) /* port enable change */ 194#define PORT_PE (1<<2) /* port enable */ 195#define PORT_CSC (1<<1) /* connect status change */ 196#define PORT_CONNECT (1<<0) /* device connected */ 197#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 198} __packed; 199 200#define QTD_NEXT(dma) cpu_to_le32((u32)dma) 201 202/* 203 * EHCI Specification 0.95 Section 3.5 204 * QTD: describe data transfer components (buffer, direction, ...) 205 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 206 * 207 * These are associated only with "QH" (Queue Head) structures, 208 * used with control, bulk, and interrupt transfers. 209 */ 210struct ehci_qtd { 211 /* first part defined by EHCI spec */ 212 __le32 hw_next; /* see EHCI 3.5.1 */ 213 __le32 hw_alt_next; /* see EHCI 3.5.2 */ 214 __le32 hw_token; /* see EHCI 3.5.3 */ 215#define QTD_TOGGLE (1 << 31) /* data toggle */ 216#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 217#define QTD_IOC (1 << 15) /* interrupt on complete */ 218#define QTD_CERR(tok) (((tok)>>10) & 0x3) 219#define QTD_PID(tok) (((tok)>>8) & 0x3) 220#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 221#define QTD_STS_HALT (1 << 6) /* halted on error */ 222#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 223#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 224#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 225#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 226#define QTD_STS_STS (1 << 1) /* split transaction state */ 227#define QTD_STS_PING (1 << 0) /* issue PING? */ 228 __le32 hw_buf[5]; /* see EHCI 3.5.4 */ 229 __le32 hw_buf_hi[5]; /* Appendix B */ 230 231 /* the rest is HCD-private */ 232 dma_addr_t qtd_dma; /* qtd address */ 233 struct list_head qtd_list; /* sw qtd list */ 234 struct urb *urb; /* qtd's urb */ 235 size_t length; /* length of buffer */ 236 237 u32 qtd_buffer_len; 238 void *buffer; 239 dma_addr_t buffer_dma; 240 void *transfer_buffer; 241 void *transfer_dma; 242} __aligned(32); 243 244/* mask NakCnt+T in qh->hw_alt_next */ 245#define QTD_MASK cpu_to_le32 (~0x1f) 246 247#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) 248 249/* Type tag from {qh, itd, sitd, fstn}->hw_next */ 250#define Q_NEXT_TYPE(dma) ((dma) & cpu_to_le32 (3 << 1)) 251 252/* values for that type tag */ 253#define Q_TYPE_QH cpu_to_le32 (1 << 1) 254 255/* next async queue entry, or pointer to interrupt/periodic QH */ 256#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH) 257 258/* for periodic/async schedules and qtd lists, mark end of list */ 259#define EHCI_LIST_END cpu_to_le32(1) /* "null pointer" to hw */ 260 261/* 262 * Entries in periodic shadow table are pointers to one of four kinds 263 * of data structure. That's dictated by the hardware; a type tag is 264 * encoded in the low bits of the hardware's periodic schedule. Use 265 * Q_NEXT_TYPE to get the tag. 266 * 267 * For entries in the async schedule, the type tag always says "qh". 268 */ 269union ehci_shadow { 270 struct ehci_qh *qh; /* Q_TYPE_QH */ 271 __le32 *hw_next; /* (all types) */ 272 void *ptr; 273}; 274 275/* 276 * EHCI Specification 0.95 Section 3.6 277 * QH: describes control/bulk/interrupt endpoints 278 * See Fig 3-7 "Queue Head Structure Layout". 279 * 280 * These appear in both the async and (for interrupt) periodic schedules. 281 */ 282 283struct ehci_qh { 284 /* first part defined by EHCI spec */ 285 __le32 hw_next; /* see EHCI 3.6.1 */ 286 __le32 hw_info1; /* see EHCI 3.6.2 */ 287#define QH_HEAD 0x00008000 288 __le32 hw_info2; /* see EHCI 3.6.2 */ 289#define QH_SMASK 0x000000ff 290#define QH_CMASK 0x0000ff00 291#define QH_HUBADDR 0x007f0000 292#define QH_HUBPORT 0x3f800000 293#define QH_MULT 0xc0000000 294 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */ 295 296 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 297 __le32 hw_qtd_next; 298 __le32 hw_alt_next; 299 __le32 hw_token; 300 __le32 hw_buf[5]; 301 __le32 hw_buf_hi[5]; 302 303 /* the rest is HCD-private */ 304 dma_addr_t qh_dma; /* address of qh */ 305 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 306 struct list_head qtd_list; /* sw qtd list */ 307 struct ehci_qtd *dummy; 308 struct ehci_qh *reclaim; /* next to reclaim */ 309 310 struct oxu_hcd *oxu; 311 struct kref kref; 312 unsigned int stamp; 313 314 u8 qh_state; 315#define QH_STATE_LINKED 1 /* HC sees this */ 316#define QH_STATE_UNLINK 2 /* HC may still see this */ 317#define QH_STATE_IDLE 3 /* HC doesn't see this */ 318#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 319#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 320 321 /* periodic schedule info */ 322 u8 usecs; /* intr bandwidth */ 323 u8 gap_uf; /* uframes split/csplit gap */ 324 u8 c_usecs; /* ... split completion bw */ 325 u16 tt_usecs; /* tt downstream bandwidth */ 326 unsigned short period; /* polling interval */ 327 unsigned short start; /* where polling starts */ 328#define NO_FRAME ((unsigned short)~0) /* pick new start */ 329 struct usb_device *dev; /* access to TT */ 330} __aligned(32); 331 332/* 333 * Proper OXU210HP structs 334 */ 335 336#define OXU_OTG_CORE_OFFSET 0x00400 337#define OXU_OTG_CAP_OFFSET (OXU_OTG_CORE_OFFSET + 0x100) 338#define OXU_SPH_CORE_OFFSET 0x00800 339#define OXU_SPH_CAP_OFFSET (OXU_SPH_CORE_OFFSET + 0x100) 340 341#define OXU_OTG_MEM 0xE000 342#define OXU_SPH_MEM 0x16000 343 344/* Only how many elements & element structure are specifies here. */ 345/* 2 host controllers are enabled - total size <= 28 kbytes */ 346#define DEFAULT_I_TDPS 1024 347#define QHEAD_NUM 16 348#define QTD_NUM 32 349#define SITD_NUM 8 350#define MURB_NUM 8 351 352#define BUFFER_NUM 8 353#define BUFFER_SIZE 512 354 355struct oxu_info { 356 struct usb_hcd *hcd[2]; 357}; 358 359struct oxu_buf { 360 u8 buffer[BUFFER_SIZE]; 361} __aligned(BUFFER_SIZE); 362 363struct oxu_onchip_mem { 364 struct oxu_buf db_pool[BUFFER_NUM]; 365 366 u32 frame_list[DEFAULT_I_TDPS]; 367 struct ehci_qh qh_pool[QHEAD_NUM]; 368 struct ehci_qtd qtd_pool[QTD_NUM]; 369} __aligned(4 << 10); 370 371#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 372 373struct oxu_murb { 374 struct urb urb; 375 struct urb *main; 376 u8 last; 377}; 378 379struct oxu_hcd { /* one per controller */ 380 unsigned int is_otg:1; 381 382 u8 qh_used[QHEAD_NUM]; 383 u8 qtd_used[QTD_NUM]; 384 u8 db_used[BUFFER_NUM]; 385 u8 murb_used[MURB_NUM]; 386 387 struct oxu_onchip_mem __iomem *mem; 388 spinlock_t mem_lock; 389 390 struct timer_list urb_timer; 391 392 struct ehci_caps __iomem *caps; 393 struct ehci_regs __iomem *regs; 394 395 u32 hcs_params; /* cached register copy */ 396 spinlock_t lock; 397 398 /* async schedule support */ 399 struct ehci_qh *async; 400 struct ehci_qh *reclaim; 401 unsigned int reclaim_ready:1; 402 unsigned int scanning:1; 403 404 /* periodic schedule support */ 405 unsigned int periodic_size; 406 __le32 *periodic; /* hw periodic table */ 407 dma_addr_t periodic_dma; 408 unsigned int i_thresh; /* uframes HC might cache */ 409 410 union ehci_shadow *pshadow; /* mirror hw periodic table */ 411 int next_uframe; /* scan periodic, start here */ 412 unsigned int periodic_sched; /* periodic activity count */ 413 414 /* per root hub port */ 415 unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; 416 /* bit vectors (one bit per port) */ 417 unsigned long bus_suspended; /* which ports were 418 * already suspended at the 419 * start of a bus suspend 420 */ 421 unsigned long companion_ports;/* which ports are dedicated 422 * to the companion controller 423 */ 424 425 struct timer_list watchdog; 426 unsigned long actions; 427 unsigned int stamp; 428 unsigned long next_statechange; 429 u32 command; 430 431 /* SILICON QUIRKS */ 432 struct list_head urb_list; /* this is the head to urb 433 * queue that didn't get enough 434 * resources 435 */ 436 struct oxu_murb *murb_pool; /* murb per split big urb */ 437 unsigned int urb_len; 438 439 u8 sbrn; /* packed release number */ 440}; 441 442#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */ 443#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 444#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 445#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ 446 447enum ehci_timer_action { 448 TIMER_IO_WATCHDOG, 449 TIMER_IAA_WATCHDOG, 450 TIMER_ASYNC_SHRINK, 451 TIMER_ASYNC_OFF, 452}; 453 454/* 455 * Main defines 456 */ 457 458#define oxu_dbg(oxu, fmt, args...) \ 459 dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args) 460#define oxu_err(oxu, fmt, args...) \ 461 dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args) 462#define oxu_info(oxu, fmt, args...) \ 463 dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args) 464 465#ifdef CONFIG_DYNAMIC_DEBUG 466#define DEBUG 467#endif 468 469static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu) 470{ 471 return container_of((void *) oxu, struct usb_hcd, hcd_priv); 472} 473 474static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd) 475{ 476 return (struct oxu_hcd *) (hcd->hcd_priv); 477} 478 479/* 480 * Debug stuff 481 */ 482 483#undef OXU_URB_TRACE 484#undef OXU_VERBOSE_DEBUG 485 486#ifdef OXU_VERBOSE_DEBUG 487#define oxu_vdbg oxu_dbg 488#else 489#define oxu_vdbg(oxu, fmt, args...) /* Nop */ 490#endif 491 492#ifdef DEBUG 493 494static int __attribute__((__unused__)) 495dbg_status_buf(char *buf, unsigned len, const char *label, u32 status) 496{ 497 return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s", 498 label, label[0] ? " " : "", status, 499 (status & STS_ASS) ? " Async" : "", 500 (status & STS_PSS) ? " Periodic" : "", 501 (status & STS_RECL) ? " Recl" : "", 502 (status & STS_HALT) ? " Halt" : "", 503 (status & STS_IAA) ? " IAA" : "", 504 (status & STS_FATAL) ? " FATAL" : "", 505 (status & STS_FLR) ? " FLR" : "", 506 (status & STS_PCD) ? " PCD" : "", 507 (status & STS_ERR) ? " ERR" : "", 508 (status & STS_INT) ? " INT" : "" 509 ); 510} 511 512static int __attribute__((__unused__)) 513dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable) 514{ 515 return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s", 516 label, label[0] ? " " : "", enable, 517 (enable & STS_IAA) ? " IAA" : "", 518 (enable & STS_FATAL) ? " FATAL" : "", 519 (enable & STS_FLR) ? " FLR" : "", 520 (enable & STS_PCD) ? " PCD" : "", 521 (enable & STS_ERR) ? " ERR" : "", 522 (enable & STS_INT) ? " INT" : "" 523 ); 524} 525 526static const char *const fls_strings[] = 527 { "1024", "512", "256", "??" }; 528 529static int dbg_command_buf(char *buf, unsigned len, 530 const char *label, u32 command) 531{ 532 return scnprintf(buf, len, 533 "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s", 534 label, label[0] ? " " : "", command, 535 (command & CMD_PARK) ? "park" : "(park)", 536 CMD_PARK_CNT(command), 537 (command >> 16) & 0x3f, 538 (command & CMD_LRESET) ? " LReset" : "", 539 (command & CMD_IAAD) ? " IAAD" : "", 540 (command & CMD_ASE) ? " Async" : "", 541 (command & CMD_PSE) ? " Periodic" : "", 542 fls_strings[(command >> 2) & 0x3], 543 (command & CMD_RESET) ? " Reset" : "", 544 (command & CMD_RUN) ? "RUN" : "HALT" 545 ); 546} 547 548static int dbg_port_buf(char *buf, unsigned len, const char *label, 549 int port, u32 status) 550{ 551 char *sig; 552 553 /* signaling state */ 554 switch (status & (3 << 10)) { 555 case 0 << 10: 556 sig = "se0"; 557 break; 558 case 1 << 10: 559 sig = "k"; /* low speed */ 560 break; 561 case 2 << 10: 562 sig = "j"; 563 break; 564 default: 565 sig = "?"; 566 break; 567 } 568 569 return scnprintf(buf, len, 570 "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s", 571 label, label[0] ? " " : "", port, status, 572 (status & PORT_POWER) ? " POWER" : "", 573 (status & PORT_OWNER) ? " OWNER" : "", 574 sig, 575 (status & PORT_RESET) ? " RESET" : "", 576 (status & PORT_SUSPEND) ? " SUSPEND" : "", 577 (status & PORT_RESUME) ? " RESUME" : "", 578 (status & PORT_OCC) ? " OCC" : "", 579 (status & PORT_OC) ? " OC" : "", 580 (status & PORT_PEC) ? " PEC" : "", 581 (status & PORT_PE) ? " PE" : "", 582 (status & PORT_CSC) ? " CSC" : "", 583 (status & PORT_CONNECT) ? " CONNECT" : "" 584 ); 585} 586 587#else 588 589static inline int __attribute__((__unused__)) 590dbg_status_buf(char *buf, unsigned len, const char *label, u32 status) 591{ return 0; } 592 593static inline int __attribute__((__unused__)) 594dbg_command_buf(char *buf, unsigned len, const char *label, u32 command) 595{ return 0; } 596 597static inline int __attribute__((__unused__)) 598dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable) 599{ return 0; } 600 601static inline int __attribute__((__unused__)) 602dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status) 603{ return 0; } 604 605#endif /* DEBUG */ 606 607/* functions have the "wrong" filename when they're output... */ 608#define dbg_status(oxu, label, status) { \ 609 char _buf[80]; \ 610 dbg_status_buf(_buf, sizeof _buf, label, status); \ 611 oxu_dbg(oxu, "%s\n", _buf); \ 612} 613 614#define dbg_cmd(oxu, label, command) { \ 615 char _buf[80]; \ 616 dbg_command_buf(_buf, sizeof _buf, label, command); \ 617 oxu_dbg(oxu, "%s\n", _buf); \ 618} 619 620#define dbg_port(oxu, label, port, status) { \ 621 char _buf[80]; \ 622 dbg_port_buf(_buf, sizeof _buf, label, port, status); \ 623 oxu_dbg(oxu, "%s\n", _buf); \ 624} 625 626/* 627 * Module parameters 628 */ 629 630/* Initial IRQ latency: faster than hw default */ 631static int log2_irq_thresh; /* 0 to 6 */ 632module_param(log2_irq_thresh, int, S_IRUGO); 633MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 634 635/* Initial park setting: slower than hw default */ 636static unsigned park; 637module_param(park, uint, S_IRUGO); 638MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets"); 639 640/* For flakey hardware, ignore overcurrent indicators */ 641static bool ignore_oc; 642module_param(ignore_oc, bool, S_IRUGO); 643MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications"); 644 645 646static void ehci_work(struct oxu_hcd *oxu); 647static int oxu_hub_control(struct usb_hcd *hcd, 648 u16 typeReq, u16 wValue, u16 wIndex, 649 char *buf, u16 wLength); 650 651/* 652 * Local functions 653 */ 654 655/* Low level read/write registers functions */ 656static inline u32 oxu_readl(void __iomem *base, u32 reg) 657{ 658 return readl(base + reg); 659} 660 661static inline void oxu_writel(void __iomem *base, u32 reg, u32 val) 662{ 663 writel(val, base + reg); 664} 665 666static inline void timer_action_done(struct oxu_hcd *oxu, 667 enum ehci_timer_action action) 668{ 669 clear_bit(action, &oxu->actions); 670} 671 672static inline void timer_action(struct oxu_hcd *oxu, 673 enum ehci_timer_action action) 674{ 675 if (!test_and_set_bit(action, &oxu->actions)) { 676 unsigned long t; 677 678 switch (action) { 679 case TIMER_IAA_WATCHDOG: 680 t = EHCI_IAA_JIFFIES; 681 break; 682 case TIMER_IO_WATCHDOG: 683 t = EHCI_IO_JIFFIES; 684 break; 685 case TIMER_ASYNC_OFF: 686 t = EHCI_ASYNC_JIFFIES; 687 break; 688 case TIMER_ASYNC_SHRINK: 689 default: 690 t = EHCI_SHRINK_JIFFIES; 691 break; 692 } 693 t += jiffies; 694 /* all timings except IAA watchdog can be overridden. 695 * async queue SHRINK often precedes IAA. while it's ready 696 * to go OFF neither can matter, and afterwards the IO 697 * watchdog stops unless there's still periodic traffic. 698 */ 699 if (action != TIMER_IAA_WATCHDOG 700 && t > oxu->watchdog.expires 701 && timer_pending(&oxu->watchdog)) 702 return; 703 mod_timer(&oxu->watchdog, t); 704 } 705} 706 707/* 708 * handshake - spin reading hc until handshake completes or fails 709 * @ptr: address of hc register to be read 710 * @mask: bits to look at in result of read 711 * @done: value of those bits when handshake succeeds 712 * @usec: timeout in microseconds 713 * 714 * Returns negative errno, or zero on success 715 * 716 * Success happens when the "mask" bits have the specified value (hardware 717 * handshake done). There are two failure modes: "usec" have passed (major 718 * hardware flakeout), or the register reads as all-ones (hardware removed). 719 * 720 * That last failure should_only happen in cases like physical cardbus eject 721 * before driver shutdown. But it also seems to be caused by bugs in cardbus 722 * bridge shutdown: shutting down the bridge before the devices using it. 723 */ 724static int handshake(struct oxu_hcd *oxu, void __iomem *ptr, 725 u32 mask, u32 done, int usec) 726{ 727 u32 result; 728 int ret; 729 730 ret = readl_poll_timeout_atomic(ptr, result, 731 ((result & mask) == done || 732 result == U32_MAX), 733 1, usec); 734 if (result == U32_MAX) /* card removed */ 735 return -ENODEV; 736 737 return ret; 738} 739 740/* Force HC to halt state from unknown (EHCI spec section 2.3) */ 741static int ehci_halt(struct oxu_hcd *oxu) 742{ 743 u32 temp = readl(&oxu->regs->status); 744 745 /* disable any irqs left enabled by previous code */ 746 writel(0, &oxu->regs->intr_enable); 747 748 if ((temp & STS_HALT) != 0) 749 return 0; 750 751 temp = readl(&oxu->regs->command); 752 temp &= ~CMD_RUN; 753 writel(temp, &oxu->regs->command); 754 return handshake(oxu, &oxu->regs->status, 755 STS_HALT, STS_HALT, 16 * 125); 756} 757 758/* Put TDI/ARC silicon into EHCI mode */ 759static void tdi_reset(struct oxu_hcd *oxu) 760{ 761 u32 __iomem *reg_ptr; 762 u32 tmp; 763 764 reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68); 765 tmp = readl(reg_ptr); 766 tmp |= 0x3; 767 writel(tmp, reg_ptr); 768} 769 770/* Reset a non-running (STS_HALT == 1) controller */ 771static int ehci_reset(struct oxu_hcd *oxu) 772{ 773 int retval; 774 u32 command = readl(&oxu->regs->command); 775 776 command |= CMD_RESET; 777 dbg_cmd(oxu, "reset", command); 778 writel(command, &oxu->regs->command); 779 oxu_to_hcd(oxu)->state = HC_STATE_HALT; 780 oxu->next_statechange = jiffies; 781 retval = handshake(oxu, &oxu->regs->command, 782 CMD_RESET, 0, 250 * 1000); 783 784 if (retval) 785 return retval; 786 787 tdi_reset(oxu); 788 789 return retval; 790} 791 792/* Idle the controller (from running) */ 793static void ehci_quiesce(struct oxu_hcd *oxu) 794{ 795 u32 temp; 796 797#ifdef DEBUG 798 BUG_ON(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)); 799#endif 800 801 /* wait for any schedule enables/disables to take effect */ 802 temp = readl(&oxu->regs->command) << 10; 803 temp &= STS_ASS | STS_PSS; 804 if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS, 805 temp, 16 * 125) != 0) { 806 oxu_to_hcd(oxu)->state = HC_STATE_HALT; 807 return; 808 } 809 810 /* then disable anything that's still active */ 811 temp = readl(&oxu->regs->command); 812 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 813 writel(temp, &oxu->regs->command); 814 815 /* hardware can take 16 microframes to turn off ... */ 816 if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS, 817 0, 16 * 125) != 0) { 818 oxu_to_hcd(oxu)->state = HC_STATE_HALT; 819 return; 820 } 821} 822 823static int check_reset_complete(struct oxu_hcd *oxu, int index, 824 u32 __iomem *status_reg, int port_status) 825{ 826 if (!(port_status & PORT_CONNECT)) { 827 oxu->reset_done[index] = 0; 828 return port_status; 829 } 830 831 /* if reset finished and it's still not enabled -- handoff */ 832 if (!(port_status & PORT_PE)) { 833 oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n", 834 index+1); 835 return port_status; 836 } else 837 oxu_dbg(oxu, "port %d high speed\n", index + 1); 838 839 return port_status; 840} 841 842static void ehci_hub_descriptor(struct oxu_hcd *oxu, 843 struct usb_hub_descriptor *desc) 844{ 845 int ports = HCS_N_PORTS(oxu->hcs_params); 846 u16 temp; 847 848 desc->bDescriptorType = USB_DT_HUB; 849 desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */ 850 desc->bHubContrCurrent = 0; 851 852 desc->bNbrPorts = ports; 853 temp = 1 + (ports / 8); 854 desc->bDescLength = 7 + 2 * temp; 855 856 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 857 memset(&desc->u.hs.DeviceRemovable[0], 0, temp); 858 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); 859 860 temp = HUB_CHAR_INDV_PORT_OCPM; /* per-port overcurrent reporting */ 861 if (HCS_PPC(oxu->hcs_params)) 862 temp |= HUB_CHAR_INDV_PORT_LPSM; /* per-port power control */ 863 else 864 temp |= HUB_CHAR_NO_LPSM; /* no power switching */ 865 desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp); 866} 867 868 869/* Allocate an OXU210HP on-chip memory data buffer 870 * 871 * An on-chip memory data buffer is required for each OXU210HP USB transfer. 872 * Each transfer descriptor has one or more on-chip memory data buffers. 873 * 874 * Data buffers are allocated from a fix sized pool of data blocks. 875 * To minimise fragmentation and give reasonable memory utlisation, 876 * data buffers are allocated with sizes the power of 2 multiples of 877 * the block size, starting on an address a multiple of the allocated size. 878 * 879 * FIXME: callers of this function require a buffer to be allocated for 880 * len=0. This is a waste of on-chip memory and should be fix. Then this 881 * function should be changed to not allocate a buffer for len=0. 882 */ 883static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len) 884{ 885 int n_blocks; /* minium blocks needed to hold len */ 886 int a_blocks; /* blocks allocated */ 887 int i, j; 888 889 /* Don't allocate bigger than supported */ 890 if (len > BUFFER_SIZE * BUFFER_NUM) { 891 oxu_err(oxu, "buffer too big (%d)\n", len); 892 return -ENOMEM; 893 } 894 895 spin_lock(&oxu->mem_lock); 896 897 /* Number of blocks needed to hold len */ 898 n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE; 899 900 /* Round the number of blocks up to the power of 2 */ 901 for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1) 902 ; 903 904 /* Find a suitable available data buffer */ 905 for (i = 0; i < BUFFER_NUM; 906 i += max_t(int, a_blocks, oxu->db_used[i])) { 907 908 /* Check all the required blocks are available */ 909 for (j = 0; j < a_blocks; j++) 910 if (oxu->db_used[i + j]) 911 break; 912 913 if (j != a_blocks) 914 continue; 915 916 /* Allocate blocks found! */ 917 qtd->buffer = (void *) &oxu->mem->db_pool[i]; 918 qtd->buffer_dma = virt_to_phys(qtd->buffer); 919 920 qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks; 921 oxu->db_used[i] = a_blocks; 922 923 spin_unlock(&oxu->mem_lock); 924 925 return 0; 926 } 927 928 /* Failed */ 929 930 spin_unlock(&oxu->mem_lock); 931 932 return -ENOMEM; 933} 934 935static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) 936{ 937 int index; 938 939 spin_lock(&oxu->mem_lock); 940 941 index = (qtd->buffer - (void *) &oxu->mem->db_pool[0]) 942 / BUFFER_SIZE; 943 oxu->db_used[index] = 0; 944 qtd->qtd_buffer_len = 0; 945 qtd->buffer_dma = 0; 946 qtd->buffer = NULL; 947 948 spin_unlock(&oxu->mem_lock); 949} 950 951static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma) 952{ 953 memset(qtd, 0, sizeof *qtd); 954 qtd->qtd_dma = dma; 955 qtd->hw_token = cpu_to_le32(QTD_STS_HALT); 956 qtd->hw_next = EHCI_LIST_END; 957 qtd->hw_alt_next = EHCI_LIST_END; 958 INIT_LIST_HEAD(&qtd->qtd_list); 959} 960 961static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd) 962{ 963 int index; 964 965 if (qtd->buffer) 966 oxu_buf_free(oxu, qtd); 967 968 spin_lock(&oxu->mem_lock); 969 970 index = qtd - &oxu->mem->qtd_pool[0]; 971 oxu->qtd_used[index] = 0; 972 973 spin_unlock(&oxu->mem_lock); 974} 975 976static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu) 977{ 978 int i; 979 struct ehci_qtd *qtd = NULL; 980 981 spin_lock(&oxu->mem_lock); 982 983 for (i = 0; i < QTD_NUM; i++) 984 if (!oxu->qtd_used[i]) 985 break; 986 987 if (i < QTD_NUM) { 988 qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i]; 989 memset(qtd, 0, sizeof *qtd); 990 991 qtd->hw_token = cpu_to_le32(QTD_STS_HALT); 992 qtd->hw_next = EHCI_LIST_END; 993 qtd->hw_alt_next = EHCI_LIST_END; 994 INIT_LIST_HEAD(&qtd->qtd_list); 995 996 qtd->qtd_dma = virt_to_phys(qtd); 997 998 oxu->qtd_used[i] = 1; 999 } 1000 1001 spin_unlock(&oxu->mem_lock); 1002 1003 return qtd; 1004} 1005 1006static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh) 1007{ 1008 int index; 1009 1010 spin_lock(&oxu->mem_lock); 1011 1012 index = qh - &oxu->mem->qh_pool[0]; 1013 oxu->qh_used[index] = 0; 1014 1015 spin_unlock(&oxu->mem_lock); 1016} 1017 1018static void qh_destroy(struct kref *kref) 1019{ 1020 struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref); 1021 struct oxu_hcd *oxu = qh->oxu; 1022 1023 /* clean qtds first, and know this is not linked */ 1024 if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) { 1025 oxu_dbg(oxu, "unused qh not empty!\n"); 1026 BUG(); 1027 } 1028 if (qh->dummy) 1029 oxu_qtd_free(oxu, qh->dummy); 1030 oxu_qh_free(oxu, qh); 1031} 1032 1033static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu) 1034{ 1035 int i; 1036 struct ehci_qh *qh = NULL; 1037 1038 spin_lock(&oxu->mem_lock); 1039 1040 for (i = 0; i < QHEAD_NUM; i++) 1041 if (!oxu->qh_used[i]) 1042 break; 1043 1044 if (i < QHEAD_NUM) { 1045 qh = (struct ehci_qh *) &oxu->mem->qh_pool[i]; 1046 memset(qh, 0, sizeof *qh); 1047 1048 kref_init(&qh->kref); 1049 qh->oxu = oxu; 1050 qh->qh_dma = virt_to_phys(qh); 1051 INIT_LIST_HEAD(&qh->qtd_list); 1052 1053 /* dummy td enables safe urb queuing */ 1054 qh->dummy = ehci_qtd_alloc(oxu); 1055 if (qh->dummy == NULL) { 1056 oxu_dbg(oxu, "no dummy td\n"); 1057 oxu->qh_used[i] = 0; 1058 qh = NULL; 1059 goto unlock; 1060 } 1061 1062 oxu->qh_used[i] = 1; 1063 } 1064unlock: 1065 spin_unlock(&oxu->mem_lock); 1066 1067 return qh; 1068} 1069 1070/* to share a qh (cpu threads, or hc) */ 1071static inline struct ehci_qh *qh_get(struct ehci_qh *qh) 1072{ 1073 kref_get(&qh->kref); 1074 return qh; 1075} 1076 1077static inline void qh_put(struct ehci_qh *qh) 1078{ 1079 kref_put(&qh->kref, qh_destroy); 1080} 1081 1082static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb) 1083{ 1084 int index; 1085 1086 spin_lock(&oxu->mem_lock); 1087 1088 index = murb - &oxu->murb_pool[0]; 1089 oxu->murb_used[index] = 0; 1090 1091 spin_unlock(&oxu->mem_lock); 1092} 1093 1094static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu) 1095 1096{ 1097 int i; 1098 struct oxu_murb *murb = NULL; 1099 1100 spin_lock(&oxu->mem_lock); 1101 1102 for (i = 0; i < MURB_NUM; i++) 1103 if (!oxu->murb_used[i]) 1104 break; 1105 1106 if (i < MURB_NUM) { 1107 murb = &(oxu->murb_pool)[i]; 1108 1109 oxu->murb_used[i] = 1; 1110 } 1111 1112 spin_unlock(&oxu->mem_lock); 1113 1114 return murb; 1115} 1116 1117/* The queue heads and transfer descriptors are managed from pools tied 1118 * to each of the "per device" structures. 1119 * This is the initialisation and cleanup code. 1120 */ 1121static void ehci_mem_cleanup(struct oxu_hcd *oxu) 1122{ 1123 kfree(oxu->murb_pool); 1124 oxu->murb_pool = NULL; 1125 1126 if (oxu->async) 1127 qh_put(oxu->async); 1128 oxu->async = NULL; 1129 1130 timer_delete(&oxu->urb_timer); 1131 1132 oxu->periodic = NULL; 1133 1134 /* shadow periodic table */ 1135 kfree(oxu->pshadow); 1136 oxu->pshadow = NULL; 1137} 1138 1139/* Remember to add cleanup code (above) if you add anything here. 1140 */ 1141static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags) 1142{ 1143 int i; 1144 1145 for (i = 0; i < oxu->periodic_size; i++) 1146 oxu->mem->frame_list[i] = EHCI_LIST_END; 1147 for (i = 0; i < QHEAD_NUM; i++) 1148 oxu->qh_used[i] = 0; 1149 for (i = 0; i < QTD_NUM; i++) 1150 oxu->qtd_used[i] = 0; 1151 1152 oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags); 1153 if (!oxu->murb_pool) 1154 goto fail; 1155 1156 for (i = 0; i < MURB_NUM; i++) 1157 oxu->murb_used[i] = 0; 1158 1159 oxu->async = oxu_qh_alloc(oxu); 1160 if (!oxu->async) 1161 goto fail; 1162 1163 oxu->periodic = (__le32 *) &oxu->mem->frame_list; 1164 oxu->periodic_dma = virt_to_phys(oxu->periodic); 1165 1166 for (i = 0; i < oxu->periodic_size; i++) 1167 oxu->periodic[i] = EHCI_LIST_END; 1168 1169 /* software shadow of hardware table */ 1170 oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags); 1171 if (oxu->pshadow != NULL) 1172 return 0; 1173 1174fail: 1175 oxu_dbg(oxu, "couldn't init memory\n"); 1176 ehci_mem_cleanup(oxu); 1177 return -ENOMEM; 1178} 1179 1180/* Fill a qtd, returning how much of the buffer we were able to queue up. 1181 */ 1182static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len, 1183 int token, int maxpacket) 1184{ 1185 int i, count; 1186 u64 addr = buf; 1187 1188 /* one buffer entry per 4K ... first might be short or unaligned */ 1189 qtd->hw_buf[0] = cpu_to_le32((u32)addr); 1190 qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32)); 1191 count = 0x1000 - (buf & 0x0fff); /* rest of that page */ 1192 if (likely(len < count)) /* ... iff needed */ 1193 count = len; 1194 else { 1195 buf += 0x1000; 1196 buf &= ~0x0fff; 1197 1198 /* per-qtd limit: from 16K to 20K (best alignment) */ 1199 for (i = 1; count < len && i < 5; i++) { 1200 addr = buf; 1201 qtd->hw_buf[i] = cpu_to_le32((u32)addr); 1202 qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32)); 1203 buf += 0x1000; 1204 if ((count + 0x1000) < len) 1205 count += 0x1000; 1206 else 1207 count = len; 1208 } 1209 1210 /* short packets may only terminate transfers */ 1211 if (count != len) 1212 count -= (count % maxpacket); 1213 } 1214 qtd->hw_token = cpu_to_le32((count << 16) | token); 1215 qtd->length = count; 1216 1217 return count; 1218} 1219 1220static inline void qh_update(struct oxu_hcd *oxu, 1221 struct ehci_qh *qh, struct ehci_qtd *qtd) 1222{ 1223 /* writes to an active overlay are unsafe */ 1224 BUG_ON(qh->qh_state != QH_STATE_IDLE); 1225 1226 qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma); 1227 qh->hw_alt_next = EHCI_LIST_END; 1228 1229 /* Except for control endpoints, we make hardware maintain data 1230 * toggle (like OHCI) ... here (re)initialize the toggle in the QH, 1231 * and set the pseudo-toggle in udev. Only usb_clear_halt() will 1232 * ever clear it. 1233 */ 1234 if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) { 1235 unsigned is_out, epnum; 1236 1237 is_out = !(qtd->hw_token & cpu_to_le32(1 << 8)); 1238 epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f; 1239 if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) { 1240 qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE); 1241 usb_settoggle(qh->dev, epnum, is_out, 1); 1242 } 1243 } 1244 1245 /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */ 1246 wmb(); 1247 qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING); 1248} 1249 1250/* If it weren't for a common silicon quirk (writing the dummy into the qh 1251 * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault 1252 * recovery (including urb dequeue) would need software changes to a QH... 1253 */ 1254static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh) 1255{ 1256 struct ehci_qtd *qtd; 1257 1258 if (list_empty(&qh->qtd_list)) 1259 qtd = qh->dummy; 1260 else { 1261 qtd = list_entry(qh->qtd_list.next, 1262 struct ehci_qtd, qtd_list); 1263 /* first qtd may already be partially processed */ 1264 if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current) 1265 qtd = NULL; 1266 } 1267 1268 if (qtd) 1269 qh_update(oxu, qh, qtd); 1270} 1271 1272static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb, 1273 size_t length, u32 token) 1274{ 1275 /* count IN/OUT bytes, not SETUP (even short packets) */ 1276 if (likely(QTD_PID(token) != 2)) 1277 urb->actual_length += length - QTD_LENGTH(token); 1278 1279 /* don't modify error codes */ 1280 if (unlikely(urb->status != -EINPROGRESS)) 1281 return; 1282 1283 /* force cleanup after short read; not always an error */ 1284 if (unlikely(IS_SHORT_READ(token))) 1285 urb->status = -EREMOTEIO; 1286 1287 /* serious "can't proceed" faults reported by the hardware */ 1288 if (token & QTD_STS_HALT) { 1289 if (token & QTD_STS_BABBLE) { 1290 /* FIXME "must" disable babbling device's port too */ 1291 urb->status = -EOVERFLOW; 1292 } else if (token & QTD_STS_MMF) { 1293 /* fs/ls interrupt xfer missed the complete-split */ 1294 urb->status = -EPROTO; 1295 } else if (token & QTD_STS_DBE) { 1296 urb->status = (QTD_PID(token) == 1) /* IN ? */ 1297 ? -ENOSR /* hc couldn't read data */ 1298 : -ECOMM; /* hc couldn't write data */ 1299 } else if (token & QTD_STS_XACT) { 1300 /* timeout, bad crc, wrong PID, etc; retried */ 1301 if (QTD_CERR(token)) 1302 urb->status = -EPIPE; 1303 else { 1304 oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n", 1305 urb->dev->devpath, 1306 usb_pipeendpoint(urb->pipe), 1307 usb_pipein(urb->pipe) ? "in" : "out"); 1308 urb->status = -EPROTO; 1309 } 1310 /* CERR nonzero + no errors + halt --> stall */ 1311 } else if (QTD_CERR(token)) 1312 urb->status = -EPIPE; 1313 else /* unknown */ 1314 urb->status = -EPROTO; 1315 1316 oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n", 1317 usb_pipedevice(urb->pipe), 1318 usb_pipeendpoint(urb->pipe), 1319 usb_pipein(urb->pipe) ? "in" : "out", 1320 token, urb->status); 1321 } 1322} 1323 1324static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb) 1325__releases(oxu->lock) 1326__acquires(oxu->lock) 1327{ 1328 if (likely(urb->hcpriv != NULL)) { 1329 struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv; 1330 1331 /* S-mask in a QH means it's an interrupt urb */ 1332 if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) { 1333 1334 /* ... update hc-wide periodic stats (for usbfs) */ 1335 oxu_to_hcd(oxu)->self.bandwidth_int_reqs--; 1336 } 1337 qh_put(qh); 1338 } 1339 1340 urb->hcpriv = NULL; 1341 switch (urb->status) { 1342 case -EINPROGRESS: /* success */ 1343 urb->status = 0; 1344 break; 1345 default: /* fault */ 1346 break; 1347 case -EREMOTEIO: /* fault or normal */ 1348 if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) 1349 urb->status = 0; 1350 break; 1351 case -ECONNRESET: /* canceled */ 1352 case -ENOENT: 1353 break; 1354 } 1355 1356#ifdef OXU_URB_TRACE 1357 oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n", 1358 __func__, urb->dev->devpath, urb, 1359 usb_pipeendpoint(urb->pipe), 1360 usb_pipein(urb->pipe) ? "in" : "out", 1361 urb->status, 1362 urb->actual_length, urb->transfer_buffer_length); 1363#endif 1364 1365 /* complete() can reenter this HCD */ 1366 spin_unlock(&oxu->lock); 1367 usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status); 1368 spin_lock(&oxu->lock); 1369} 1370 1371static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh); 1372static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh); 1373 1374static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh); 1375static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh); 1376 1377#define HALT_BIT cpu_to_le32(QTD_STS_HALT) 1378 1379/* Process and free completed qtds for a qh, returning URBs to drivers. 1380 * Chases up to qh->hw_current. Returns number of completions called, 1381 * indicating how much "real" work we did. 1382 */ 1383static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh) 1384{ 1385 struct ehci_qtd *last = NULL, *end = qh->dummy; 1386 struct ehci_qtd *qtd, *tmp; 1387 int stopped; 1388 unsigned count = 0; 1389 int do_status = 0; 1390 u8 state; 1391 struct oxu_murb *murb = NULL; 1392 1393 if (unlikely(list_empty(&qh->qtd_list))) 1394 return count; 1395 1396 /* completions (or tasks on other cpus) must never clobber HALT 1397 * till we've gone through and cleaned everything up, even when 1398 * they add urbs to this qh's queue or mark them for unlinking. 1399 * 1400 * NOTE: unlinking expects to be done in queue order. 1401 */ 1402 state = qh->qh_state; 1403 qh->qh_state = QH_STATE_COMPLETING; 1404 stopped = (state == QH_STATE_IDLE); 1405 1406 /* remove de-activated QTDs from front of queue. 1407 * after faults (including short reads), cleanup this urb 1408 * then let the queue advance. 1409 * if queue is stopped, handles unlinks. 1410 */ 1411 list_for_each_entry_safe(qtd, tmp, &qh->qtd_list, qtd_list) { 1412 struct urb *urb; 1413 u32 token = 0; 1414 1415 urb = qtd->urb; 1416 1417 /* Clean up any state from previous QTD ...*/ 1418 if (last) { 1419 if (likely(last->urb != urb)) { 1420 if (last->urb->complete == NULL) { 1421 murb = (struct oxu_murb *) last->urb; 1422 last->urb = murb->main; 1423 if (murb->last) { 1424 ehci_urb_done(oxu, last->urb); 1425 count++; 1426 } 1427 oxu_murb_free(oxu, murb); 1428 } else { 1429 ehci_urb_done(oxu, last->urb); 1430 count++; 1431 } 1432 } 1433 oxu_qtd_free(oxu, last); 1434 last = NULL; 1435 } 1436 1437 /* ignore urbs submitted during completions we reported */ 1438 if (qtd == end) 1439 break; 1440 1441 /* hardware copies qtd out of qh overlay */ 1442 rmb(); 1443 token = le32_to_cpu(qtd->hw_token); 1444 1445 /* always clean up qtds the hc de-activated */ 1446 if ((token & QTD_STS_ACTIVE) == 0) { 1447 1448 if ((token & QTD_STS_HALT) != 0) { 1449 stopped = 1; 1450 1451 /* magic dummy for some short reads; qh won't advance. 1452 * that silicon quirk can kick in with this dummy too. 1453 */ 1454 } else if (IS_SHORT_READ(token) && 1455 !(qtd->hw_alt_next & EHCI_LIST_END)) { 1456 stopped = 1; 1457 goto halt; 1458 } 1459 1460 /* stop scanning when we reach qtds the hc is using */ 1461 } else if (likely(!stopped && 1462 HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) { 1463 break; 1464 1465 } else { 1466 stopped = 1; 1467 1468 if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) 1469 urb->status = -ESHUTDOWN; 1470 1471 /* ignore active urbs unless some previous qtd 1472 * for the urb faulted (including short read) or 1473 * its urb was canceled. we may patch qh or qtds. 1474 */ 1475 if (likely(urb->status == -EINPROGRESS)) 1476 continue; 1477 1478 /* issue status after short control reads */ 1479 if (unlikely(do_status != 0) 1480 && QTD_PID(token) == 0 /* OUT */) { 1481 do_status = 0; 1482 continue; 1483 } 1484 1485 /* token in overlay may be most current */ 1486 if (state == QH_STATE_IDLE 1487 && cpu_to_le32(qtd->qtd_dma) 1488 == qh->hw_current) 1489 token = le32_to_cpu(qh->hw_token); 1490 1491 /* force halt for unlinked or blocked qh, so we'll 1492 * patch the qh later and so that completions can't 1493 * activate it while we "know" it's stopped. 1494 */ 1495 if ((HALT_BIT & qh->hw_token) == 0) { 1496halt: 1497 qh->hw_token |= HALT_BIT; 1498 wmb(); 1499 } 1500 } 1501 1502 /* Remove it from the queue */ 1503 qtd_copy_status(oxu, urb->complete ? 1504 urb : ((struct oxu_murb *) urb)->main, 1505 qtd->length, token); 1506 if ((usb_pipein(qtd->urb->pipe)) && 1507 (NULL != qtd->transfer_buffer)) 1508 memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length); 1509 do_status = (urb->status == -EREMOTEIO) 1510 && usb_pipecontrol(urb->pipe); 1511 1512 if (stopped && qtd->qtd_list.prev != &qh->qtd_list) { 1513 last = list_entry(qtd->qtd_list.prev, 1514 struct ehci_qtd, qtd_list); 1515 last->hw_next = qtd->hw_next; 1516 } 1517 list_del(&qtd->qtd_list); 1518 last = qtd; 1519 } 1520 1521 /* last urb's completion might still need calling */ 1522 if (likely(last != NULL)) { 1523 if (last->urb->complete == NULL) { 1524 murb = (struct oxu_murb *) last->urb; 1525 last->urb = murb->main; 1526 if (murb->last) { 1527 ehci_urb_done(oxu, last->urb); 1528 count++; 1529 } 1530 oxu_murb_free(oxu, murb); 1531 } else { 1532 ehci_urb_done(oxu, last->urb); 1533 count++; 1534 } 1535 oxu_qtd_free(oxu, last); 1536 } 1537 1538 /* restore original state; caller must unlink or relink */ 1539 qh->qh_state = state; 1540 1541 /* be sure the hardware's done with the qh before refreshing 1542 * it after fault cleanup, or recovering from silicon wrongly 1543 * overlaying the dummy qtd (which reduces DMA chatter). 1544 */ 1545 if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) { 1546 switch (state) { 1547 case QH_STATE_IDLE: 1548 qh_refresh(oxu, qh); 1549 break; 1550 case QH_STATE_LINKED: 1551 /* should be rare for periodic transfers, 1552 * except maybe high bandwidth ... 1553 */ 1554 if ((cpu_to_le32(QH_SMASK) 1555 & qh->hw_info2) != 0) { 1556 intr_deschedule(oxu, qh); 1557 (void) qh_schedule(oxu, qh); 1558 } else 1559 unlink_async(oxu, qh); 1560 break; 1561 /* otherwise, unlink already started */ 1562 } 1563 } 1564 1565 return count; 1566} 1567 1568/* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */ 1569#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) 1570/* ... and packet size, for any kind of endpoint descriptor */ 1571#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1572 1573/* Reverse of qh_urb_transaction: free a list of TDs. 1574 * used for cleanup after errors, before HC sees an URB's TDs. 1575 */ 1576static void qtd_list_free(struct oxu_hcd *oxu, 1577 struct urb *urb, struct list_head *head) 1578{ 1579 struct ehci_qtd *qtd, *temp; 1580 1581 list_for_each_entry_safe(qtd, temp, head, qtd_list) { 1582 list_del(&qtd->qtd_list); 1583 oxu_qtd_free(oxu, qtd); 1584 } 1585} 1586 1587/* Create a list of filled qtds for this URB; won't link into qh. 1588 */ 1589static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu, 1590 struct urb *urb, 1591 struct list_head *head, 1592 gfp_t flags) 1593{ 1594 struct ehci_qtd *qtd, *qtd_prev; 1595 dma_addr_t buf; 1596 int len, maxpacket; 1597 int is_input; 1598 u32 token; 1599 void *transfer_buf = NULL; 1600 int ret; 1601 1602 /* 1603 * URBs map to sequences of QTDs: one logical transaction 1604 */ 1605 qtd = ehci_qtd_alloc(oxu); 1606 if (unlikely(!qtd)) 1607 return NULL; 1608 list_add_tail(&qtd->qtd_list, head); 1609 qtd->urb = urb; 1610 1611 token = QTD_STS_ACTIVE; 1612 token |= (EHCI_TUNE_CERR << 10); 1613 /* for split transactions, SplitXState initialized to zero */ 1614 1615 len = urb->transfer_buffer_length; 1616 is_input = usb_pipein(urb->pipe); 1617 if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input) 1618 urb->transfer_buffer = phys_to_virt(urb->transfer_dma); 1619 1620 if (usb_pipecontrol(urb->pipe)) { 1621 /* SETUP pid */ 1622 ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest)); 1623 if (ret) 1624 goto cleanup; 1625 1626 qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest), 1627 token | (2 /* "setup" */ << 8), 8); 1628 memcpy(qtd->buffer, qtd->urb->setup_packet, 1629 sizeof(struct usb_ctrlrequest)); 1630 1631 /* ... and always at least one more pid */ 1632 token ^= QTD_TOGGLE; 1633 qtd_prev = qtd; 1634 qtd = ehci_qtd_alloc(oxu); 1635 if (unlikely(!qtd)) 1636 goto cleanup; 1637 qtd->urb = urb; 1638 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); 1639 list_add_tail(&qtd->qtd_list, head); 1640 1641 /* for zero length DATA stages, STATUS is always IN */ 1642 if (len == 0) 1643 token |= (1 /* "in" */ << 8); 1644 } 1645 1646 /* 1647 * Data transfer stage: buffer setup 1648 */ 1649 1650 ret = oxu_buf_alloc(oxu, qtd, len); 1651 if (ret) 1652 goto cleanup; 1653 1654 buf = qtd->buffer_dma; 1655 transfer_buf = urb->transfer_buffer; 1656 1657 if (!is_input) 1658 memcpy(qtd->buffer, qtd->urb->transfer_buffer, len); 1659 1660 if (is_input) 1661 token |= (1 /* "in" */ << 8); 1662 /* else it's already initted to "out" pid (0 << 8) */ 1663 1664 maxpacket = usb_maxpacket(urb->dev, urb->pipe); 1665 1666 /* 1667 * buffer gets wrapped in one or more qtds; 1668 * last one may be "short" (including zero len) 1669 * and may serve as a control status ack 1670 */ 1671 for (;;) { 1672 int this_qtd_len; 1673 1674 this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket); 1675 qtd->transfer_buffer = transfer_buf; 1676 len -= this_qtd_len; 1677 buf += this_qtd_len; 1678 transfer_buf += this_qtd_len; 1679 if (is_input) 1680 qtd->hw_alt_next = oxu->async->hw_alt_next; 1681 1682 /* qh makes control packets use qtd toggle; maybe switch it */ 1683 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) 1684 token ^= QTD_TOGGLE; 1685 1686 if (likely(len <= 0)) 1687 break; 1688 1689 qtd_prev = qtd; 1690 qtd = ehci_qtd_alloc(oxu); 1691 if (unlikely(!qtd)) 1692 goto cleanup; 1693 if (likely(len > 0)) { 1694 ret = oxu_buf_alloc(oxu, qtd, len); 1695 if (ret) 1696 goto cleanup; 1697 } 1698 qtd->urb = urb; 1699 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); 1700 list_add_tail(&qtd->qtd_list, head); 1701 } 1702 1703 /* unless the bulk/interrupt caller wants a chance to clean 1704 * up after short reads, hc should advance qh past this urb 1705 */ 1706 if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 1707 || usb_pipecontrol(urb->pipe))) 1708 qtd->hw_alt_next = EHCI_LIST_END; 1709 1710 /* 1711 * control requests may need a terminating data "status" ack; 1712 * bulk ones may need a terminating short packet (zero length). 1713 */ 1714 if (likely(urb->transfer_buffer_length != 0)) { 1715 int one_more = 0; 1716 1717 if (usb_pipecontrol(urb->pipe)) { 1718 one_more = 1; 1719 token ^= 0x0100; /* "in" <--> "out" */ 1720 token |= QTD_TOGGLE; /* force DATA1 */ 1721 } else if (usb_pipebulk(urb->pipe) 1722 && (urb->transfer_flags & URB_ZERO_PACKET) 1723 && !(urb->transfer_buffer_length % maxpacket)) { 1724 one_more = 1; 1725 } 1726 if (one_more) { 1727 qtd_prev = qtd; 1728 qtd = ehci_qtd_alloc(oxu); 1729 if (unlikely(!qtd)) 1730 goto cleanup; 1731 qtd->urb = urb; 1732 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma); 1733 list_add_tail(&qtd->qtd_list, head); 1734 1735 /* never any data in such packets */ 1736 qtd_fill(qtd, 0, 0, token, 0); 1737 } 1738 } 1739 1740 /* by default, enable interrupt on urb completion */ 1741 qtd->hw_token |= cpu_to_le32(QTD_IOC); 1742 return head; 1743 1744cleanup: 1745 qtd_list_free(oxu, urb, head); 1746 return NULL; 1747} 1748 1749/* Each QH holds a qtd list; a QH is used for everything except iso. 1750 * 1751 * For interrupt urbs, the scheduler must set the microframe scheduling 1752 * mask(s) each time the QH gets scheduled. For highspeed, that's 1753 * just one microframe in the s-mask. For split interrupt transactions 1754 * there are additional complications: c-mask, maybe FSTNs. 1755 */ 1756static struct ehci_qh *qh_make(struct oxu_hcd *oxu, 1757 struct urb *urb, gfp_t flags) 1758{ 1759 struct ehci_qh *qh = oxu_qh_alloc(oxu); 1760 u32 info1 = 0, info2 = 0; 1761 int is_input, type; 1762 int maxp = 0; 1763 1764 if (!qh) 1765 return qh; 1766 1767 /* 1768 * init endpoint/device data for this QH 1769 */ 1770 info1 |= usb_pipeendpoint(urb->pipe) << 8; 1771 info1 |= usb_pipedevice(urb->pipe) << 0; 1772 1773 is_input = usb_pipein(urb->pipe); 1774 type = usb_pipetype(urb->pipe); 1775 maxp = usb_maxpacket(urb->dev, urb->pipe); 1776 1777 /* Compute interrupt scheduling parameters just once, and save. 1778 * - allowing for high bandwidth, how many nsec/uframe are used? 1779 * - split transactions need a second CSPLIT uframe; same question 1780 * - splits also need a schedule gap (for full/low speed I/O) 1781 * - qh has a polling interval 1782 * 1783 * For control/bulk requests, the HC or TT handles these. 1784 */ 1785 if (type == PIPE_INTERRUPT) { 1786 qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH, 1787 is_input, 0, 1788 hb_mult(maxp) * max_packet(maxp))); 1789 qh->start = NO_FRAME; 1790 1791 if (urb->dev->speed == USB_SPEED_HIGH) { 1792 qh->c_usecs = 0; 1793 qh->gap_uf = 0; 1794 1795 qh->period = urb->interval >> 3; 1796 if (qh->period == 0 && urb->interval != 1) { 1797 /* NOTE interval 2 or 4 uframes could work. 1798 * But interval 1 scheduling is simpler, and 1799 * includes high bandwidth. 1800 */ 1801 oxu_dbg(oxu, "intr period %d uframes, NYET!\n", 1802 urb->interval); 1803 goto done; 1804 } 1805 } else { 1806 struct usb_tt *tt = urb->dev->tt; 1807 int think_time; 1808 1809 /* gap is f(FS/LS transfer times) */ 1810 qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed, 1811 is_input, 0, maxp) / (125 * 1000); 1812 1813 /* FIXME this just approximates SPLIT/CSPLIT times */ 1814 if (is_input) { /* SPLIT, gap, CSPLIT+DATA */ 1815 qh->c_usecs = qh->usecs + HS_USECS(0); 1816 qh->usecs = HS_USECS(1); 1817 } else { /* SPLIT+DATA, gap, CSPLIT */ 1818 qh->usecs += HS_USECS(1); 1819 qh->c_usecs = HS_USECS(0); 1820 } 1821 1822 think_time = tt ? tt->think_time : 0; 1823 qh->tt_usecs = NS_TO_US(think_time + 1824 usb_calc_bus_time(urb->dev->speed, 1825 is_input, 0, max_packet(maxp))); 1826 qh->period = urb->interval; 1827 } 1828 } 1829 1830 /* support for tt scheduling, and access to toggles */ 1831 qh->dev = urb->dev; 1832 1833 /* using TT? */ 1834 switch (urb->dev->speed) { 1835 case USB_SPEED_LOW: 1836 info1 |= (1 << 12); /* EPS "low" */ 1837 fallthrough; 1838 1839 case USB_SPEED_FULL: 1840 /* EPS 0 means "full" */ 1841 if (type != PIPE_INTERRUPT) 1842 info1 |= (EHCI_TUNE_RL_TT << 28); 1843 if (type == PIPE_CONTROL) { 1844 info1 |= (1 << 27); /* for TT */ 1845 info1 |= 1 << 14; /* toggle from qtd */ 1846 } 1847 info1 |= maxp << 16; 1848 1849 info2 |= (EHCI_TUNE_MULT_TT << 30); 1850 info2 |= urb->dev->ttport << 23; 1851 1852 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */ 1853 1854 break; 1855 1856 case USB_SPEED_HIGH: /* no TT involved */ 1857 info1 |= (2 << 12); /* EPS "high" */ 1858 if (type == PIPE_CONTROL) { 1859 info1 |= (EHCI_TUNE_RL_HS << 28); 1860 info1 |= 64 << 16; /* usb2 fixed maxpacket */ 1861 info1 |= 1 << 14; /* toggle from qtd */ 1862 info2 |= (EHCI_TUNE_MULT_HS << 30); 1863 } else if (type == PIPE_BULK) { 1864 info1 |= (EHCI_TUNE_RL_HS << 28); 1865 info1 |= 512 << 16; /* usb2 fixed maxpacket */ 1866 info2 |= (EHCI_TUNE_MULT_HS << 30); 1867 } else { /* PIPE_INTERRUPT */ 1868 info1 |= max_packet(maxp) << 16; 1869 info2 |= hb_mult(maxp) << 30; 1870 } 1871 break; 1872 default: 1873 oxu_dbg(oxu, "bogus dev %p speed %d\n", urb->dev, urb->dev->speed); 1874done: 1875 qh_put(qh); 1876 return NULL; 1877 } 1878 1879 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */ 1880 1881 /* init as live, toggle clear, advance to dummy */ 1882 qh->qh_state = QH_STATE_IDLE; 1883 qh->hw_info1 = cpu_to_le32(info1); 1884 qh->hw_info2 = cpu_to_le32(info2); 1885 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1); 1886 qh_refresh(oxu, qh); 1887 return qh; 1888} 1889 1890/* Move qh (and its qtds) onto async queue; maybe enable queue. 1891 */ 1892static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh) 1893{ 1894 __le32 dma = QH_NEXT(qh->qh_dma); 1895 struct ehci_qh *head; 1896 1897 /* (re)start the async schedule? */ 1898 head = oxu->async; 1899 timer_action_done(oxu, TIMER_ASYNC_OFF); 1900 if (!head->qh_next.qh) { 1901 u32 cmd = readl(&oxu->regs->command); 1902 1903 if (!(cmd & CMD_ASE)) { 1904 /* in case a clear of CMD_ASE didn't take yet */ 1905 (void)handshake(oxu, &oxu->regs->status, 1906 STS_ASS, 0, 150); 1907 cmd |= CMD_ASE | CMD_RUN; 1908 writel(cmd, &oxu->regs->command); 1909 oxu_to_hcd(oxu)->state = HC_STATE_RUNNING; 1910 /* posted write need not be known to HC yet ... */ 1911 } 1912 } 1913 1914 /* clear halt and/or toggle; and maybe recover from silicon quirk */ 1915 if (qh->qh_state == QH_STATE_IDLE) 1916 qh_refresh(oxu, qh); 1917 1918 /* splice right after start */ 1919 qh->qh_next = head->qh_next; 1920 qh->hw_next = head->hw_next; 1921 wmb(); 1922 1923 head->qh_next.qh = qh; 1924 head->hw_next = dma; 1925 1926 qh->qh_state = QH_STATE_LINKED; 1927 /* qtd completions reported later by interrupt */ 1928} 1929 1930#define QH_ADDR_MASK cpu_to_le32(0x7f) 1931 1932/* 1933 * For control/bulk/interrupt, return QH with these TDs appended. 1934 * Allocates and initializes the QH if necessary. 1935 * Returns null if it can't allocate a QH it needs to. 1936 * If the QH has TDs (urbs) already, that's great. 1937 */ 1938static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu, 1939 struct urb *urb, struct list_head *qtd_list, 1940 int epnum, void **ptr) 1941{ 1942 struct ehci_qh *qh = NULL; 1943 1944 qh = (struct ehci_qh *) *ptr; 1945 if (unlikely(qh == NULL)) { 1946 /* can't sleep here, we have oxu->lock... */ 1947 qh = qh_make(oxu, urb, GFP_ATOMIC); 1948 *ptr = qh; 1949 } 1950 if (likely(qh != NULL)) { 1951 struct ehci_qtd *qtd; 1952 1953 if (unlikely(list_empty(qtd_list))) 1954 qtd = NULL; 1955 else 1956 qtd = list_entry(qtd_list->next, struct ehci_qtd, 1957 qtd_list); 1958 1959 /* control qh may need patching ... */ 1960 if (unlikely(epnum == 0)) { 1961 1962 /* usb_reset_device() briefly reverts to address 0 */ 1963 if (usb_pipedevice(urb->pipe) == 0) 1964 qh->hw_info1 &= ~QH_ADDR_MASK; 1965 } 1966 1967 /* just one way to queue requests: swap with the dummy qtd. 1968 * only hc or qh_refresh() ever modify the overlay. 1969 */ 1970 if (likely(qtd != NULL)) { 1971 struct ehci_qtd *dummy; 1972 dma_addr_t dma; 1973 __le32 token; 1974 1975 /* to avoid racing the HC, use the dummy td instead of 1976 * the first td of our list (becomes new dummy). both 1977 * tds stay deactivated until we're done, when the 1978 * HC is allowed to fetch the old dummy (4.10.2). 1979 */ 1980 token = qtd->hw_token; 1981 qtd->hw_token = HALT_BIT; 1982 wmb(); 1983 dummy = qh->dummy; 1984 1985 dma = dummy->qtd_dma; 1986 *dummy = *qtd; 1987 dummy->qtd_dma = dma; 1988 1989 list_del(&qtd->qtd_list); 1990 list_add(&dummy->qtd_list, qtd_list); 1991 list_splice(qtd_list, qh->qtd_list.prev); 1992 1993 ehci_qtd_init(qtd, qtd->qtd_dma); 1994 qh->dummy = qtd; 1995 1996 /* hc must see the new dummy at list end */ 1997 dma = qtd->qtd_dma; 1998 qtd = list_entry(qh->qtd_list.prev, 1999 struct ehci_qtd, qtd_list); 2000 qtd->hw_next = QTD_NEXT(dma); 2001 2002 /* let the hc process these next qtds */ 2003 dummy->hw_token = (token & ~(0x80)); 2004 wmb(); 2005 dummy->hw_token = token; 2006 2007 urb->hcpriv = qh_get(qh); 2008 } 2009 } 2010 return qh; 2011} 2012 2013static int submit_async(struct oxu_hcd *oxu, struct urb *urb, 2014 struct list_head *qtd_list, gfp_t mem_flags) 2015{ 2016 int epnum = urb->ep->desc.bEndpointAddress; 2017 unsigned long flags; 2018 struct ehci_qh *qh = NULL; 2019 int rc = 0; 2020#ifdef OXU_URB_TRACE 2021 struct ehci_qtd *qtd; 2022 2023 qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list); 2024 2025 oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", 2026 __func__, urb->dev->devpath, urb, 2027 epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", 2028 urb->transfer_buffer_length, 2029 qtd, urb->ep->hcpriv); 2030#endif 2031 2032 spin_lock_irqsave(&oxu->lock, flags); 2033 if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) { 2034 rc = -ESHUTDOWN; 2035 goto done; 2036 } 2037 2038 qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv); 2039 if (unlikely(qh == NULL)) { 2040 rc = -ENOMEM; 2041 goto done; 2042 } 2043 2044 /* Control/bulk operations through TTs don't need scheduling, 2045 * the HC and TT handle it when the TT has a buffer ready. 2046 */ 2047 if (likely(qh->qh_state == QH_STATE_IDLE)) 2048 qh_link_async(oxu, qh_get(qh)); 2049done: 2050 spin_unlock_irqrestore(&oxu->lock, flags); 2051 if (unlikely(qh == NULL)) 2052 qtd_list_free(oxu, urb, qtd_list); 2053 return rc; 2054} 2055 2056/* The async qh for the qtds being reclaimed are now unlinked from the HC */ 2057 2058static void end_unlink_async(struct oxu_hcd *oxu) 2059{ 2060 struct ehci_qh *qh = oxu->reclaim; 2061 struct ehci_qh *next; 2062 2063 timer_action_done(oxu, TIMER_IAA_WATCHDOG); 2064 2065 qh->qh_state = QH_STATE_IDLE; 2066 qh->qh_next.qh = NULL; 2067 qh_put(qh); /* refcount from reclaim */ 2068 2069 /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */ 2070 next = qh->reclaim; 2071 oxu->reclaim = next; 2072 oxu->reclaim_ready = 0; 2073 qh->reclaim = NULL; 2074 2075 qh_completions(oxu, qh); 2076 2077 if (!list_empty(&qh->qtd_list) 2078 && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) 2079 qh_link_async(oxu, qh); 2080 else { 2081 qh_put(qh); /* refcount from async list */ 2082 2083 /* it's not free to turn the async schedule on/off; leave it 2084 * active but idle for a while once it empties. 2085 */ 2086 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) 2087 && oxu->async->qh_next.qh == NULL) 2088 timer_action(oxu, TIMER_ASYNC_OFF); 2089 } 2090 2091 if (next) { 2092 oxu->reclaim = NULL; 2093 start_unlink_async(oxu, next); 2094 } 2095} 2096 2097/* makes sure the async qh will become idle */ 2098/* caller must own oxu->lock */ 2099 2100static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh) 2101{ 2102 int cmd = readl(&oxu->regs->command); 2103 struct ehci_qh *prev; 2104 2105#ifdef DEBUG 2106 assert_spin_locked(&oxu->lock); 2107 BUG_ON(oxu->reclaim || (qh->qh_state != QH_STATE_LINKED 2108 && qh->qh_state != QH_STATE_UNLINK_WAIT)); 2109#endif 2110 2111 /* stop async schedule right now? */ 2112 if (unlikely(qh == oxu->async)) { 2113 /* can't get here without STS_ASS set */ 2114 if (oxu_to_hcd(oxu)->state != HC_STATE_HALT 2115 && !oxu->reclaim) { 2116 /* ... and CMD_IAAD clear */ 2117 writel(cmd & ~CMD_ASE, &oxu->regs->command); 2118 wmb(); 2119 /* handshake later, if we need to */ 2120 timer_action_done(oxu, TIMER_ASYNC_OFF); 2121 } 2122 return; 2123 } 2124 2125 qh->qh_state = QH_STATE_UNLINK; 2126 oxu->reclaim = qh = qh_get(qh); 2127 2128 prev = oxu->async; 2129 while (prev->qh_next.qh != qh) 2130 prev = prev->qh_next.qh; 2131 2132 prev->hw_next = qh->hw_next; 2133 prev->qh_next = qh->qh_next; 2134 wmb(); 2135 2136 if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) { 2137 /* if (unlikely(qh->reclaim != 0)) 2138 * this will recurse, probably not much 2139 */ 2140 end_unlink_async(oxu); 2141 return; 2142 } 2143 2144 oxu->reclaim_ready = 0; 2145 cmd |= CMD_IAAD; 2146 writel(cmd, &oxu->regs->command); 2147 (void) readl(&oxu->regs->command); 2148 timer_action(oxu, TIMER_IAA_WATCHDOG); 2149} 2150 2151static void scan_async(struct oxu_hcd *oxu) 2152{ 2153 struct ehci_qh *qh; 2154 enum ehci_timer_action action = TIMER_IO_WATCHDOG; 2155 2156 if (!++(oxu->stamp)) 2157 oxu->stamp++; 2158 timer_action_done(oxu, TIMER_ASYNC_SHRINK); 2159rescan: 2160 qh = oxu->async->qh_next.qh; 2161 if (likely(qh != NULL)) { 2162 do { 2163 /* clean any finished work for this qh */ 2164 if (!list_empty(&qh->qtd_list) 2165 && qh->stamp != oxu->stamp) { 2166 int temp; 2167 2168 /* unlinks could happen here; completion 2169 * reporting drops the lock. rescan using 2170 * the latest schedule, but don't rescan 2171 * qhs we already finished (no looping). 2172 */ 2173 qh = qh_get(qh); 2174 qh->stamp = oxu->stamp; 2175 temp = qh_completions(oxu, qh); 2176 qh_put(qh); 2177 if (temp != 0) 2178 goto rescan; 2179 } 2180 2181 /* unlink idle entries, reducing HC PCI usage as well 2182 * as HCD schedule-scanning costs. delay for any qh 2183 * we just scanned, there's a not-unusual case that it 2184 * doesn't stay idle for long. 2185 * (plus, avoids some kind of re-activation race.) 2186 */ 2187 if (list_empty(&qh->qtd_list)) { 2188 if (qh->stamp == oxu->stamp) 2189 action = TIMER_ASYNC_SHRINK; 2190 else if (!oxu->reclaim 2191 && qh->qh_state == QH_STATE_LINKED) 2192 start_unlink_async(oxu, qh); 2193 } 2194 2195 qh = qh->qh_next.qh; 2196 } while (qh); 2197 } 2198 if (action == TIMER_ASYNC_SHRINK) 2199 timer_action(oxu, TIMER_ASYNC_SHRINK); 2200} 2201 2202/* 2203 * periodic_next_shadow - return "next" pointer on shadow list 2204 * @periodic: host pointer to qh/itd/sitd 2205 * @tag: hardware tag for type of this record 2206 */ 2207static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic, 2208 __le32 tag) 2209{ 2210 switch (tag) { 2211 default: 2212 case Q_TYPE_QH: 2213 return &periodic->qh->qh_next; 2214 } 2215} 2216 2217/* caller must hold oxu->lock */ 2218static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr) 2219{ 2220 union ehci_shadow *prev_p = &oxu->pshadow[frame]; 2221 __le32 *hw_p = &oxu->periodic[frame]; 2222 union ehci_shadow here = *prev_p; 2223 2224 /* find predecessor of "ptr"; hw and shadow lists are in sync */ 2225 while (here.ptr && here.ptr != ptr) { 2226 prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p)); 2227 hw_p = here.hw_next; 2228 here = *prev_p; 2229 } 2230 /* an interrupt entry (at list end) could have been shared */ 2231 if (!here.ptr) 2232 return; 2233 2234 /* update shadow and hardware lists ... the old "next" pointers 2235 * from ptr may still be in use, the caller updates them. 2236 */ 2237 *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p)); 2238 *hw_p = *here.hw_next; 2239} 2240 2241/* how many of the uframe's 125 usecs are allocated? */ 2242static unsigned short periodic_usecs(struct oxu_hcd *oxu, 2243 unsigned frame, unsigned uframe) 2244{ 2245 __le32 *hw_p = &oxu->periodic[frame]; 2246 union ehci_shadow *q = &oxu->pshadow[frame]; 2247 unsigned usecs = 0; 2248 2249 while (q->ptr) { 2250 switch (Q_NEXT_TYPE(*hw_p)) { 2251 case Q_TYPE_QH: 2252 default: 2253 /* is it in the S-mask? */ 2254 if (q->qh->hw_info2 & cpu_to_le32(1 << uframe)) 2255 usecs += q->qh->usecs; 2256 /* ... or C-mask? */ 2257 if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe))) 2258 usecs += q->qh->c_usecs; 2259 hw_p = &q->qh->hw_next; 2260 q = &q->qh->qh_next; 2261 break; 2262 } 2263 } 2264#ifdef DEBUG 2265 if (usecs > 100) 2266 oxu_err(oxu, "uframe %d sched overrun: %d usecs\n", 2267 frame * 8 + uframe, usecs); 2268#endif 2269 return usecs; 2270} 2271 2272static int enable_periodic(struct oxu_hcd *oxu) 2273{ 2274 u32 cmd; 2275 int status; 2276 2277 /* did clearing PSE did take effect yet? 2278 * takes effect only at frame boundaries... 2279 */ 2280 status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125); 2281 if (status != 0) { 2282 oxu_to_hcd(oxu)->state = HC_STATE_HALT; 2283 usb_hc_died(oxu_to_hcd(oxu)); 2284 return status; 2285 } 2286 2287 cmd = readl(&oxu->regs->command) | CMD_PSE; 2288 writel(cmd, &oxu->regs->command); 2289 /* posted write ... PSS happens later */ 2290 oxu_to_hcd(oxu)->state = HC_STATE_RUNNING; 2291 2292 /* make sure ehci_work scans these */ 2293 oxu->next_uframe = readl(&oxu->regs->frame_index) 2294 % (oxu->periodic_size << 3); 2295 return 0; 2296} 2297 2298static int disable_periodic(struct oxu_hcd *oxu) 2299{ 2300 u32 cmd; 2301 int status; 2302 2303 /* did setting PSE not take effect yet? 2304 * takes effect only at frame boundaries... 2305 */ 2306 status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125); 2307 if (status != 0) { 2308 oxu_to_hcd(oxu)->state = HC_STATE_HALT; 2309 usb_hc_died(oxu_to_hcd(oxu)); 2310 return status; 2311 } 2312 2313 cmd = readl(&oxu->regs->command) & ~CMD_PSE; 2314 writel(cmd, &oxu->regs->command); 2315 /* posted write ... */ 2316 2317 oxu->next_uframe = -1; 2318 return 0; 2319} 2320 2321/* periodic schedule slots have iso tds (normal or split) first, then a 2322 * sparse tree for active interrupt transfers. 2323 * 2324 * this just links in a qh; caller guarantees uframe masks are set right. 2325 * no FSTN support (yet; oxu 0.96+) 2326 */ 2327static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh) 2328{ 2329 unsigned i; 2330 unsigned period = qh->period; 2331 2332 dev_dbg(&qh->dev->dev, 2333 "link qh%d-%04x/%p start %d [%d/%d us]\n", 2334 period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK), 2335 qh, qh->start, qh->usecs, qh->c_usecs); 2336 2337 /* high bandwidth, or otherwise every microframe */ 2338 if (period == 0) 2339 period = 1; 2340 2341 for (i = qh->start; i < oxu->periodic_size; i += period) { 2342 union ehci_shadow *prev = &oxu->pshadow[i]; 2343 __le32 *hw_p = &oxu->periodic[i]; 2344 union ehci_shadow here = *prev; 2345 __le32 type = 0; 2346 2347 /* skip the iso nodes at list head */ 2348 while (here.ptr) { 2349 type = Q_NEXT_TYPE(*hw_p); 2350 if (type == Q_TYPE_QH) 2351 break; 2352 prev = periodic_next_shadow(prev, type); 2353 hw_p = &here.qh->hw_next; 2354 here = *prev; 2355 } 2356 2357 /* sorting each branch by period (slow-->fast) 2358 * enables sharing interior tree nodes 2359 */ 2360 while (here.ptr && qh != here.qh) { 2361 if (qh->period > here.qh->period) 2362 break; 2363 prev = &here.qh->qh_next; 2364 hw_p = &here.qh->hw_next; 2365 here = *prev; 2366 } 2367 /* link in this qh, unless some earlier pass did that */ 2368 if (qh != here.qh) { 2369 qh->qh_next = here; 2370 if (here.qh) 2371 qh->hw_next = *hw_p; 2372 wmb(); 2373 prev->qh = qh; 2374 *hw_p = QH_NEXT(qh->qh_dma); 2375 } 2376 } 2377 qh->qh_state = QH_STATE_LINKED; 2378 qh_get(qh); 2379 2380 /* update per-qh bandwidth for usbfs */ 2381 oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period 2382 ? ((qh->usecs + qh->c_usecs) / qh->period) 2383 : (qh->usecs * 8); 2384 2385 /* maybe enable periodic schedule processing */ 2386 if (!oxu->periodic_sched++) 2387 return enable_periodic(oxu); 2388 2389 return 0; 2390} 2391 2392static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh) 2393{ 2394 unsigned i; 2395 unsigned period; 2396 2397 /* FIXME: 2398 * IF this isn't high speed 2399 * and this qh is active in the current uframe 2400 * (and overlay token SplitXstate is false?) 2401 * THEN 2402 * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore"); 2403 */ 2404 2405 /* high bandwidth, or otherwise part of every microframe */ 2406 period = qh->period; 2407 if (period == 0) 2408 period = 1; 2409 2410 for (i = qh->start; i < oxu->periodic_size; i += period) 2411 periodic_unlink(oxu, i, qh); 2412 2413 /* update per-qh bandwidth for usbfs */ 2414 oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period 2415 ? ((qh->usecs + qh->c_usecs) / qh->period) 2416 : (qh->usecs * 8); 2417 2418 dev_dbg(&qh->dev->dev, 2419 "unlink qh%d-%04x/%p start %d [%d/%d us]\n", 2420 qh->period, 2421 le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK), 2422 qh, qh->start, qh->usecs, qh->c_usecs); 2423 2424 /* qh->qh_next still "live" to HC */ 2425 qh->qh_state = QH_STATE_UNLINK; 2426 qh->qh_next.ptr = NULL; 2427 qh_put(qh); 2428 2429 /* maybe turn off periodic schedule */ 2430 oxu->periodic_sched--; 2431 if (!oxu->periodic_sched) 2432 (void) disable_periodic(oxu); 2433} 2434 2435static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh) 2436{ 2437 unsigned wait; 2438 2439 qh_unlink_periodic(oxu, qh); 2440 2441 /* simple/paranoid: always delay, expecting the HC needs to read 2442 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and 2443 * expect hub_wq to clean up after any CSPLITs we won't issue. 2444 * active high speed queues may need bigger delays... 2445 */ 2446 if (list_empty(&qh->qtd_list) 2447 || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0) 2448 wait = 2; 2449 else 2450 wait = 55; /* worst case: 3 * 1024 */ 2451 2452 udelay(wait); 2453 qh->qh_state = QH_STATE_IDLE; 2454 qh->hw_next = EHCI_LIST_END; 2455 wmb(); 2456} 2457 2458static int check_period(struct oxu_hcd *oxu, 2459 unsigned frame, unsigned uframe, 2460 unsigned period, unsigned usecs) 2461{ 2462 int claimed; 2463 2464 /* complete split running into next frame? 2465 * given FSTN support, we could sometimes check... 2466 */ 2467 if (uframe >= 8) 2468 return 0; 2469 2470 /* 2471 * 80% periodic == 100 usec/uframe available 2472 * convert "usecs we need" to "max already claimed" 2473 */ 2474 usecs = 100 - usecs; 2475 2476 /* we "know" 2 and 4 uframe intervals were rejected; so 2477 * for period 0, check _every_ microframe in the schedule. 2478 */ 2479 if (unlikely(period == 0)) { 2480 do { 2481 for (uframe = 0; uframe < 7; uframe++) { 2482 claimed = periodic_usecs(oxu, frame, uframe); 2483 if (claimed > usecs) 2484 return 0; 2485 } 2486 } while ((frame += 1) < oxu->periodic_size); 2487 2488 /* just check the specified uframe, at that period */ 2489 } else { 2490 do { 2491 claimed = periodic_usecs(oxu, frame, uframe); 2492 if (claimed > usecs) 2493 return 0; 2494 } while ((frame += period) < oxu->periodic_size); 2495 } 2496 2497 return 1; 2498} 2499 2500static int check_intr_schedule(struct oxu_hcd *oxu, 2501 unsigned frame, unsigned uframe, 2502 const struct ehci_qh *qh, __le32 *c_maskp) 2503{ 2504 int retval = -ENOSPC; 2505 2506 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */ 2507 goto done; 2508 2509 if (!check_period(oxu, frame, uframe, qh->period, qh->usecs)) 2510 goto done; 2511 if (!qh->c_usecs) { 2512 retval = 0; 2513 *c_maskp = 0; 2514 goto done; 2515 } 2516 2517done: 2518 return retval; 2519} 2520 2521/* "first fit" scheduling policy used the first time through, 2522 * or when the previous schedule slot can't be re-used. 2523 */ 2524static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh) 2525{ 2526 int status; 2527 unsigned uframe; 2528 __le32 c_mask; 2529 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */ 2530 2531 qh_refresh(oxu, qh); 2532 qh->hw_next = EHCI_LIST_END; 2533 frame = qh->start; 2534 2535 /* reuse the previous schedule slots, if we can */ 2536 if (frame < qh->period) { 2537 uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK); 2538 status = check_intr_schedule(oxu, frame, --uframe, 2539 qh, &c_mask); 2540 } else { 2541 uframe = 0; 2542 c_mask = 0; 2543 status = -ENOSPC; 2544 } 2545 2546 /* else scan the schedule to find a group of slots such that all 2547 * uframes have enough periodic bandwidth available. 2548 */ 2549 if (status) { 2550 /* "normal" case, uframing flexible except with splits */ 2551 if (qh->period) { 2552 frame = qh->period - 1; 2553 do { 2554 for (uframe = 0; uframe < 8; uframe++) { 2555 status = check_intr_schedule(oxu, 2556 frame, uframe, qh, 2557 &c_mask); 2558 if (status == 0) 2559 break; 2560 } 2561 } while (status && frame--); 2562 2563 /* qh->period == 0 means every uframe */ 2564 } else { 2565 frame = 0; 2566 status = check_intr_schedule(oxu, 0, 0, qh, &c_mask); 2567 } 2568 if (status) 2569 goto done; 2570 qh->start = frame; 2571 2572 /* reset S-frame and (maybe) C-frame masks */ 2573 qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK)); 2574 qh->hw_info2 |= qh->period 2575 ? cpu_to_le32(1 << uframe) 2576 : cpu_to_le32(QH_SMASK); 2577 qh->hw_info2 |= c_mask; 2578 } else 2579 oxu_dbg(oxu, "reused qh %p schedule\n", qh); 2580 2581 /* stuff into the periodic schedule */ 2582 status = qh_link_periodic(oxu, qh); 2583done: 2584 return status; 2585} 2586 2587static int intr_submit(struct oxu_hcd *oxu, struct urb *urb, 2588 struct list_head *qtd_list, gfp_t mem_flags) 2589{ 2590 unsigned epnum; 2591 unsigned long flags; 2592 struct ehci_qh *qh; 2593 int status = 0; 2594 struct list_head empty; 2595 2596 /* get endpoint and transfer/schedule data */ 2597 epnum = urb->ep->desc.bEndpointAddress; 2598 2599 spin_lock_irqsave(&oxu->lock, flags); 2600 2601 if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) { 2602 status = -ESHUTDOWN; 2603 goto done; 2604 } 2605 2606 /* get qh and force any scheduling errors */ 2607 INIT_LIST_HEAD(&empty); 2608 qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv); 2609 if (qh == NULL) { 2610 status = -ENOMEM; 2611 goto done; 2612 } 2613 if (qh->qh_state == QH_STATE_IDLE) { 2614 status = qh_schedule(oxu, qh); 2615 if (status != 0) 2616 goto done; 2617 } 2618 2619 /* then queue the urb's tds to the qh */ 2620 qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv); 2621 BUG_ON(qh == NULL); 2622 2623 /* ... update usbfs periodic stats */ 2624 oxu_to_hcd(oxu)->self.bandwidth_int_reqs++; 2625 2626done: 2627 spin_unlock_irqrestore(&oxu->lock, flags); 2628 if (status) 2629 qtd_list_free(oxu, urb, qtd_list); 2630 2631 return status; 2632} 2633 2634static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb, 2635 gfp_t mem_flags) 2636{ 2637 oxu_dbg(oxu, "iso support is missing!\n"); 2638 return -ENOSYS; 2639} 2640 2641static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb, 2642 gfp_t mem_flags) 2643{ 2644 oxu_dbg(oxu, "split iso support is missing!\n"); 2645 return -ENOSYS; 2646} 2647 2648static void scan_periodic(struct oxu_hcd *oxu) 2649{ 2650 unsigned frame, clock, now_uframe, mod; 2651 unsigned modified; 2652 2653 mod = oxu->periodic_size << 3; 2654 2655 /* 2656 * When running, scan from last scan point up to "now" 2657 * else clean up by scanning everything that's left. 2658 * Touches as few pages as possible: cache-friendly. 2659 */ 2660 now_uframe = oxu->next_uframe; 2661 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) 2662 clock = readl(&oxu->regs->frame_index); 2663 else 2664 clock = now_uframe + mod - 1; 2665 clock %= mod; 2666 2667 for (;;) { 2668 union ehci_shadow q, *q_p; 2669 __le32 type, *hw_p; 2670 2671 /* don't scan past the live uframe */ 2672 frame = now_uframe >> 3; 2673 if (frame != (clock >> 3)) { 2674 /* safe to scan the whole frame at once */ 2675 now_uframe |= 0x07; 2676 } 2677 2678restart: 2679 /* scan each element in frame's queue for completions */ 2680 q_p = &oxu->pshadow[frame]; 2681 hw_p = &oxu->periodic[frame]; 2682 q.ptr = q_p->ptr; 2683 type = Q_NEXT_TYPE(*hw_p); 2684 modified = 0; 2685 2686 while (q.ptr != NULL) { 2687 union ehci_shadow temp; 2688 2689 switch (type) { 2690 case Q_TYPE_QH: 2691 /* handle any completions */ 2692 temp.qh = qh_get(q.qh); 2693 type = Q_NEXT_TYPE(q.qh->hw_next); 2694 q = q.qh->qh_next; 2695 modified = qh_completions(oxu, temp.qh); 2696 if (unlikely(list_empty(&temp.qh->qtd_list))) 2697 intr_deschedule(oxu, temp.qh); 2698 qh_put(temp.qh); 2699 break; 2700 default: 2701 oxu_dbg(oxu, "corrupt type %d frame %d shadow %p\n", 2702 type, frame, q.ptr); 2703 q.ptr = NULL; 2704 } 2705 2706 /* assume completion callbacks modify the queue */ 2707 if (unlikely(modified)) 2708 goto restart; 2709 } 2710 2711 /* Stop when we catch up to the HC */ 2712 2713 /* FIXME: this assumes we won't get lapped when 2714 * latencies climb; that should be rare, but... 2715 * detect it, and just go all the way around. 2716 * FLR might help detect this case, so long as latencies 2717 * don't exceed periodic_size msec (default 1.024 sec). 2718 */ 2719 2720 /* FIXME: likewise assumes HC doesn't halt mid-scan */ 2721 2722 if (now_uframe == clock) { 2723 unsigned now; 2724 2725 if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) 2726 break; 2727 oxu->next_uframe = now_uframe; 2728 now = readl(&oxu->regs->frame_index) % mod; 2729 if (now_uframe == now) 2730 break; 2731 2732 /* rescan the rest of this frame, then ... */ 2733 clock = now; 2734 } else { 2735 now_uframe++; 2736 now_uframe %= mod; 2737 } 2738 } 2739} 2740 2741/* On some systems, leaving remote wakeup enabled prevents system shutdown. 2742 * The firmware seems to think that powering off is a wakeup event! 2743 * This routine turns off remote wakeup and everything else, on all ports. 2744 */ 2745static void ehci_turn_off_all_ports(struct oxu_hcd *oxu) 2746{ 2747 int port = HCS_N_PORTS(oxu->hcs_params); 2748 2749 while (port--) 2750 writel(PORT_RWC_BITS, &oxu->regs->port_status[port]); 2751} 2752 2753static void ehci_port_power(struct oxu_hcd *oxu, int is_on) 2754{ 2755 unsigned port; 2756 2757 if (!HCS_PPC(oxu->hcs_params)) 2758 return; 2759 2760 oxu_dbg(oxu, "...power%s ports...\n", str_up_down(is_on)); 2761 for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; ) { 2762 if (is_on) 2763 oxu_hub_control(oxu_to_hcd(oxu), SetPortFeature, 2764 USB_PORT_FEAT_POWER, port--, NULL, 0); 2765 else 2766 oxu_hub_control(oxu_to_hcd(oxu), ClearPortFeature, 2767 USB_PORT_FEAT_POWER, port--, NULL, 0); 2768 } 2769 2770 msleep(20); 2771} 2772 2773/* Called from some interrupts, timers, and so on. 2774 * It calls driver completion functions, after dropping oxu->lock. 2775 */ 2776static void ehci_work(struct oxu_hcd *oxu) 2777{ 2778 timer_action_done(oxu, TIMER_IO_WATCHDOG); 2779 if (oxu->reclaim_ready) 2780 end_unlink_async(oxu); 2781 2782 /* another CPU may drop oxu->lock during a schedule scan while 2783 * it reports urb completions. this flag guards against bogus 2784 * attempts at re-entrant schedule scanning. 2785 */ 2786 if (oxu->scanning) 2787 return; 2788 oxu->scanning = 1; 2789 scan_async(oxu); 2790 if (oxu->next_uframe != -1) 2791 scan_periodic(oxu); 2792 oxu->scanning = 0; 2793 2794 /* the IO watchdog guards against hardware or driver bugs that 2795 * misplace IRQs, and should let us run completely without IRQs. 2796 * such lossage has been observed on both VT6202 and VT8235. 2797 */ 2798 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && 2799 (oxu->async->qh_next.ptr != NULL || 2800 oxu->periodic_sched != 0)) 2801 timer_action(oxu, TIMER_IO_WATCHDOG); 2802} 2803 2804static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh) 2805{ 2806 /* if we need to use IAA and it's busy, defer */ 2807 if (qh->qh_state == QH_STATE_LINKED 2808 && oxu->reclaim 2809 && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) { 2810 struct ehci_qh *last; 2811 2812 for (last = oxu->reclaim; 2813 last->reclaim; 2814 last = last->reclaim) 2815 continue; 2816 qh->qh_state = QH_STATE_UNLINK_WAIT; 2817 last->reclaim = qh; 2818 2819 /* bypass IAA if the hc can't care */ 2820 } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim) 2821 end_unlink_async(oxu); 2822 2823 /* something else might have unlinked the qh by now */ 2824 if (qh->qh_state == QH_STATE_LINKED) 2825 start_unlink_async(oxu, qh); 2826} 2827 2828/* 2829 * USB host controller methods 2830 */ 2831 2832static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd) 2833{ 2834 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 2835 u32 status, pcd_status = 0; 2836 int bh; 2837 2838 spin_lock(&oxu->lock); 2839 2840 status = readl(&oxu->regs->status); 2841 2842 /* e.g. cardbus physical eject */ 2843 if (status == ~(u32) 0) { 2844 oxu_dbg(oxu, "device removed\n"); 2845 goto dead; 2846 } 2847 2848 /* Shared IRQ? */ 2849 status &= INTR_MASK; 2850 if (!status || unlikely(hcd->state == HC_STATE_HALT)) { 2851 spin_unlock(&oxu->lock); 2852 return IRQ_NONE; 2853 } 2854 2855 /* clear (just) interrupts */ 2856 writel(status, &oxu->regs->status); 2857 readl(&oxu->regs->command); /* unblock posted write */ 2858 bh = 0; 2859 2860#ifdef OXU_VERBOSE_DEBUG 2861 /* unrequested/ignored: Frame List Rollover */ 2862 dbg_status(oxu, "irq", status); 2863#endif 2864 2865 /* INT, ERR, and IAA interrupt rates can be throttled */ 2866 2867 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 2868 if (likely((status & (STS_INT|STS_ERR)) != 0)) 2869 bh = 1; 2870 2871 /* complete the unlinking of some qh [4.15.2.3] */ 2872 if (status & STS_IAA) { 2873 oxu->reclaim_ready = 1; 2874 bh = 1; 2875 } 2876 2877 /* remote wakeup [4.3.1] */ 2878 if (status & STS_PCD) { 2879 unsigned i = HCS_N_PORTS(oxu->hcs_params); 2880 pcd_status = status; 2881 2882 /* resume root hub? */ 2883 if (!(readl(&oxu->regs->command) & CMD_RUN)) 2884 usb_hcd_resume_root_hub(hcd); 2885 2886 while (i--) { 2887 int pstatus = readl(&oxu->regs->port_status[i]); 2888 2889 if (pstatus & PORT_OWNER) 2890 continue; 2891 if (!(pstatus & PORT_RESUME) 2892 || oxu->reset_done[i] != 0) 2893 continue; 2894 2895 /* start USB_RESUME_TIMEOUT resume signaling from this 2896 * port, and make hub_wq collect PORT_STAT_C_SUSPEND to 2897 * stop that signaling. 2898 */ 2899 oxu->reset_done[i] = jiffies + 2900 msecs_to_jiffies(USB_RESUME_TIMEOUT); 2901 oxu_dbg(oxu, "port %d remote wakeup\n", i + 1); 2902 mod_timer(&hcd->rh_timer, oxu->reset_done[i]); 2903 } 2904 } 2905 2906 /* PCI errors [4.15.2.4] */ 2907 if (unlikely((status & STS_FATAL) != 0)) { 2908 /* bogus "fatal" IRQs appear on some chips... why? */ 2909 status = readl(&oxu->regs->status); 2910 dbg_cmd(oxu, "fatal", readl(&oxu->regs->command)); 2911 dbg_status(oxu, "fatal", status); 2912 if (status & STS_HALT) { 2913 oxu_err(oxu, "fatal error\n"); 2914dead: 2915 ehci_reset(oxu); 2916 writel(0, &oxu->regs->configured_flag); 2917 usb_hc_died(hcd); 2918 /* generic layer kills/unlinks all urbs, then 2919 * uses oxu_stop to clean up the rest 2920 */ 2921 bh = 1; 2922 } 2923 } 2924 2925 if (bh) 2926 ehci_work(oxu); 2927 spin_unlock(&oxu->lock); 2928 if (pcd_status & STS_PCD) 2929 usb_hcd_poll_rh_status(hcd); 2930 return IRQ_HANDLED; 2931} 2932 2933static irqreturn_t oxu_irq(struct usb_hcd *hcd) 2934{ 2935 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 2936 int ret = IRQ_HANDLED; 2937 2938 u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS); 2939 u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET); 2940 2941 /* Disable all interrupt */ 2942 oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable); 2943 2944 if ((oxu->is_otg && (status & OXU_USBOTGI)) || 2945 (!oxu->is_otg && (status & OXU_USBSPHI))) 2946 oxu210_hcd_irq(hcd); 2947 else 2948 ret = IRQ_NONE; 2949 2950 /* Enable all interrupt back */ 2951 oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable); 2952 2953 return ret; 2954} 2955 2956static void oxu_watchdog(struct timer_list *t) 2957{ 2958 struct oxu_hcd *oxu = timer_container_of(oxu, t, watchdog); 2959 unsigned long flags; 2960 2961 spin_lock_irqsave(&oxu->lock, flags); 2962 2963 /* lost IAA irqs wedge things badly; seen with a vt8235 */ 2964 if (oxu->reclaim) { 2965 u32 status = readl(&oxu->regs->status); 2966 if (status & STS_IAA) { 2967 oxu_vdbg(oxu, "lost IAA\n"); 2968 writel(STS_IAA, &oxu->regs->status); 2969 oxu->reclaim_ready = 1; 2970 } 2971 } 2972 2973 /* stop async processing after it's idled a bit */ 2974 if (test_bit(TIMER_ASYNC_OFF, &oxu->actions)) 2975 start_unlink_async(oxu, oxu->async); 2976 2977 /* oxu could run by timer, without IRQs ... */ 2978 ehci_work(oxu); 2979 2980 spin_unlock_irqrestore(&oxu->lock, flags); 2981} 2982 2983/* One-time init, only for memory state. 2984 */ 2985static int oxu_hcd_init(struct usb_hcd *hcd) 2986{ 2987 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 2988 u32 temp; 2989 int retval; 2990 u32 hcc_params; 2991 2992 spin_lock_init(&oxu->lock); 2993 2994 timer_setup(&oxu->watchdog, oxu_watchdog, 0); 2995 2996 /* 2997 * hw default: 1K periodic list heads, one per frame. 2998 * periodic_size can shrink by USBCMD update if hcc_params allows. 2999 */ 3000 oxu->periodic_size = DEFAULT_I_TDPS; 3001 retval = ehci_mem_init(oxu, GFP_KERNEL); 3002 if (retval < 0) 3003 return retval; 3004 3005 /* controllers may cache some of the periodic schedule ... */ 3006 hcc_params = readl(&oxu->caps->hcc_params); 3007 if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */ 3008 oxu->i_thresh = 8; 3009 else /* N microframes cached */ 3010 oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 3011 3012 oxu->reclaim = NULL; 3013 oxu->reclaim_ready = 0; 3014 oxu->next_uframe = -1; 3015 3016 /* 3017 * dedicate a qh for the async ring head, since we couldn't unlink 3018 * a 'real' qh without stopping the async schedule [4.8]. use it 3019 * as the 'reclamation list head' too. 3020 * its dummy is used in hw_alt_next of many tds, to prevent the qh 3021 * from automatically advancing to the next td after short reads. 3022 */ 3023 oxu->async->qh_next.qh = NULL; 3024 oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma); 3025 oxu->async->hw_info1 = cpu_to_le32(QH_HEAD); 3026 oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT); 3027 oxu->async->hw_qtd_next = EHCI_LIST_END; 3028 oxu->async->qh_state = QH_STATE_LINKED; 3029 oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma); 3030 3031 /* clear interrupt enables, set irq latency */ 3032 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 3033 log2_irq_thresh = 0; 3034 temp = 1 << (16 + log2_irq_thresh); 3035 if (HCC_CANPARK(hcc_params)) { 3036 /* HW default park == 3, on hardware that supports it (like 3037 * NVidia and ALI silicon), maximizes throughput on the async 3038 * schedule by avoiding QH fetches between transfers. 3039 * 3040 * With fast usb storage devices and NForce2, "park" seems to 3041 * make problems: throughput reduction (!), data errors... 3042 */ 3043 if (park) { 3044 park = min_t(unsigned int, park, 3); 3045 temp |= CMD_PARK; 3046 temp |= park << 8; 3047 } 3048 oxu_dbg(oxu, "park %d\n", park); 3049 } 3050 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 3051 /* periodic schedule size can be smaller than default */ 3052 temp &= ~(3 << 2); 3053 temp |= (EHCI_TUNE_FLS << 2); 3054 } 3055 oxu->command = temp; 3056 3057 return 0; 3058} 3059 3060/* Called during probe() after chip reset completes. 3061 */ 3062static int oxu_reset(struct usb_hcd *hcd) 3063{ 3064 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3065 3066 spin_lock_init(&oxu->mem_lock); 3067 INIT_LIST_HEAD(&oxu->urb_list); 3068 oxu->urb_len = 0; 3069 3070 if (oxu->is_otg) { 3071 oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET; 3072 oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \ 3073 HC_LENGTH(readl(&oxu->caps->hc_capbase)); 3074 3075 oxu->mem = hcd->regs + OXU_SPH_MEM; 3076 } else { 3077 oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET; 3078 oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \ 3079 HC_LENGTH(readl(&oxu->caps->hc_capbase)); 3080 3081 oxu->mem = hcd->regs + OXU_OTG_MEM; 3082 } 3083 3084 oxu->hcs_params = readl(&oxu->caps->hcs_params); 3085 oxu->sbrn = 0x20; 3086 3087 return oxu_hcd_init(hcd); 3088} 3089 3090static int oxu_run(struct usb_hcd *hcd) 3091{ 3092 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3093 int retval; 3094 u32 temp, hcc_params; 3095 3096 hcd->uses_new_polling = 1; 3097 3098 /* EHCI spec section 4.1 */ 3099 retval = ehci_reset(oxu); 3100 if (retval != 0) { 3101 ehci_mem_cleanup(oxu); 3102 return retval; 3103 } 3104 writel(oxu->periodic_dma, &oxu->regs->frame_list); 3105 writel((u32) oxu->async->qh_dma, &oxu->regs->async_next); 3106 3107 /* hcc_params controls whether oxu->regs->segment must (!!!) 3108 * be used; it constrains QH/ITD/SITD and QTD locations. 3109 * dma_pool consistent memory always uses segment zero. 3110 * streaming mappings for I/O buffers, like dma_map_single(), 3111 * can return segments above 4GB, if the device allows. 3112 * 3113 * NOTE: the dma mask is visible through dev->dma_mask, so 3114 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 3115 * Scsi_Host.highmem_io, and so forth. It's readonly to all 3116 * host side drivers though. 3117 */ 3118 hcc_params = readl(&oxu->caps->hcc_params); 3119 if (HCC_64BIT_ADDR(hcc_params)) 3120 writel(0, &oxu->regs->segment); 3121 3122 oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | 3123 CMD_ASE | CMD_RESET); 3124 oxu->command |= CMD_RUN; 3125 writel(oxu->command, &oxu->regs->command); 3126 dbg_cmd(oxu, "init", oxu->command); 3127 3128 /* 3129 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 3130 * are explicitly handed to companion controller(s), so no TT is 3131 * involved with the root hub. (Except where one is integrated, 3132 * and there's no companion controller unless maybe for USB OTG.) 3133 */ 3134 hcd->state = HC_STATE_RUNNING; 3135 writel(FLAG_CF, &oxu->regs->configured_flag); 3136 readl(&oxu->regs->command); /* unblock posted writes */ 3137 3138 temp = HC_VERSION(readl(&oxu->caps->hc_capbase)); 3139 oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n", 3140 ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f), 3141 temp >> 8, temp & 0xff, DRIVER_VERSION, 3142 ignore_oc ? ", overcurrent ignored" : ""); 3143 3144 writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */ 3145 3146 return 0; 3147} 3148 3149static void oxu_stop(struct usb_hcd *hcd) 3150{ 3151 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3152 3153 /* Turn off port power on all root hub ports. */ 3154 ehci_port_power(oxu, 0); 3155 3156 /* no more interrupts ... */ 3157 timer_delete_sync(&oxu->watchdog); 3158 3159 spin_lock_irq(&oxu->lock); 3160 if (HC_IS_RUNNING(hcd->state)) 3161 ehci_quiesce(oxu); 3162 3163 ehci_reset(oxu); 3164 writel(0, &oxu->regs->intr_enable); 3165 spin_unlock_irq(&oxu->lock); 3166 3167 /* let companion controllers work when we aren't */ 3168 writel(0, &oxu->regs->configured_flag); 3169 3170 /* root hub is shut down separately (first, when possible) */ 3171 spin_lock_irq(&oxu->lock); 3172 if (oxu->async) 3173 ehci_work(oxu); 3174 spin_unlock_irq(&oxu->lock); 3175 ehci_mem_cleanup(oxu); 3176 3177 dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status)); 3178} 3179 3180/* Kick in for silicon on any bus (not just pci, etc). 3181 * This forcibly disables dma and IRQs, helping kexec and other cases 3182 * where the next system software may expect clean state. 3183 */ 3184static void oxu_shutdown(struct usb_hcd *hcd) 3185{ 3186 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3187 3188 (void) ehci_halt(oxu); 3189 ehci_turn_off_all_ports(oxu); 3190 3191 /* make BIOS/etc use companion controller during reboot */ 3192 writel(0, &oxu->regs->configured_flag); 3193 3194 /* unblock posted writes */ 3195 readl(&oxu->regs->configured_flag); 3196} 3197 3198/* Non-error returns are a promise to giveback() the urb later 3199 * we drop ownership so next owner (or urb unlink) can get it 3200 * 3201 * urb + dev is in hcd.self.controller.urb_list 3202 * we're queueing TDs onto software and hardware lists 3203 * 3204 * hcd-specific init for hcpriv hasn't been done yet 3205 * 3206 * NOTE: control, bulk, and interrupt share the same code to append TDs 3207 * to a (possibly active) QH, and the same QH scanning code. 3208 */ 3209static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 3210 gfp_t mem_flags) 3211{ 3212 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3213 struct list_head qtd_list; 3214 3215 INIT_LIST_HEAD(&qtd_list); 3216 3217 switch (usb_pipetype(urb->pipe)) { 3218 case PIPE_CONTROL: 3219 case PIPE_BULK: 3220 default: 3221 if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags)) 3222 return -ENOMEM; 3223 return submit_async(oxu, urb, &qtd_list, mem_flags); 3224 3225 case PIPE_INTERRUPT: 3226 if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags)) 3227 return -ENOMEM; 3228 return intr_submit(oxu, urb, &qtd_list, mem_flags); 3229 3230 case PIPE_ISOCHRONOUS: 3231 if (urb->dev->speed == USB_SPEED_HIGH) 3232 return itd_submit(oxu, urb, mem_flags); 3233 else 3234 return sitd_submit(oxu, urb, mem_flags); 3235 } 3236} 3237 3238/* This function is responsible for breaking URBs with big data size 3239 * into smaller size and processing small urbs in sequence. 3240 */ 3241static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 3242 gfp_t mem_flags) 3243{ 3244 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3245 int num, rem; 3246 void *transfer_buffer; 3247 struct urb *murb; 3248 int i, ret; 3249 3250 /* If not bulk pipe just enqueue the URB */ 3251 if (!usb_pipebulk(urb->pipe)) 3252 return __oxu_urb_enqueue(hcd, urb, mem_flags); 3253 3254 /* Otherwise we should verify the USB transfer buffer size! */ 3255 transfer_buffer = urb->transfer_buffer; 3256 3257 num = urb->transfer_buffer_length / 4096; 3258 rem = urb->transfer_buffer_length % 4096; 3259 if (rem != 0) 3260 num++; 3261 3262 /* If URB is smaller than 4096 bytes just enqueue it! */ 3263 if (num == 1) 3264 return __oxu_urb_enqueue(hcd, urb, mem_flags); 3265 3266 /* Ok, we have more job to do! :) */ 3267 3268 for (i = 0; i < num - 1; i++) { 3269 /* Get free micro URB poll till a free urb is received */ 3270 3271 do { 3272 murb = (struct urb *) oxu_murb_alloc(oxu); 3273 if (!murb) 3274 schedule(); 3275 } while (!murb); 3276 3277 /* Coping the urb */ 3278 memcpy(murb, urb, sizeof(struct urb)); 3279 3280 murb->transfer_buffer_length = 4096; 3281 murb->transfer_buffer = transfer_buffer + i * 4096; 3282 3283 /* Null pointer for the encodes that this is a micro urb */ 3284 murb->complete = NULL; 3285 3286 ((struct oxu_murb *) murb)->main = urb; 3287 ((struct oxu_murb *) murb)->last = 0; 3288 3289 /* This loop is to guarantee urb to be processed when there's 3290 * not enough resources at a particular time by retrying. 3291 */ 3292 do { 3293 ret = __oxu_urb_enqueue(hcd, murb, mem_flags); 3294 if (ret) 3295 schedule(); 3296 } while (ret); 3297 } 3298 3299 /* Last urb requires special handling */ 3300 3301 /* Get free micro URB poll till a free urb is received */ 3302 do { 3303 murb = (struct urb *) oxu_murb_alloc(oxu); 3304 if (!murb) 3305 schedule(); 3306 } while (!murb); 3307 3308 /* Coping the urb */ 3309 memcpy(murb, urb, sizeof(struct urb)); 3310 3311 murb->transfer_buffer_length = rem > 0 ? rem : 4096; 3312 murb->transfer_buffer = transfer_buffer + (num - 1) * 4096; 3313 3314 /* Null pointer for the encodes that this is a micro urb */ 3315 murb->complete = NULL; 3316 3317 ((struct oxu_murb *) murb)->main = urb; 3318 ((struct oxu_murb *) murb)->last = 1; 3319 3320 do { 3321 ret = __oxu_urb_enqueue(hcd, murb, mem_flags); 3322 if (ret) 3323 schedule(); 3324 } while (ret); 3325 3326 return ret; 3327} 3328 3329/* Remove from hardware lists. 3330 * Completions normally happen asynchronously 3331 */ 3332static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 3333{ 3334 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3335 struct ehci_qh *qh; 3336 unsigned long flags; 3337 3338 spin_lock_irqsave(&oxu->lock, flags); 3339 switch (usb_pipetype(urb->pipe)) { 3340 case PIPE_CONTROL: 3341 case PIPE_BULK: 3342 default: 3343 qh = (struct ehci_qh *) urb->hcpriv; 3344 if (!qh) 3345 break; 3346 unlink_async(oxu, qh); 3347 break; 3348 3349 case PIPE_INTERRUPT: 3350 qh = (struct ehci_qh *) urb->hcpriv; 3351 if (!qh) 3352 break; 3353 switch (qh->qh_state) { 3354 case QH_STATE_LINKED: 3355 intr_deschedule(oxu, qh); 3356 fallthrough; 3357 case QH_STATE_IDLE: 3358 qh_completions(oxu, qh); 3359 break; 3360 default: 3361 oxu_dbg(oxu, "bogus qh %p state %d\n", 3362 qh, qh->qh_state); 3363 goto done; 3364 } 3365 3366 /* reschedule QH iff another request is queued */ 3367 if (!list_empty(&qh->qtd_list) 3368 && HC_IS_RUNNING(hcd->state)) { 3369 int status; 3370 3371 status = qh_schedule(oxu, qh); 3372 spin_unlock_irqrestore(&oxu->lock, flags); 3373 3374 if (status != 0) { 3375 /* shouldn't happen often, but ... 3376 * FIXME kill those tds' urbs 3377 */ 3378 dev_err(hcd->self.controller, 3379 "can't reschedule qh %p, err %d\n", qh, 3380 status); 3381 } 3382 return status; 3383 } 3384 break; 3385 } 3386done: 3387 spin_unlock_irqrestore(&oxu->lock, flags); 3388 return 0; 3389} 3390 3391/* Bulk qh holds the data toggle */ 3392static void oxu_endpoint_disable(struct usb_hcd *hcd, 3393 struct usb_host_endpoint *ep) 3394{ 3395 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3396 unsigned long flags; 3397 struct ehci_qh *qh, *tmp; 3398 3399 /* ASSERT: any requests/urbs are being unlinked */ 3400 /* ASSERT: nobody can be submitting urbs for this any more */ 3401 3402rescan: 3403 spin_lock_irqsave(&oxu->lock, flags); 3404 qh = ep->hcpriv; 3405 if (!qh) 3406 goto done; 3407 3408 /* endpoints can be iso streams. for now, we don't 3409 * accelerate iso completions ... so spin a while. 3410 */ 3411 if (qh->hw_info1 == 0) { 3412 oxu_vdbg(oxu, "iso delay\n"); 3413 goto idle_timeout; 3414 } 3415 3416 if (!HC_IS_RUNNING(hcd->state)) 3417 qh->qh_state = QH_STATE_IDLE; 3418 switch (qh->qh_state) { 3419 case QH_STATE_LINKED: 3420 for (tmp = oxu->async->qh_next.qh; 3421 tmp && tmp != qh; 3422 tmp = tmp->qh_next.qh) 3423 continue; 3424 /* periodic qh self-unlinks on empty */ 3425 if (!tmp) 3426 goto nogood; 3427 unlink_async(oxu, qh); 3428 fallthrough; 3429 case QH_STATE_UNLINK: /* wait for hw to finish? */ 3430idle_timeout: 3431 spin_unlock_irqrestore(&oxu->lock, flags); 3432 schedule_timeout_uninterruptible(1); 3433 goto rescan; 3434 case QH_STATE_IDLE: /* fully unlinked */ 3435 if (list_empty(&qh->qtd_list)) { 3436 qh_put(qh); 3437 break; 3438 } 3439 fallthrough; 3440 default: 3441nogood: 3442 /* caller was supposed to have unlinked any requests; 3443 * that's not our job. just leak this memory. 3444 */ 3445 oxu_err(oxu, "qh %p (#%02x) state %d%s\n", 3446 qh, ep->desc.bEndpointAddress, qh->qh_state, 3447 list_empty(&qh->qtd_list) ? "" : "(has tds)"); 3448 break; 3449 } 3450 ep->hcpriv = NULL; 3451done: 3452 spin_unlock_irqrestore(&oxu->lock, flags); 3453} 3454 3455static int oxu_get_frame(struct usb_hcd *hcd) 3456{ 3457 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3458 3459 return (readl(&oxu->regs->frame_index) >> 3) % 3460 oxu->periodic_size; 3461} 3462 3463/* Build "status change" packet (one or two bytes) from HC registers */ 3464static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf) 3465{ 3466 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3467 u32 temp, mask, status = 0; 3468 int ports, i, retval = 1; 3469 unsigned long flags; 3470 3471 /* if !PM, root hub timers won't get shut down ... */ 3472 if (!HC_IS_RUNNING(hcd->state)) 3473 return 0; 3474 3475 /* init status to no-changes */ 3476 buf[0] = 0; 3477 ports = HCS_N_PORTS(oxu->hcs_params); 3478 if (ports > 7) { 3479 buf[1] = 0; 3480 retval++; 3481 } 3482 3483 /* Some boards (mostly VIA?) report bogus overcurrent indications, 3484 * causing massive log spam unless we completely ignore them. It 3485 * may be relevant that VIA VT8235 controllers, where PORT_POWER is 3486 * always set, seem to clear PORT_OCC and PORT_CSC when writing to 3487 * PORT_POWER; that's surprising, but maybe within-spec. 3488 */ 3489 if (!ignore_oc) 3490 mask = PORT_CSC | PORT_PEC | PORT_OCC; 3491 else 3492 mask = PORT_CSC | PORT_PEC; 3493 3494 /* no hub change reports (bit 0) for now (power, ...) */ 3495 3496 /* port N changes (bit N)? */ 3497 spin_lock_irqsave(&oxu->lock, flags); 3498 for (i = 0; i < ports; i++) { 3499 temp = readl(&oxu->regs->port_status[i]); 3500 3501 /* 3502 * Return status information even for ports with OWNER set. 3503 * Otherwise hub_wq wouldn't see the disconnect event when a 3504 * high-speed device is switched over to the companion 3505 * controller by the user. 3506 */ 3507 3508 if (!(temp & PORT_CONNECT)) 3509 oxu->reset_done[i] = 0; 3510 if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 && 3511 time_after_eq(jiffies, oxu->reset_done[i]))) { 3512 if (i < 7) 3513 buf[0] |= 1 << (i + 1); 3514 else 3515 buf[1] |= 1 << (i - 7); 3516 status = STS_PCD; 3517 } 3518 } 3519 /* FIXME autosuspend idle root hubs */ 3520 spin_unlock_irqrestore(&oxu->lock, flags); 3521 return status ? retval : 0; 3522} 3523 3524/* Returns the speed of a device attached to a port on the root hub. */ 3525static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu, 3526 unsigned int portsc) 3527{ 3528 switch ((portsc >> 26) & 3) { 3529 case 0: 3530 return 0; 3531 case 1: 3532 return USB_PORT_STAT_LOW_SPEED; 3533 case 2: 3534 default: 3535 return USB_PORT_STAT_HIGH_SPEED; 3536 } 3537} 3538 3539#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) 3540static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq, 3541 u16 wValue, u16 wIndex, char *buf, u16 wLength) 3542{ 3543 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3544 int ports = HCS_N_PORTS(oxu->hcs_params); 3545 u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1]; 3546 u32 temp, status; 3547 unsigned long flags; 3548 int retval = 0; 3549 unsigned selector; 3550 3551 /* 3552 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. 3553 * HCS_INDICATOR may say we can change LEDs to off/amber/green. 3554 * (track current state ourselves) ... blink for diagnostics, 3555 * power, "this is the one", etc. EHCI spec supports this. 3556 */ 3557 3558 spin_lock_irqsave(&oxu->lock, flags); 3559 switch (typeReq) { 3560 case ClearHubFeature: 3561 switch (wValue) { 3562 case C_HUB_LOCAL_POWER: 3563 case C_HUB_OVER_CURRENT: 3564 /* no hub-wide feature/status flags */ 3565 break; 3566 default: 3567 goto error; 3568 } 3569 break; 3570 case ClearPortFeature: 3571 if (!wIndex || wIndex > ports) 3572 goto error; 3573 wIndex--; 3574 temp = readl(status_reg); 3575 3576 /* 3577 * Even if OWNER is set, so the port is owned by the 3578 * companion controller, hub_wq needs to be able to clear 3579 * the port-change status bits (especially 3580 * USB_PORT_STAT_C_CONNECTION). 3581 */ 3582 3583 switch (wValue) { 3584 case USB_PORT_FEAT_ENABLE: 3585 writel(temp & ~PORT_PE, status_reg); 3586 break; 3587 case USB_PORT_FEAT_C_ENABLE: 3588 writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg); 3589 break; 3590 case USB_PORT_FEAT_SUSPEND: 3591 if (temp & PORT_RESET) 3592 goto error; 3593 if (temp & PORT_SUSPEND) { 3594 if ((temp & PORT_PE) == 0) 3595 goto error; 3596 /* resume signaling for 20 msec */ 3597 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 3598 writel(temp | PORT_RESUME, status_reg); 3599 oxu->reset_done[wIndex] = jiffies 3600 + msecs_to_jiffies(20); 3601 } 3602 break; 3603 case USB_PORT_FEAT_C_SUSPEND: 3604 /* we auto-clear this feature */ 3605 break; 3606 case USB_PORT_FEAT_POWER: 3607 if (HCS_PPC(oxu->hcs_params)) 3608 writel(temp & ~(PORT_RWC_BITS | PORT_POWER), 3609 status_reg); 3610 break; 3611 case USB_PORT_FEAT_C_CONNECTION: 3612 writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg); 3613 break; 3614 case USB_PORT_FEAT_C_OVER_CURRENT: 3615 writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg); 3616 break; 3617 case USB_PORT_FEAT_C_RESET: 3618 /* GetPortStatus clears reset */ 3619 break; 3620 default: 3621 goto error; 3622 } 3623 readl(&oxu->regs->command); /* unblock posted write */ 3624 break; 3625 case GetHubDescriptor: 3626 ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *) 3627 buf); 3628 break; 3629 case GetHubStatus: 3630 /* no hub-wide feature/status flags */ 3631 memset(buf, 0, 4); 3632 break; 3633 case GetPortStatus: 3634 if (!wIndex || wIndex > ports) 3635 goto error; 3636 wIndex--; 3637 status = 0; 3638 temp = readl(status_reg); 3639 3640 /* wPortChange bits */ 3641 if (temp & PORT_CSC) 3642 status |= USB_PORT_STAT_C_CONNECTION << 16; 3643 if (temp & PORT_PEC) 3644 status |= USB_PORT_STAT_C_ENABLE << 16; 3645 if ((temp & PORT_OCC) && !ignore_oc) 3646 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3647 3648 /* whoever resumes must GetPortStatus to complete it!! */ 3649 if (temp & PORT_RESUME) { 3650 3651 /* Remote Wakeup received? */ 3652 if (!oxu->reset_done[wIndex]) { 3653 /* resume signaling for 20 msec */ 3654 oxu->reset_done[wIndex] = jiffies 3655 + msecs_to_jiffies(20); 3656 /* check the port again */ 3657 mod_timer(&oxu_to_hcd(oxu)->rh_timer, 3658 oxu->reset_done[wIndex]); 3659 } 3660 3661 /* resume completed? */ 3662 else if (time_after_eq(jiffies, 3663 oxu->reset_done[wIndex])) { 3664 status |= USB_PORT_STAT_C_SUSPEND << 16; 3665 oxu->reset_done[wIndex] = 0; 3666 3667 /* stop resume signaling */ 3668 temp = readl(status_reg); 3669 writel(temp & ~(PORT_RWC_BITS | PORT_RESUME), 3670 status_reg); 3671 retval = handshake(oxu, status_reg, 3672 PORT_RESUME, 0, 2000 /* 2msec */); 3673 if (retval != 0) { 3674 oxu_err(oxu, 3675 "port %d resume error %d\n", 3676 wIndex + 1, retval); 3677 goto error; 3678 } 3679 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); 3680 } 3681 } 3682 3683 /* whoever resets must GetPortStatus to complete it!! */ 3684 if ((temp & PORT_RESET) 3685 && time_after_eq(jiffies, 3686 oxu->reset_done[wIndex])) { 3687 status |= USB_PORT_STAT_C_RESET << 16; 3688 oxu->reset_done[wIndex] = 0; 3689 3690 /* force reset to complete */ 3691 writel(temp & ~(PORT_RWC_BITS | PORT_RESET), 3692 status_reg); 3693 /* REVISIT: some hardware needs 550+ usec to clear 3694 * this bit; seems too long to spin routinely... 3695 */ 3696 retval = handshake(oxu, status_reg, 3697 PORT_RESET, 0, 750); 3698 if (retval != 0) { 3699 oxu_err(oxu, "port %d reset error %d\n", 3700 wIndex + 1, retval); 3701 goto error; 3702 } 3703 3704 /* see what we found out */ 3705 temp = check_reset_complete(oxu, wIndex, status_reg, 3706 readl(status_reg)); 3707 } 3708 3709 /* transfer dedicated ports to the companion hc */ 3710 if ((temp & PORT_CONNECT) && 3711 test_bit(wIndex, &oxu->companion_ports)) { 3712 temp &= ~PORT_RWC_BITS; 3713 temp |= PORT_OWNER; 3714 writel(temp, status_reg); 3715 oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1); 3716 temp = readl(status_reg); 3717 } 3718 3719 /* 3720 * Even if OWNER is set, there's no harm letting hub_wq 3721 * see the wPortStatus values (they should all be 0 except 3722 * for PORT_POWER anyway). 3723 */ 3724 3725 if (temp & PORT_CONNECT) { 3726 status |= USB_PORT_STAT_CONNECTION; 3727 /* status may be from integrated TT */ 3728 status |= oxu_port_speed(oxu, temp); 3729 } 3730 if (temp & PORT_PE) 3731 status |= USB_PORT_STAT_ENABLE; 3732 if (temp & (PORT_SUSPEND|PORT_RESUME)) 3733 status |= USB_PORT_STAT_SUSPEND; 3734 if (temp & PORT_OC) 3735 status |= USB_PORT_STAT_OVERCURRENT; 3736 if (temp & PORT_RESET) 3737 status |= USB_PORT_STAT_RESET; 3738 if (temp & PORT_POWER) 3739 status |= USB_PORT_STAT_POWER; 3740 3741#ifndef OXU_VERBOSE_DEBUG 3742 if (status & ~0xffff) /* only if wPortChange is interesting */ 3743#endif 3744 dbg_port(oxu, "GetStatus", wIndex + 1, temp); 3745 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 3746 break; 3747 case SetHubFeature: 3748 switch (wValue) { 3749 case C_HUB_LOCAL_POWER: 3750 case C_HUB_OVER_CURRENT: 3751 /* no hub-wide feature/status flags */ 3752 break; 3753 default: 3754 goto error; 3755 } 3756 break; 3757 case SetPortFeature: 3758 selector = wIndex >> 8; 3759 wIndex &= 0xff; 3760 if (!wIndex || wIndex > ports) 3761 goto error; 3762 wIndex--; 3763 temp = readl(status_reg); 3764 if (temp & PORT_OWNER) 3765 break; 3766 3767 temp &= ~PORT_RWC_BITS; 3768 switch (wValue) { 3769 case USB_PORT_FEAT_SUSPEND: 3770 if ((temp & PORT_PE) == 0 3771 || (temp & PORT_RESET) != 0) 3772 goto error; 3773 if (device_may_wakeup(&hcd->self.root_hub->dev)) 3774 temp |= PORT_WAKE_BITS; 3775 writel(temp | PORT_SUSPEND, status_reg); 3776 break; 3777 case USB_PORT_FEAT_POWER: 3778 if (HCS_PPC(oxu->hcs_params)) 3779 writel(temp | PORT_POWER, status_reg); 3780 break; 3781 case USB_PORT_FEAT_RESET: 3782 if (temp & PORT_RESUME) 3783 goto error; 3784 /* line status bits may report this as low speed, 3785 * which can be fine if this root hub has a 3786 * transaction translator built in. 3787 */ 3788 oxu_vdbg(oxu, "port %d reset\n", wIndex + 1); 3789 temp |= PORT_RESET; 3790 temp &= ~PORT_PE; 3791 3792 /* 3793 * caller must wait, then call GetPortStatus 3794 * usb 2.0 spec says 50 ms resets on root 3795 */ 3796 oxu->reset_done[wIndex] = jiffies 3797 + msecs_to_jiffies(50); 3798 writel(temp, status_reg); 3799 break; 3800 3801 /* For downstream facing ports (these): one hub port is put 3802 * into test mode according to USB2 11.24.2.13, then the hub 3803 * must be reset (which for root hub now means rmmod+modprobe, 3804 * or else system reboot). See EHCI 2.3.9 and 4.14 for info 3805 * about the EHCI-specific stuff. 3806 */ 3807 case USB_PORT_FEAT_TEST: 3808 if (!selector || selector > 5) 3809 goto error; 3810 ehci_quiesce(oxu); 3811 ehci_halt(oxu); 3812 temp |= selector << 16; 3813 writel(temp, status_reg); 3814 break; 3815 3816 default: 3817 goto error; 3818 } 3819 readl(&oxu->regs->command); /* unblock posted writes */ 3820 break; 3821 3822 default: 3823error: 3824 /* "stall" on error */ 3825 retval = -EPIPE; 3826 } 3827 spin_unlock_irqrestore(&oxu->lock, flags); 3828 return retval; 3829} 3830 3831#ifdef CONFIG_PM 3832 3833static int oxu_bus_suspend(struct usb_hcd *hcd) 3834{ 3835 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3836 int port; 3837 int mask; 3838 3839 oxu_dbg(oxu, "suspend root hub\n"); 3840 3841 if (time_before(jiffies, oxu->next_statechange)) 3842 msleep(5); 3843 3844 port = HCS_N_PORTS(oxu->hcs_params); 3845 spin_lock_irq(&oxu->lock); 3846 3847 /* stop schedules, clean any completed work */ 3848 if (HC_IS_RUNNING(hcd->state)) { 3849 ehci_quiesce(oxu); 3850 hcd->state = HC_STATE_QUIESCING; 3851 } 3852 oxu->command = readl(&oxu->regs->command); 3853 if (oxu->reclaim) 3854 oxu->reclaim_ready = 1; 3855 ehci_work(oxu); 3856 3857 /* Unlike other USB host controller types, EHCI doesn't have 3858 * any notion of "global" or bus-wide suspend. The driver has 3859 * to manually suspend all the active unsuspended ports, and 3860 * then manually resume them in the bus_resume() routine. 3861 */ 3862 oxu->bus_suspended = 0; 3863 while (port--) { 3864 u32 __iomem *reg = &oxu->regs->port_status[port]; 3865 u32 t1 = readl(reg) & ~PORT_RWC_BITS; 3866 u32 t2 = t1; 3867 3868 /* keep track of which ports we suspend */ 3869 if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) && 3870 !(t1 & PORT_SUSPEND)) { 3871 t2 |= PORT_SUSPEND; 3872 set_bit(port, &oxu->bus_suspended); 3873 } 3874 3875 /* enable remote wakeup on all ports */ 3876 if (device_may_wakeup(&hcd->self.root_hub->dev)) 3877 t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E; 3878 else 3879 t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E); 3880 3881 if (t1 != t2) { 3882 oxu_vdbg(oxu, "port %d, %08x -> %08x\n", 3883 port + 1, t1, t2); 3884 writel(t2, reg); 3885 } 3886 } 3887 3888 spin_unlock_irq(&oxu->lock); 3889 /* turn off now-idle HC */ 3890 timer_delete_sync(&oxu->watchdog); 3891 spin_lock_irq(&oxu->lock); 3892 ehci_halt(oxu); 3893 hcd->state = HC_STATE_SUSPENDED; 3894 3895 /* allow remote wakeup */ 3896 mask = INTR_MASK; 3897 if (!device_may_wakeup(&hcd->self.root_hub->dev)) 3898 mask &= ~STS_PCD; 3899 writel(mask, &oxu->regs->intr_enable); 3900 readl(&oxu->regs->intr_enable); 3901 3902 oxu->next_statechange = jiffies + msecs_to_jiffies(10); 3903 spin_unlock_irq(&oxu->lock); 3904 return 0; 3905} 3906 3907/* Caller has locked the root hub, and should reset/reinit on error */ 3908static int oxu_bus_resume(struct usb_hcd *hcd) 3909{ 3910 struct oxu_hcd *oxu = hcd_to_oxu(hcd); 3911 u32 temp; 3912 int i; 3913 3914 if (time_before(jiffies, oxu->next_statechange)) 3915 msleep(5); 3916 spin_lock_irq(&oxu->lock); 3917 3918 /* Ideally and we've got a real resume here, and no port's power 3919 * was lost. (For PCI, that means Vaux was maintained.) But we 3920 * could instead be restoring a swsusp snapshot -- so that BIOS was 3921 * the last user of the controller, not reset/pm hardware keeping 3922 * state we gave to it. 3923 */ 3924 temp = readl(&oxu->regs->intr_enable); 3925 oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss"); 3926 3927 /* at least some APM implementations will try to deliver 3928 * IRQs right away, so delay them until we're ready. 3929 */ 3930 writel(0, &oxu->regs->intr_enable); 3931 3932 /* re-init operational registers */ 3933 writel(0, &oxu->regs->segment); 3934 writel(oxu->periodic_dma, &oxu->regs->frame_list); 3935 writel((u32) oxu->async->qh_dma, &oxu->regs->async_next); 3936 3937 /* restore CMD_RUN, framelist size, and irq threshold */ 3938 writel(oxu->command, &oxu->regs->command); 3939 3940 /* Some controller/firmware combinations need a delay during which 3941 * they set up the port statuses. See Bugzilla #8190. */ 3942 mdelay(8); 3943 3944 /* manually resume the ports we suspended during bus_suspend() */ 3945 i = HCS_N_PORTS(oxu->hcs_params); 3946 while (i--) { 3947 temp = readl(&oxu->regs->port_status[i]); 3948 temp &= ~(PORT_RWC_BITS 3949 | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E); 3950 if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) { 3951 oxu->reset_done[i] = jiffies + msecs_to_jiffies(20); 3952 temp |= PORT_RESUME; 3953 } 3954 writel(temp, &oxu->regs->port_status[i]); 3955 } 3956 i = HCS_N_PORTS(oxu->hcs_params); 3957 mdelay(20); 3958 while (i--) { 3959 temp = readl(&oxu->regs->port_status[i]); 3960 if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) { 3961 temp &= ~(PORT_RWC_BITS | PORT_RESUME); 3962 writel(temp, &oxu->regs->port_status[i]); 3963 oxu_vdbg(oxu, "resumed port %d\n", i + 1); 3964 } 3965 } 3966 (void) readl(&oxu->regs->command); 3967 3968 /* maybe re-activate the schedule(s) */ 3969 temp = 0; 3970 if (oxu->async->qh_next.qh) 3971 temp |= CMD_ASE; 3972 if (oxu->periodic_sched) 3973 temp |= CMD_PSE; 3974 if (temp) { 3975 oxu->command |= temp; 3976 writel(oxu->command, &oxu->regs->command); 3977 } 3978 3979 oxu->next_statechange = jiffies + msecs_to_jiffies(5); 3980 hcd->state = HC_STATE_RUNNING; 3981 3982 /* Now we can safely re-enable irqs */ 3983 writel(INTR_MASK, &oxu->regs->intr_enable); 3984 3985 spin_unlock_irq(&oxu->lock); 3986 return 0; 3987} 3988 3989#else 3990 3991static int oxu_bus_suspend(struct usb_hcd *hcd) 3992{ 3993 return 0; 3994} 3995 3996static int oxu_bus_resume(struct usb_hcd *hcd) 3997{ 3998 return 0; 3999} 4000 4001#endif /* CONFIG_PM */ 4002 4003static const struct hc_driver oxu_hc_driver = { 4004 .description = "oxu210hp_hcd", 4005 .product_desc = "oxu210hp HCD", 4006 .hcd_priv_size = sizeof(struct oxu_hcd), 4007 4008 /* 4009 * Generic hardware linkage 4010 */ 4011 .irq = oxu_irq, 4012 .flags = HCD_MEMORY | HCD_USB2, 4013 4014 /* 4015 * Basic lifecycle operations 4016 */ 4017 .reset = oxu_reset, 4018 .start = oxu_run, 4019 .stop = oxu_stop, 4020 .shutdown = oxu_shutdown, 4021 4022 /* 4023 * Managing i/o requests and associated device resources 4024 */ 4025 .urb_enqueue = oxu_urb_enqueue, 4026 .urb_dequeue = oxu_urb_dequeue, 4027 .endpoint_disable = oxu_endpoint_disable, 4028 4029 /* 4030 * Scheduling support 4031 */ 4032 .get_frame_number = oxu_get_frame, 4033 4034 /* 4035 * Root hub support 4036 */ 4037 .hub_status_data = oxu_hub_status_data, 4038 .hub_control = oxu_hub_control, 4039 .bus_suspend = oxu_bus_suspend, 4040 .bus_resume = oxu_bus_resume, 4041}; 4042 4043/* 4044 * Module stuff 4045 */ 4046 4047static void oxu_configuration(struct platform_device *pdev, void __iomem *base) 4048{ 4049 u32 tmp; 4050 4051 /* Initialize top level registers. 4052 * First write ever 4053 */ 4054 oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); 4055 oxu_writel(base, OXU_SOFTRESET, OXU_SRESET); 4056 oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); 4057 4058 tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL); 4059 oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040); 4060 4061 oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN | 4062 OXU_COMPARATOR | OXU_ASO_OP); 4063 4064 tmp = oxu_readl(base, OXU_CLKCTRL_SET); 4065 oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN); 4066 4067 /* Clear all top interrupt enable */ 4068 oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff); 4069 4070 /* Clear all top interrupt status */ 4071 oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff); 4072 4073 /* Enable all needed top interrupt except OTG SPH core */ 4074 oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI); 4075} 4076 4077static int oxu_verify_id(struct platform_device *pdev, void __iomem *base) 4078{ 4079 u32 id; 4080 static const char * const bo[] = { 4081 "reserved", 4082 "128-pin LQFP", 4083 "84-pin TFBGA", 4084 "reserved", 4085 }; 4086 4087 /* Read controller signature register to find a match */ 4088 id = oxu_readl(base, OXU_DEVICEID); 4089 dev_info(&pdev->dev, "device ID %x\n", id); 4090 if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT)) 4091 return -1; 4092 4093 dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n", 4094 id >> OXU_REV_SHIFT, 4095 bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT], 4096 (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT, 4097 (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT); 4098 4099 return 0; 4100} 4101 4102static const struct hc_driver oxu_hc_driver; 4103static struct usb_hcd *oxu_create(struct platform_device *pdev, 4104 unsigned long memstart, unsigned long memlen, 4105 void __iomem *base, int irq, int otg) 4106{ 4107 struct device *dev = &pdev->dev; 4108 4109 struct usb_hcd *hcd; 4110 struct oxu_hcd *oxu; 4111 int ret; 4112 4113 /* Set endian mode and host mode */ 4114 oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET), 4115 OXU_USBMODE, 4116 OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS); 4117 4118 hcd = usb_create_hcd(&oxu_hc_driver, dev, 4119 otg ? "oxu210hp_otg" : "oxu210hp_sph"); 4120 if (!hcd) 4121 return ERR_PTR(-ENOMEM); 4122 4123 hcd->rsrc_start = memstart; 4124 hcd->rsrc_len = memlen; 4125 hcd->regs = base; 4126 hcd->irq = irq; 4127 hcd->state = HC_STATE_HALT; 4128 4129 oxu = hcd_to_oxu(hcd); 4130 oxu->is_otg = otg; 4131 4132 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 4133 if (ret < 0) { 4134 usb_put_hcd(hcd); 4135 return ERR_PTR(ret); 4136 } 4137 4138 device_wakeup_enable(hcd->self.controller); 4139 return hcd; 4140} 4141 4142static int oxu_init(struct platform_device *pdev, 4143 unsigned long memstart, unsigned long memlen, 4144 void __iomem *base, int irq) 4145{ 4146 struct oxu_info *info = platform_get_drvdata(pdev); 4147 struct usb_hcd *hcd; 4148 int ret; 4149 4150 /* First time configuration at start up */ 4151 oxu_configuration(pdev, base); 4152 4153 ret = oxu_verify_id(pdev, base); 4154 if (ret) { 4155 dev_err(&pdev->dev, "no devices found!\n"); 4156 return -ENODEV; 4157 } 4158 4159 /* Create the OTG controller */ 4160 hcd = oxu_create(pdev, memstart, memlen, base, irq, 1); 4161 if (IS_ERR(hcd)) { 4162 dev_err(&pdev->dev, "cannot create OTG controller!\n"); 4163 ret = PTR_ERR(hcd); 4164 goto error_create_otg; 4165 } 4166 info->hcd[0] = hcd; 4167 4168 /* Create the SPH host controller */ 4169 hcd = oxu_create(pdev, memstart, memlen, base, irq, 0); 4170 if (IS_ERR(hcd)) { 4171 dev_err(&pdev->dev, "cannot create SPH controller!\n"); 4172 ret = PTR_ERR(hcd); 4173 goto error_create_sph; 4174 } 4175 info->hcd[1] = hcd; 4176 4177 oxu_writel(base, OXU_CHIPIRQEN_SET, 4178 oxu_readl(base, OXU_CHIPIRQEN_SET) | 3); 4179 4180 return 0; 4181 4182error_create_sph: 4183 usb_remove_hcd(info->hcd[0]); 4184 usb_put_hcd(info->hcd[0]); 4185 4186error_create_otg: 4187 return ret; 4188} 4189 4190static int oxu_drv_probe(struct platform_device *pdev) 4191{ 4192 struct resource *res; 4193 void __iomem *base; 4194 unsigned long memstart, memlen; 4195 int irq, ret; 4196 struct oxu_info *info; 4197 4198 if (usb_disabled()) 4199 return -ENODEV; 4200 4201 /* 4202 * Get the platform resources 4203 */ 4204 irq = platform_get_irq(pdev, 0); 4205 if (irq < 0) 4206 return irq; 4207 dev_dbg(&pdev->dev, "IRQ resource %d\n", irq); 4208 4209 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 4210 if (IS_ERR(base)) { 4211 ret = PTR_ERR(base); 4212 goto error; 4213 } 4214 memstart = res->start; 4215 memlen = resource_size(res); 4216 4217 ret = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING); 4218 if (ret) { 4219 dev_err(&pdev->dev, "error setting irq type\n"); 4220 ret = -EFAULT; 4221 goto error; 4222 } 4223 4224 /* Allocate a driver data struct to hold useful info for both 4225 * SPH & OTG devices 4226 */ 4227 info = devm_kzalloc(&pdev->dev, sizeof(struct oxu_info), GFP_KERNEL); 4228 if (!info) { 4229 ret = -EFAULT; 4230 goto error; 4231 } 4232 platform_set_drvdata(pdev, info); 4233 4234 ret = oxu_init(pdev, memstart, memlen, base, irq); 4235 if (ret < 0) { 4236 dev_dbg(&pdev->dev, "cannot init USB devices\n"); 4237 goto error; 4238 } 4239 4240 dev_info(&pdev->dev, "devices enabled and running\n"); 4241 platform_set_drvdata(pdev, info); 4242 4243 return 0; 4244 4245error: 4246 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret); 4247 return ret; 4248} 4249 4250static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd) 4251{ 4252 usb_remove_hcd(hcd); 4253 usb_put_hcd(hcd); 4254} 4255 4256static void oxu_drv_remove(struct platform_device *pdev) 4257{ 4258 struct oxu_info *info = platform_get_drvdata(pdev); 4259 4260 oxu_remove(pdev, info->hcd[0]); 4261 oxu_remove(pdev, info->hcd[1]); 4262} 4263 4264static void oxu_drv_shutdown(struct platform_device *pdev) 4265{ 4266 oxu_drv_remove(pdev); 4267} 4268 4269#if 0 4270/* FIXME: TODO */ 4271static int oxu_drv_suspend(struct device *dev) 4272{ 4273 struct platform_device *pdev = to_platform_device(dev); 4274 struct usb_hcd *hcd = dev_get_drvdata(dev); 4275 4276 return 0; 4277} 4278 4279static int oxu_drv_resume(struct device *dev) 4280{ 4281 struct platform_device *pdev = to_platform_device(dev); 4282 struct usb_hcd *hcd = dev_get_drvdata(dev); 4283 4284 return 0; 4285} 4286#else 4287#define oxu_drv_suspend NULL 4288#define oxu_drv_resume NULL 4289#endif 4290 4291static struct platform_driver oxu_driver = { 4292 .probe = oxu_drv_probe, 4293 .remove = oxu_drv_remove, 4294 .shutdown = oxu_drv_shutdown, 4295 .suspend = oxu_drv_suspend, 4296 .resume = oxu_drv_resume, 4297 .driver = { 4298 .name = "oxu210hp-hcd", 4299 .bus = &platform_bus_type 4300 } 4301}; 4302 4303module_platform_driver(oxu_driver); 4304 4305MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION); 4306MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>"); 4307MODULE_LICENSE("GPL");
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