ehci-fsl.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright 2005-2009 MontaVista Software, Inc.
  4 * Copyright 2008,2012,2015      Freescale Semiconductor, Inc.
  5 *
  6 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  7 * by Hunter Wu.
  8 * Power Management support by Dave Liu <daveliu@freescale.com>,
  9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
 10 * Anton Vorontsov <avorontsov@ru.mvista.com>.
 11 */
 12
 13#include <linux/kernel.h>
 14#include <linux/module.h>
 15#include <linux/types.h>
 16#include <linux/delay.h>
 17#include <linux/pm.h>
 18#include <linux/err.h>
 19#include <linux/usb.h>
 20#include <linux/usb/ehci_def.h>
 21#include <linux/usb/hcd.h>
 22#include <linux/usb/otg.h>
 23#include <linux/platform_device.h>
 24#include <linux/fsl_devices.h>
 25#include <linux/of.h>
 26#include <linux/io.h>
 27
 28#include "ehci.h"
 29#include "ehci-fsl.h"
 30
 31#define DRIVER_DESC "Freescale EHCI Host controller driver"
 32#define DRV_NAME "fsl-ehci"
 33
 34static struct hc_driver __read_mostly fsl_ehci_hc_driver;
 35
 36/* configure so an HC device and id are always provided */
 37/* always called with process context; sleeping is OK */
 38
 39/*
 40 * fsl_ehci_drv_probe - initialize FSL-based HCDs
 41 * @pdev: USB Host Controller being probed
 42 *
 43 * Context: task context, might sleep
 44 *
 45 * Allocates basic resources for this USB host controller.
 46 */
 47static int fsl_ehci_drv_probe(struct platform_device *pdev)
 48{
 49	struct fsl_usb2_platform_data *pdata;
 50	struct usb_hcd *hcd;
 51	struct resource *res;
 52	int irq;
 53	int retval;
 54	u32 tmp;
 55
 56	pr_debug("initializing FSL-SOC USB Controller\n");
 57
 58	/* Need platform data for setup */
 59	pdata = dev_get_platdata(&pdev->dev);
 60	if (!pdata) {
 61		dev_err(&pdev->dev,
 62			"No platform data for %s.\n", dev_name(&pdev->dev));
 63		return -ENODEV;
 64	}
 65
 66	/*
 67	 * This is a host mode driver, verify that we're supposed to be
 68	 * in host mode.
 69	 */
 70	if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
 71	      (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
 72	      (pdata->operating_mode == FSL_USB2_DR_OTG))) {
 73		dev_err(&pdev->dev,
 74			"Non Host Mode configured for %s. Wrong driver linked.\n",
 75			dev_name(&pdev->dev));
 76		return -ENODEV;
 77	}
 78
 79	irq = platform_get_irq(pdev, 0);
 80	if (irq < 0)
 81		return irq;
 82
 83	hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent,
 84			       &pdev->dev, dev_name(&pdev->dev), NULL);
 85	if (!hcd) {
 86		retval = -ENOMEM;
 87		goto err1;
 88	}
 89
 90	hcd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 91	if (IS_ERR(hcd->regs)) {
 92		retval = PTR_ERR(hcd->regs);
 93		goto err2;
 94	}
 95
 96	hcd->rsrc_start = res->start;
 97	hcd->rsrc_len = resource_size(res);
 98
 99	pdata->regs = hcd->regs;
100
101	if (pdata->power_budget)
102		hcd->power_budget = pdata->power_budget;
103
104	/*
105	 * do platform specific init: check the clock, grab/config pins, etc.
106	 */
107	if (pdata->init && pdata->init(pdev)) {
108		retval = -ENODEV;
109		goto err2;
110	}
111
112	/* Enable USB controller, 83xx or 8536 */
113	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {
114		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
115		tmp &= ~CONTROL_REGISTER_W1C_MASK;
116		tmp |= 0x4;
117		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
118	}
119
120	/* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
121	if (pdata->controller_ver == FSL_USB_VER_2_5 &&
122	    pdata->phy_mode == FSL_USB2_PHY_ULPI)
123		iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
124
125	/*
126	 * Enable UTMI phy and program PTS field in UTMI mode before asserting
127	 * controller reset for USB Controller version 2.5
128	 */
129	if (pdata->has_fsl_erratum_a007792) {
130		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
131		tmp &= ~CONTROL_REGISTER_W1C_MASK;
132		tmp |= CTRL_UTMI_PHY_EN;
133		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
134
135		writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
136	}
137
138	/* Don't need to set host mode here. It will be done by tdi_reset() */
139
140	retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
141	if (retval != 0)
142		goto err2;
143	device_wakeup_enable(hcd->self.controller);
144
145#ifdef CONFIG_USB_OTG
146	if (pdata->operating_mode == FSL_USB2_DR_OTG) {
147		struct ehci_hcd *ehci = hcd_to_ehci(hcd);
148
149		hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
150		dev_dbg(&pdev->dev, "hcd=0x%p  ehci=0x%p, phy=0x%p\n",
151			hcd, ehci, hcd->usb_phy);
152
153		if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
154			retval = otg_set_host(hcd->usb_phy->otg,
155					      &ehci_to_hcd(ehci)->self);
156			if (retval) {
157				usb_put_phy(hcd->usb_phy);
158				goto err2;
159			}
160		} else {
161			dev_err(&pdev->dev, "can't find phy\n");
162			retval = -ENODEV;
163			goto err2;
164		}
165
166		hcd->skip_phy_initialization = 1;
167	}
168#endif
169	return retval;
170
171      err2:
172	usb_put_hcd(hcd);
173      err1:
174	dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
175	if (pdata->exit)
176		pdata->exit(pdev);
177	return retval;
178}
179
180static bool usb_phy_clk_valid(struct usb_hcd *hcd)
181{
182	void __iomem *non_ehci = hcd->regs;
183	bool ret = true;
184
185	if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
186		ret = false;
187
188	return ret;
189}
190
191static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
192			       enum fsl_usb2_phy_modes phy_mode,
193			       unsigned int port_offset)
194{
195	u32 portsc, tmp;
196	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
197	void __iomem *non_ehci = hcd->regs;
198	struct device *dev = hcd->self.controller;
199	struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
200
201	if (pdata->controller_ver < 0) {
202		dev_warn(hcd->self.controller, "Could not get controller version\n");
203		return -ENODEV;
204	}
205
206	portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
207	portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
208
209	switch (phy_mode) {
210	case FSL_USB2_PHY_ULPI:
211		if (pdata->have_sysif_regs && pdata->controller_ver) {
212			/* controller version 1.6 or above */
213			/* turn off UTMI PHY first */
214			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
215			tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
216			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
217
218			/* then turn on ULPI and enable USB controller */
219			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
220			tmp &= ~CONTROL_REGISTER_W1C_MASK;
221			tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;
222			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
223		}
224		portsc |= PORT_PTS_ULPI;
225		break;
226	case FSL_USB2_PHY_SERIAL:
227		portsc |= PORT_PTS_SERIAL;
228		break;
229	case FSL_USB2_PHY_UTMI_WIDE:
230		portsc |= PORT_PTS_PTW;
231		fallthrough;
232	case FSL_USB2_PHY_UTMI:
233		/* Presence of this node "has_fsl_erratum_a006918"
234		 * in device-tree is used to stop USB controller
235		 * initialization in Linux
236		 */
237		if (pdata->has_fsl_erratum_a006918) {
238			dev_warn(dev, "USB PHY clock invalid\n");
239			return -EINVAL;
240		}
241		fallthrough;
242	case FSL_USB2_PHY_UTMI_DUAL:
243		/* PHY_CLK_VALID bit is de-featured from all controller
244		 * versions below 2.4 and is to be checked only for
245		 * internal UTMI phy
246		 */
247		if (pdata->controller_ver > FSL_USB_VER_2_4 &&
248		    pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
249			dev_err(dev, "USB PHY clock invalid\n");
250			return -EINVAL;
251		}
252
253		if (pdata->have_sysif_regs && pdata->controller_ver) {
254			/* controller version 1.6 or above */
255			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
256			tmp &= ~CONTROL_REGISTER_W1C_MASK;
257			tmp |= UTMI_PHY_EN;
258			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
259
260			mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
261						become stable - 10ms*/
262		}
263		/* enable UTMI PHY */
264		if (pdata->have_sysif_regs) {
265			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
266			tmp &= ~CONTROL_REGISTER_W1C_MASK;
267			tmp |= CTRL_UTMI_PHY_EN;
268			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
269		}
270		portsc |= PORT_PTS_UTMI;
271		break;
272	case FSL_USB2_PHY_NONE:
273		break;
274	}
275
276	if (pdata->have_sysif_regs &&
277	    pdata->controller_ver > FSL_USB_VER_1_6 &&
278	    !usb_phy_clk_valid(hcd)) {
279		dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
280		return -EINVAL;
281	}
282
283	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
284
285	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {
286		tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
287		tmp &= ~CONTROL_REGISTER_W1C_MASK;
288		tmp |= USB_CTRL_USB_EN;
289		iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
290	}
291
292	return 0;
293}
294
295static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
296{
297	struct usb_hcd *hcd = ehci_to_hcd(ehci);
298	struct fsl_usb2_platform_data *pdata;
299	void __iomem *non_ehci = hcd->regs;
300
301	pdata = dev_get_platdata(hcd->self.controller);
302
303	if (pdata->have_sysif_regs) {
304		/*
305		* Turn on cache snooping hardware, since some PowerPC platforms
306		* wholly rely on hardware to deal with cache coherent
307		*/
308
309		/* Setup Snooping for all the 4GB space */
310		/* SNOOP1 starts from 0x0, size 2G */
311		iowrite32be(0x0 | SNOOP_SIZE_2GB,
312			    non_ehci + FSL_SOC_USB_SNOOP1);
313		/* SNOOP2 starts from 0x80000000, size 2G */
314		iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
315			    non_ehci + FSL_SOC_USB_SNOOP2);
316	}
317
318	/* Deal with USB erratum A-005275 */
319	if (pdata->has_fsl_erratum_a005275 == 1)
320		ehci->has_fsl_hs_errata = 1;
321
322	if (pdata->has_fsl_erratum_a005697 == 1)
323		ehci->has_fsl_susp_errata = 1;
324
325	if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
326			(pdata->operating_mode == FSL_USB2_DR_OTG))
327		if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
328			return -EINVAL;
329
330	if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
331
332		/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
333		if (pdata->has_fsl_erratum_14 == 1)
334			ehci->has_fsl_port_bug = 1;
335
336		if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
337			if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
338				return -EINVAL;
339
340		if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
341			if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
342				return -EINVAL;
343	}
344
345	if (pdata->have_sysif_regs) {
346#ifdef CONFIG_FSL_SOC_BOOKE
347		iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
348		iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
349#else
350		iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
351		iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
352#endif
353		iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
354	}
355
356	return 0;
357}
358
359/* called after powerup, by probe or system-pm "wakeup" */
360static int ehci_fsl_reinit(struct ehci_hcd *ehci)
361{
362	if (ehci_fsl_usb_setup(ehci))
363		return -EINVAL;
364
365	return 0;
366}
367
368/* called during probe() after chip reset completes */
369static int ehci_fsl_setup(struct usb_hcd *hcd)
370{
371	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
372	int retval;
373	struct fsl_usb2_platform_data *pdata;
374	struct device *dev;
375
376	dev = hcd->self.controller;
377	pdata = dev_get_platdata(hcd->self.controller);
378	ehci->big_endian_desc = pdata->big_endian_desc;
379	ehci->big_endian_mmio = pdata->big_endian_mmio;
380
381	/* EHCI registers start at offset 0x100 */
382	ehci->caps = hcd->regs + 0x100;
383
384#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_85xx)
385	/*
386	 * Deal with MPC834X/85XX that need port power to be cycled
387	 * after the power fault condition is removed. Otherwise the
388	 * state machine does not reflect PORTSC[CSC] correctly.
389	 */
390	ehci->need_oc_pp_cycle = 1;
391#endif
392
393	hcd->has_tt = 1;
394
395	retval = ehci_setup(hcd);
396	if (retval)
397		return retval;
398
399	if (of_device_is_compatible(dev->parent->of_node,
400				    "fsl,mpc5121-usb2-dr")) {
401		/*
402		 * set SBUSCFG:AHBBRST so that control msgs don't
403		 * fail when doing heavy PATA writes.
404		 */
405		ehci_writel(ehci, SBUSCFG_INCR8,
406			    hcd->regs + FSL_SOC_USB_SBUSCFG);
407	}
408
409	retval = ehci_fsl_reinit(ehci);
410	return retval;
411}
412
413struct ehci_fsl_priv {
414	/* Saved USB PHY settings, need to restore after deep sleep. */
415	u32 usb_ctrl;
416};
417
418#define hcd_to_ehci_fsl_priv(h) ((struct ehci_fsl_priv *) hcd_to_ehci(h)->priv)
419
420#ifdef CONFIG_PM
421
422#ifdef CONFIG_PPC_MPC512x
423static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
424{
425	struct usb_hcd *hcd = dev_get_drvdata(dev);
426	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
427	struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
428	u32 tmp;
429
430#ifdef CONFIG_DYNAMIC_DEBUG
431	u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
432	mode &= USBMODE_CM_MASK;
433	tmp = ehci_readl(ehci, hcd->regs + 0x140);	/* usbcmd */
434
435	dev_dbg(dev, "suspend=%d already_suspended=%d "
436		"mode=%d  usbcmd %08x\n", pdata->suspended,
437		pdata->already_suspended, mode, tmp);
438#endif
439
440	/*
441	 * If the controller is already suspended, then this must be a
442	 * PM suspend.  Remember this fact, so that we will leave the
443	 * controller suspended at PM resume time.
444	 */
445	if (pdata->suspended) {
446		dev_dbg(dev, "already suspended, leaving early\n");
447		pdata->already_suspended = 1;
448		return 0;
449	}
450
451	dev_dbg(dev, "suspending...\n");
452
453	ehci->rh_state = EHCI_RH_SUSPENDED;
454	dev->power.power_state = PMSG_SUSPEND;
455
456	/* ignore non-host interrupts */
457	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
458
459	/* stop the controller */
460	tmp = ehci_readl(ehci, &ehci->regs->command);
461	tmp &= ~CMD_RUN;
462	ehci_writel(ehci, tmp, &ehci->regs->command);
463
464	/* save EHCI registers */
465	pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
466	pdata->pm_command &= ~CMD_RUN;
467	pdata->pm_status  = ehci_readl(ehci, &ehci->regs->status);
468	pdata->pm_intr_enable  = ehci_readl(ehci, &ehci->regs->intr_enable);
469	pdata->pm_frame_index  = ehci_readl(ehci, &ehci->regs->frame_index);
470	pdata->pm_segment  = ehci_readl(ehci, &ehci->regs->segment);
471	pdata->pm_frame_list  = ehci_readl(ehci, &ehci->regs->frame_list);
472	pdata->pm_async_next  = ehci_readl(ehci, &ehci->regs->async_next);
473	pdata->pm_configured_flag  =
474		ehci_readl(ehci, &ehci->regs->configured_flag);
475	pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
476	pdata->pm_usbgenctrl = ehci_readl(ehci,
477					  hcd->regs + FSL_SOC_USB_USBGENCTRL);
478
479	/* clear the W1C bits */
480	pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
481
482	pdata->suspended = 1;
483
484	/* clear PP to cut power to the port */
485	tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
486	tmp &= ~PORT_POWER;
487	ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
488
489	return 0;
490}
491
492static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
493{
494	struct usb_hcd *hcd = dev_get_drvdata(dev);
495	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
496	struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
497	u32 tmp;
498
499	dev_dbg(dev, "suspend=%d already_suspended=%d\n",
500		pdata->suspended, pdata->already_suspended);
501
502	/*
503	 * If the controller was already suspended at suspend time,
504	 * then don't resume it now.
505	 */
506	if (pdata->already_suspended) {
507		dev_dbg(dev, "already suspended, leaving early\n");
508		pdata->already_suspended = 0;
509		return 0;
510	}
511
512	if (!pdata->suspended) {
513		dev_dbg(dev, "not suspended, leaving early\n");
514		return 0;
515	}
516
517	pdata->suspended = 0;
518
519	dev_dbg(dev, "resuming...\n");
520
521	/* set host mode */
522	tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
523	ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
524
525	ehci_writel(ehci, pdata->pm_usbgenctrl,
526		    hcd->regs + FSL_SOC_USB_USBGENCTRL);
527	ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
528		    hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
529
530	ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
531
532	/* restore EHCI registers */
533	ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
534	ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
535	ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
536	ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
537	ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
538	ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
539	ehci_writel(ehci, pdata->pm_configured_flag,
540		    &ehci->regs->configured_flag);
541	ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
542
543	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
544	ehci->rh_state = EHCI_RH_RUNNING;
545	dev->power.power_state = PMSG_ON;
546
547	tmp = ehci_readl(ehci, &ehci->regs->command);
548	tmp |= CMD_RUN;
549	ehci_writel(ehci, tmp, &ehci->regs->command);
550
551	usb_hcd_resume_root_hub(hcd);
552
553	return 0;
554}
555#else
556static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
557{
558	return 0;
559}
560
561static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
562{
563	return 0;
564}
565#endif /* CONFIG_PPC_MPC512x */
566
567static int ehci_fsl_drv_suspend(struct device *dev)
568{
569	struct usb_hcd *hcd = dev_get_drvdata(dev);
570	struct ehci_fsl_priv *priv = hcd_to_ehci_fsl_priv(hcd);
571	void __iomem *non_ehci = hcd->regs;
572
573	if (of_device_is_compatible(dev->parent->of_node,
574				    "fsl,mpc5121-usb2-dr")) {
575		return ehci_fsl_mpc512x_drv_suspend(dev);
576	}
577
578	ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
579			device_may_wakeup(dev));
580	if (!fsl_deep_sleep())
581		return 0;
582
583	priv->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
584	return 0;
585}
586
587static int ehci_fsl_drv_resume(struct device *dev)
588{
589	struct usb_hcd *hcd = dev_get_drvdata(dev);
590	struct ehci_fsl_priv *priv = hcd_to_ehci_fsl_priv(hcd);
591	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
592	void __iomem *non_ehci = hcd->regs;
593
594	if (of_device_is_compatible(dev->parent->of_node,
595				    "fsl,mpc5121-usb2-dr")) {
596		return ehci_fsl_mpc512x_drv_resume(dev);
597	}
598
599	ehci_prepare_ports_for_controller_resume(ehci);
600	if (!fsl_deep_sleep())
601		return 0;
602
603	usb_root_hub_lost_power(hcd->self.root_hub);
604
605	/* Restore USB PHY settings and enable the controller. */
606	iowrite32be(priv->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
607
608	ehci_reset(ehci);
609	ehci_fsl_reinit(ehci);
610
611	return 0;
612}
613
614static int ehci_fsl_drv_restore(struct device *dev)
615{
616	struct usb_hcd *hcd = dev_get_drvdata(dev);
617
618	usb_root_hub_lost_power(hcd->self.root_hub);
619	return 0;
620}
621
622static const struct dev_pm_ops ehci_fsl_pm_ops = {
623	.suspend = ehci_fsl_drv_suspend,
624	.resume = ehci_fsl_drv_resume,
625	.restore = ehci_fsl_drv_restore,
626};
627
628#define EHCI_FSL_PM_OPS		(&ehci_fsl_pm_ops)
629#else
630#define EHCI_FSL_PM_OPS		NULL
631#endif /* CONFIG_PM */
632
633#ifdef CONFIG_USB_OTG
634static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
635{
636	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
637	u32 status;
638
639	if (!port)
640		return -EINVAL;
641
642	port--;
643
644	/* start port reset before HNP protocol time out */
645	status = readl(&ehci->regs->port_status[port]);
646	if (!(status & PORT_CONNECT))
647		return -ENODEV;
648
649	/* hub_wq will finish the reset later */
650	if (ehci_is_TDI(ehci)) {
651		writel(PORT_RESET |
652		       (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
653		       &ehci->regs->port_status[port]);
654	} else {
655		writel(PORT_RESET, &ehci->regs->port_status[port]);
656	}
657
658	return 0;
659}
660#else
661#define ehci_start_port_reset	NULL
662#endif /* CONFIG_USB_OTG */
663
664static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = {
665	.extra_priv_size = sizeof(struct ehci_fsl_priv),
666	.reset = ehci_fsl_setup,
667};
668
669/**
670 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
671 * @pdev: USB Host Controller being removed
672 *
673 * Context: task context, might sleep
674 *
675 * Reverses the effect of usb_hcd_fsl_probe().
676 */
677static void fsl_ehci_drv_remove(struct platform_device *pdev)
678{
679	struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
680	struct usb_hcd *hcd = platform_get_drvdata(pdev);
681
682	if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
683		otg_set_host(hcd->usb_phy->otg, NULL);
684		usb_put_phy(hcd->usb_phy);
685	}
686
687	usb_remove_hcd(hcd);
688
689	/*
690	 * do platform specific un-initialization:
691	 * release iomux pins, disable clock, etc.
692	 */
693	if (pdata->exit)
694		pdata->exit(pdev);
695	usb_put_hcd(hcd);
696}
697
698static struct platform_driver ehci_fsl_driver = {
699	.probe = fsl_ehci_drv_probe,
700	.remove = fsl_ehci_drv_remove,
701	.shutdown = usb_hcd_platform_shutdown,
702	.driver = {
703		.name = DRV_NAME,
704		.pm = EHCI_FSL_PM_OPS,
705	},
706};
707
708static int __init ehci_fsl_init(void)
709{
710	if (usb_disabled())
711		return -ENODEV;
712
713	ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
714
715	fsl_ehci_hc_driver.product_desc =
716			"Freescale On-Chip EHCI Host Controller";
717	fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
718
719
720	return platform_driver_register(&ehci_fsl_driver);
721}
722module_init(ehci_fsl_init);
723
724static void __exit ehci_fsl_cleanup(void)
725{
726	platform_driver_unregister(&ehci_fsl_driver);
727}
728module_exit(ehci_fsl_cleanup);
729
730MODULE_DESCRIPTION(DRIVER_DESC);
731MODULE_LICENSE("GPL");
732MODULE_ALIAS("platform:" DRV_NAME);