FILE
tegra-xudc.c
File preview with syntax highlighting.
linux-6.19.14/drivers/usb/gadget/udc/tegra-xudc.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * NVIDIA Tegra XUSB device mode controller 4 * 5 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. 6 * Copyright (c) 2015, Google Inc. 7 */ 8 9#include <linux/clk.h> 10#include <linux/completion.h> 11#include <linux/delay.h> 12#include <linux/dma-mapping.h> 13#include <linux/dmapool.h> 14#include <linux/interrupt.h> 15#include <linux/iopoll.h> 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/phy/phy.h> 20#include <linux/phy/tegra/xusb.h> 21#include <linux/pm_domain.h> 22#include <linux/platform_device.h> 23#include <linux/pm_runtime.h> 24#include <linux/regulator/consumer.h> 25#include <linux/reset.h> 26#include <linux/usb/ch9.h> 27#include <linux/usb/gadget.h> 28#include <linux/usb/otg.h> 29#include <linux/usb/role.h> 30#include <linux/usb/phy.h> 31#include <linux/workqueue.h> 32 33/* XUSB_DEV registers */ 34#define DB 0x004 35#define DB_TARGET_MASK GENMASK(15, 8) 36#define DB_TARGET(x) (((x) << 8) & DB_TARGET_MASK) 37#define DB_STREAMID_MASK GENMASK(31, 16) 38#define DB_STREAMID(x) (((x) << 16) & DB_STREAMID_MASK) 39#define ERSTSZ 0x008 40#define ERSTSZ_ERSTXSZ_SHIFT(x) ((x) * 16) 41#define ERSTSZ_ERSTXSZ_MASK GENMASK(15, 0) 42#define ERSTXBALO(x) (0x010 + 8 * (x)) 43#define ERSTXBAHI(x) (0x014 + 8 * (x)) 44#define ERDPLO 0x020 45#define ERDPLO_EHB BIT(3) 46#define ERDPHI 0x024 47#define EREPLO 0x028 48#define EREPLO_ECS BIT(0) 49#define EREPLO_SEGI BIT(1) 50#define EREPHI 0x02c 51#define CTRL 0x030 52#define CTRL_RUN BIT(0) 53#define CTRL_LSE BIT(1) 54#define CTRL_IE BIT(4) 55#define CTRL_SMI_EVT BIT(5) 56#define CTRL_SMI_DSE BIT(6) 57#define CTRL_EWE BIT(7) 58#define CTRL_DEVADDR_MASK GENMASK(30, 24) 59#define CTRL_DEVADDR(x) (((x) << 24) & CTRL_DEVADDR_MASK) 60#define CTRL_ENABLE BIT(31) 61#define ST 0x034 62#define ST_RC BIT(0) 63#define ST_IP BIT(4) 64#define RT_IMOD 0x038 65#define RT_IMOD_IMODI_MASK GENMASK(15, 0) 66#define RT_IMOD_IMODI(x) ((x) & RT_IMOD_IMODI_MASK) 67#define RT_IMOD_IMODC_MASK GENMASK(31, 16) 68#define RT_IMOD_IMODC(x) (((x) << 16) & RT_IMOD_IMODC_MASK) 69#define PORTSC 0x03c 70#define PORTSC_CCS BIT(0) 71#define PORTSC_PED BIT(1) 72#define PORTSC_PR BIT(4) 73#define PORTSC_PLS_SHIFT 5 74#define PORTSC_PLS_MASK GENMASK(8, 5) 75#define PORTSC_PLS_U0 0x0 76#define PORTSC_PLS_U2 0x2 77#define PORTSC_PLS_U3 0x3 78#define PORTSC_PLS_DISABLED 0x4 79#define PORTSC_PLS_RXDETECT 0x5 80#define PORTSC_PLS_INACTIVE 0x6 81#define PORTSC_PLS_RESUME 0xf 82#define PORTSC_PLS(x) (((x) << PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK) 83#define PORTSC_PS_SHIFT 10 84#define PORTSC_PS_MASK GENMASK(13, 10) 85#define PORTSC_PS_UNDEFINED 0x0 86#define PORTSC_PS_FS 0x1 87#define PORTSC_PS_LS 0x2 88#define PORTSC_PS_HS 0x3 89#define PORTSC_PS_SS 0x4 90#define PORTSC_LWS BIT(16) 91#define PORTSC_CSC BIT(17) 92#define PORTSC_WRC BIT(19) 93#define PORTSC_PRC BIT(21) 94#define PORTSC_PLC BIT(22) 95#define PORTSC_CEC BIT(23) 96#define PORTSC_WPR BIT(30) 97#define PORTSC_CHANGE_MASK (PORTSC_CSC | PORTSC_WRC | PORTSC_PRC | \ 98 PORTSC_PLC | PORTSC_CEC) 99#define ECPLO 0x040 100#define ECPHI 0x044 101#define MFINDEX 0x048 102#define MFINDEX_FRAME_SHIFT 3 103#define MFINDEX_FRAME_MASK GENMASK(13, 3) 104#define PORTPM 0x04c 105#define PORTPM_L1S_MASK GENMASK(1, 0) 106#define PORTPM_L1S_DROP 0x0 107#define PORTPM_L1S_ACCEPT 0x1 108#define PORTPM_L1S_NYET 0x2 109#define PORTPM_L1S_STALL 0x3 110#define PORTPM_L1S(x) ((x) & PORTPM_L1S_MASK) 111#define PORTPM_RWE BIT(3) 112#define PORTPM_U2TIMEOUT_MASK GENMASK(15, 8) 113#define PORTPM_U1TIMEOUT_MASK GENMASK(23, 16) 114#define PORTPM_FLA BIT(24) 115#define PORTPM_VBA BIT(25) 116#define PORTPM_WOC BIT(26) 117#define PORTPM_WOD BIT(27) 118#define PORTPM_U1E BIT(28) 119#define PORTPM_U2E BIT(29) 120#define PORTPM_FRWE BIT(30) 121#define PORTPM_PNG_CYA BIT(31) 122#define EP_HALT 0x050 123#define EP_PAUSE 0x054 124#define EP_RELOAD 0x058 125#define EP_STCHG 0x05c 126#define DEVNOTIF_LO 0x064 127#define DEVNOTIF_LO_TRIG BIT(0) 128#define DEVNOTIF_LO_TYPE_MASK GENMASK(7, 4) 129#define DEVNOTIF_LO_TYPE(x) (((x) << 4) & DEVNOTIF_LO_TYPE_MASK) 130#define DEVNOTIF_LO_TYPE_FUNCTION_WAKE 0x1 131#define DEVNOTIF_HI 0x068 132#define PORTHALT 0x06c 133#define PORTHALT_HALT_LTSSM BIT(0) 134#define PORTHALT_HALT_REJECT BIT(1) 135#define PORTHALT_STCHG_REQ BIT(20) 136#define PORTHALT_STCHG_INTR_EN BIT(24) 137#define PORT_TM 0x070 138#define EP_THREAD_ACTIVE 0x074 139#define EP_STOPPED 0x078 140#define HSFSPI_COUNT0 0x100 141#define HSFSPI_COUNT13 0x134 142#define HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK GENMASK(29, 0) 143#define HSFSPI_COUNT13_U2_RESUME_K_DURATION(x) ((x) & \ 144 HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK) 145#define BLCG 0x840 146#define SSPX_CORE_CNT0 0x610 147#define SSPX_CORE_CNT0_PING_TBURST_MASK GENMASK(7, 0) 148#define SSPX_CORE_CNT0_PING_TBURST(x) ((x) & SSPX_CORE_CNT0_PING_TBURST_MASK) 149#define SSPX_CORE_CNT30 0x688 150#define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(19, 0) 151#define SSPX_CORE_CNT30_LMPITP_TIMER(x) ((x) & \ 152 SSPX_CORE_CNT30_LMPITP_TIMER_MASK) 153#define SSPX_CORE_CNT32 0x690 154#define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0) 155#define SSPX_CORE_CNT32_POLL_TBURST_MAX(x) ((x) & \ 156 SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK) 157#define SSPX_CORE_CNT56 0x6fc 158#define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK GENMASK(19, 0) 159#define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(x) ((x) & \ 160 SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK) 161#define SSPX_CORE_CNT57 0x700 162#define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK GENMASK(19, 0) 163#define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(x) ((x) & \ 164 SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK) 165#define SSPX_CORE_CNT65 0x720 166#define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK GENMASK(19, 0) 167#define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(x) ((x) & \ 168 SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK) 169#define SSPX_CORE_CNT66 0x724 170#define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK GENMASK(19, 0) 171#define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(x) ((x) & \ 172 SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK) 173#define SSPX_CORE_CNT67 0x728 174#define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK GENMASK(19, 0) 175#define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(x) ((x) & \ 176 SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK) 177#define SSPX_CORE_CNT72 0x73c 178#define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK GENMASK(19, 0) 179#define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(x) ((x) & \ 180 SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK) 181#define SSPX_CORE_PADCTL4 0x750 182#define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK GENMASK(19, 0) 183#define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(x) ((x) & \ 184 SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK) 185#define BLCG_DFPCI BIT(0) 186#define BLCG_UFPCI BIT(1) 187#define BLCG_FE BIT(2) 188#define BLCG_COREPLL_PWRDN BIT(8) 189#define BLCG_IOPLL_0_PWRDN BIT(9) 190#define BLCG_IOPLL_1_PWRDN BIT(10) 191#define BLCG_IOPLL_2_PWRDN BIT(11) 192#define BLCG_ALL 0x1ff 193#define CFG_DEV_SSPI_XFER 0x858 194#define CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK GENMASK(31, 0) 195#define CFG_DEV_SSPI_XFER_ACKTIMEOUT(x) ((x) & \ 196 CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK) 197#define CFG_DEV_FE 0x85c 198#define CFG_DEV_FE_PORTREGSEL_MASK GENMASK(1, 0) 199#define CFG_DEV_FE_PORTREGSEL_SS_PI 1 200#define CFG_DEV_FE_PORTREGSEL_HSFS_PI 2 201#define CFG_DEV_FE_PORTREGSEL(x) ((x) & CFG_DEV_FE_PORTREGSEL_MASK) 202#define CFG_DEV_FE_INFINITE_SS_RETRY BIT(29) 203 204/* FPCI registers */ 205#define XUSB_DEV_CFG_1 0x004 206#define XUSB_DEV_CFG_1_IO_SPACE_EN BIT(0) 207#define XUSB_DEV_CFG_1_MEMORY_SPACE_EN BIT(1) 208#define XUSB_DEV_CFG_1_BUS_MASTER_EN BIT(2) 209#define XUSB_DEV_CFG_4 0x010 210#define XUSB_DEV_CFG_4_BASE_ADDR_MASK GENMASK(31, 15) 211#define XUSB_DEV_CFG_5 0x014 212 213/* IPFS registers */ 214#define XUSB_DEV_CONFIGURATION_0 0x180 215#define XUSB_DEV_CONFIGURATION_0_EN_FPCI BIT(0) 216#define XUSB_DEV_INTR_MASK_0 0x188 217#define XUSB_DEV_INTR_MASK_0_IP_INT_MASK BIT(16) 218 219struct tegra_xudc_ep_context { 220 __le32 info0; 221 __le32 info1; 222 __le32 deq_lo; 223 __le32 deq_hi; 224 __le32 tx_info; 225 __le32 rsvd[11]; 226}; 227 228#define EP_STATE_DISABLED 0 229#define EP_STATE_RUNNING 1 230#define EP_STATE_HALTED 2 231#define EP_STATE_STOPPED 3 232#define EP_STATE_ERROR 4 233 234#define EP_TYPE_INVALID 0 235#define EP_TYPE_ISOCH_OUT 1 236#define EP_TYPE_BULK_OUT 2 237#define EP_TYPE_INTERRUPT_OUT 3 238#define EP_TYPE_CONTROL 4 239#define EP_TYPE_ISCOH_IN 5 240#define EP_TYPE_BULK_IN 6 241#define EP_TYPE_INTERRUPT_IN 7 242 243#define BUILD_EP_CONTEXT_RW(name, member, shift, mask) \ 244static inline u32 ep_ctx_read_##name(struct tegra_xudc_ep_context *ctx) \ 245{ \ 246 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \ 247} \ 248static inline void \ 249ep_ctx_write_##name(struct tegra_xudc_ep_context *ctx, u32 val) \ 250{ \ 251 u32 tmp; \ 252 \ 253 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \ 254 tmp |= (val & (mask)) << (shift); \ 255 ctx->member = cpu_to_le32(tmp); \ 256} 257 258BUILD_EP_CONTEXT_RW(state, info0, 0, 0x7) 259BUILD_EP_CONTEXT_RW(mult, info0, 8, 0x3) 260BUILD_EP_CONTEXT_RW(max_pstreams, info0, 10, 0x1f) 261BUILD_EP_CONTEXT_RW(lsa, info0, 15, 0x1) 262BUILD_EP_CONTEXT_RW(interval, info0, 16, 0xff) 263BUILD_EP_CONTEXT_RW(cerr, info1, 1, 0x3) 264BUILD_EP_CONTEXT_RW(type, info1, 3, 0x7) 265BUILD_EP_CONTEXT_RW(hid, info1, 7, 0x1) 266BUILD_EP_CONTEXT_RW(max_burst_size, info1, 8, 0xff) 267BUILD_EP_CONTEXT_RW(max_packet_size, info1, 16, 0xffff) 268BUILD_EP_CONTEXT_RW(dcs, deq_lo, 0, 0x1) 269BUILD_EP_CONTEXT_RW(deq_lo, deq_lo, 4, 0xfffffff) 270BUILD_EP_CONTEXT_RW(deq_hi, deq_hi, 0, 0xffffffff) 271BUILD_EP_CONTEXT_RW(avg_trb_len, tx_info, 0, 0xffff) 272BUILD_EP_CONTEXT_RW(max_esit_payload, tx_info, 16, 0xffff) 273BUILD_EP_CONTEXT_RW(edtla, rsvd[0], 0, 0xffffff) 274BUILD_EP_CONTEXT_RW(rsvd, rsvd[0], 24, 0x1) 275BUILD_EP_CONTEXT_RW(partial_td, rsvd[0], 25, 0x1) 276BUILD_EP_CONTEXT_RW(splitxstate, rsvd[0], 26, 0x1) 277BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 27, 0x1f) 278BUILD_EP_CONTEXT_RW(cerrcnt, rsvd[1], 18, 0x3) 279BUILD_EP_CONTEXT_RW(data_offset, rsvd[2], 0, 0x1ffff) 280BUILD_EP_CONTEXT_RW(numtrbs, rsvd[2], 22, 0x1f) 281BUILD_EP_CONTEXT_RW(devaddr, rsvd[6], 0, 0x7f) 282 283static inline u64 ep_ctx_read_deq_ptr(struct tegra_xudc_ep_context *ctx) 284{ 285 return ((u64)ep_ctx_read_deq_hi(ctx) << 32) | 286 (ep_ctx_read_deq_lo(ctx) << 4); 287} 288 289static inline void 290ep_ctx_write_deq_ptr(struct tegra_xudc_ep_context *ctx, u64 addr) 291{ 292 ep_ctx_write_deq_lo(ctx, lower_32_bits(addr) >> 4); 293 ep_ctx_write_deq_hi(ctx, upper_32_bits(addr)); 294} 295 296struct tegra_xudc_trb { 297 __le32 data_lo; 298 __le32 data_hi; 299 __le32 status; 300 __le32 control; 301}; 302 303#define TRB_TYPE_RSVD 0 304#define TRB_TYPE_NORMAL 1 305#define TRB_TYPE_SETUP_STAGE 2 306#define TRB_TYPE_DATA_STAGE 3 307#define TRB_TYPE_STATUS_STAGE 4 308#define TRB_TYPE_ISOCH 5 309#define TRB_TYPE_LINK 6 310#define TRB_TYPE_TRANSFER_EVENT 32 311#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34 312#define TRB_TYPE_STREAM 48 313#define TRB_TYPE_SETUP_PACKET_EVENT 63 314 315#define TRB_CMPL_CODE_INVALID 0 316#define TRB_CMPL_CODE_SUCCESS 1 317#define TRB_CMPL_CODE_DATA_BUFFER_ERR 2 318#define TRB_CMPL_CODE_BABBLE_DETECTED_ERR 3 319#define TRB_CMPL_CODE_USB_TRANS_ERR 4 320#define TRB_CMPL_CODE_TRB_ERR 5 321#define TRB_CMPL_CODE_STALL 6 322#define TRB_CMPL_CODE_INVALID_STREAM_TYPE_ERR 10 323#define TRB_CMPL_CODE_SHORT_PACKET 13 324#define TRB_CMPL_CODE_RING_UNDERRUN 14 325#define TRB_CMPL_CODE_RING_OVERRUN 15 326#define TRB_CMPL_CODE_EVENT_RING_FULL_ERR 21 327#define TRB_CMPL_CODE_STOPPED 26 328#define TRB_CMPL_CODE_ISOCH_BUFFER_OVERRUN 31 329#define TRB_CMPL_CODE_STREAM_NUMP_ERROR 219 330#define TRB_CMPL_CODE_PRIME_PIPE_RECEIVED 220 331#define TRB_CMPL_CODE_HOST_REJECTED 221 332#define TRB_CMPL_CODE_CTRL_DIR_ERR 222 333#define TRB_CMPL_CODE_CTRL_SEQNUM_ERR 223 334 335#define BUILD_TRB_RW(name, member, shift, mask) \ 336static inline u32 trb_read_##name(struct tegra_xudc_trb *trb) \ 337{ \ 338 return (le32_to_cpu(trb->member) >> (shift)) & (mask); \ 339} \ 340static inline void \ 341trb_write_##name(struct tegra_xudc_trb *trb, u32 val) \ 342{ \ 343 u32 tmp; \ 344 \ 345 tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \ 346 tmp |= (val & (mask)) << (shift); \ 347 trb->member = cpu_to_le32(tmp); \ 348} 349 350BUILD_TRB_RW(data_lo, data_lo, 0, 0xffffffff) 351BUILD_TRB_RW(data_hi, data_hi, 0, 0xffffffff) 352BUILD_TRB_RW(seq_num, status, 0, 0xffff) 353BUILD_TRB_RW(transfer_len, status, 0, 0xffffff) 354BUILD_TRB_RW(td_size, status, 17, 0x1f) 355BUILD_TRB_RW(cmpl_code, status, 24, 0xff) 356BUILD_TRB_RW(cycle, control, 0, 0x1) 357BUILD_TRB_RW(toggle_cycle, control, 1, 0x1) 358BUILD_TRB_RW(isp, control, 2, 0x1) 359BUILD_TRB_RW(chain, control, 4, 0x1) 360BUILD_TRB_RW(ioc, control, 5, 0x1) 361BUILD_TRB_RW(type, control, 10, 0x3f) 362BUILD_TRB_RW(stream_id, control, 16, 0xffff) 363BUILD_TRB_RW(endpoint_id, control, 16, 0x1f) 364BUILD_TRB_RW(tlbpc, control, 16, 0xf) 365BUILD_TRB_RW(data_stage_dir, control, 16, 0x1) 366BUILD_TRB_RW(frame_id, control, 20, 0x7ff) 367BUILD_TRB_RW(sia, control, 31, 0x1) 368 369static inline u64 trb_read_data_ptr(struct tegra_xudc_trb *trb) 370{ 371 return ((u64)trb_read_data_hi(trb) << 32) | 372 trb_read_data_lo(trb); 373} 374 375static inline void trb_write_data_ptr(struct tegra_xudc_trb *trb, u64 addr) 376{ 377 trb_write_data_lo(trb, lower_32_bits(addr)); 378 trb_write_data_hi(trb, upper_32_bits(addr)); 379} 380 381struct tegra_xudc_request { 382 struct usb_request usb_req; 383 384 size_t buf_queued; 385 unsigned int trbs_queued; 386 unsigned int trbs_needed; 387 bool need_zlp; 388 389 struct tegra_xudc_trb *first_trb; 390 struct tegra_xudc_trb *last_trb; 391 392 struct list_head list; 393}; 394 395struct tegra_xudc_ep { 396 struct tegra_xudc *xudc; 397 struct usb_ep usb_ep; 398 unsigned int index; 399 char name[8]; 400 401 struct tegra_xudc_ep_context *context; 402 403#define XUDC_TRANSFER_RING_SIZE 64 404 struct tegra_xudc_trb *transfer_ring; 405 dma_addr_t transfer_ring_phys; 406 407 unsigned int enq_ptr; 408 unsigned int deq_ptr; 409 bool pcs; 410 bool ring_full; 411 bool stream_rejected; 412 413 struct list_head queue; 414 const struct usb_endpoint_descriptor *desc; 415 const struct usb_ss_ep_comp_descriptor *comp_desc; 416}; 417 418struct tegra_xudc_sel_timing { 419 __u8 u1sel; 420 __u8 u1pel; 421 __le16 u2sel; 422 __le16 u2pel; 423}; 424 425enum tegra_xudc_setup_state { 426 WAIT_FOR_SETUP, 427 DATA_STAGE_XFER, 428 DATA_STAGE_RECV, 429 STATUS_STAGE_XFER, 430 STATUS_STAGE_RECV, 431}; 432 433struct tegra_xudc_setup_packet { 434 struct usb_ctrlrequest ctrl_req; 435 unsigned int seq_num; 436}; 437 438struct tegra_xudc_save_regs { 439 u32 ctrl; 440 u32 portpm; 441}; 442 443struct tegra_xudc { 444 struct device *dev; 445 const struct tegra_xudc_soc *soc; 446 struct tegra_xusb_padctl *padctl; 447 448 spinlock_t lock; 449 450 struct usb_gadget gadget; 451 struct usb_gadget_driver *driver; 452 453#define XUDC_NR_EVENT_RINGS 2 454#define XUDC_EVENT_RING_SIZE 4096 455 struct tegra_xudc_trb *event_ring[XUDC_NR_EVENT_RINGS]; 456 dma_addr_t event_ring_phys[XUDC_NR_EVENT_RINGS]; 457 unsigned int event_ring_index; 458 unsigned int event_ring_deq_ptr; 459 bool ccs; 460 461#define XUDC_NR_EPS 32 462 struct tegra_xudc_ep ep[XUDC_NR_EPS]; 463 struct tegra_xudc_ep_context *ep_context; 464 dma_addr_t ep_context_phys; 465 466 struct device *genpd_dev_device; 467 struct device *genpd_dev_ss; 468 struct device_link *genpd_dl_device; 469 struct device_link *genpd_dl_ss; 470 471 struct dma_pool *transfer_ring_pool; 472 473 bool queued_setup_packet; 474 struct tegra_xudc_setup_packet setup_packet; 475 enum tegra_xudc_setup_state setup_state; 476 u16 setup_seq_num; 477 478 u16 dev_addr; 479 u16 isoch_delay; 480 struct tegra_xudc_sel_timing sel_timing; 481 u8 test_mode_pattern; 482 u16 status_buf; 483 struct tegra_xudc_request *ep0_req; 484 485 bool pullup; 486 487 unsigned int nr_enabled_eps; 488 unsigned int nr_isoch_eps; 489 490 unsigned int device_state; 491 unsigned int resume_state; 492 493 int irq; 494 495 void __iomem *base; 496 resource_size_t phys_base; 497 void __iomem *ipfs; 498 void __iomem *fpci; 499 500 struct regulator_bulk_data *supplies; 501 502 struct clk_bulk_data *clks; 503 504 bool device_mode; 505 bool current_device_mode; 506 struct work_struct usb_role_sw_work; 507 508 struct phy **usb3_phy; 509 struct phy *curr_usb3_phy; 510 struct phy **utmi_phy; 511 struct phy *curr_utmi_phy; 512 513 struct tegra_xudc_save_regs saved_regs; 514 bool suspended; 515 bool powergated; 516 517 struct usb_phy **usbphy; 518 struct usb_phy *curr_usbphy; 519 struct notifier_block vbus_nb; 520 521 struct completion disconnect_complete; 522 523 bool selfpowered; 524 525#define TOGGLE_VBUS_WAIT_MS 100 526 struct delayed_work plc_reset_work; 527 bool wait_csc; 528 529 struct delayed_work port_reset_war_work; 530 bool wait_for_sec_prc; 531}; 532 533#define XUDC_TRB_MAX_BUFFER_SIZE 65536 534#define XUDC_MAX_ISOCH_EPS 4 535#define XUDC_INTERRUPT_MODERATION_US 0 536 537static struct usb_endpoint_descriptor tegra_xudc_ep0_desc = { 538 .bLength = USB_DT_ENDPOINT_SIZE, 539 .bDescriptorType = USB_DT_ENDPOINT, 540 .bEndpointAddress = 0, 541 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 542 .wMaxPacketSize = cpu_to_le16(64), 543}; 544 545struct tegra_xudc_soc { 546 const char * const *supply_names; 547 unsigned int num_supplies; 548 const char * const *clock_names; 549 unsigned int num_clks; 550 unsigned int num_phys; 551 bool u1_enable; 552 bool u2_enable; 553 bool lpm_enable; 554 bool invalid_seq_num; 555 bool pls_quirk; 556 bool port_reset_quirk; 557 bool port_speed_quirk; 558 bool has_ipfs; 559}; 560 561static inline u32 fpci_readl(struct tegra_xudc *xudc, unsigned int offset) 562{ 563 return readl(xudc->fpci + offset); 564} 565 566static inline void fpci_writel(struct tegra_xudc *xudc, u32 val, 567 unsigned int offset) 568{ 569 writel(val, xudc->fpci + offset); 570} 571 572static inline u32 ipfs_readl(struct tegra_xudc *xudc, unsigned int offset) 573{ 574 return readl(xudc->ipfs + offset); 575} 576 577static inline void ipfs_writel(struct tegra_xudc *xudc, u32 val, 578 unsigned int offset) 579{ 580 writel(val, xudc->ipfs + offset); 581} 582 583static inline u32 xudc_readl(struct tegra_xudc *xudc, unsigned int offset) 584{ 585 return readl(xudc->base + offset); 586} 587 588static inline void xudc_writel(struct tegra_xudc *xudc, u32 val, 589 unsigned int offset) 590{ 591 writel(val, xudc->base + offset); 592} 593 594static inline int xudc_readl_poll(struct tegra_xudc *xudc, 595 unsigned int offset, u32 mask, u32 val) 596{ 597 u32 regval; 598 599 return readl_poll_timeout_atomic(xudc->base + offset, regval, 600 (regval & mask) == val, 1, 100); 601} 602 603static inline struct tegra_xudc *to_xudc(struct usb_gadget *gadget) 604{ 605 return container_of(gadget, struct tegra_xudc, gadget); 606} 607 608static inline struct tegra_xudc_ep *to_xudc_ep(struct usb_ep *ep) 609{ 610 return container_of(ep, struct tegra_xudc_ep, usb_ep); 611} 612 613static inline struct tegra_xudc_request *to_xudc_req(struct usb_request *req) 614{ 615 return container_of(req, struct tegra_xudc_request, usb_req); 616} 617 618static inline void dump_trb(struct tegra_xudc *xudc, const char *type, 619 struct tegra_xudc_trb *trb) 620{ 621 dev_dbg(xudc->dev, 622 "%s: %p, lo = %#x, hi = %#x, status = %#x, control = %#x\n", 623 type, trb, trb->data_lo, trb->data_hi, trb->status, 624 trb->control); 625} 626 627static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc) 628{ 629 u32 val; 630 631 /* limit port speed to gen 1 */ 632 val = xudc_readl(xudc, SSPX_CORE_CNT56); 633 val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); 634 val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x260); 635 xudc_writel(xudc, val, SSPX_CORE_CNT56); 636 637 val = xudc_readl(xudc, SSPX_CORE_CNT57); 638 val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK); 639 val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x6D6); 640 xudc_writel(xudc, val, SSPX_CORE_CNT57); 641 642 val = xudc_readl(xudc, SSPX_CORE_CNT65); 643 val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); 644 val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0x4B0); 645 xudc_writel(xudc, val, SSPX_CORE_CNT66); 646 647 val = xudc_readl(xudc, SSPX_CORE_CNT66); 648 val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); 649 val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x4B0); 650 xudc_writel(xudc, val, SSPX_CORE_CNT66); 651 652 val = xudc_readl(xudc, SSPX_CORE_CNT67); 653 val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); 654 val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x4B0); 655 xudc_writel(xudc, val, SSPX_CORE_CNT67); 656 657 val = xudc_readl(xudc, SSPX_CORE_CNT72); 658 val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); 659 val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x10); 660 xudc_writel(xudc, val, SSPX_CORE_CNT72); 661} 662 663static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc) 664{ 665 u32 val; 666 667 /* restore port speed to gen2 */ 668 val = xudc_readl(xudc, SSPX_CORE_CNT56); 669 val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); 670 val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x438); 671 xudc_writel(xudc, val, SSPX_CORE_CNT56); 672 673 val = xudc_readl(xudc, SSPX_CORE_CNT57); 674 val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK); 675 val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x528); 676 xudc_writel(xudc, val, SSPX_CORE_CNT57); 677 678 val = xudc_readl(xudc, SSPX_CORE_CNT65); 679 val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); 680 val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0xE10); 681 xudc_writel(xudc, val, SSPX_CORE_CNT66); 682 683 val = xudc_readl(xudc, SSPX_CORE_CNT66); 684 val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); 685 val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x348); 686 xudc_writel(xudc, val, SSPX_CORE_CNT66); 687 688 val = xudc_readl(xudc, SSPX_CORE_CNT67); 689 val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); 690 val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x5a0); 691 xudc_writel(xudc, val, SSPX_CORE_CNT67); 692 693 val = xudc_readl(xudc, SSPX_CORE_CNT72); 694 val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); 695 val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x1c21); 696 xudc_writel(xudc, val, SSPX_CORE_CNT72); 697} 698 699static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc) 700{ 701 int err; 702 703 pm_runtime_get_sync(xudc->dev); 704 705 tegra_phy_xusb_utmi_pad_power_on(xudc->curr_utmi_phy); 706 707 err = phy_power_on(xudc->curr_utmi_phy); 708 if (err < 0) 709 dev_err(xudc->dev, "UTMI power on failed: %d\n", err); 710 711 err = phy_power_on(xudc->curr_usb3_phy); 712 if (err < 0) 713 dev_err(xudc->dev, "USB3 PHY power on failed: %d\n", err); 714 715 dev_dbg(xudc->dev, "device mode on\n"); 716 717 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, 718 USB_ROLE_DEVICE); 719 720 xudc->current_device_mode = true; 721} 722 723static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc) 724{ 725 bool connected = false; 726 u32 pls, val; 727 int err; 728 729 dev_dbg(xudc->dev, "device mode off\n"); 730 731 xudc->current_device_mode = false; 732 733 connected = !!(xudc_readl(xudc, PORTSC) & PORTSC_CCS); 734 735 reinit_completion(&xudc->disconnect_complete); 736 737 if (xudc->soc->port_speed_quirk) 738 tegra_xudc_restore_port_speed(xudc); 739 740 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); 741 742 pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >> 743 PORTSC_PLS_SHIFT; 744 745 /* Direct link to U0 if disconnected in RESUME or U2. */ 746 if (xudc->soc->pls_quirk && xudc->gadget.speed == USB_SPEED_SUPER && 747 (pls == PORTSC_PLS_RESUME || pls == PORTSC_PLS_U2)) { 748 val = xudc_readl(xudc, PORTPM); 749 val |= PORTPM_FRWE; 750 xudc_writel(xudc, val, PORTPM); 751 752 val = xudc_readl(xudc, PORTSC); 753 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK); 754 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_U0); 755 xudc_writel(xudc, val, PORTSC); 756 } 757 758 /* Wait for disconnect event. */ 759 if (connected) 760 wait_for_completion(&xudc->disconnect_complete); 761 762 /* Make sure interrupt handler has completed before powergating. */ 763 synchronize_irq(xudc->irq); 764 765 tegra_phy_xusb_utmi_pad_power_down(xudc->curr_utmi_phy); 766 767 err = phy_power_off(xudc->curr_utmi_phy); 768 if (err < 0) 769 dev_err(xudc->dev, "UTMI PHY power off failed: %d\n", err); 770 771 err = phy_power_off(xudc->curr_usb3_phy); 772 if (err < 0) 773 dev_err(xudc->dev, "USB3 PHY power off failed: %d\n", err); 774 775 pm_runtime_put(xudc->dev); 776} 777 778static void tegra_xudc_usb_role_sw_work(struct work_struct *work) 779{ 780 struct tegra_xudc *xudc = container_of(work, struct tegra_xudc, 781 usb_role_sw_work); 782 783 if (xudc->device_mode) 784 tegra_xudc_device_mode_on(xudc); 785 else 786 tegra_xudc_device_mode_off(xudc); 787} 788 789static int tegra_xudc_get_phy_index(struct tegra_xudc *xudc, 790 struct usb_phy *usbphy) 791{ 792 unsigned int i; 793 794 for (i = 0; i < xudc->soc->num_phys; i++) { 795 if (xudc->usbphy[i] && usbphy == xudc->usbphy[i]) 796 return i; 797 } 798 799 dev_info(xudc->dev, "phy index could not be found for shared USB PHY"); 800 return -1; 801} 802 803static void tegra_xudc_update_data_role(struct tegra_xudc *xudc, 804 struct usb_phy *usbphy) 805{ 806 int phy_index; 807 808 if ((xudc->device_mode && usbphy->last_event == USB_EVENT_VBUS) || 809 (!xudc->device_mode && usbphy->last_event != USB_EVENT_VBUS)) { 810 dev_dbg(xudc->dev, "Same role(%d) received. Ignore", 811 xudc->device_mode); 812 return; 813 } 814 815 xudc->device_mode = usbphy->last_event == USB_EVENT_VBUS; 816 817 phy_index = tegra_xudc_get_phy_index(xudc, usbphy); 818 dev_dbg(xudc->dev, "%s(): current phy index is %d\n", __func__, 819 phy_index); 820 821 if (!xudc->suspended && phy_index != -1) { 822 xudc->curr_utmi_phy = xudc->utmi_phy[phy_index]; 823 xudc->curr_usb3_phy = xudc->usb3_phy[phy_index]; 824 xudc->curr_usbphy = usbphy; 825 schedule_work(&xudc->usb_role_sw_work); 826 } 827} 828 829static int tegra_xudc_vbus_notify(struct notifier_block *nb, 830 unsigned long action, void *data) 831{ 832 struct tegra_xudc *xudc = container_of(nb, struct tegra_xudc, 833 vbus_nb); 834 struct usb_phy *usbphy = (struct usb_phy *)data; 835 836 dev_dbg(xudc->dev, "%s(): event is %d\n", __func__, usbphy->last_event); 837 838 tegra_xudc_update_data_role(xudc, usbphy); 839 840 return NOTIFY_OK; 841} 842 843static void tegra_xudc_plc_reset_work(struct work_struct *work) 844{ 845 struct delayed_work *dwork = to_delayed_work(work); 846 struct tegra_xudc *xudc = container_of(dwork, struct tegra_xudc, 847 plc_reset_work); 848 unsigned long flags; 849 850 spin_lock_irqsave(&xudc->lock, flags); 851 852 if (xudc->wait_csc) { 853 u32 pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >> 854 PORTSC_PLS_SHIFT; 855 856 if (pls == PORTSC_PLS_INACTIVE) { 857 dev_info(xudc->dev, "PLS = Inactive. Toggle VBUS\n"); 858 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, 859 USB_ROLE_NONE); 860 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, 861 USB_ROLE_DEVICE); 862 863 xudc->wait_csc = false; 864 } 865 } 866 867 spin_unlock_irqrestore(&xudc->lock, flags); 868} 869 870static void tegra_xudc_port_reset_war_work(struct work_struct *work) 871{ 872 struct delayed_work *dwork = to_delayed_work(work); 873 struct tegra_xudc *xudc = 874 container_of(dwork, struct tegra_xudc, port_reset_war_work); 875 unsigned long flags; 876 u32 pls; 877 int ret; 878 879 spin_lock_irqsave(&xudc->lock, flags); 880 881 if (xudc->device_mode && xudc->wait_for_sec_prc) { 882 pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >> 883 PORTSC_PLS_SHIFT; 884 dev_dbg(xudc->dev, "pls = %x\n", pls); 885 886 if (pls == PORTSC_PLS_DISABLED) { 887 dev_dbg(xudc->dev, "toggle vbus\n"); 888 /* PRC doesn't complete in 100ms, toggle the vbus */ 889 ret = tegra_phy_xusb_utmi_port_reset( 890 xudc->curr_utmi_phy); 891 if (ret == 1) 892 xudc->wait_for_sec_prc = 0; 893 } 894 } 895 896 spin_unlock_irqrestore(&xudc->lock, flags); 897} 898 899static dma_addr_t trb_virt_to_phys(struct tegra_xudc_ep *ep, 900 struct tegra_xudc_trb *trb) 901{ 902 unsigned int index; 903 904 index = trb - ep->transfer_ring; 905 906 if (WARN_ON(index >= XUDC_TRANSFER_RING_SIZE)) 907 return 0; 908 909 return (ep->transfer_ring_phys + index * sizeof(*trb)); 910} 911 912static struct tegra_xudc_trb *trb_phys_to_virt(struct tegra_xudc_ep *ep, 913 dma_addr_t addr) 914{ 915 struct tegra_xudc_trb *trb; 916 unsigned int index; 917 918 index = (addr - ep->transfer_ring_phys) / sizeof(*trb); 919 920 if (WARN_ON(index >= XUDC_TRANSFER_RING_SIZE)) 921 return NULL; 922 923 trb = &ep->transfer_ring[index]; 924 925 return trb; 926} 927 928static void ep_reload(struct tegra_xudc *xudc, unsigned int ep) 929{ 930 xudc_writel(xudc, BIT(ep), EP_RELOAD); 931 xudc_readl_poll(xudc, EP_RELOAD, BIT(ep), 0); 932} 933 934static void ep_pause(struct tegra_xudc *xudc, unsigned int ep) 935{ 936 u32 val; 937 938 val = xudc_readl(xudc, EP_PAUSE); 939 if (val & BIT(ep)) 940 return; 941 val |= BIT(ep); 942 943 xudc_writel(xudc, val, EP_PAUSE); 944 945 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep)); 946 947 xudc_writel(xudc, BIT(ep), EP_STCHG); 948} 949 950static void ep_unpause(struct tegra_xudc *xudc, unsigned int ep) 951{ 952 u32 val; 953 954 val = xudc_readl(xudc, EP_PAUSE); 955 if (!(val & BIT(ep))) 956 return; 957 val &= ~BIT(ep); 958 959 xudc_writel(xudc, val, EP_PAUSE); 960 961 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep)); 962 963 xudc_writel(xudc, BIT(ep), EP_STCHG); 964} 965 966static void ep_unpause_all(struct tegra_xudc *xudc) 967{ 968 u32 val; 969 970 val = xudc_readl(xudc, EP_PAUSE); 971 972 xudc_writel(xudc, 0, EP_PAUSE); 973 974 xudc_readl_poll(xudc, EP_STCHG, val, val); 975 976 xudc_writel(xudc, val, EP_STCHG); 977} 978 979static void ep_halt(struct tegra_xudc *xudc, unsigned int ep) 980{ 981 u32 val; 982 983 val = xudc_readl(xudc, EP_HALT); 984 if (val & BIT(ep)) 985 return; 986 val |= BIT(ep); 987 xudc_writel(xudc, val, EP_HALT); 988 989 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep)); 990 991 xudc_writel(xudc, BIT(ep), EP_STCHG); 992} 993 994static void ep_unhalt(struct tegra_xudc *xudc, unsigned int ep) 995{ 996 u32 val; 997 998 val = xudc_readl(xudc, EP_HALT); 999 if (!(val & BIT(ep))) 1000 return; 1001 val &= ~BIT(ep); 1002 xudc_writel(xudc, val, EP_HALT); 1003 1004 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep)); 1005 1006 xudc_writel(xudc, BIT(ep), EP_STCHG); 1007} 1008 1009static void ep_unhalt_all(struct tegra_xudc *xudc) 1010{ 1011 u32 val; 1012 1013 val = xudc_readl(xudc, EP_HALT); 1014 if (!val) 1015 return; 1016 xudc_writel(xudc, 0, EP_HALT); 1017 1018 xudc_readl_poll(xudc, EP_STCHG, val, val); 1019 1020 xudc_writel(xudc, val, EP_STCHG); 1021} 1022 1023static void ep_wait_for_stopped(struct tegra_xudc *xudc, unsigned int ep) 1024{ 1025 xudc_readl_poll(xudc, EP_STOPPED, BIT(ep), BIT(ep)); 1026 xudc_writel(xudc, BIT(ep), EP_STOPPED); 1027} 1028 1029static void ep_wait_for_inactive(struct tegra_xudc *xudc, unsigned int ep) 1030{ 1031 xudc_readl_poll(xudc, EP_THREAD_ACTIVE, BIT(ep), 0); 1032} 1033 1034static void tegra_xudc_req_done(struct tegra_xudc_ep *ep, 1035 struct tegra_xudc_request *req, int status) 1036{ 1037 struct tegra_xudc *xudc = ep->xudc; 1038 1039 dev_dbg(xudc->dev, "completing request %p on EP %u with status %d\n", 1040 req, ep->index, status); 1041 1042 if (likely(req->usb_req.status == -EINPROGRESS)) 1043 req->usb_req.status = status; 1044 1045 list_del_init(&req->list); 1046 1047 if (usb_endpoint_xfer_control(ep->desc)) { 1048 usb_gadget_unmap_request(&xudc->gadget, &req->usb_req, 1049 (xudc->setup_state == 1050 DATA_STAGE_XFER)); 1051 } else { 1052 usb_gadget_unmap_request(&xudc->gadget, &req->usb_req, 1053 usb_endpoint_dir_in(ep->desc)); 1054 } 1055 1056 spin_unlock(&xudc->lock); 1057 usb_gadget_giveback_request(&ep->usb_ep, &req->usb_req); 1058 spin_lock(&xudc->lock); 1059} 1060 1061static void tegra_xudc_ep_nuke(struct tegra_xudc_ep *ep, int status) 1062{ 1063 struct tegra_xudc_request *req; 1064 1065 while (!list_empty(&ep->queue)) { 1066 req = list_first_entry(&ep->queue, struct tegra_xudc_request, 1067 list); 1068 tegra_xudc_req_done(ep, req, status); 1069 } 1070} 1071 1072static unsigned int ep_available_trbs(struct tegra_xudc_ep *ep) 1073{ 1074 if (ep->ring_full) 1075 return 0; 1076 1077 if (ep->deq_ptr > ep->enq_ptr) 1078 return ep->deq_ptr - ep->enq_ptr - 1; 1079 1080 return XUDC_TRANSFER_RING_SIZE - (ep->enq_ptr - ep->deq_ptr) - 2; 1081} 1082 1083static void tegra_xudc_queue_one_trb(struct tegra_xudc_ep *ep, 1084 struct tegra_xudc_request *req, 1085 struct tegra_xudc_trb *trb, 1086 bool ioc) 1087{ 1088 struct tegra_xudc *xudc = ep->xudc; 1089 dma_addr_t buf_addr; 1090 size_t len; 1091 1092 len = min_t(size_t, XUDC_TRB_MAX_BUFFER_SIZE, req->usb_req.length - 1093 req->buf_queued); 1094 if (len > 0) 1095 buf_addr = req->usb_req.dma + req->buf_queued; 1096 else 1097 buf_addr = 0; 1098 1099 trb_write_data_ptr(trb, buf_addr); 1100 1101 trb_write_transfer_len(trb, len); 1102 trb_write_td_size(trb, req->trbs_needed - req->trbs_queued - 1); 1103 1104 if (req->trbs_queued == req->trbs_needed - 1 || 1105 (req->need_zlp && req->trbs_queued == req->trbs_needed - 2)) 1106 trb_write_chain(trb, 0); 1107 else 1108 trb_write_chain(trb, 1); 1109 1110 trb_write_ioc(trb, ioc); 1111 1112 if (usb_endpoint_dir_out(ep->desc) || 1113 (usb_endpoint_xfer_control(ep->desc) && 1114 (xudc->setup_state == DATA_STAGE_RECV))) 1115 trb_write_isp(trb, 1); 1116 else 1117 trb_write_isp(trb, 0); 1118 1119 if (usb_endpoint_xfer_control(ep->desc)) { 1120 if (xudc->setup_state == DATA_STAGE_XFER || 1121 xudc->setup_state == DATA_STAGE_RECV) 1122 trb_write_type(trb, TRB_TYPE_DATA_STAGE); 1123 else 1124 trb_write_type(trb, TRB_TYPE_STATUS_STAGE); 1125 1126 if (xudc->setup_state == DATA_STAGE_XFER || 1127 xudc->setup_state == STATUS_STAGE_XFER) 1128 trb_write_data_stage_dir(trb, 1); 1129 else 1130 trb_write_data_stage_dir(trb, 0); 1131 } else if (usb_endpoint_xfer_isoc(ep->desc)) { 1132 trb_write_type(trb, TRB_TYPE_ISOCH); 1133 trb_write_sia(trb, 1); 1134 trb_write_frame_id(trb, 0); 1135 trb_write_tlbpc(trb, 0); 1136 } else if (usb_ss_max_streams(ep->comp_desc)) { 1137 trb_write_type(trb, TRB_TYPE_STREAM); 1138 trb_write_stream_id(trb, req->usb_req.stream_id); 1139 } else { 1140 trb_write_type(trb, TRB_TYPE_NORMAL); 1141 trb_write_stream_id(trb, 0); 1142 } 1143 1144 trb_write_cycle(trb, ep->pcs); 1145 1146 req->trbs_queued++; 1147 req->buf_queued += len; 1148 1149 dump_trb(xudc, "TRANSFER", trb); 1150} 1151 1152static unsigned int tegra_xudc_queue_trbs(struct tegra_xudc_ep *ep, 1153 struct tegra_xudc_request *req) 1154{ 1155 unsigned int i, count, available; 1156 bool wait_td = false; 1157 1158 available = ep_available_trbs(ep); 1159 count = req->trbs_needed - req->trbs_queued; 1160 if (available < count) { 1161 count = available; 1162 ep->ring_full = true; 1163 } 1164 1165 /* 1166 * To generate zero-length packet on USB bus, SW needs schedule a 1167 * standalone zero-length TD. According to HW's behavior, SW needs 1168 * to schedule TDs in different ways for different endpoint types. 1169 * 1170 * For control endpoint: 1171 * - Data stage TD (IOC = 1, CH = 0) 1172 * - Ring doorbell and wait transfer event 1173 * - Data stage TD for ZLP (IOC = 1, CH = 0) 1174 * - Ring doorbell 1175 * 1176 * For bulk and interrupt endpoints: 1177 * - Normal transfer TD (IOC = 0, CH = 0) 1178 * - Normal transfer TD for ZLP (IOC = 1, CH = 0) 1179 * - Ring doorbell 1180 */ 1181 1182 if (req->need_zlp && usb_endpoint_xfer_control(ep->desc) && count > 1) 1183 wait_td = true; 1184 1185 if (!req->first_trb) 1186 req->first_trb = &ep->transfer_ring[ep->enq_ptr]; 1187 1188 for (i = 0; i < count; i++) { 1189 struct tegra_xudc_trb *trb = &ep->transfer_ring[ep->enq_ptr]; 1190 bool ioc = false; 1191 1192 if ((i == count - 1) || (wait_td && i == count - 2)) 1193 ioc = true; 1194 1195 tegra_xudc_queue_one_trb(ep, req, trb, ioc); 1196 req->last_trb = trb; 1197 1198 ep->enq_ptr++; 1199 if (ep->enq_ptr == XUDC_TRANSFER_RING_SIZE - 1) { 1200 trb = &ep->transfer_ring[ep->enq_ptr]; 1201 trb_write_cycle(trb, ep->pcs); 1202 ep->pcs = !ep->pcs; 1203 ep->enq_ptr = 0; 1204 } 1205 1206 if (ioc) 1207 break; 1208 } 1209 1210 return count; 1211} 1212 1213static void tegra_xudc_ep_ring_doorbell(struct tegra_xudc_ep *ep) 1214{ 1215 struct tegra_xudc *xudc = ep->xudc; 1216 u32 val; 1217 1218 if (list_empty(&ep->queue)) 1219 return; 1220 1221 val = DB_TARGET(ep->index); 1222 if (usb_endpoint_xfer_control(ep->desc)) { 1223 val |= DB_STREAMID(xudc->setup_seq_num); 1224 } else if (usb_ss_max_streams(ep->comp_desc) > 0) { 1225 struct tegra_xudc_request *req; 1226 1227 /* Don't ring doorbell if the stream has been rejected. */ 1228 if (ep->stream_rejected) 1229 return; 1230 1231 req = list_first_entry(&ep->queue, struct tegra_xudc_request, 1232 list); 1233 val |= DB_STREAMID(req->usb_req.stream_id); 1234 } 1235 1236 dev_dbg(xudc->dev, "ring doorbell: %#x\n", val); 1237 xudc_writel(xudc, val, DB); 1238} 1239 1240static void tegra_xudc_ep_kick_queue(struct tegra_xudc_ep *ep) 1241{ 1242 struct tegra_xudc_request *req; 1243 bool trbs_queued = false; 1244 1245 list_for_each_entry(req, &ep->queue, list) { 1246 if (ep->ring_full) 1247 break; 1248 1249 if (tegra_xudc_queue_trbs(ep, req) > 0) 1250 trbs_queued = true; 1251 } 1252 1253 if (trbs_queued) 1254 tegra_xudc_ep_ring_doorbell(ep); 1255} 1256 1257static int 1258__tegra_xudc_ep_queue(struct tegra_xudc_ep *ep, struct tegra_xudc_request *req) 1259{ 1260 struct tegra_xudc *xudc = ep->xudc; 1261 int err; 1262 1263 if (usb_endpoint_xfer_control(ep->desc) && !list_empty(&ep->queue)) { 1264 dev_err(xudc->dev, "control EP has pending transfers\n"); 1265 return -EINVAL; 1266 } 1267 1268 if (usb_endpoint_xfer_control(ep->desc)) { 1269 err = usb_gadget_map_request(&xudc->gadget, &req->usb_req, 1270 (xudc->setup_state == 1271 DATA_STAGE_XFER)); 1272 } else { 1273 err = usb_gadget_map_request(&xudc->gadget, &req->usb_req, 1274 usb_endpoint_dir_in(ep->desc)); 1275 } 1276 1277 if (err < 0) { 1278 dev_err(xudc->dev, "failed to map request: %d\n", err); 1279 return err; 1280 } 1281 1282 req->first_trb = NULL; 1283 req->last_trb = NULL; 1284 req->buf_queued = 0; 1285 req->trbs_queued = 0; 1286 req->need_zlp = false; 1287 req->trbs_needed = DIV_ROUND_UP(req->usb_req.length, 1288 XUDC_TRB_MAX_BUFFER_SIZE); 1289 if (req->usb_req.length == 0) 1290 req->trbs_needed++; 1291 1292 if (!usb_endpoint_xfer_isoc(ep->desc) && 1293 req->usb_req.zero && req->usb_req.length && 1294 ((req->usb_req.length % ep->usb_ep.maxpacket) == 0)) { 1295 req->trbs_needed++; 1296 req->need_zlp = true; 1297 } 1298 1299 req->usb_req.status = -EINPROGRESS; 1300 req->usb_req.actual = 0; 1301 1302 list_add_tail(&req->list, &ep->queue); 1303 1304 tegra_xudc_ep_kick_queue(ep); 1305 1306 return 0; 1307} 1308 1309static int 1310tegra_xudc_ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req, 1311 gfp_t gfp) 1312{ 1313 struct tegra_xudc_request *req; 1314 struct tegra_xudc_ep *ep; 1315 struct tegra_xudc *xudc; 1316 unsigned long flags; 1317 int ret; 1318 1319 if (!usb_ep || !usb_req) 1320 return -EINVAL; 1321 1322 ep = to_xudc_ep(usb_ep); 1323 req = to_xudc_req(usb_req); 1324 xudc = ep->xudc; 1325 1326 spin_lock_irqsave(&xudc->lock, flags); 1327 if (xudc->powergated || !ep->desc) { 1328 ret = -ESHUTDOWN; 1329 goto unlock; 1330 } 1331 1332 ret = __tegra_xudc_ep_queue(ep, req); 1333unlock: 1334 spin_unlock_irqrestore(&xudc->lock, flags); 1335 1336 return ret; 1337} 1338 1339static void squeeze_transfer_ring(struct tegra_xudc_ep *ep, 1340 struct tegra_xudc_request *req) 1341{ 1342 struct tegra_xudc_trb *trb = req->first_trb; 1343 bool pcs_enq = trb_read_cycle(trb); 1344 bool pcs; 1345 1346 /* 1347 * Clear out all the TRBs part of or after the cancelled request, 1348 * and must correct trb cycle bit to the last un-enqueued state. 1349 */ 1350 while (trb != &ep->transfer_ring[ep->enq_ptr]) { 1351 pcs = trb_read_cycle(trb); 1352 memset(trb, 0, sizeof(*trb)); 1353 trb_write_cycle(trb, !pcs); 1354 trb++; 1355 1356 if (trb_read_type(trb) == TRB_TYPE_LINK) 1357 trb = ep->transfer_ring; 1358 } 1359 1360 /* Requests will be re-queued at the start of the cancelled request. */ 1361 ep->enq_ptr = req->first_trb - ep->transfer_ring; 1362 /* 1363 * Retrieve the correct cycle bit state from the first trb of 1364 * the cancelled request. 1365 */ 1366 ep->pcs = pcs_enq; 1367 ep->ring_full = false; 1368 list_for_each_entry_continue(req, &ep->queue, list) { 1369 req->usb_req.status = -EINPROGRESS; 1370 req->usb_req.actual = 0; 1371 1372 req->first_trb = NULL; 1373 req->last_trb = NULL; 1374 req->buf_queued = 0; 1375 req->trbs_queued = 0; 1376 } 1377} 1378 1379/* 1380 * Determine if the given TRB is in the range [first trb, last trb] for the 1381 * given request. 1382 */ 1383static bool trb_in_request(struct tegra_xudc_ep *ep, 1384 struct tegra_xudc_request *req, 1385 struct tegra_xudc_trb *trb) 1386{ 1387 dev_dbg(ep->xudc->dev, "%s: request %p -> %p; trb %p\n", __func__, 1388 req->first_trb, req->last_trb, trb); 1389 1390 if (trb >= req->first_trb && (trb <= req->last_trb || 1391 req->last_trb < req->first_trb)) 1392 return true; 1393 1394 if (trb < req->first_trb && trb <= req->last_trb && 1395 req->last_trb < req->first_trb) 1396 return true; 1397 1398 return false; 1399} 1400 1401/* 1402 * Determine if the given TRB is in the range [EP enqueue pointer, first TRB) 1403 * for the given endpoint and request. 1404 */ 1405static bool trb_before_request(struct tegra_xudc_ep *ep, 1406 struct tegra_xudc_request *req, 1407 struct tegra_xudc_trb *trb) 1408{ 1409 struct tegra_xudc_trb *enq_trb = &ep->transfer_ring[ep->enq_ptr]; 1410 1411 dev_dbg(ep->xudc->dev, "%s: request %p -> %p; enq ptr: %p; trb %p\n", 1412 __func__, req->first_trb, req->last_trb, enq_trb, trb); 1413 1414 if (trb < req->first_trb && (enq_trb <= trb || 1415 req->first_trb < enq_trb)) 1416 return true; 1417 1418 if (trb > req->first_trb && req->first_trb < enq_trb && enq_trb <= trb) 1419 return true; 1420 1421 return false; 1422} 1423 1424static int 1425__tegra_xudc_ep_dequeue(struct tegra_xudc_ep *ep, 1426 struct tegra_xudc_request *req) 1427{ 1428 struct tegra_xudc *xudc = ep->xudc; 1429 struct tegra_xudc_request *r = NULL, *iter; 1430 struct tegra_xudc_trb *deq_trb; 1431 bool busy, kick_queue = false; 1432 int ret = 0; 1433 1434 /* Make sure the request is actually queued to this endpoint. */ 1435 list_for_each_entry(iter, &ep->queue, list) { 1436 if (iter != req) 1437 continue; 1438 r = iter; 1439 break; 1440 } 1441 1442 if (!r) 1443 return -EINVAL; 1444 1445 /* Request hasn't been queued in the transfer ring yet. */ 1446 if (!req->trbs_queued) { 1447 tegra_xudc_req_done(ep, req, -ECONNRESET); 1448 return 0; 1449 } 1450 1451 /* Halt DMA for this endpoint. */ 1452 if (ep_ctx_read_state(ep->context) == EP_STATE_RUNNING) { 1453 ep_pause(xudc, ep->index); 1454 ep_wait_for_inactive(xudc, ep->index); 1455 } 1456 1457 deq_trb = trb_phys_to_virt(ep, ep_ctx_read_deq_ptr(ep->context)); 1458 /* Is the hardware processing the TRB at the dequeue pointer? */ 1459 busy = (trb_read_cycle(deq_trb) == ep_ctx_read_dcs(ep->context)); 1460 1461 if (trb_in_request(ep, req, deq_trb) && busy) { 1462 /* 1463 * Request has been partially completed or it hasn't 1464 * started processing yet. 1465 */ 1466 dma_addr_t deq_ptr; 1467 1468 squeeze_transfer_ring(ep, req); 1469 1470 req->usb_req.actual = ep_ctx_read_edtla(ep->context); 1471 tegra_xudc_req_done(ep, req, -ECONNRESET); 1472 kick_queue = true; 1473 1474 /* EDTLA is > 0: request has been partially completed */ 1475 if (req->usb_req.actual > 0) { 1476 /* 1477 * Abort the pending transfer and update the dequeue 1478 * pointer 1479 */ 1480 ep_ctx_write_edtla(ep->context, 0); 1481 ep_ctx_write_partial_td(ep->context, 0); 1482 ep_ctx_write_data_offset(ep->context, 0); 1483 1484 deq_ptr = trb_virt_to_phys(ep, 1485 &ep->transfer_ring[ep->enq_ptr]); 1486 1487 if (dma_mapping_error(xudc->dev, deq_ptr)) { 1488 ret = -EINVAL; 1489 } else { 1490 ep_ctx_write_deq_ptr(ep->context, deq_ptr); 1491 ep_ctx_write_dcs(ep->context, ep->pcs); 1492 ep_reload(xudc, ep->index); 1493 } 1494 } 1495 } else if (trb_before_request(ep, req, deq_trb) && busy) { 1496 /* Request hasn't started processing yet. */ 1497 squeeze_transfer_ring(ep, req); 1498 1499 tegra_xudc_req_done(ep, req, -ECONNRESET); 1500 kick_queue = true; 1501 } else { 1502 /* 1503 * Request has completed, but we haven't processed the 1504 * completion event yet. 1505 */ 1506 tegra_xudc_req_done(ep, req, -ECONNRESET); 1507 ret = -EINVAL; 1508 } 1509 1510 /* Resume the endpoint. */ 1511 ep_unpause(xudc, ep->index); 1512 1513 if (kick_queue) 1514 tegra_xudc_ep_kick_queue(ep); 1515 1516 return ret; 1517} 1518 1519static int 1520tegra_xudc_ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req) 1521{ 1522 struct tegra_xudc_request *req; 1523 struct tegra_xudc_ep *ep; 1524 struct tegra_xudc *xudc; 1525 unsigned long flags; 1526 int ret; 1527 1528 if (!usb_ep || !usb_req) 1529 return -EINVAL; 1530 1531 ep = to_xudc_ep(usb_ep); 1532 req = to_xudc_req(usb_req); 1533 xudc = ep->xudc; 1534 1535 spin_lock_irqsave(&xudc->lock, flags); 1536 1537 if (xudc->powergated || !ep->desc) { 1538 ret = -ESHUTDOWN; 1539 goto unlock; 1540 } 1541 1542 ret = __tegra_xudc_ep_dequeue(ep, req); 1543unlock: 1544 spin_unlock_irqrestore(&xudc->lock, flags); 1545 1546 return ret; 1547} 1548 1549static int __tegra_xudc_ep_set_halt(struct tegra_xudc_ep *ep, bool halt) 1550{ 1551 struct tegra_xudc *xudc = ep->xudc; 1552 1553 if (!ep->desc) 1554 return -EINVAL; 1555 1556 if (usb_endpoint_xfer_isoc(ep->desc)) { 1557 dev_err(xudc->dev, "can't halt isochronous EP\n"); 1558 return -ENOTSUPP; 1559 } 1560 1561 if (halt) { 1562 ep_halt(xudc, ep->index); 1563 } else { 1564 ep_ctx_write_state(ep->context, EP_STATE_DISABLED); 1565 1566 ep_reload(xudc, ep->index); 1567 1568 ep_ctx_write_state(ep->context, EP_STATE_RUNNING); 1569 ep_ctx_write_rsvd(ep->context, 0); 1570 ep_ctx_write_partial_td(ep->context, 0); 1571 ep_ctx_write_splitxstate(ep->context, 0); 1572 ep_ctx_write_seq_num(ep->context, 0); 1573 1574 ep_reload(xudc, ep->index); 1575 ep_unpause(xudc, ep->index); 1576 ep_unhalt(xudc, ep->index); 1577 1578 tegra_xudc_ep_ring_doorbell(ep); 1579 } 1580 1581 return 0; 1582} 1583 1584static int tegra_xudc_ep_set_halt(struct usb_ep *usb_ep, int value) 1585{ 1586 struct tegra_xudc_ep *ep; 1587 struct tegra_xudc *xudc; 1588 unsigned long flags; 1589 int ret; 1590 1591 if (!usb_ep) 1592 return -EINVAL; 1593 1594 ep = to_xudc_ep(usb_ep); 1595 xudc = ep->xudc; 1596 1597 spin_lock_irqsave(&xudc->lock, flags); 1598 if (xudc->powergated) { 1599 ret = -ESHUTDOWN; 1600 goto unlock; 1601 } 1602 1603 if (value && usb_endpoint_dir_in(ep->desc) && 1604 !list_empty(&ep->queue)) { 1605 dev_err(xudc->dev, "can't halt EP with requests pending\n"); 1606 ret = -EAGAIN; 1607 goto unlock; 1608 } 1609 1610 ret = __tegra_xudc_ep_set_halt(ep, value); 1611unlock: 1612 spin_unlock_irqrestore(&xudc->lock, flags); 1613 1614 return ret; 1615} 1616 1617static void tegra_xudc_ep_context_setup(struct tegra_xudc_ep *ep) 1618{ 1619 const struct usb_endpoint_descriptor *desc = ep->desc; 1620 const struct usb_ss_ep_comp_descriptor *comp_desc = ep->comp_desc; 1621 struct tegra_xudc *xudc = ep->xudc; 1622 u16 maxpacket, maxburst = 0, esit = 0; 1623 u32 val; 1624 1625 maxpacket = usb_endpoint_maxp(desc); 1626 if (xudc->gadget.speed == USB_SPEED_SUPER) { 1627 if (!usb_endpoint_xfer_control(desc)) 1628 maxburst = comp_desc->bMaxBurst; 1629 1630 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) 1631 esit = le16_to_cpu(comp_desc->wBytesPerInterval); 1632 } else if ((xudc->gadget.speed < USB_SPEED_SUPER) && 1633 (usb_endpoint_xfer_int(desc) || 1634 usb_endpoint_xfer_isoc(desc))) { 1635 if (xudc->gadget.speed == USB_SPEED_HIGH) { 1636 maxburst = usb_endpoint_maxp_mult(desc) - 1; 1637 if (maxburst == 0x3) { 1638 dev_warn(xudc->dev, 1639 "invalid endpoint maxburst\n"); 1640 maxburst = 0x2; 1641 } 1642 } 1643 esit = maxpacket * (maxburst + 1); 1644 } 1645 1646 memset(ep->context, 0, sizeof(*ep->context)); 1647 1648 ep_ctx_write_state(ep->context, EP_STATE_RUNNING); 1649 ep_ctx_write_interval(ep->context, desc->bInterval); 1650 if (xudc->gadget.speed == USB_SPEED_SUPER) { 1651 if (usb_endpoint_xfer_isoc(desc)) { 1652 ep_ctx_write_mult(ep->context, 1653 comp_desc->bmAttributes & 0x3); 1654 } 1655 1656 if (usb_endpoint_xfer_bulk(desc)) { 1657 ep_ctx_write_max_pstreams(ep->context, 1658 comp_desc->bmAttributes & 1659 0x1f); 1660 ep_ctx_write_lsa(ep->context, 1); 1661 } 1662 } 1663 1664 if (!usb_endpoint_xfer_control(desc) && usb_endpoint_dir_out(desc)) 1665 val = usb_endpoint_type(desc); 1666 else 1667 val = usb_endpoint_type(desc) + EP_TYPE_CONTROL; 1668 1669 ep_ctx_write_type(ep->context, val); 1670 ep_ctx_write_cerr(ep->context, 0x3); 1671 ep_ctx_write_max_packet_size(ep->context, maxpacket); 1672 ep_ctx_write_max_burst_size(ep->context, maxburst); 1673 1674 ep_ctx_write_deq_ptr(ep->context, ep->transfer_ring_phys); 1675 ep_ctx_write_dcs(ep->context, ep->pcs); 1676 1677 /* Select a reasonable average TRB length based on endpoint type. */ 1678 switch (usb_endpoint_type(desc)) { 1679 case USB_ENDPOINT_XFER_CONTROL: 1680 val = 8; 1681 break; 1682 case USB_ENDPOINT_XFER_INT: 1683 val = 1024; 1684 break; 1685 case USB_ENDPOINT_XFER_BULK: 1686 case USB_ENDPOINT_XFER_ISOC: 1687 default: 1688 val = 3072; 1689 break; 1690 } 1691 1692 ep_ctx_write_avg_trb_len(ep->context, val); 1693 ep_ctx_write_max_esit_payload(ep->context, esit); 1694 1695 ep_ctx_write_cerrcnt(ep->context, 0x3); 1696} 1697 1698static void setup_link_trb(struct tegra_xudc_ep *ep, 1699 struct tegra_xudc_trb *trb) 1700{ 1701 trb_write_data_ptr(trb, ep->transfer_ring_phys); 1702 trb_write_type(trb, TRB_TYPE_LINK); 1703 trb_write_toggle_cycle(trb, 1); 1704} 1705 1706static int __tegra_xudc_ep_disable(struct tegra_xudc_ep *ep) 1707{ 1708 struct tegra_xudc *xudc = ep->xudc; 1709 1710 if (ep_ctx_read_state(ep->context) == EP_STATE_DISABLED) { 1711 dev_err(xudc->dev, "endpoint %u already disabled\n", 1712 ep->index); 1713 return -EINVAL; 1714 } 1715 1716 ep_ctx_write_state(ep->context, EP_STATE_DISABLED); 1717 1718 ep_reload(xudc, ep->index); 1719 1720 tegra_xudc_ep_nuke(ep, -ESHUTDOWN); 1721 1722 xudc->nr_enabled_eps--; 1723 if (usb_endpoint_xfer_isoc(ep->desc)) 1724 xudc->nr_isoch_eps--; 1725 1726 ep->desc = NULL; 1727 ep->comp_desc = NULL; 1728 1729 memset(ep->context, 0, sizeof(*ep->context)); 1730 1731 ep_unpause(xudc, ep->index); 1732 ep_unhalt(xudc, ep->index); 1733 if (xudc_readl(xudc, EP_STOPPED) & BIT(ep->index)) 1734 xudc_writel(xudc, BIT(ep->index), EP_STOPPED); 1735 1736 /* 1737 * If this is the last endpoint disabled in a de-configure request, 1738 * switch back to address state. 1739 */ 1740 if ((xudc->device_state == USB_STATE_CONFIGURED) && 1741 (xudc->nr_enabled_eps == 1)) { 1742 u32 val; 1743 1744 xudc->device_state = USB_STATE_ADDRESS; 1745 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 1746 1747 val = xudc_readl(xudc, CTRL); 1748 val &= ~CTRL_RUN; 1749 xudc_writel(xudc, val, CTRL); 1750 1751 val = xudc_readl(xudc, ST); 1752 if (val & ST_RC) 1753 xudc_writel(xudc, ST_RC, ST); 1754 } 1755 1756 dev_info(xudc->dev, "ep %u disabled\n", ep->index); 1757 1758 return 0; 1759} 1760 1761static int tegra_xudc_ep_disable(struct usb_ep *usb_ep) 1762{ 1763 struct tegra_xudc_ep *ep; 1764 struct tegra_xudc *xudc; 1765 unsigned long flags; 1766 int ret; 1767 1768 if (!usb_ep) 1769 return -EINVAL; 1770 1771 ep = to_xudc_ep(usb_ep); 1772 xudc = ep->xudc; 1773 1774 spin_lock_irqsave(&xudc->lock, flags); 1775 if (xudc->powergated) { 1776 ret = -ESHUTDOWN; 1777 goto unlock; 1778 } 1779 1780 ret = __tegra_xudc_ep_disable(ep); 1781unlock: 1782 spin_unlock_irqrestore(&xudc->lock, flags); 1783 1784 return ret; 1785} 1786 1787static int __tegra_xudc_ep_enable(struct tegra_xudc_ep *ep, 1788 const struct usb_endpoint_descriptor *desc) 1789{ 1790 struct tegra_xudc *xudc = ep->xudc; 1791 unsigned int i; 1792 u32 val; 1793 1794 if (xudc->gadget.speed == USB_SPEED_SUPER && 1795 !usb_endpoint_xfer_control(desc) && !ep->usb_ep.comp_desc) 1796 return -EINVAL; 1797 1798 /* Disable the EP if it is not disabled */ 1799 if (ep_ctx_read_state(ep->context) != EP_STATE_DISABLED) 1800 __tegra_xudc_ep_disable(ep); 1801 1802 ep->desc = desc; 1803 ep->comp_desc = ep->usb_ep.comp_desc; 1804 1805 if (usb_endpoint_xfer_isoc(desc)) { 1806 if (xudc->nr_isoch_eps > XUDC_MAX_ISOCH_EPS) { 1807 dev_err(xudc->dev, "too many isochronous endpoints\n"); 1808 return -EBUSY; 1809 } 1810 xudc->nr_isoch_eps++; 1811 } 1812 1813 memset(ep->transfer_ring, 0, XUDC_TRANSFER_RING_SIZE * 1814 sizeof(*ep->transfer_ring)); 1815 setup_link_trb(ep, &ep->transfer_ring[XUDC_TRANSFER_RING_SIZE - 1]); 1816 1817 ep->enq_ptr = 0; 1818 ep->deq_ptr = 0; 1819 ep->pcs = true; 1820 ep->ring_full = false; 1821 xudc->nr_enabled_eps++; 1822 1823 tegra_xudc_ep_context_setup(ep); 1824 1825 /* 1826 * No need to reload and un-halt EP0. This will be done automatically 1827 * once a valid SETUP packet is received. 1828 */ 1829 if (usb_endpoint_xfer_control(desc)) 1830 goto out; 1831 1832 /* 1833 * Transition to configured state once the first non-control 1834 * endpoint is enabled. 1835 */ 1836 if (xudc->device_state == USB_STATE_ADDRESS) { 1837 val = xudc_readl(xudc, CTRL); 1838 val |= CTRL_RUN; 1839 xudc_writel(xudc, val, CTRL); 1840 1841 xudc->device_state = USB_STATE_CONFIGURED; 1842 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 1843 } 1844 1845 if (usb_endpoint_xfer_isoc(desc)) { 1846 /* 1847 * Pause all bulk endpoints when enabling an isoch endpoint 1848 * to ensure the isoch endpoint is allocated enough bandwidth. 1849 */ 1850 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) { 1851 if (xudc->ep[i].desc && 1852 usb_endpoint_xfer_bulk(xudc->ep[i].desc)) 1853 ep_pause(xudc, i); 1854 } 1855 } 1856 1857 ep_reload(xudc, ep->index); 1858 ep_unpause(xudc, ep->index); 1859 ep_unhalt(xudc, ep->index); 1860 1861 if (usb_endpoint_xfer_isoc(desc)) { 1862 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) { 1863 if (xudc->ep[i].desc && 1864 usb_endpoint_xfer_bulk(xudc->ep[i].desc)) 1865 ep_unpause(xudc, i); 1866 } 1867 } 1868 1869out: 1870 dev_info(xudc->dev, "EP %u (type: %s, dir: %s) enabled\n", ep->index, 1871 usb_ep_type_string(usb_endpoint_type(ep->desc)), 1872 usb_endpoint_dir_in(ep->desc) ? "in" : "out"); 1873 1874 return 0; 1875} 1876 1877static int tegra_xudc_ep_enable(struct usb_ep *usb_ep, 1878 const struct usb_endpoint_descriptor *desc) 1879{ 1880 struct tegra_xudc_ep *ep; 1881 struct tegra_xudc *xudc; 1882 unsigned long flags; 1883 int ret; 1884 1885 if (!usb_ep || !desc || (desc->bDescriptorType != USB_DT_ENDPOINT)) 1886 return -EINVAL; 1887 1888 ep = to_xudc_ep(usb_ep); 1889 xudc = ep->xudc; 1890 1891 spin_lock_irqsave(&xudc->lock, flags); 1892 if (xudc->powergated) { 1893 ret = -ESHUTDOWN; 1894 goto unlock; 1895 } 1896 1897 ret = __tegra_xudc_ep_enable(ep, desc); 1898unlock: 1899 spin_unlock_irqrestore(&xudc->lock, flags); 1900 1901 return ret; 1902} 1903 1904static struct usb_request * 1905tegra_xudc_ep_alloc_request(struct usb_ep *usb_ep, gfp_t gfp) 1906{ 1907 struct tegra_xudc_request *req; 1908 1909 req = kzalloc(sizeof(*req), gfp); 1910 if (!req) 1911 return NULL; 1912 1913 INIT_LIST_HEAD(&req->list); 1914 1915 return &req->usb_req; 1916} 1917 1918static void tegra_xudc_ep_free_request(struct usb_ep *usb_ep, 1919 struct usb_request *usb_req) 1920{ 1921 struct tegra_xudc_request *req = to_xudc_req(usb_req); 1922 1923 kfree(req); 1924} 1925 1926static const struct usb_ep_ops tegra_xudc_ep_ops = { 1927 .enable = tegra_xudc_ep_enable, 1928 .disable = tegra_xudc_ep_disable, 1929 .alloc_request = tegra_xudc_ep_alloc_request, 1930 .free_request = tegra_xudc_ep_free_request, 1931 .queue = tegra_xudc_ep_queue, 1932 .dequeue = tegra_xudc_ep_dequeue, 1933 .set_halt = tegra_xudc_ep_set_halt, 1934}; 1935 1936static int tegra_xudc_ep0_enable(struct usb_ep *usb_ep, 1937 const struct usb_endpoint_descriptor *desc) 1938{ 1939 return -EBUSY; 1940} 1941 1942static int tegra_xudc_ep0_disable(struct usb_ep *usb_ep) 1943{ 1944 return -EBUSY; 1945} 1946 1947static const struct usb_ep_ops tegra_xudc_ep0_ops = { 1948 .enable = tegra_xudc_ep0_enable, 1949 .disable = tegra_xudc_ep0_disable, 1950 .alloc_request = tegra_xudc_ep_alloc_request, 1951 .free_request = tegra_xudc_ep_free_request, 1952 .queue = tegra_xudc_ep_queue, 1953 .dequeue = tegra_xudc_ep_dequeue, 1954 .set_halt = tegra_xudc_ep_set_halt, 1955}; 1956 1957static int tegra_xudc_gadget_get_frame(struct usb_gadget *gadget) 1958{ 1959 struct tegra_xudc *xudc = to_xudc(gadget); 1960 unsigned long flags; 1961 int ret; 1962 1963 spin_lock_irqsave(&xudc->lock, flags); 1964 if (xudc->powergated) { 1965 ret = -ESHUTDOWN; 1966 goto unlock; 1967 } 1968 1969 ret = (xudc_readl(xudc, MFINDEX) & MFINDEX_FRAME_MASK) >> 1970 MFINDEX_FRAME_SHIFT; 1971unlock: 1972 spin_unlock_irqrestore(&xudc->lock, flags); 1973 1974 return ret; 1975} 1976 1977static void tegra_xudc_resume_device_state(struct tegra_xudc *xudc) 1978{ 1979 unsigned int i; 1980 u32 val; 1981 1982 ep_unpause_all(xudc); 1983 1984 /* Direct link to U0. */ 1985 val = xudc_readl(xudc, PORTSC); 1986 if (((val & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT) != PORTSC_PLS_U0) { 1987 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK); 1988 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_U0); 1989 xudc_writel(xudc, val, PORTSC); 1990 } 1991 1992 if (xudc->device_state == USB_STATE_SUSPENDED) { 1993 xudc->device_state = xudc->resume_state; 1994 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 1995 xudc->resume_state = 0; 1996 } 1997 1998 /* 1999 * Doorbells may be dropped if they are sent too soon (< ~200ns) 2000 * after unpausing the endpoint. Wait for 500ns just to be safe. 2001 */ 2002 ndelay(500); 2003 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) 2004 tegra_xudc_ep_ring_doorbell(&xudc->ep[i]); 2005} 2006 2007static int tegra_xudc_gadget_wakeup(struct usb_gadget *gadget) 2008{ 2009 struct tegra_xudc *xudc = to_xudc(gadget); 2010 unsigned long flags; 2011 int ret = 0; 2012 u32 val; 2013 2014 spin_lock_irqsave(&xudc->lock, flags); 2015 2016 if (xudc->powergated) { 2017 ret = -ESHUTDOWN; 2018 goto unlock; 2019 } 2020 val = xudc_readl(xudc, PORTPM); 2021 dev_dbg(xudc->dev, "%s: PORTPM=%#x, speed=%x\n", __func__, 2022 val, gadget->speed); 2023 2024 if (((xudc->gadget.speed <= USB_SPEED_HIGH) && 2025 (val & PORTPM_RWE)) || 2026 ((xudc->gadget.speed == USB_SPEED_SUPER) && 2027 (val & PORTPM_FRWE))) { 2028 tegra_xudc_resume_device_state(xudc); 2029 2030 /* Send Device Notification packet. */ 2031 if (xudc->gadget.speed == USB_SPEED_SUPER) { 2032 val = DEVNOTIF_LO_TYPE(DEVNOTIF_LO_TYPE_FUNCTION_WAKE) 2033 | DEVNOTIF_LO_TRIG; 2034 xudc_writel(xudc, 0, DEVNOTIF_HI); 2035 xudc_writel(xudc, val, DEVNOTIF_LO); 2036 } 2037 } 2038 2039unlock: 2040 dev_dbg(xudc->dev, "%s: ret value is %d", __func__, ret); 2041 spin_unlock_irqrestore(&xudc->lock, flags); 2042 2043 return ret; 2044} 2045 2046static int tegra_xudc_gadget_pullup(struct usb_gadget *gadget, int is_on) 2047{ 2048 struct tegra_xudc *xudc = to_xudc(gadget); 2049 unsigned long flags; 2050 u32 val; 2051 2052 pm_runtime_get_sync(xudc->dev); 2053 2054 spin_lock_irqsave(&xudc->lock, flags); 2055 2056 if (is_on != xudc->pullup) { 2057 val = xudc_readl(xudc, CTRL); 2058 if (is_on) 2059 val |= CTRL_ENABLE; 2060 else 2061 val &= ~CTRL_ENABLE; 2062 xudc_writel(xudc, val, CTRL); 2063 } 2064 2065 xudc->pullup = is_on; 2066 dev_dbg(xudc->dev, "%s: pullup:%d", __func__, is_on); 2067 2068 spin_unlock_irqrestore(&xudc->lock, flags); 2069 2070 pm_runtime_put(xudc->dev); 2071 2072 return 0; 2073} 2074 2075static int tegra_xudc_gadget_start(struct usb_gadget *gadget, 2076 struct usb_gadget_driver *driver) 2077{ 2078 struct tegra_xudc *xudc = to_xudc(gadget); 2079 unsigned long flags; 2080 u32 val; 2081 int ret; 2082 unsigned int i; 2083 2084 if (!driver) 2085 return -EINVAL; 2086 2087 pm_runtime_get_sync(xudc->dev); 2088 2089 spin_lock_irqsave(&xudc->lock, flags); 2090 2091 if (xudc->driver) { 2092 ret = -EBUSY; 2093 goto unlock; 2094 } 2095 2096 xudc->setup_state = WAIT_FOR_SETUP; 2097 xudc->device_state = USB_STATE_DEFAULT; 2098 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 2099 2100 ret = __tegra_xudc_ep_enable(&xudc->ep[0], &tegra_xudc_ep0_desc); 2101 if (ret < 0) 2102 goto unlock; 2103 2104 val = xudc_readl(xudc, CTRL); 2105 val |= CTRL_IE | CTRL_LSE; 2106 xudc_writel(xudc, val, CTRL); 2107 2108 val = xudc_readl(xudc, PORTHALT); 2109 val |= PORTHALT_STCHG_INTR_EN; 2110 xudc_writel(xudc, val, PORTHALT); 2111 2112 if (xudc->pullup) { 2113 val = xudc_readl(xudc, CTRL); 2114 val |= CTRL_ENABLE; 2115 xudc_writel(xudc, val, CTRL); 2116 } 2117 2118 for (i = 0; i < xudc->soc->num_phys; i++) 2119 if (xudc->usbphy[i]) 2120 otg_set_peripheral(xudc->usbphy[i]->otg, gadget); 2121 2122 xudc->driver = driver; 2123unlock: 2124 dev_dbg(xudc->dev, "%s: ret value is %d", __func__, ret); 2125 spin_unlock_irqrestore(&xudc->lock, flags); 2126 2127 pm_runtime_put(xudc->dev); 2128 2129 return ret; 2130} 2131 2132static int tegra_xudc_gadget_stop(struct usb_gadget *gadget) 2133{ 2134 struct tegra_xudc *xudc = to_xudc(gadget); 2135 unsigned long flags; 2136 u32 val; 2137 unsigned int i; 2138 2139 pm_runtime_get_sync(xudc->dev); 2140 2141 spin_lock_irqsave(&xudc->lock, flags); 2142 2143 for (i = 0; i < xudc->soc->num_phys; i++) 2144 if (xudc->usbphy[i]) 2145 otg_set_peripheral(xudc->usbphy[i]->otg, NULL); 2146 2147 val = xudc_readl(xudc, CTRL); 2148 val &= ~(CTRL_IE | CTRL_ENABLE); 2149 xudc_writel(xudc, val, CTRL); 2150 2151 __tegra_xudc_ep_disable(&xudc->ep[0]); 2152 2153 xudc->driver = NULL; 2154 dev_dbg(xudc->dev, "Gadget stopped"); 2155 2156 spin_unlock_irqrestore(&xudc->lock, flags); 2157 2158 pm_runtime_put(xudc->dev); 2159 2160 return 0; 2161} 2162 2163static int tegra_xudc_gadget_vbus_draw(struct usb_gadget *gadget, 2164 unsigned int m_a) 2165{ 2166 struct tegra_xudc *xudc = to_xudc(gadget); 2167 2168 dev_dbg(xudc->dev, "%s: %u mA\n", __func__, m_a); 2169 2170 if (xudc->curr_usbphy && xudc->curr_usbphy->chg_type == SDP_TYPE) 2171 return usb_phy_set_power(xudc->curr_usbphy, m_a); 2172 2173 return 0; 2174} 2175 2176static int tegra_xudc_set_selfpowered(struct usb_gadget *gadget, int is_on) 2177{ 2178 struct tegra_xudc *xudc = to_xudc(gadget); 2179 2180 dev_dbg(xudc->dev, "%s: %d\n", __func__, is_on); 2181 xudc->selfpowered = !!is_on; 2182 2183 return 0; 2184} 2185 2186static const struct usb_gadget_ops tegra_xudc_gadget_ops = { 2187 .get_frame = tegra_xudc_gadget_get_frame, 2188 .wakeup = tegra_xudc_gadget_wakeup, 2189 .pullup = tegra_xudc_gadget_pullup, 2190 .udc_start = tegra_xudc_gadget_start, 2191 .udc_stop = tegra_xudc_gadget_stop, 2192 .vbus_draw = tegra_xudc_gadget_vbus_draw, 2193 .set_selfpowered = tegra_xudc_set_selfpowered, 2194}; 2195 2196static void no_op_complete(struct usb_ep *ep, struct usb_request *req) 2197{ 2198} 2199 2200static int 2201tegra_xudc_ep0_queue_status(struct tegra_xudc *xudc, 2202 void (*cmpl)(struct usb_ep *, struct usb_request *)) 2203{ 2204 xudc->ep0_req->usb_req.buf = NULL; 2205 xudc->ep0_req->usb_req.dma = 0; 2206 xudc->ep0_req->usb_req.length = 0; 2207 xudc->ep0_req->usb_req.complete = cmpl; 2208 xudc->ep0_req->usb_req.context = xudc; 2209 2210 return __tegra_xudc_ep_queue(&xudc->ep[0], xudc->ep0_req); 2211} 2212 2213static int 2214tegra_xudc_ep0_queue_data(struct tegra_xudc *xudc, void *buf, size_t len, 2215 void (*cmpl)(struct usb_ep *, struct usb_request *)) 2216{ 2217 xudc->ep0_req->usb_req.buf = buf; 2218 xudc->ep0_req->usb_req.length = len; 2219 xudc->ep0_req->usb_req.complete = cmpl; 2220 xudc->ep0_req->usb_req.context = xudc; 2221 2222 return __tegra_xudc_ep_queue(&xudc->ep[0], xudc->ep0_req); 2223} 2224 2225static void tegra_xudc_ep0_req_done(struct tegra_xudc *xudc) 2226{ 2227 switch (xudc->setup_state) { 2228 case DATA_STAGE_XFER: 2229 xudc->setup_state = STATUS_STAGE_RECV; 2230 tegra_xudc_ep0_queue_status(xudc, no_op_complete); 2231 break; 2232 case DATA_STAGE_RECV: 2233 xudc->setup_state = STATUS_STAGE_XFER; 2234 tegra_xudc_ep0_queue_status(xudc, no_op_complete); 2235 break; 2236 default: 2237 xudc->setup_state = WAIT_FOR_SETUP; 2238 break; 2239 } 2240} 2241 2242static int tegra_xudc_ep0_delegate_req(struct tegra_xudc *xudc, 2243 struct usb_ctrlrequest *ctrl) 2244{ 2245 int ret; 2246 2247 spin_unlock(&xudc->lock); 2248 ret = xudc->driver->setup(&xudc->gadget, ctrl); 2249 spin_lock(&xudc->lock); 2250 2251 return ret; 2252} 2253 2254static void set_feature_complete(struct usb_ep *ep, struct usb_request *req) 2255{ 2256 struct tegra_xudc *xudc = req->context; 2257 2258 if (xudc->test_mode_pattern) { 2259 xudc_writel(xudc, xudc->test_mode_pattern, PORT_TM); 2260 xudc->test_mode_pattern = 0; 2261 } 2262} 2263 2264static int tegra_xudc_ep0_set_feature(struct tegra_xudc *xudc, 2265 struct usb_ctrlrequest *ctrl) 2266{ 2267 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); 2268 u32 feature = le16_to_cpu(ctrl->wValue); 2269 u32 index = le16_to_cpu(ctrl->wIndex); 2270 u32 val, ep; 2271 int ret; 2272 2273 if (le16_to_cpu(ctrl->wLength) != 0) 2274 return -EINVAL; 2275 2276 switch (ctrl->bRequestType & USB_RECIP_MASK) { 2277 case USB_RECIP_DEVICE: 2278 switch (feature) { 2279 case USB_DEVICE_REMOTE_WAKEUP: 2280 if ((xudc->gadget.speed == USB_SPEED_SUPER) || 2281 (xudc->device_state == USB_STATE_DEFAULT)) 2282 return -EINVAL; 2283 2284 val = xudc_readl(xudc, PORTPM); 2285 if (set) 2286 val |= PORTPM_RWE; 2287 else 2288 val &= ~PORTPM_RWE; 2289 2290 xudc_writel(xudc, val, PORTPM); 2291 break; 2292 case USB_DEVICE_U1_ENABLE: 2293 case USB_DEVICE_U2_ENABLE: 2294 if ((xudc->device_state != USB_STATE_CONFIGURED) || 2295 (xudc->gadget.speed != USB_SPEED_SUPER)) 2296 return -EINVAL; 2297 2298 val = xudc_readl(xudc, PORTPM); 2299 if ((feature == USB_DEVICE_U1_ENABLE) && 2300 xudc->soc->u1_enable) { 2301 if (set) 2302 val |= PORTPM_U1E; 2303 else 2304 val &= ~PORTPM_U1E; 2305 } 2306 2307 if ((feature == USB_DEVICE_U2_ENABLE) && 2308 xudc->soc->u2_enable) { 2309 if (set) 2310 val |= PORTPM_U2E; 2311 else 2312 val &= ~PORTPM_U2E; 2313 } 2314 2315 xudc_writel(xudc, val, PORTPM); 2316 break; 2317 case USB_DEVICE_TEST_MODE: 2318 if (xudc->gadget.speed != USB_SPEED_HIGH) 2319 return -EINVAL; 2320 2321 if (!set) 2322 return -EINVAL; 2323 2324 xudc->test_mode_pattern = index >> 8; 2325 break; 2326 default: 2327 return -EINVAL; 2328 } 2329 2330 break; 2331 case USB_RECIP_INTERFACE: 2332 if (xudc->device_state != USB_STATE_CONFIGURED) 2333 return -EINVAL; 2334 2335 switch (feature) { 2336 case USB_INTRF_FUNC_SUSPEND: 2337 if (set) { 2338 val = xudc_readl(xudc, PORTPM); 2339 2340 if (index & USB_INTRF_FUNC_SUSPEND_RW) 2341 val |= PORTPM_FRWE; 2342 else 2343 val &= ~PORTPM_FRWE; 2344 2345 xudc_writel(xudc, val, PORTPM); 2346 } 2347 2348 return tegra_xudc_ep0_delegate_req(xudc, ctrl); 2349 default: 2350 return -EINVAL; 2351 } 2352 2353 break; 2354 case USB_RECIP_ENDPOINT: 2355 ep = (index & USB_ENDPOINT_NUMBER_MASK) * 2 + 2356 ((index & USB_DIR_IN) ? 1 : 0); 2357 2358 if ((xudc->device_state == USB_STATE_DEFAULT) || 2359 ((xudc->device_state == USB_STATE_ADDRESS) && 2360 (index != 0))) 2361 return -EINVAL; 2362 2363 ret = __tegra_xudc_ep_set_halt(&xudc->ep[ep], set); 2364 if (ret < 0) 2365 return ret; 2366 break; 2367 default: 2368 return -EINVAL; 2369 } 2370 2371 return tegra_xudc_ep0_queue_status(xudc, set_feature_complete); 2372} 2373 2374static int tegra_xudc_ep0_get_status(struct tegra_xudc *xudc, 2375 struct usb_ctrlrequest *ctrl) 2376{ 2377 struct tegra_xudc_ep_context *ep_ctx; 2378 u32 val, ep, index = le16_to_cpu(ctrl->wIndex); 2379 u16 status = 0; 2380 2381 if (!(ctrl->bRequestType & USB_DIR_IN)) 2382 return -EINVAL; 2383 2384 if ((le16_to_cpu(ctrl->wValue) != 0) || 2385 (le16_to_cpu(ctrl->wLength) != 2)) 2386 return -EINVAL; 2387 2388 switch (ctrl->bRequestType & USB_RECIP_MASK) { 2389 case USB_RECIP_DEVICE: 2390 val = xudc_readl(xudc, PORTPM); 2391 2392 if (xudc->selfpowered) 2393 status |= BIT(USB_DEVICE_SELF_POWERED); 2394 2395 if ((xudc->gadget.speed < USB_SPEED_SUPER) && 2396 (val & PORTPM_RWE)) 2397 status |= BIT(USB_DEVICE_REMOTE_WAKEUP); 2398 2399 if (xudc->gadget.speed == USB_SPEED_SUPER) { 2400 if (val & PORTPM_U1E) 2401 status |= BIT(USB_DEV_STAT_U1_ENABLED); 2402 if (val & PORTPM_U2E) 2403 status |= BIT(USB_DEV_STAT_U2_ENABLED); 2404 } 2405 break; 2406 case USB_RECIP_INTERFACE: 2407 if (xudc->gadget.speed == USB_SPEED_SUPER) { 2408 status |= USB_INTRF_STAT_FUNC_RW_CAP; 2409 val = xudc_readl(xudc, PORTPM); 2410 if (val & PORTPM_FRWE) 2411 status |= USB_INTRF_STAT_FUNC_RW; 2412 } 2413 break; 2414 case USB_RECIP_ENDPOINT: 2415 ep = (index & USB_ENDPOINT_NUMBER_MASK) * 2 + 2416 ((index & USB_DIR_IN) ? 1 : 0); 2417 ep_ctx = &xudc->ep_context[ep]; 2418 2419 if ((xudc->device_state != USB_STATE_CONFIGURED) && 2420 ((xudc->device_state != USB_STATE_ADDRESS) || (ep != 0))) 2421 return -EINVAL; 2422 2423 if (ep_ctx_read_state(ep_ctx) == EP_STATE_DISABLED) 2424 return -EINVAL; 2425 2426 if (xudc_readl(xudc, EP_HALT) & BIT(ep)) 2427 status |= BIT(USB_ENDPOINT_HALT); 2428 break; 2429 default: 2430 return -EINVAL; 2431 } 2432 2433 xudc->status_buf = cpu_to_le16(status); 2434 return tegra_xudc_ep0_queue_data(xudc, &xudc->status_buf, 2435 sizeof(xudc->status_buf), 2436 no_op_complete); 2437} 2438 2439static void set_sel_complete(struct usb_ep *ep, struct usb_request *req) 2440{ 2441 /* Nothing to do with SEL values */ 2442} 2443 2444static int tegra_xudc_ep0_set_sel(struct tegra_xudc *xudc, 2445 struct usb_ctrlrequest *ctrl) 2446{ 2447 if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE | 2448 USB_TYPE_STANDARD)) 2449 return -EINVAL; 2450 2451 if (xudc->device_state == USB_STATE_DEFAULT) 2452 return -EINVAL; 2453 2454 if ((le16_to_cpu(ctrl->wIndex) != 0) || 2455 (le16_to_cpu(ctrl->wValue) != 0) || 2456 (le16_to_cpu(ctrl->wLength) != 6)) 2457 return -EINVAL; 2458 2459 return tegra_xudc_ep0_queue_data(xudc, &xudc->sel_timing, 2460 sizeof(xudc->sel_timing), 2461 set_sel_complete); 2462} 2463 2464static void set_isoch_delay_complete(struct usb_ep *ep, struct usb_request *req) 2465{ 2466 /* Nothing to do with isoch delay */ 2467} 2468 2469static int tegra_xudc_ep0_set_isoch_delay(struct tegra_xudc *xudc, 2470 struct usb_ctrlrequest *ctrl) 2471{ 2472 u32 delay = le16_to_cpu(ctrl->wValue); 2473 2474 if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE | 2475 USB_TYPE_STANDARD)) 2476 return -EINVAL; 2477 2478 if ((delay > 65535) || (le16_to_cpu(ctrl->wIndex) != 0) || 2479 (le16_to_cpu(ctrl->wLength) != 0)) 2480 return -EINVAL; 2481 2482 xudc->isoch_delay = delay; 2483 2484 return tegra_xudc_ep0_queue_status(xudc, set_isoch_delay_complete); 2485} 2486 2487static void set_address_complete(struct usb_ep *ep, struct usb_request *req) 2488{ 2489 struct tegra_xudc *xudc = req->context; 2490 2491 if ((xudc->device_state == USB_STATE_DEFAULT) && 2492 (xudc->dev_addr != 0)) { 2493 xudc->device_state = USB_STATE_ADDRESS; 2494 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 2495 } else if ((xudc->device_state == USB_STATE_ADDRESS) && 2496 (xudc->dev_addr == 0)) { 2497 xudc->device_state = USB_STATE_DEFAULT; 2498 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 2499 } 2500} 2501 2502static int tegra_xudc_ep0_set_address(struct tegra_xudc *xudc, 2503 struct usb_ctrlrequest *ctrl) 2504{ 2505 struct tegra_xudc_ep *ep0 = &xudc->ep[0]; 2506 u32 val, addr = le16_to_cpu(ctrl->wValue); 2507 2508 if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE | 2509 USB_TYPE_STANDARD)) 2510 return -EINVAL; 2511 2512 if ((addr > 127) || (le16_to_cpu(ctrl->wIndex) != 0) || 2513 (le16_to_cpu(ctrl->wLength) != 0)) 2514 return -EINVAL; 2515 2516 if (xudc->device_state == USB_STATE_CONFIGURED) 2517 return -EINVAL; 2518 2519 dev_dbg(xudc->dev, "set address: %u\n", addr); 2520 2521 xudc->dev_addr = addr; 2522 val = xudc_readl(xudc, CTRL); 2523 val &= ~(CTRL_DEVADDR_MASK); 2524 val |= CTRL_DEVADDR(addr); 2525 xudc_writel(xudc, val, CTRL); 2526 2527 ep_ctx_write_devaddr(ep0->context, addr); 2528 2529 return tegra_xudc_ep0_queue_status(xudc, set_address_complete); 2530} 2531 2532static int tegra_xudc_ep0_standard_req(struct tegra_xudc *xudc, 2533 struct usb_ctrlrequest *ctrl) 2534{ 2535 int ret; 2536 2537 switch (ctrl->bRequest) { 2538 case USB_REQ_GET_STATUS: 2539 dev_dbg(xudc->dev, "USB_REQ_GET_STATUS\n"); 2540 ret = tegra_xudc_ep0_get_status(xudc, ctrl); 2541 break; 2542 case USB_REQ_SET_ADDRESS: 2543 dev_dbg(xudc->dev, "USB_REQ_SET_ADDRESS\n"); 2544 ret = tegra_xudc_ep0_set_address(xudc, ctrl); 2545 break; 2546 case USB_REQ_SET_SEL: 2547 dev_dbg(xudc->dev, "USB_REQ_SET_SEL\n"); 2548 ret = tegra_xudc_ep0_set_sel(xudc, ctrl); 2549 break; 2550 case USB_REQ_SET_ISOCH_DELAY: 2551 dev_dbg(xudc->dev, "USB_REQ_SET_ISOCH_DELAY\n"); 2552 ret = tegra_xudc_ep0_set_isoch_delay(xudc, ctrl); 2553 break; 2554 case USB_REQ_CLEAR_FEATURE: 2555 case USB_REQ_SET_FEATURE: 2556 dev_dbg(xudc->dev, "USB_REQ_CLEAR/SET_FEATURE\n"); 2557 ret = tegra_xudc_ep0_set_feature(xudc, ctrl); 2558 break; 2559 case USB_REQ_SET_CONFIGURATION: 2560 dev_dbg(xudc->dev, "USB_REQ_SET_CONFIGURATION\n"); 2561 /* 2562 * In theory we need to clear RUN bit before status stage of 2563 * deconfig request sent, but this seems to be causing problems. 2564 * Clear RUN once all endpoints are disabled instead. 2565 */ 2566 fallthrough; 2567 default: 2568 ret = tegra_xudc_ep0_delegate_req(xudc, ctrl); 2569 break; 2570 } 2571 2572 return ret; 2573} 2574 2575static void tegra_xudc_handle_ep0_setup_packet(struct tegra_xudc *xudc, 2576 struct usb_ctrlrequest *ctrl, 2577 u16 seq_num) 2578{ 2579 int ret; 2580 2581 xudc->setup_seq_num = seq_num; 2582 2583 /* Ensure EP0 is unhalted. */ 2584 ep_unhalt(xudc, 0); 2585 2586 /* 2587 * On Tegra210, setup packets with sequence numbers 0xfffe or 0xffff 2588 * are invalid. Halt EP0 until we get a valid packet. 2589 */ 2590 if (xudc->soc->invalid_seq_num && 2591 (seq_num == 0xfffe || seq_num == 0xffff)) { 2592 dev_warn(xudc->dev, "invalid sequence number detected\n"); 2593 ep_halt(xudc, 0); 2594 return; 2595 } 2596 2597 if (ctrl->wLength) 2598 xudc->setup_state = (ctrl->bRequestType & USB_DIR_IN) ? 2599 DATA_STAGE_XFER : DATA_STAGE_RECV; 2600 else 2601 xudc->setup_state = STATUS_STAGE_XFER; 2602 2603 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 2604 ret = tegra_xudc_ep0_standard_req(xudc, ctrl); 2605 else 2606 ret = tegra_xudc_ep0_delegate_req(xudc, ctrl); 2607 2608 if (ret < 0) { 2609 dev_warn(xudc->dev, "setup request failed: %d\n", ret); 2610 xudc->setup_state = WAIT_FOR_SETUP; 2611 ep_halt(xudc, 0); 2612 } 2613} 2614 2615static void tegra_xudc_handle_ep0_event(struct tegra_xudc *xudc, 2616 struct tegra_xudc_trb *event) 2617{ 2618 struct usb_ctrlrequest *ctrl = (struct usb_ctrlrequest *)event; 2619 u16 seq_num = trb_read_seq_num(event); 2620 2621 if (xudc->setup_state != WAIT_FOR_SETUP) { 2622 /* 2623 * The controller is in the process of handling another 2624 * setup request. Queue subsequent requests and handle 2625 * the last one once the controller reports a sequence 2626 * number error. 2627 */ 2628 memcpy(&xudc->setup_packet.ctrl_req, ctrl, sizeof(*ctrl)); 2629 xudc->setup_packet.seq_num = seq_num; 2630 xudc->queued_setup_packet = true; 2631 } else { 2632 tegra_xudc_handle_ep0_setup_packet(xudc, ctrl, seq_num); 2633 } 2634} 2635 2636static struct tegra_xudc_request * 2637trb_to_request(struct tegra_xudc_ep *ep, struct tegra_xudc_trb *trb) 2638{ 2639 struct tegra_xudc_request *req; 2640 2641 list_for_each_entry(req, &ep->queue, list) { 2642 if (!req->trbs_queued) 2643 break; 2644 2645 if (trb_in_request(ep, req, trb)) 2646 return req; 2647 } 2648 2649 return NULL; 2650} 2651 2652static void tegra_xudc_handle_transfer_completion(struct tegra_xudc *xudc, 2653 struct tegra_xudc_ep *ep, 2654 struct tegra_xudc_trb *event) 2655{ 2656 struct tegra_xudc_request *req; 2657 struct tegra_xudc_trb *trb; 2658 bool short_packet; 2659 2660 short_packet = (trb_read_cmpl_code(event) == 2661 TRB_CMPL_CODE_SHORT_PACKET); 2662 2663 trb = trb_phys_to_virt(ep, trb_read_data_ptr(event)); 2664 req = trb_to_request(ep, trb); 2665 2666 /* 2667 * TDs are complete on short packet or when the completed TRB is the 2668 * last TRB in the TD (the CHAIN bit is unset). 2669 */ 2670 if (req && (short_packet || (!trb_read_chain(trb) && 2671 (req->trbs_needed == req->trbs_queued)))) { 2672 struct tegra_xudc_trb *last = req->last_trb; 2673 unsigned int residual; 2674 2675 residual = trb_read_transfer_len(event); 2676 req->usb_req.actual = req->usb_req.length - residual; 2677 2678 dev_dbg(xudc->dev, "bytes transferred %u / %u\n", 2679 req->usb_req.actual, req->usb_req.length); 2680 2681 tegra_xudc_req_done(ep, req, 0); 2682 2683 if (ep->desc && usb_endpoint_xfer_control(ep->desc)) 2684 tegra_xudc_ep0_req_done(xudc); 2685 2686 /* 2687 * Advance the dequeue pointer past the end of the current TD 2688 * on short packet completion. 2689 */ 2690 if (short_packet) { 2691 ep->deq_ptr = (last - ep->transfer_ring) + 1; 2692 if (ep->deq_ptr == XUDC_TRANSFER_RING_SIZE - 1) 2693 ep->deq_ptr = 0; 2694 } 2695 } else if (!req) { 2696 dev_warn(xudc->dev, "transfer event on dequeued request\n"); 2697 } 2698 2699 if (ep->desc) 2700 tegra_xudc_ep_kick_queue(ep); 2701} 2702 2703static void tegra_xudc_handle_transfer_event(struct tegra_xudc *xudc, 2704 struct tegra_xudc_trb *event) 2705{ 2706 unsigned int ep_index = trb_read_endpoint_id(event); 2707 struct tegra_xudc_ep *ep = &xudc->ep[ep_index]; 2708 struct tegra_xudc_trb *trb; 2709 u16 comp_code; 2710 2711 if (ep_ctx_read_state(ep->context) == EP_STATE_DISABLED) { 2712 dev_warn(xudc->dev, "transfer event on disabled EP %u\n", 2713 ep_index); 2714 return; 2715 } 2716 2717 /* Update transfer ring dequeue pointer. */ 2718 trb = trb_phys_to_virt(ep, trb_read_data_ptr(event)); 2719 comp_code = trb_read_cmpl_code(event); 2720 if (comp_code != TRB_CMPL_CODE_BABBLE_DETECTED_ERR) { 2721 ep->deq_ptr = (trb - ep->transfer_ring) + 1; 2722 2723 if (ep->deq_ptr == XUDC_TRANSFER_RING_SIZE - 1) 2724 ep->deq_ptr = 0; 2725 ep->ring_full = false; 2726 } 2727 2728 switch (comp_code) { 2729 case TRB_CMPL_CODE_SUCCESS: 2730 case TRB_CMPL_CODE_SHORT_PACKET: 2731 tegra_xudc_handle_transfer_completion(xudc, ep, event); 2732 break; 2733 case TRB_CMPL_CODE_HOST_REJECTED: 2734 dev_info(xudc->dev, "stream rejected on EP %u\n", ep_index); 2735 2736 ep->stream_rejected = true; 2737 break; 2738 case TRB_CMPL_CODE_PRIME_PIPE_RECEIVED: 2739 dev_info(xudc->dev, "prime pipe received on EP %u\n", ep_index); 2740 2741 if (ep->stream_rejected) { 2742 ep->stream_rejected = false; 2743 /* 2744 * An EP is stopped when a stream is rejected. Wait 2745 * for the EP to report that it is stopped and then 2746 * un-stop it. 2747 */ 2748 ep_wait_for_stopped(xudc, ep_index); 2749 } 2750 tegra_xudc_ep_ring_doorbell(ep); 2751 break; 2752 case TRB_CMPL_CODE_BABBLE_DETECTED_ERR: 2753 /* 2754 * Wait for the EP to be stopped so the controller stops 2755 * processing doorbells. 2756 */ 2757 ep_wait_for_stopped(xudc, ep_index); 2758 ep->enq_ptr = ep->deq_ptr; 2759 tegra_xudc_ep_nuke(ep, -EIO); 2760 fallthrough; 2761 case TRB_CMPL_CODE_STREAM_NUMP_ERROR: 2762 case TRB_CMPL_CODE_CTRL_DIR_ERR: 2763 case TRB_CMPL_CODE_INVALID_STREAM_TYPE_ERR: 2764 case TRB_CMPL_CODE_RING_UNDERRUN: 2765 case TRB_CMPL_CODE_RING_OVERRUN: 2766 case TRB_CMPL_CODE_ISOCH_BUFFER_OVERRUN: 2767 case TRB_CMPL_CODE_USB_TRANS_ERR: 2768 case TRB_CMPL_CODE_TRB_ERR: 2769 dev_err(xudc->dev, "completion error %#x on EP %u\n", 2770 comp_code, ep_index); 2771 2772 ep_halt(xudc, ep_index); 2773 break; 2774 case TRB_CMPL_CODE_CTRL_SEQNUM_ERR: 2775 dev_info(xudc->dev, "sequence number error\n"); 2776 2777 /* 2778 * Kill any queued control request and skip to the last 2779 * setup packet we received. 2780 */ 2781 tegra_xudc_ep_nuke(ep, -EINVAL); 2782 xudc->setup_state = WAIT_FOR_SETUP; 2783 if (!xudc->queued_setup_packet) 2784 break; 2785 2786 tegra_xudc_handle_ep0_setup_packet(xudc, 2787 &xudc->setup_packet.ctrl_req, 2788 xudc->setup_packet.seq_num); 2789 xudc->queued_setup_packet = false; 2790 break; 2791 case TRB_CMPL_CODE_STOPPED: 2792 dev_dbg(xudc->dev, "stop completion code on EP %u\n", 2793 ep_index); 2794 2795 /* Disconnected. */ 2796 tegra_xudc_ep_nuke(ep, -ECONNREFUSED); 2797 break; 2798 default: 2799 dev_dbg(xudc->dev, "completion event %#x on EP %u\n", 2800 comp_code, ep_index); 2801 break; 2802 } 2803} 2804 2805static void tegra_xudc_reset(struct tegra_xudc *xudc) 2806{ 2807 struct tegra_xudc_ep *ep0 = &xudc->ep[0]; 2808 dma_addr_t deq_ptr; 2809 unsigned int i; 2810 2811 xudc->setup_state = WAIT_FOR_SETUP; 2812 xudc->device_state = USB_STATE_DEFAULT; 2813 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 2814 2815 ep_unpause_all(xudc); 2816 2817 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) 2818 tegra_xudc_ep_nuke(&xudc->ep[i], -ESHUTDOWN); 2819 2820 /* 2821 * Reset sequence number and dequeue pointer to flush the transfer 2822 * ring. 2823 */ 2824 ep0->deq_ptr = ep0->enq_ptr; 2825 ep0->ring_full = false; 2826 2827 xudc->setup_seq_num = 0; 2828 xudc->queued_setup_packet = false; 2829 2830 ep_ctx_write_rsvd(ep0->context, 0); 2831 ep_ctx_write_partial_td(ep0->context, 0); 2832 ep_ctx_write_splitxstate(ep0->context, 0); 2833 ep_ctx_write_seq_num(ep0->context, 0); 2834 2835 deq_ptr = trb_virt_to_phys(ep0, &ep0->transfer_ring[ep0->deq_ptr]); 2836 2837 if (!dma_mapping_error(xudc->dev, deq_ptr)) { 2838 ep_ctx_write_deq_ptr(ep0->context, deq_ptr); 2839 ep_ctx_write_dcs(ep0->context, ep0->pcs); 2840 } 2841 2842 ep_unhalt_all(xudc); 2843 ep_reload(xudc, 0); 2844 ep_unpause(xudc, 0); 2845} 2846 2847static void tegra_xudc_port_connect(struct tegra_xudc *xudc) 2848{ 2849 struct tegra_xudc_ep *ep0 = &xudc->ep[0]; 2850 u16 maxpacket; 2851 u32 val; 2852 2853 val = (xudc_readl(xudc, PORTSC) & PORTSC_PS_MASK) >> PORTSC_PS_SHIFT; 2854 switch (val) { 2855 case PORTSC_PS_LS: 2856 xudc->gadget.speed = USB_SPEED_LOW; 2857 break; 2858 case PORTSC_PS_FS: 2859 xudc->gadget.speed = USB_SPEED_FULL; 2860 break; 2861 case PORTSC_PS_HS: 2862 xudc->gadget.speed = USB_SPEED_HIGH; 2863 break; 2864 case PORTSC_PS_SS: 2865 xudc->gadget.speed = USB_SPEED_SUPER; 2866 break; 2867 default: 2868 xudc->gadget.speed = USB_SPEED_UNKNOWN; 2869 break; 2870 } 2871 2872 xudc->device_state = USB_STATE_DEFAULT; 2873 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 2874 2875 xudc->setup_state = WAIT_FOR_SETUP; 2876 2877 if (xudc->gadget.speed == USB_SPEED_SUPER) 2878 maxpacket = 512; 2879 else 2880 maxpacket = 64; 2881 2882 ep_ctx_write_max_packet_size(ep0->context, maxpacket); 2883 tegra_xudc_ep0_desc.wMaxPacketSize = cpu_to_le16(maxpacket); 2884 usb_ep_set_maxpacket_limit(&ep0->usb_ep, maxpacket); 2885 2886 if (!xudc->soc->u1_enable) { 2887 val = xudc_readl(xudc, PORTPM); 2888 val &= ~(PORTPM_U1TIMEOUT_MASK); 2889 xudc_writel(xudc, val, PORTPM); 2890 } 2891 2892 if (!xudc->soc->u2_enable) { 2893 val = xudc_readl(xudc, PORTPM); 2894 val &= ~(PORTPM_U2TIMEOUT_MASK); 2895 xudc_writel(xudc, val, PORTPM); 2896 } 2897 2898 if (xudc->gadget.speed <= USB_SPEED_HIGH) { 2899 val = xudc_readl(xudc, PORTPM); 2900 val &= ~(PORTPM_L1S_MASK); 2901 if (xudc->soc->lpm_enable) 2902 val |= PORTPM_L1S(PORTPM_L1S_ACCEPT); 2903 else 2904 val |= PORTPM_L1S(PORTPM_L1S_NYET); 2905 xudc_writel(xudc, val, PORTPM); 2906 } 2907 2908 val = xudc_readl(xudc, ST); 2909 if (val & ST_RC) 2910 xudc_writel(xudc, ST_RC, ST); 2911} 2912 2913static void tegra_xudc_port_disconnect(struct tegra_xudc *xudc) 2914{ 2915 tegra_xudc_reset(xudc); 2916 2917 if (xudc->driver && xudc->driver->disconnect) { 2918 spin_unlock(&xudc->lock); 2919 xudc->driver->disconnect(&xudc->gadget); 2920 spin_lock(&xudc->lock); 2921 } 2922 2923 xudc->device_state = USB_STATE_NOTATTACHED; 2924 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 2925 2926 complete(&xudc->disconnect_complete); 2927} 2928 2929static void tegra_xudc_port_reset(struct tegra_xudc *xudc) 2930{ 2931 tegra_xudc_reset(xudc); 2932 2933 if (xudc->driver) { 2934 spin_unlock(&xudc->lock); 2935 usb_gadget_udc_reset(&xudc->gadget, xudc->driver); 2936 spin_lock(&xudc->lock); 2937 } 2938 2939 tegra_xudc_port_connect(xudc); 2940} 2941 2942static void tegra_xudc_port_suspend(struct tegra_xudc *xudc) 2943{ 2944 dev_dbg(xudc->dev, "port suspend\n"); 2945 2946 xudc->resume_state = xudc->device_state; 2947 xudc->device_state = USB_STATE_SUSPENDED; 2948 usb_gadget_set_state(&xudc->gadget, xudc->device_state); 2949 2950 if (xudc->driver->suspend) { 2951 spin_unlock(&xudc->lock); 2952 xudc->driver->suspend(&xudc->gadget); 2953 spin_lock(&xudc->lock); 2954 } 2955} 2956 2957static void tegra_xudc_port_resume(struct tegra_xudc *xudc) 2958{ 2959 dev_dbg(xudc->dev, "port resume\n"); 2960 2961 tegra_xudc_resume_device_state(xudc); 2962 2963 if (xudc->driver->resume) { 2964 spin_unlock(&xudc->lock); 2965 xudc->driver->resume(&xudc->gadget); 2966 spin_lock(&xudc->lock); 2967 } 2968} 2969 2970static inline void clear_port_change(struct tegra_xudc *xudc, u32 flag) 2971{ 2972 u32 val; 2973 2974 val = xudc_readl(xudc, PORTSC); 2975 val &= ~PORTSC_CHANGE_MASK; 2976 val |= flag; 2977 xudc_writel(xudc, val, PORTSC); 2978} 2979 2980static void __tegra_xudc_handle_port_status(struct tegra_xudc *xudc) 2981{ 2982 u32 portsc, porthalt; 2983 2984 porthalt = xudc_readl(xudc, PORTHALT); 2985 if ((porthalt & PORTHALT_STCHG_REQ) && 2986 (porthalt & PORTHALT_HALT_LTSSM)) { 2987 dev_dbg(xudc->dev, "STCHG_REQ, PORTHALT = %#x\n", porthalt); 2988 porthalt &= ~PORTHALT_HALT_LTSSM; 2989 xudc_writel(xudc, porthalt, PORTHALT); 2990 } 2991 2992 portsc = xudc_readl(xudc, PORTSC); 2993 if ((portsc & PORTSC_PRC) && (portsc & PORTSC_PR)) { 2994 dev_dbg(xudc->dev, "PRC, PR, PORTSC = %#x\n", portsc); 2995 clear_port_change(xudc, PORTSC_PRC | PORTSC_PED); 2996#define TOGGLE_VBUS_WAIT_MS 100 2997 if (xudc->soc->port_reset_quirk) { 2998 schedule_delayed_work(&xudc->port_reset_war_work, 2999 msecs_to_jiffies(TOGGLE_VBUS_WAIT_MS)); 3000 xudc->wait_for_sec_prc = 1; 3001 } 3002 } 3003 3004 if ((portsc & PORTSC_PRC) && !(portsc & PORTSC_PR)) { 3005 dev_dbg(xudc->dev, "PRC, Not PR, PORTSC = %#x\n", portsc); 3006 clear_port_change(xudc, PORTSC_PRC | PORTSC_PED); 3007 tegra_xudc_port_reset(xudc); 3008 cancel_delayed_work(&xudc->port_reset_war_work); 3009 xudc->wait_for_sec_prc = 0; 3010 } 3011 3012 portsc = xudc_readl(xudc, PORTSC); 3013 if (portsc & PORTSC_WRC) { 3014 dev_dbg(xudc->dev, "WRC, PORTSC = %#x\n", portsc); 3015 clear_port_change(xudc, PORTSC_WRC | PORTSC_PED); 3016 if (!(xudc_readl(xudc, PORTSC) & PORTSC_WPR)) 3017 tegra_xudc_port_reset(xudc); 3018 } 3019 3020 portsc = xudc_readl(xudc, PORTSC); 3021 if (portsc & PORTSC_CSC) { 3022 dev_dbg(xudc->dev, "CSC, PORTSC = %#x\n", portsc); 3023 clear_port_change(xudc, PORTSC_CSC); 3024 3025 if (portsc & PORTSC_CCS) 3026 tegra_xudc_port_connect(xudc); 3027 else 3028 tegra_xudc_port_disconnect(xudc); 3029 3030 if (xudc->wait_csc) { 3031 cancel_delayed_work(&xudc->plc_reset_work); 3032 xudc->wait_csc = false; 3033 } 3034 } 3035 3036 portsc = xudc_readl(xudc, PORTSC); 3037 if (portsc & PORTSC_PLC) { 3038 u32 pls = (portsc & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT; 3039 3040 dev_dbg(xudc->dev, "PLC, PORTSC = %#x\n", portsc); 3041 clear_port_change(xudc, PORTSC_PLC); 3042 switch (pls) { 3043 case PORTSC_PLS_U3: 3044 tegra_xudc_port_suspend(xudc); 3045 break; 3046 case PORTSC_PLS_U0: 3047 if (xudc->gadget.speed < USB_SPEED_SUPER) 3048 tegra_xudc_port_resume(xudc); 3049 break; 3050 case PORTSC_PLS_RESUME: 3051 if (xudc->gadget.speed == USB_SPEED_SUPER) 3052 tegra_xudc_port_resume(xudc); 3053 break; 3054 case PORTSC_PLS_INACTIVE: 3055 schedule_delayed_work(&xudc->plc_reset_work, 3056 msecs_to_jiffies(TOGGLE_VBUS_WAIT_MS)); 3057 xudc->wait_csc = true; 3058 break; 3059 default: 3060 break; 3061 } 3062 } 3063 3064 if (portsc & PORTSC_CEC) { 3065 dev_warn(xudc->dev, "CEC, PORTSC = %#x\n", portsc); 3066 clear_port_change(xudc, PORTSC_CEC); 3067 } 3068 3069 dev_dbg(xudc->dev, "PORTSC = %#x\n", xudc_readl(xudc, PORTSC)); 3070} 3071 3072static void tegra_xudc_handle_port_status(struct tegra_xudc *xudc) 3073{ 3074 while ((xudc_readl(xudc, PORTSC) & PORTSC_CHANGE_MASK) || 3075 (xudc_readl(xudc, PORTHALT) & PORTHALT_STCHG_REQ)) 3076 __tegra_xudc_handle_port_status(xudc); 3077} 3078 3079static void tegra_xudc_handle_event(struct tegra_xudc *xudc, 3080 struct tegra_xudc_trb *event) 3081{ 3082 u32 type = trb_read_type(event); 3083 3084 dump_trb(xudc, "EVENT", event); 3085 3086 switch (type) { 3087 case TRB_TYPE_PORT_STATUS_CHANGE_EVENT: 3088 tegra_xudc_handle_port_status(xudc); 3089 break; 3090 case TRB_TYPE_TRANSFER_EVENT: 3091 tegra_xudc_handle_transfer_event(xudc, event); 3092 break; 3093 case TRB_TYPE_SETUP_PACKET_EVENT: 3094 tegra_xudc_handle_ep0_event(xudc, event); 3095 break; 3096 default: 3097 dev_info(xudc->dev, "Unrecognized TRB type = %#x\n", type); 3098 break; 3099 } 3100} 3101 3102static void tegra_xudc_process_event_ring(struct tegra_xudc *xudc) 3103{ 3104 struct tegra_xudc_trb *event; 3105 dma_addr_t erdp; 3106 3107 while (true) { 3108 event = xudc->event_ring[xudc->event_ring_index] + 3109 xudc->event_ring_deq_ptr; 3110 3111 if (trb_read_cycle(event) != xudc->ccs) 3112 break; 3113 3114 tegra_xudc_handle_event(xudc, event); 3115 3116 xudc->event_ring_deq_ptr++; 3117 if (xudc->event_ring_deq_ptr == XUDC_EVENT_RING_SIZE) { 3118 xudc->event_ring_deq_ptr = 0; 3119 xudc->event_ring_index++; 3120 } 3121 3122 if (xudc->event_ring_index == XUDC_NR_EVENT_RINGS) { 3123 xudc->event_ring_index = 0; 3124 xudc->ccs = !xudc->ccs; 3125 } 3126 } 3127 3128 erdp = xudc->event_ring_phys[xudc->event_ring_index] + 3129 xudc->event_ring_deq_ptr * sizeof(*event); 3130 3131 xudc_writel(xudc, upper_32_bits(erdp), ERDPHI); 3132 xudc_writel(xudc, lower_32_bits(erdp) | ERDPLO_EHB, ERDPLO); 3133} 3134 3135static irqreturn_t tegra_xudc_irq(int irq, void *data) 3136{ 3137 struct tegra_xudc *xudc = data; 3138 unsigned long flags; 3139 u32 val; 3140 3141 val = xudc_readl(xudc, ST); 3142 if (!(val & ST_IP)) 3143 return IRQ_NONE; 3144 xudc_writel(xudc, ST_IP, ST); 3145 3146 spin_lock_irqsave(&xudc->lock, flags); 3147 tegra_xudc_process_event_ring(xudc); 3148 spin_unlock_irqrestore(&xudc->lock, flags); 3149 3150 return IRQ_HANDLED; 3151} 3152 3153static int tegra_xudc_alloc_ep(struct tegra_xudc *xudc, unsigned int index) 3154{ 3155 struct tegra_xudc_ep *ep = &xudc->ep[index]; 3156 3157 ep->xudc = xudc; 3158 ep->index = index; 3159 ep->context = &xudc->ep_context[index]; 3160 INIT_LIST_HEAD(&ep->queue); 3161 3162 /* 3163 * EP1 would be the input endpoint corresponding to EP0, but since 3164 * EP0 is bi-directional, EP1 is unused. 3165 */ 3166 if (index == 1) 3167 return 0; 3168 3169 ep->transfer_ring = dma_pool_alloc(xudc->transfer_ring_pool, 3170 GFP_KERNEL, 3171 &ep->transfer_ring_phys); 3172 if (!ep->transfer_ring) 3173 return -ENOMEM; 3174 3175 if (index) { 3176 snprintf(ep->name, sizeof(ep->name), "ep%u%s", index / 2, 3177 (index % 2 == 0) ? "out" : "in"); 3178 ep->usb_ep.name = ep->name; 3179 usb_ep_set_maxpacket_limit(&ep->usb_ep, 1024); 3180 ep->usb_ep.max_streams = 16; 3181 ep->usb_ep.ops = &tegra_xudc_ep_ops; 3182 ep->usb_ep.caps.type_bulk = true; 3183 ep->usb_ep.caps.type_int = true; 3184 if (index & 1) 3185 ep->usb_ep.caps.dir_in = true; 3186 else 3187 ep->usb_ep.caps.dir_out = true; 3188 list_add_tail(&ep->usb_ep.ep_list, &xudc->gadget.ep_list); 3189 } else { 3190 strscpy(ep->name, "ep0", 3); 3191 ep->usb_ep.name = ep->name; 3192 usb_ep_set_maxpacket_limit(&ep->usb_ep, 512); 3193 ep->usb_ep.ops = &tegra_xudc_ep0_ops; 3194 ep->usb_ep.caps.type_control = true; 3195 ep->usb_ep.caps.dir_in = true; 3196 ep->usb_ep.caps.dir_out = true; 3197 } 3198 3199 return 0; 3200} 3201 3202static void tegra_xudc_free_ep(struct tegra_xudc *xudc, unsigned int index) 3203{ 3204 struct tegra_xudc_ep *ep = &xudc->ep[index]; 3205 3206 /* 3207 * EP1 would be the input endpoint corresponding to EP0, but since 3208 * EP0 is bi-directional, EP1 is unused. 3209 */ 3210 if (index == 1) 3211 return; 3212 3213 dma_pool_free(xudc->transfer_ring_pool, ep->transfer_ring, 3214 ep->transfer_ring_phys); 3215} 3216 3217static int tegra_xudc_alloc_eps(struct tegra_xudc *xudc) 3218{ 3219 struct usb_request *req; 3220 unsigned int i; 3221 int err; 3222 3223 xudc->ep_context = 3224 dma_alloc_coherent(xudc->dev, XUDC_NR_EPS * 3225 sizeof(*xudc->ep_context), 3226 &xudc->ep_context_phys, GFP_KERNEL); 3227 if (!xudc->ep_context) 3228 return -ENOMEM; 3229 3230 xudc->transfer_ring_pool = 3231 dmam_pool_create(dev_name(xudc->dev), xudc->dev, 3232 XUDC_TRANSFER_RING_SIZE * 3233 sizeof(struct tegra_xudc_trb), 3234 sizeof(struct tegra_xudc_trb), 0); 3235 if (!xudc->transfer_ring_pool) { 3236 err = -ENOMEM; 3237 goto free_ep_context; 3238 } 3239 3240 INIT_LIST_HEAD(&xudc->gadget.ep_list); 3241 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) { 3242 err = tegra_xudc_alloc_ep(xudc, i); 3243 if (err < 0) 3244 goto free_eps; 3245 } 3246 3247 req = tegra_xudc_ep_alloc_request(&xudc->ep[0].usb_ep, GFP_KERNEL); 3248 if (!req) { 3249 err = -ENOMEM; 3250 goto free_eps; 3251 } 3252 xudc->ep0_req = to_xudc_req(req); 3253 3254 return 0; 3255 3256free_eps: 3257 for (; i > 0; i--) 3258 tegra_xudc_free_ep(xudc, i - 1); 3259free_ep_context: 3260 dma_free_coherent(xudc->dev, XUDC_NR_EPS * sizeof(*xudc->ep_context), 3261 xudc->ep_context, xudc->ep_context_phys); 3262 return err; 3263} 3264 3265static void tegra_xudc_init_eps(struct tegra_xudc *xudc) 3266{ 3267 xudc_writel(xudc, lower_32_bits(xudc->ep_context_phys), ECPLO); 3268 xudc_writel(xudc, upper_32_bits(xudc->ep_context_phys), ECPHI); 3269} 3270 3271static void tegra_xudc_free_eps(struct tegra_xudc *xudc) 3272{ 3273 unsigned int i; 3274 3275 tegra_xudc_ep_free_request(&xudc->ep[0].usb_ep, 3276 &xudc->ep0_req->usb_req); 3277 3278 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) 3279 tegra_xudc_free_ep(xudc, i); 3280 3281 dma_free_coherent(xudc->dev, XUDC_NR_EPS * sizeof(*xudc->ep_context), 3282 xudc->ep_context, xudc->ep_context_phys); 3283} 3284 3285static int tegra_xudc_alloc_event_ring(struct tegra_xudc *xudc) 3286{ 3287 unsigned int i; 3288 3289 for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) { 3290 xudc->event_ring[i] = 3291 dma_alloc_coherent(xudc->dev, XUDC_EVENT_RING_SIZE * 3292 sizeof(*xudc->event_ring[i]), 3293 &xudc->event_ring_phys[i], 3294 GFP_KERNEL); 3295 if (!xudc->event_ring[i]) 3296 goto free_dma; 3297 } 3298 3299 return 0; 3300 3301free_dma: 3302 for (; i > 0; i--) { 3303 dma_free_coherent(xudc->dev, XUDC_EVENT_RING_SIZE * 3304 sizeof(*xudc->event_ring[i - 1]), 3305 xudc->event_ring[i - 1], 3306 xudc->event_ring_phys[i - 1]); 3307 } 3308 return -ENOMEM; 3309} 3310 3311static void tegra_xudc_init_event_ring(struct tegra_xudc *xudc) 3312{ 3313 unsigned int i; 3314 u32 val; 3315 3316 for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) { 3317 memset(xudc->event_ring[i], 0, XUDC_EVENT_RING_SIZE * 3318 sizeof(*xudc->event_ring[i])); 3319 3320 val = xudc_readl(xudc, ERSTSZ); 3321 val &= ~(ERSTSZ_ERSTXSZ_MASK << ERSTSZ_ERSTXSZ_SHIFT(i)); 3322 val |= XUDC_EVENT_RING_SIZE << ERSTSZ_ERSTXSZ_SHIFT(i); 3323 xudc_writel(xudc, val, ERSTSZ); 3324 3325 xudc_writel(xudc, lower_32_bits(xudc->event_ring_phys[i]), 3326 ERSTXBALO(i)); 3327 xudc_writel(xudc, upper_32_bits(xudc->event_ring_phys[i]), 3328 ERSTXBAHI(i)); 3329 } 3330 3331 val = lower_32_bits(xudc->event_ring_phys[0]); 3332 xudc_writel(xudc, val, ERDPLO); 3333 val |= EREPLO_ECS; 3334 xudc_writel(xudc, val, EREPLO); 3335 3336 val = upper_32_bits(xudc->event_ring_phys[0]); 3337 xudc_writel(xudc, val, ERDPHI); 3338 xudc_writel(xudc, val, EREPHI); 3339 3340 xudc->ccs = true; 3341 xudc->event_ring_index = 0; 3342 xudc->event_ring_deq_ptr = 0; 3343} 3344 3345static void tegra_xudc_free_event_ring(struct tegra_xudc *xudc) 3346{ 3347 unsigned int i; 3348 3349 for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) { 3350 dma_free_coherent(xudc->dev, XUDC_EVENT_RING_SIZE * 3351 sizeof(*xudc->event_ring[i]), 3352 xudc->event_ring[i], 3353 xudc->event_ring_phys[i]); 3354 } 3355} 3356 3357static void tegra_xudc_fpci_ipfs_init(struct tegra_xudc *xudc) 3358{ 3359 u32 val; 3360 3361 if (xudc->soc->has_ipfs) { 3362 val = ipfs_readl(xudc, XUSB_DEV_CONFIGURATION_0); 3363 val |= XUSB_DEV_CONFIGURATION_0_EN_FPCI; 3364 ipfs_writel(xudc, val, XUSB_DEV_CONFIGURATION_0); 3365 usleep_range(10, 15); 3366 } 3367 3368 /* Enable bus master */ 3369 val = XUSB_DEV_CFG_1_IO_SPACE_EN | XUSB_DEV_CFG_1_MEMORY_SPACE_EN | 3370 XUSB_DEV_CFG_1_BUS_MASTER_EN; 3371 fpci_writel(xudc, val, XUSB_DEV_CFG_1); 3372 3373 /* Program BAR0 space */ 3374 val = fpci_readl(xudc, XUSB_DEV_CFG_4); 3375 val &= ~(XUSB_DEV_CFG_4_BASE_ADDR_MASK); 3376 val |= xudc->phys_base & (XUSB_DEV_CFG_4_BASE_ADDR_MASK); 3377 3378 fpci_writel(xudc, val, XUSB_DEV_CFG_4); 3379 fpci_writel(xudc, upper_32_bits(xudc->phys_base), XUSB_DEV_CFG_5); 3380 3381 usleep_range(100, 200); 3382 3383 if (xudc->soc->has_ipfs) { 3384 /* Enable interrupt assertion */ 3385 val = ipfs_readl(xudc, XUSB_DEV_INTR_MASK_0); 3386 val |= XUSB_DEV_INTR_MASK_0_IP_INT_MASK; 3387 ipfs_writel(xudc, val, XUSB_DEV_INTR_MASK_0); 3388 } 3389} 3390 3391static void tegra_xudc_device_params_init(struct tegra_xudc *xudc) 3392{ 3393 u32 val, imod; 3394 3395 val = xudc_readl(xudc, BLCG); 3396 if (xudc->soc->has_ipfs) { 3397 val |= BLCG_ALL; 3398 val &= ~(BLCG_DFPCI | BLCG_UFPCI | BLCG_FE | 3399 BLCG_COREPLL_PWRDN); 3400 val |= BLCG_IOPLL_0_PWRDN; 3401 val |= BLCG_IOPLL_1_PWRDN; 3402 val |= BLCG_IOPLL_2_PWRDN; 3403 } else { 3404 val &= ~BLCG_COREPLL_PWRDN; 3405 } 3406 xudc_writel(xudc, val, BLCG); 3407 3408 if (xudc->soc->port_speed_quirk) 3409 tegra_xudc_limit_port_speed(xudc); 3410 3411 /* Set a reasonable U3 exit timer value. */ 3412 val = xudc_readl(xudc, SSPX_CORE_PADCTL4); 3413 val &= ~(SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK); 3414 val |= SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(0x5dc0); 3415 xudc_writel(xudc, val, SSPX_CORE_PADCTL4); 3416 3417 /* Default ping LFPS tBurst is too large. */ 3418 val = xudc_readl(xudc, SSPX_CORE_CNT0); 3419 val &= ~(SSPX_CORE_CNT0_PING_TBURST_MASK); 3420 val |= SSPX_CORE_CNT0_PING_TBURST(0xa); 3421 xudc_writel(xudc, val, SSPX_CORE_CNT0); 3422 3423 /* Default tPortConfiguration timeout is too small. */ 3424 val = xudc_readl(xudc, SSPX_CORE_CNT30); 3425 val &= ~(SSPX_CORE_CNT30_LMPITP_TIMER_MASK); 3426 val |= SSPX_CORE_CNT30_LMPITP_TIMER(0x978); 3427 xudc_writel(xudc, val, SSPX_CORE_CNT30); 3428 3429 if (xudc->soc->lpm_enable) { 3430 /* Set L1 resume duration to 95 us. */ 3431 val = xudc_readl(xudc, HSFSPI_COUNT13); 3432 val &= ~(HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK); 3433 val |= HSFSPI_COUNT13_U2_RESUME_K_DURATION(0x2c88); 3434 xudc_writel(xudc, val, HSFSPI_COUNT13); 3435 } 3436 3437 /* 3438 * Compliance suite appears to be violating polling LFPS tBurst max 3439 * of 1.4us. Send 1.45us instead. 3440 */ 3441 val = xudc_readl(xudc, SSPX_CORE_CNT32); 3442 val &= ~(SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK); 3443 val |= SSPX_CORE_CNT32_POLL_TBURST_MAX(0xb0); 3444 xudc_writel(xudc, val, SSPX_CORE_CNT32); 3445 3446 /* Direct HS/FS port instance to RxDetect. */ 3447 val = xudc_readl(xudc, CFG_DEV_FE); 3448 val &= ~(CFG_DEV_FE_PORTREGSEL_MASK); 3449 val |= CFG_DEV_FE_PORTREGSEL(CFG_DEV_FE_PORTREGSEL_HSFS_PI); 3450 xudc_writel(xudc, val, CFG_DEV_FE); 3451 3452 val = xudc_readl(xudc, PORTSC); 3453 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK); 3454 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_RXDETECT); 3455 xudc_writel(xudc, val, PORTSC); 3456 3457 /* Direct SS port instance to RxDetect. */ 3458 val = xudc_readl(xudc, CFG_DEV_FE); 3459 val &= ~(CFG_DEV_FE_PORTREGSEL_MASK); 3460 val |= CFG_DEV_FE_PORTREGSEL_SS_PI & CFG_DEV_FE_PORTREGSEL_MASK; 3461 xudc_writel(xudc, val, CFG_DEV_FE); 3462 3463 val = xudc_readl(xudc, PORTSC); 3464 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK); 3465 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_RXDETECT); 3466 xudc_writel(xudc, val, PORTSC); 3467 3468 /* Restore port instance. */ 3469 val = xudc_readl(xudc, CFG_DEV_FE); 3470 val &= ~(CFG_DEV_FE_PORTREGSEL_MASK); 3471 xudc_writel(xudc, val, CFG_DEV_FE); 3472 3473 /* 3474 * Enable INFINITE_SS_RETRY to prevent device from entering 3475 * Disabled.Error when attached to buggy SuperSpeed hubs. 3476 */ 3477 val = xudc_readl(xudc, CFG_DEV_FE); 3478 val |= CFG_DEV_FE_INFINITE_SS_RETRY; 3479 xudc_writel(xudc, val, CFG_DEV_FE); 3480 3481 /* Set interrupt moderation. */ 3482 imod = XUDC_INTERRUPT_MODERATION_US * 4; 3483 val = xudc_readl(xudc, RT_IMOD); 3484 val &= ~((RT_IMOD_IMODI_MASK) | (RT_IMOD_IMODC_MASK)); 3485 val |= (RT_IMOD_IMODI(imod) | RT_IMOD_IMODC(imod)); 3486 xudc_writel(xudc, val, RT_IMOD); 3487 3488 /* increase SSPI transaction timeout from 32us to 512us */ 3489 val = xudc_readl(xudc, CFG_DEV_SSPI_XFER); 3490 val &= ~(CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK); 3491 val |= CFG_DEV_SSPI_XFER_ACKTIMEOUT(0xf000); 3492 xudc_writel(xudc, val, CFG_DEV_SSPI_XFER); 3493} 3494 3495static int tegra_xudc_phy_get(struct tegra_xudc *xudc) 3496{ 3497 int err = 0, usb3_companion_port; 3498 unsigned int i, j; 3499 3500 xudc->utmi_phy = devm_kcalloc(xudc->dev, xudc->soc->num_phys, 3501 sizeof(*xudc->utmi_phy), GFP_KERNEL); 3502 if (!xudc->utmi_phy) 3503 return -ENOMEM; 3504 3505 xudc->usb3_phy = devm_kcalloc(xudc->dev, xudc->soc->num_phys, 3506 sizeof(*xudc->usb3_phy), GFP_KERNEL); 3507 if (!xudc->usb3_phy) 3508 return -ENOMEM; 3509 3510 xudc->usbphy = devm_kcalloc(xudc->dev, xudc->soc->num_phys, 3511 sizeof(*xudc->usbphy), GFP_KERNEL); 3512 if (!xudc->usbphy) 3513 return -ENOMEM; 3514 3515 xudc->vbus_nb.notifier_call = tegra_xudc_vbus_notify; 3516 3517 for (i = 0; i < xudc->soc->num_phys; i++) { 3518 char phy_name[] = "usb.-."; 3519 3520 /* Get USB2 phy */ 3521 snprintf(phy_name, sizeof(phy_name), "usb2-%d", i); 3522 xudc->utmi_phy[i] = devm_phy_optional_get(xudc->dev, phy_name); 3523 if (IS_ERR(xudc->utmi_phy[i])) { 3524 err = PTR_ERR(xudc->utmi_phy[i]); 3525 dev_err_probe(xudc->dev, err, 3526 "failed to get PHY for phy-name usb2-%d\n", i); 3527 goto clean_up; 3528 } else if (xudc->utmi_phy[i]) { 3529 /* Get usb-phy, if utmi phy is available */ 3530 xudc->usbphy[i] = devm_usb_get_phy_by_node(xudc->dev, 3531 xudc->utmi_phy[i]->dev.of_node, 3532 NULL); 3533 if (IS_ERR(xudc->usbphy[i])) { 3534 err = PTR_ERR(xudc->usbphy[i]); 3535 dev_err_probe(xudc->dev, err, 3536 "failed to get usbphy-%d\n", i); 3537 goto clean_up; 3538 } 3539 } else if (!xudc->utmi_phy[i]) { 3540 /* if utmi phy is not available, ignore USB3 phy get */ 3541 continue; 3542 } 3543 3544 /* Get USB3 phy */ 3545 usb3_companion_port = tegra_xusb_padctl_get_usb3_companion(xudc->padctl, i); 3546 if (usb3_companion_port < 0) 3547 continue; 3548 3549 for (j = 0; j < xudc->soc->num_phys; j++) { 3550 snprintf(phy_name, sizeof(phy_name), "usb3-%d", j); 3551 xudc->usb3_phy[i] = devm_phy_optional_get(xudc->dev, phy_name); 3552 if (IS_ERR(xudc->usb3_phy[i])) { 3553 err = PTR_ERR(xudc->usb3_phy[i]); 3554 dev_err_probe(xudc->dev, err, 3555 "failed to get PHY for phy-name usb3-%d\n", j); 3556 goto clean_up; 3557 } else if (xudc->usb3_phy[i]) { 3558 int usb2_port = 3559 tegra_xusb_padctl_get_port_number(xudc->utmi_phy[i]); 3560 int usb3_port = 3561 tegra_xusb_padctl_get_port_number(xudc->usb3_phy[i]); 3562 if (usb3_port == usb3_companion_port) { 3563 dev_dbg(xudc->dev, "USB2 port %d is paired with USB3 port %d for device mode port %d\n", 3564 usb2_port, usb3_port, i); 3565 break; 3566 } 3567 } 3568 } 3569 } 3570 3571 return err; 3572 3573clean_up: 3574 for (i = 0; i < xudc->soc->num_phys; i++) { 3575 xudc->usb3_phy[i] = NULL; 3576 xudc->utmi_phy[i] = NULL; 3577 xudc->usbphy[i] = NULL; 3578 } 3579 3580 return err; 3581} 3582 3583static void tegra_xudc_phy_exit(struct tegra_xudc *xudc) 3584{ 3585 unsigned int i; 3586 3587 for (i = 0; i < xudc->soc->num_phys; i++) { 3588 phy_exit(xudc->usb3_phy[i]); 3589 phy_exit(xudc->utmi_phy[i]); 3590 } 3591} 3592 3593static int tegra_xudc_phy_init(struct tegra_xudc *xudc) 3594{ 3595 int err; 3596 unsigned int i; 3597 3598 for (i = 0; i < xudc->soc->num_phys; i++) { 3599 err = phy_init(xudc->utmi_phy[i]); 3600 if (err < 0) { 3601 dev_err(xudc->dev, "UTMI PHY #%u initialization failed: %d\n", i, err); 3602 goto exit_phy; 3603 } 3604 3605 err = phy_init(xudc->usb3_phy[i]); 3606 if (err < 0) { 3607 dev_err(xudc->dev, "USB3 PHY #%u initialization failed: %d\n", i, err); 3608 goto exit_phy; 3609 } 3610 } 3611 return 0; 3612 3613exit_phy: 3614 tegra_xudc_phy_exit(xudc); 3615 return err; 3616} 3617 3618static const char * const tegra210_xudc_supply_names[] = { 3619 "hvdd-usb", 3620 "avddio-usb", 3621}; 3622 3623static const char * const tegra210_xudc_clock_names[] = { 3624 "dev", 3625 "ss", 3626 "ss_src", 3627 "hs_src", 3628 "fs_src", 3629}; 3630 3631static const char * const tegra186_xudc_clock_names[] = { 3632 "dev", 3633 "ss", 3634 "ss_src", 3635 "fs_src", 3636}; 3637 3638static struct tegra_xudc_soc tegra210_xudc_soc_data = { 3639 .supply_names = tegra210_xudc_supply_names, 3640 .num_supplies = ARRAY_SIZE(tegra210_xudc_supply_names), 3641 .clock_names = tegra210_xudc_clock_names, 3642 .num_clks = ARRAY_SIZE(tegra210_xudc_clock_names), 3643 .num_phys = 4, 3644 .u1_enable = false, 3645 .u2_enable = true, 3646 .lpm_enable = false, 3647 .invalid_seq_num = true, 3648 .pls_quirk = true, 3649 .port_reset_quirk = true, 3650 .port_speed_quirk = false, 3651 .has_ipfs = true, 3652}; 3653 3654static struct tegra_xudc_soc tegra186_xudc_soc_data = { 3655 .clock_names = tegra186_xudc_clock_names, 3656 .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), 3657 .num_phys = 4, 3658 .u1_enable = true, 3659 .u2_enable = true, 3660 .lpm_enable = false, 3661 .invalid_seq_num = false, 3662 .pls_quirk = false, 3663 .port_reset_quirk = false, 3664 .port_speed_quirk = false, 3665 .has_ipfs = false, 3666}; 3667 3668static struct tegra_xudc_soc tegra194_xudc_soc_data = { 3669 .clock_names = tegra186_xudc_clock_names, 3670 .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), 3671 .num_phys = 4, 3672 .u1_enable = true, 3673 .u2_enable = true, 3674 .lpm_enable = true, 3675 .invalid_seq_num = false, 3676 .pls_quirk = false, 3677 .port_reset_quirk = false, 3678 .port_speed_quirk = true, 3679 .has_ipfs = false, 3680}; 3681 3682static struct tegra_xudc_soc tegra234_xudc_soc_data = { 3683 .clock_names = tegra186_xudc_clock_names, 3684 .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), 3685 .num_phys = 4, 3686 .u1_enable = true, 3687 .u2_enable = true, 3688 .lpm_enable = true, 3689 .invalid_seq_num = false, 3690 .pls_quirk = false, 3691 .port_reset_quirk = false, 3692 .has_ipfs = false, 3693}; 3694 3695static const struct of_device_id tegra_xudc_of_match[] = { 3696 { 3697 .compatible = "nvidia,tegra210-xudc", 3698 .data = &tegra210_xudc_soc_data 3699 }, 3700 { 3701 .compatible = "nvidia,tegra186-xudc", 3702 .data = &tegra186_xudc_soc_data 3703 }, 3704 { 3705 .compatible = "nvidia,tegra194-xudc", 3706 .data = &tegra194_xudc_soc_data 3707 }, 3708 { 3709 .compatible = "nvidia,tegra234-xudc", 3710 .data = &tegra234_xudc_soc_data 3711 }, 3712 { } 3713}; 3714MODULE_DEVICE_TABLE(of, tegra_xudc_of_match); 3715 3716static void tegra_xudc_powerdomain_remove(struct tegra_xudc *xudc) 3717{ 3718 if (xudc->genpd_dl_ss) 3719 device_link_del(xudc->genpd_dl_ss); 3720 if (xudc->genpd_dl_device) 3721 device_link_del(xudc->genpd_dl_device); 3722 if (xudc->genpd_dev_ss) 3723 dev_pm_domain_detach(xudc->genpd_dev_ss, true); 3724 if (xudc->genpd_dev_device) 3725 dev_pm_domain_detach(xudc->genpd_dev_device, true); 3726} 3727 3728static int tegra_xudc_powerdomain_init(struct tegra_xudc *xudc) 3729{ 3730 struct device *dev = xudc->dev; 3731 int err; 3732 3733 xudc->genpd_dev_device = dev_pm_domain_attach_by_name(dev, "dev"); 3734 if (IS_ERR(xudc->genpd_dev_device)) { 3735 err = PTR_ERR(xudc->genpd_dev_device); 3736 dev_err(dev, "failed to get device power domain: %d\n", err); 3737 return err; 3738 } 3739 3740 xudc->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "ss"); 3741 if (IS_ERR(xudc->genpd_dev_ss)) { 3742 err = PTR_ERR(xudc->genpd_dev_ss); 3743 dev_err(dev, "failed to get SuperSpeed power domain: %d\n", err); 3744 return err; 3745 } 3746 3747 xudc->genpd_dl_device = device_link_add(dev, xudc->genpd_dev_device, 3748 DL_FLAG_PM_RUNTIME | 3749 DL_FLAG_STATELESS); 3750 if (!xudc->genpd_dl_device) { 3751 dev_err(dev, "failed to add USB device link\n"); 3752 return -ENODEV; 3753 } 3754 3755 xudc->genpd_dl_ss = device_link_add(dev, xudc->genpd_dev_ss, 3756 DL_FLAG_PM_RUNTIME | 3757 DL_FLAG_STATELESS); 3758 if (!xudc->genpd_dl_ss) { 3759 dev_err(dev, "failed to add SuperSpeed device link\n"); 3760 return -ENODEV; 3761 } 3762 3763 return 0; 3764} 3765 3766static int tegra_xudc_probe(struct platform_device *pdev) 3767{ 3768 struct tegra_xudc *xudc; 3769 struct resource *res; 3770 unsigned int i; 3771 int err; 3772 3773 xudc = devm_kzalloc(&pdev->dev, sizeof(*xudc), GFP_KERNEL); 3774 if (!xudc) 3775 return -ENOMEM; 3776 3777 xudc->dev = &pdev->dev; 3778 platform_set_drvdata(pdev, xudc); 3779 3780 xudc->soc = of_device_get_match_data(&pdev->dev); 3781 if (!xudc->soc) 3782 return -ENODEV; 3783 3784 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); 3785 xudc->base = devm_ioremap_resource(&pdev->dev, res); 3786 if (IS_ERR(xudc->base)) 3787 return PTR_ERR(xudc->base); 3788 xudc->phys_base = res->start; 3789 3790 xudc->fpci = devm_platform_ioremap_resource_byname(pdev, "fpci"); 3791 if (IS_ERR(xudc->fpci)) 3792 return PTR_ERR(xudc->fpci); 3793 3794 if (xudc->soc->has_ipfs) { 3795 xudc->ipfs = devm_platform_ioremap_resource_byname(pdev, "ipfs"); 3796 if (IS_ERR(xudc->ipfs)) 3797 return PTR_ERR(xudc->ipfs); 3798 } 3799 3800 xudc->irq = platform_get_irq(pdev, 0); 3801 if (xudc->irq < 0) 3802 return xudc->irq; 3803 3804 err = devm_request_irq(&pdev->dev, xudc->irq, tegra_xudc_irq, 0, 3805 dev_name(&pdev->dev), xudc); 3806 if (err < 0) { 3807 dev_err(xudc->dev, "failed to claim IRQ#%u: %d\n", xudc->irq, 3808 err); 3809 return err; 3810 } 3811 3812 xudc->clks = devm_kcalloc(&pdev->dev, xudc->soc->num_clks, sizeof(*xudc->clks), 3813 GFP_KERNEL); 3814 if (!xudc->clks) 3815 return -ENOMEM; 3816 3817 for (i = 0; i < xudc->soc->num_clks; i++) 3818 xudc->clks[i].id = xudc->soc->clock_names[i]; 3819 3820 err = devm_clk_bulk_get(&pdev->dev, xudc->soc->num_clks, xudc->clks); 3821 if (err) { 3822 dev_err_probe(xudc->dev, err, "failed to request clocks\n"); 3823 return err; 3824 } 3825 3826 xudc->supplies = devm_kcalloc(&pdev->dev, xudc->soc->num_supplies, 3827 sizeof(*xudc->supplies), GFP_KERNEL); 3828 if (!xudc->supplies) 3829 return -ENOMEM; 3830 3831 for (i = 0; i < xudc->soc->num_supplies; i++) 3832 xudc->supplies[i].supply = xudc->soc->supply_names[i]; 3833 3834 err = devm_regulator_bulk_get(&pdev->dev, xudc->soc->num_supplies, 3835 xudc->supplies); 3836 if (err) { 3837 dev_err_probe(xudc->dev, err, "failed to request regulators\n"); 3838 return err; 3839 } 3840 3841 xudc->padctl = tegra_xusb_padctl_get(&pdev->dev); 3842 if (IS_ERR(xudc->padctl)) 3843 return PTR_ERR(xudc->padctl); 3844 3845 err = regulator_bulk_enable(xudc->soc->num_supplies, xudc->supplies); 3846 if (err) { 3847 dev_err(xudc->dev, "failed to enable regulators: %d\n", err); 3848 goto put_padctl; 3849 } 3850 3851 err = tegra_xudc_phy_get(xudc); 3852 if (err) 3853 goto disable_regulator; 3854 3855 err = tegra_xudc_powerdomain_init(xudc); 3856 if (err) 3857 goto put_powerdomains; 3858 3859 err = tegra_xudc_phy_init(xudc); 3860 if (err) 3861 goto put_powerdomains; 3862 3863 err = tegra_xudc_alloc_event_ring(xudc); 3864 if (err) 3865 goto disable_phy; 3866 3867 err = tegra_xudc_alloc_eps(xudc); 3868 if (err) 3869 goto free_event_ring; 3870 3871 spin_lock_init(&xudc->lock); 3872 3873 init_completion(&xudc->disconnect_complete); 3874 3875 INIT_WORK(&xudc->usb_role_sw_work, tegra_xudc_usb_role_sw_work); 3876 3877 INIT_DELAYED_WORK(&xudc->plc_reset_work, tegra_xudc_plc_reset_work); 3878 3879 INIT_DELAYED_WORK(&xudc->port_reset_war_work, 3880 tegra_xudc_port_reset_war_work); 3881 3882 pm_runtime_enable(&pdev->dev); 3883 3884 xudc->gadget.ops = &tegra_xudc_gadget_ops; 3885 xudc->gadget.ep0 = &xudc->ep[0].usb_ep; 3886 xudc->gadget.name = "tegra-xudc"; 3887 xudc->gadget.max_speed = USB_SPEED_SUPER; 3888 3889 err = usb_add_gadget_udc(&pdev->dev, &xudc->gadget); 3890 if (err) { 3891 dev_err(&pdev->dev, "failed to add USB gadget: %d\n", err); 3892 goto free_eps; 3893 } 3894 3895 for (i = 0; i < xudc->soc->num_phys; i++) { 3896 if (!xudc->usbphy[i]) 3897 continue; 3898 3899 usb_register_notifier(xudc->usbphy[i], &xudc->vbus_nb); 3900 tegra_xudc_update_data_role(xudc, xudc->usbphy[i]); 3901 } 3902 3903 return 0; 3904 3905free_eps: 3906 pm_runtime_disable(&pdev->dev); 3907 tegra_xudc_free_eps(xudc); 3908free_event_ring: 3909 tegra_xudc_free_event_ring(xudc); 3910disable_phy: 3911 tegra_xudc_phy_exit(xudc); 3912put_powerdomains: 3913 tegra_xudc_powerdomain_remove(xudc); 3914disable_regulator: 3915 regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies); 3916put_padctl: 3917 tegra_xusb_padctl_put(xudc->padctl); 3918 3919 return err; 3920} 3921 3922static void tegra_xudc_remove(struct platform_device *pdev) 3923{ 3924 struct tegra_xudc *xudc = platform_get_drvdata(pdev); 3925 unsigned int i; 3926 3927 pm_runtime_get_sync(xudc->dev); 3928 3929 cancel_delayed_work_sync(&xudc->plc_reset_work); 3930 cancel_work_sync(&xudc->usb_role_sw_work); 3931 3932 usb_del_gadget_udc(&xudc->gadget); 3933 3934 tegra_xudc_free_eps(xudc); 3935 tegra_xudc_free_event_ring(xudc); 3936 3937 tegra_xudc_powerdomain_remove(xudc); 3938 3939 regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies); 3940 3941 for (i = 0; i < xudc->soc->num_phys; i++) { 3942 phy_power_off(xudc->utmi_phy[i]); 3943 phy_power_off(xudc->usb3_phy[i]); 3944 } 3945 3946 tegra_xudc_phy_exit(xudc); 3947 3948 pm_runtime_disable(xudc->dev); 3949 pm_runtime_put(xudc->dev); 3950 3951 tegra_xusb_padctl_put(xudc->padctl); 3952} 3953 3954static int __maybe_unused tegra_xudc_powergate(struct tegra_xudc *xudc) 3955{ 3956 unsigned long flags; 3957 u32 val; 3958 3959 dev_dbg(xudc->dev, "entering ELPG\n"); 3960 3961 spin_lock_irqsave(&xudc->lock, flags); 3962 3963 xudc->powergated = true; 3964 xudc->saved_regs.ctrl = xudc_readl(xudc, CTRL); 3965 xudc->saved_regs.portpm = xudc_readl(xudc, PORTPM); 3966 xudc_writel(xudc, 0, CTRL); 3967 3968 spin_unlock_irqrestore(&xudc->lock, flags); 3969 3970 val = xudc_readl(xudc, BLCG); 3971 val |= BLCG_COREPLL_PWRDN; 3972 xudc_writel(xudc, val, BLCG); 3973 3974 clk_bulk_disable_unprepare(xudc->soc->num_clks, xudc->clks); 3975 3976 regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies); 3977 3978 dev_dbg(xudc->dev, "entering ELPG done\n"); 3979 return 0; 3980} 3981 3982static int __maybe_unused tegra_xudc_unpowergate(struct tegra_xudc *xudc) 3983{ 3984 unsigned long flags; 3985 int err; 3986 3987 dev_dbg(xudc->dev, "exiting ELPG\n"); 3988 3989 err = regulator_bulk_enable(xudc->soc->num_supplies, 3990 xudc->supplies); 3991 if (err < 0) 3992 return err; 3993 3994 err = clk_bulk_prepare_enable(xudc->soc->num_clks, xudc->clks); 3995 if (err < 0) 3996 return err; 3997 3998 tegra_xudc_fpci_ipfs_init(xudc); 3999 4000 tegra_xudc_device_params_init(xudc); 4001 4002 tegra_xudc_init_event_ring(xudc); 4003 4004 tegra_xudc_init_eps(xudc); 4005 4006 xudc_writel(xudc, xudc->saved_regs.portpm, PORTPM); 4007 xudc_writel(xudc, xudc->saved_regs.ctrl, CTRL); 4008 4009 spin_lock_irqsave(&xudc->lock, flags); 4010 xudc->powergated = false; 4011 spin_unlock_irqrestore(&xudc->lock, flags); 4012 4013 dev_dbg(xudc->dev, "exiting ELPG done\n"); 4014 return 0; 4015} 4016 4017static int __maybe_unused tegra_xudc_suspend(struct device *dev) 4018{ 4019 struct tegra_xudc *xudc = dev_get_drvdata(dev); 4020 unsigned long flags; 4021 4022 spin_lock_irqsave(&xudc->lock, flags); 4023 xudc->suspended = true; 4024 spin_unlock_irqrestore(&xudc->lock, flags); 4025 4026 flush_work(&xudc->usb_role_sw_work); 4027 4028 if (!pm_runtime_status_suspended(dev)) { 4029 /* Forcibly disconnect before powergating. */ 4030 tegra_xudc_device_mode_off(xudc); 4031 tegra_xudc_powergate(xudc); 4032 } 4033 4034 pm_runtime_disable(dev); 4035 4036 return 0; 4037} 4038 4039static int __maybe_unused tegra_xudc_resume(struct device *dev) 4040{ 4041 struct tegra_xudc *xudc = dev_get_drvdata(dev); 4042 unsigned long flags; 4043 int err; 4044 4045 err = tegra_xudc_unpowergate(xudc); 4046 if (err < 0) 4047 return err; 4048 4049 spin_lock_irqsave(&xudc->lock, flags); 4050 xudc->suspended = false; 4051 if (xudc->device_mode != xudc->current_device_mode) 4052 schedule_work(&xudc->usb_role_sw_work); 4053 spin_unlock_irqrestore(&xudc->lock, flags); 4054 4055 pm_runtime_enable(dev); 4056 4057 return 0; 4058} 4059 4060static int __maybe_unused tegra_xudc_runtime_suspend(struct device *dev) 4061{ 4062 struct tegra_xudc *xudc = dev_get_drvdata(dev); 4063 4064 return tegra_xudc_powergate(xudc); 4065} 4066 4067static int __maybe_unused tegra_xudc_runtime_resume(struct device *dev) 4068{ 4069 struct tegra_xudc *xudc = dev_get_drvdata(dev); 4070 4071 return tegra_xudc_unpowergate(xudc); 4072} 4073 4074static const struct dev_pm_ops tegra_xudc_pm_ops = { 4075 SET_SYSTEM_SLEEP_PM_OPS(tegra_xudc_suspend, tegra_xudc_resume) 4076 SET_RUNTIME_PM_OPS(tegra_xudc_runtime_suspend, 4077 tegra_xudc_runtime_resume, NULL) 4078}; 4079 4080static struct platform_driver tegra_xudc_driver = { 4081 .probe = tegra_xudc_probe, 4082 .remove = tegra_xudc_remove, 4083 .driver = { 4084 .name = "tegra-xudc", 4085 .pm = &tegra_xudc_pm_ops, 4086 .of_match_table = tegra_xudc_of_match, 4087 }, 4088}; 4089module_platform_driver(tegra_xudc_driver); 4090 4091MODULE_DESCRIPTION("NVIDIA Tegra XUSB Device Controller"); 4092MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 4093MODULE_AUTHOR("Hui Fu <hfu@nvidia.com>"); 4094MODULE_AUTHOR("Nagarjuna Kristam <nkristam@nvidia.com>"); 4095MODULE_LICENSE("GPL v2");
~/
Read-only file preview.