omap_udc.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   4 *
   5 * Copyright (C) 2004 Texas Instruments, Inc.
   6 * Copyright (C) 2004-2005 David Brownell
   7 *
   8 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   9 */
  10
  11#undef	DEBUG
  12#undef	VERBOSE
  13
  14#include <linux/module.h>
  15#include <linux/kernel.h>
  16#include <linux/ioport.h>
  17#include <linux/types.h>
  18#include <linux/errno.h>
  19#include <linux/delay.h>
  20#include <linux/slab.h>
  21#include <linux/string_choices.h>
  22#include <linux/timer.h>
  23#include <linux/list.h>
  24#include <linux/interrupt.h>
  25#include <linux/proc_fs.h>
  26#include <linux/mm.h>
  27#include <linux/moduleparam.h>
  28#include <linux/platform_device.h>
  29#include <linux/usb/ch9.h>
  30#include <linux/usb/gadget.h>
  31#include <linux/usb/otg.h>
  32#include <linux/dma-mapping.h>
  33#include <linux/clk.h>
  34#include <linux/err.h>
  35#include <linux/prefetch.h>
  36#include <linux/io.h>
  37
  38#include <asm/byteorder.h>
  39#include <asm/irq.h>
  40#include <linux/unaligned.h>
  41#include <asm/mach-types.h>
  42
  43#include <linux/omap-dma.h>
  44#include <linux/platform_data/usb-omap1.h>
  45
  46#include <linux/soc/ti/omap1-usb.h>
  47#include <linux/soc/ti/omap1-soc.h>
  48#include <linux/soc/ti/omap1-io.h>
  49
  50#include "omap_udc.h"
  51
  52#undef	USB_TRACE
  53
  54/* bulk DMA seems to be behaving for both IN and OUT */
  55#define	USE_DMA
  56
  57/* ISO too */
  58#define	USE_ISO
  59
  60#define	DRIVER_VERSION	"4 October 2004"
  61
  62#define OMAP_DMA_USB_W2FC_TX0		29
  63#define OMAP_DMA_USB_W2FC_RX0		26
  64
  65/*
  66 * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  67 * D+ pullup to allow enumeration.  That's too early for the gadget
  68 * framework to use from usb_endpoint_enable(), which happens after
  69 * enumeration as part of activating an interface.  (But if we add an
  70 * optional new "UDC not yet running" state to the gadget driver model,
  71 * even just during driver binding, the endpoint autoconfig logic is the
  72 * natural spot to manufacture new endpoints.)
  73 *
  74 * So instead of using endpoint enable calls to control the hardware setup,
  75 * this driver defines a "fifo mode" parameter.  It's used during driver
  76 * initialization to choose among a set of pre-defined endpoint configs.
  77 * See omap_udc_setup() for available modes, or to add others.  That code
  78 * lives in an init section, so use this driver as a module if you need
  79 * to change the fifo mode after the kernel boots.
  80 *
  81 * Gadget drivers normally ignore endpoints they don't care about, and
  82 * won't include them in configuration descriptors.  That means only
  83 * misbehaving hosts would even notice they exist.
  84 */
  85#ifdef	USE_ISO
  86static unsigned fifo_mode = 3;
  87#else
  88static unsigned fifo_mode;
  89#endif
  90
  91/* "modprobe omap_udc fifo_mode=42", or else as a kernel
  92 * boot parameter "omap_udc:fifo_mode=42"
  93 */
  94module_param(fifo_mode, uint, 0);
  95MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
  96
  97#ifdef	USE_DMA
  98static bool use_dma = 1;
  99
 100/* "modprobe omap_udc use_dma=y", or else as a kernel
 101 * boot parameter "omap_udc:use_dma=y"
 102 */
 103module_param(use_dma, bool, 0);
 104MODULE_PARM_DESC(use_dma, "enable/disable DMA");
 105#else	/* !USE_DMA */
 106
 107/* save a bit of code */
 108#define	use_dma		0
 109#endif	/* !USE_DMA */
 110
 111
 112static const char driver_name[] = "omap_udc";
 113
 114/*-------------------------------------------------------------------------*/
 115
 116/* there's a notion of "current endpoint" for modifying endpoint
 117 * state, and PIO access to its FIFO.
 118 */
 119
 120static void use_ep(struct omap_ep *ep, u16 select)
 121{
 122	u16	num = ep->bEndpointAddress & 0x0f;
 123
 124	if (ep->bEndpointAddress & USB_DIR_IN)
 125		num |= UDC_EP_DIR;
 126	omap_writew(num | select, UDC_EP_NUM);
 127	/* when select, MUST deselect later !! */
 128}
 129
 130static inline void deselect_ep(void)
 131{
 132	u16 w;
 133
 134	w = omap_readw(UDC_EP_NUM);
 135	w &= ~UDC_EP_SEL;
 136	omap_writew(w, UDC_EP_NUM);
 137	/* 6 wait states before TX will happen */
 138}
 139
 140static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 141
 142/*-------------------------------------------------------------------------*/
 143
 144static int omap_ep_enable(struct usb_ep *_ep,
 145		const struct usb_endpoint_descriptor *desc)
 146{
 147	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
 148	struct omap_udc	*udc;
 149	unsigned long	flags;
 150	u16		maxp;
 151
 152	/* catch various bogus parameters */
 153	if (!_ep || !desc
 154			|| desc->bDescriptorType != USB_DT_ENDPOINT
 155			|| ep->bEndpointAddress != desc->bEndpointAddress
 156			|| ep->maxpacket < usb_endpoint_maxp(desc)) {
 157		DBG("%s, bad ep or descriptor\n", __func__);
 158		return -EINVAL;
 159	}
 160	maxp = usb_endpoint_maxp(desc);
 161	if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 162				&& maxp != ep->maxpacket)
 163			|| usb_endpoint_maxp(desc) > ep->maxpacket
 164			|| !desc->wMaxPacketSize) {
 165		DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 166		return -ERANGE;
 167	}
 168
 169#ifdef	USE_ISO
 170	if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 171				&& desc->bInterval != 1)) {
 172		/* hardware wants period = 1; USB allows 2^(Interval-1) */
 173		DBG("%s, unsupported ISO period %dms\n", _ep->name,
 174				1 << (desc->bInterval - 1));
 175		return -EDOM;
 176	}
 177#else
 178	if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 179		DBG("%s, ISO nyet\n", _ep->name);
 180		return -EDOM;
 181	}
 182#endif
 183
 184	/* xfer types must match, except that interrupt ~= bulk */
 185	if (ep->bmAttributes != desc->bmAttributes
 186			&& ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 187			&& desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 188		DBG("%s, %s type mismatch\n", __func__, _ep->name);
 189		return -EINVAL;
 190	}
 191
 192	udc = ep->udc;
 193	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 194		DBG("%s, bogus device state\n", __func__);
 195		return -ESHUTDOWN;
 196	}
 197
 198	spin_lock_irqsave(&udc->lock, flags);
 199
 200	ep->ep.desc = desc;
 201	ep->irqs = 0;
 202	ep->stopped = 0;
 203	ep->ep.maxpacket = maxp;
 204
 205	/* set endpoint to initial state */
 206	ep->dma_channel = 0;
 207	ep->has_dma = 0;
 208	ep->lch = -1;
 209	use_ep(ep, UDC_EP_SEL);
 210	omap_writew(udc->clr_halt, UDC_CTRL);
 211	ep->ackwait = 0;
 212	deselect_ep();
 213
 214	if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 215		list_add(&ep->iso, &udc->iso);
 216
 217	/* maybe assign a DMA channel to this endpoint */
 218	if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 219		/* FIXME ISO can dma, but prefers first channel */
 220		dma_channel_claim(ep, 0);
 221
 222	/* PIO OUT may RX packets */
 223	if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 224			&& !ep->has_dma
 225			&& !(ep->bEndpointAddress & USB_DIR_IN)) {
 226		omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 227		ep->ackwait = 1 + ep->double_buf;
 228	}
 229
 230	spin_unlock_irqrestore(&udc->lock, flags);
 231	VDBG("%s enabled\n", _ep->name);
 232	return 0;
 233}
 234
 235static void nuke(struct omap_ep *, int status);
 236
 237static int omap_ep_disable(struct usb_ep *_ep)
 238{
 239	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
 240	unsigned long	flags;
 241
 242	if (!_ep || !ep->ep.desc) {
 243		DBG("%s, %s not enabled\n", __func__,
 244			_ep ? ep->ep.name : NULL);
 245		return -EINVAL;
 246	}
 247
 248	spin_lock_irqsave(&ep->udc->lock, flags);
 249	ep->ep.desc = NULL;
 250	nuke(ep, -ESHUTDOWN);
 251	ep->ep.maxpacket = ep->maxpacket;
 252	ep->has_dma = 0;
 253	omap_writew(UDC_SET_HALT, UDC_CTRL);
 254	list_del_init(&ep->iso);
 255	timer_delete(&ep->timer);
 256
 257	spin_unlock_irqrestore(&ep->udc->lock, flags);
 258
 259	VDBG("%s disabled\n", _ep->name);
 260	return 0;
 261}
 262
 263/*-------------------------------------------------------------------------*/
 264
 265static struct usb_request *
 266omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 267{
 268	struct omap_req	*req;
 269
 270	req = kzalloc(sizeof(*req), gfp_flags);
 271	if (!req)
 272		return NULL;
 273
 274	INIT_LIST_HEAD(&req->queue);
 275
 276	return &req->req;
 277}
 278
 279static void
 280omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 281{
 282	struct omap_req	*req = container_of(_req, struct omap_req, req);
 283
 284	kfree(req);
 285}
 286
 287/*-------------------------------------------------------------------------*/
 288
 289static void
 290done(struct omap_ep *ep, struct omap_req *req, int status)
 291{
 292	struct omap_udc		*udc = ep->udc;
 293	unsigned		stopped = ep->stopped;
 294
 295	list_del_init(&req->queue);
 296
 297	if (req->req.status == -EINPROGRESS)
 298		req->req.status = status;
 299	else
 300		status = req->req.status;
 301
 302	if (use_dma && ep->has_dma)
 303		usb_gadget_unmap_request(&udc->gadget, &req->req,
 304				(ep->bEndpointAddress & USB_DIR_IN));
 305
 306#ifndef	USB_TRACE
 307	if (status && status != -ESHUTDOWN)
 308#endif
 309		VDBG("complete %s req %p stat %d len %u/%u\n",
 310			ep->ep.name, &req->req, status,
 311			req->req.actual, req->req.length);
 312
 313	/* don't modify queue heads during completion callback */
 314	ep->stopped = 1;
 315	spin_unlock(&ep->udc->lock);
 316	usb_gadget_giveback_request(&ep->ep, &req->req);
 317	spin_lock(&ep->udc->lock);
 318	ep->stopped = stopped;
 319}
 320
 321/*-------------------------------------------------------------------------*/
 322
 323#define UDC_FIFO_FULL		(UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 324#define UDC_FIFO_UNWRITABLE	(UDC_EP_HALTED | UDC_FIFO_FULL)
 325
 326#define FIFO_EMPTY	(UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 327#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 328
 329static inline int
 330write_packet(u8 *buf, struct omap_req *req, unsigned max)
 331{
 332	unsigned	len;
 333	u16		*wp;
 334
 335	len = min(req->req.length - req->req.actual, max);
 336	req->req.actual += len;
 337
 338	max = len;
 339	if (likely((((int)buf) & 1) == 0)) {
 340		wp = (u16 *)buf;
 341		while (max >= 2) {
 342			omap_writew(*wp++, UDC_DATA);
 343			max -= 2;
 344		}
 345		buf = (u8 *)wp;
 346	}
 347	while (max--)
 348		omap_writeb(*buf++, UDC_DATA);
 349	return len;
 350}
 351
 352/* FIXME change r/w fifo calling convention */
 353
 354
 355/* return:  0 = still running, 1 = completed, negative = errno */
 356static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 357{
 358	u8		*buf;
 359	unsigned	count;
 360	int		is_last;
 361	u16		ep_stat;
 362
 363	buf = req->req.buf + req->req.actual;
 364	prefetch(buf);
 365
 366	/* PIO-IN isn't double buffered except for iso */
 367	ep_stat = omap_readw(UDC_STAT_FLG);
 368	if (ep_stat & UDC_FIFO_UNWRITABLE)
 369		return 0;
 370
 371	count = ep->ep.maxpacket;
 372	count = write_packet(buf, req, count);
 373	omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 374	ep->ackwait = 1;
 375
 376	/* last packet is often short (sometimes a zlp) */
 377	if (count != ep->ep.maxpacket)
 378		is_last = 1;
 379	else if (req->req.length == req->req.actual
 380			&& !req->req.zero)
 381		is_last = 1;
 382	else
 383		is_last = 0;
 384
 385	/* NOTE:  requests complete when all IN data is in a
 386	 * FIFO (or sometimes later, if a zlp was needed).
 387	 * Use usb_ep_fifo_status() where needed.
 388	 */
 389	if (is_last)
 390		done(ep, req, 0);
 391	return is_last;
 392}
 393
 394static inline int
 395read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 396{
 397	unsigned	len;
 398	u16		*wp;
 399
 400	len = min(req->req.length - req->req.actual, avail);
 401	req->req.actual += len;
 402	avail = len;
 403
 404	if (likely((((int)buf) & 1) == 0)) {
 405		wp = (u16 *)buf;
 406		while (avail >= 2) {
 407			*wp++ = omap_readw(UDC_DATA);
 408			avail -= 2;
 409		}
 410		buf = (u8 *)wp;
 411	}
 412	while (avail--)
 413		*buf++ = omap_readb(UDC_DATA);
 414	return len;
 415}
 416
 417/* return:  0 = still running, 1 = queue empty, negative = errno */
 418static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 419{
 420	u8		*buf;
 421	unsigned	count, avail;
 422	int		is_last;
 423
 424	buf = req->req.buf + req->req.actual;
 425	prefetchw(buf);
 426
 427	for (;;) {
 428		u16	ep_stat = omap_readw(UDC_STAT_FLG);
 429
 430		is_last = 0;
 431		if (ep_stat & FIFO_EMPTY) {
 432			if (!ep->double_buf)
 433				break;
 434			ep->fnf = 1;
 435		}
 436		if (ep_stat & UDC_EP_HALTED)
 437			break;
 438
 439		if (ep_stat & UDC_FIFO_FULL)
 440			avail = ep->ep.maxpacket;
 441		else  {
 442			avail = omap_readw(UDC_RXFSTAT);
 443			ep->fnf = ep->double_buf;
 444		}
 445		count = read_packet(buf, req, avail);
 446
 447		/* partial packet reads may not be errors */
 448		if (count < ep->ep.maxpacket) {
 449			is_last = 1;
 450			/* overflowed this request?  flush extra data */
 451			if (count != avail) {
 452				req->req.status = -EOVERFLOW;
 453				avail -= count;
 454				while (avail--)
 455					omap_readw(UDC_DATA);
 456			}
 457		} else if (req->req.length == req->req.actual)
 458			is_last = 1;
 459		else
 460			is_last = 0;
 461
 462		if (!ep->bEndpointAddress)
 463			break;
 464		if (is_last)
 465			done(ep, req, 0);
 466		break;
 467	}
 468	return is_last;
 469}
 470
 471/*-------------------------------------------------------------------------*/
 472
 473static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 474{
 475	dma_addr_t	end;
 476
 477	/* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 478	 * the last transfer's bytecount by more than a FIFO's worth.
 479	 */
 480	if (cpu_is_omap15xx())
 481		return 0;
 482
 483	end = omap_get_dma_src_pos(ep->lch);
 484	if (end == ep->dma_counter)
 485		return 0;
 486
 487	end |= start & (0xffff << 16);
 488	if (end < start)
 489		end += 0x10000;
 490	return end - start;
 491}
 492
 493static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 494{
 495	dma_addr_t	end;
 496
 497	end = omap_get_dma_dst_pos(ep->lch);
 498	if (end == ep->dma_counter)
 499		return 0;
 500
 501	end |= start & (0xffff << 16);
 502	if (cpu_is_omap15xx())
 503		end++;
 504	if (end < start)
 505		end += 0x10000;
 506	return end - start;
 507}
 508
 509
 510/* Each USB transfer request using DMA maps to one or more DMA transfers.
 511 * When DMA completion isn't request completion, the UDC continues with
 512 * the next DMA transfer for that USB transfer.
 513 */
 514
 515static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 516{
 517	u16		txdma_ctrl, w;
 518	unsigned	length = req->req.length - req->req.actual;
 519	const int	sync_mode = cpu_is_omap15xx()
 520				? OMAP_DMA_SYNC_FRAME
 521				: OMAP_DMA_SYNC_ELEMENT;
 522	int		dma_trigger = 0;
 523
 524	/* measure length in either bytes or packets */
 525	if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 526			|| (cpu_is_omap15xx() && length < ep->maxpacket)) {
 527		txdma_ctrl = UDC_TXN_EOT | length;
 528		omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 529				length, 1, sync_mode, dma_trigger, 0);
 530	} else {
 531		length = min(length / ep->maxpacket,
 532				(unsigned) UDC_TXN_TSC + 1);
 533		txdma_ctrl = length;
 534		omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 535				ep->ep.maxpacket >> 1, length, sync_mode,
 536				dma_trigger, 0);
 537		length *= ep->maxpacket;
 538	}
 539	omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 540		OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 541		0, 0);
 542
 543	omap_start_dma(ep->lch);
 544	ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 545	w = omap_readw(UDC_DMA_IRQ_EN);
 546	w |= UDC_TX_DONE_IE(ep->dma_channel);
 547	omap_writew(w, UDC_DMA_IRQ_EN);
 548	omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
 549	req->dma_bytes = length;
 550}
 551
 552static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 553{
 554	u16 w;
 555
 556	if (status == 0) {
 557		req->req.actual += req->dma_bytes;
 558
 559		/* return if this request needs to send data or zlp */
 560		if (req->req.actual < req->req.length)
 561			return;
 562		if (req->req.zero
 563				&& req->dma_bytes != 0
 564				&& (req->req.actual % ep->maxpacket) == 0)
 565			return;
 566	} else
 567		req->req.actual += dma_src_len(ep, req->req.dma
 568							+ req->req.actual);
 569
 570	/* tx completion */
 571	omap_stop_dma(ep->lch);
 572	w = omap_readw(UDC_DMA_IRQ_EN);
 573	w &= ~UDC_TX_DONE_IE(ep->dma_channel);
 574	omap_writew(w, UDC_DMA_IRQ_EN);
 575	done(ep, req, status);
 576}
 577
 578static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 579{
 580	unsigned int packets = req->req.length - req->req.actual;
 581	int dma_trigger = 0;
 582	u16 w;
 583
 584	/* set up this DMA transfer, enable the fifo, start */
 585	packets /= ep->ep.maxpacket;
 586	packets = min_t(unsigned int, packets, UDC_RXN_TC + 1);
 587	req->dma_bytes = packets * ep->ep.maxpacket;
 588	omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 589			ep->ep.maxpacket >> 1, packets,
 590			OMAP_DMA_SYNC_ELEMENT,
 591			dma_trigger, 0);
 592	omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 593		OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 594		0, 0);
 595	ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 596
 597	omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
 598	w = omap_readw(UDC_DMA_IRQ_EN);
 599	w |= UDC_RX_EOT_IE(ep->dma_channel);
 600	omap_writew(w, UDC_DMA_IRQ_EN);
 601	omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
 602	omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 603
 604	omap_start_dma(ep->lch);
 605}
 606
 607static void
 608finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 609{
 610	u16	count, w;
 611
 612	if (status == 0)
 613		ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 614	count = dma_dest_len(ep, req->req.dma + req->req.actual);
 615	count += req->req.actual;
 616	if (one)
 617		count--;
 618	if (count <= req->req.length)
 619		req->req.actual = count;
 620
 621	if (count != req->dma_bytes || status)
 622		omap_stop_dma(ep->lch);
 623
 624	/* if this wasn't short, request may need another transfer */
 625	else if (req->req.actual < req->req.length)
 626		return;
 627
 628	/* rx completion */
 629	w = omap_readw(UDC_DMA_IRQ_EN);
 630	w &= ~UDC_RX_EOT_IE(ep->dma_channel);
 631	omap_writew(w, UDC_DMA_IRQ_EN);
 632	done(ep, req, status);
 633}
 634
 635static void dma_irq(struct omap_udc *udc, u16 irq_src)
 636{
 637	u16		dman_stat = omap_readw(UDC_DMAN_STAT);
 638	struct omap_ep	*ep;
 639	struct omap_req	*req;
 640
 641	/* IN dma: tx to host */
 642	if (irq_src & UDC_TXN_DONE) {
 643		ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 644		ep->irqs++;
 645		/* can see TXN_DONE after dma abort */
 646		if (!list_empty(&ep->queue)) {
 647			req = container_of(ep->queue.next,
 648						struct omap_req, queue);
 649			finish_in_dma(ep, req, 0);
 650		}
 651		omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 652
 653		if (!list_empty(&ep->queue)) {
 654			req = container_of(ep->queue.next,
 655					struct omap_req, queue);
 656			next_in_dma(ep, req);
 657		}
 658	}
 659
 660	/* OUT dma: rx from host */
 661	if (irq_src & UDC_RXN_EOT) {
 662		ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 663		ep->irqs++;
 664		/* can see RXN_EOT after dma abort */
 665		if (!list_empty(&ep->queue)) {
 666			req = container_of(ep->queue.next,
 667					struct omap_req, queue);
 668			finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 669		}
 670		omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 671
 672		if (!list_empty(&ep->queue)) {
 673			req = container_of(ep->queue.next,
 674					struct omap_req, queue);
 675			next_out_dma(ep, req);
 676		}
 677	}
 678
 679	if (irq_src & UDC_RXN_CNT) {
 680		ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 681		ep->irqs++;
 682		/* omap15xx does this unasked... */
 683		VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 684		omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
 685	}
 686}
 687
 688static void dma_error(int lch, u16 ch_status, void *data)
 689{
 690	struct omap_ep	*ep = data;
 691
 692	/* if ch_status & OMAP_DMA_DROP_IRQ ... */
 693	/* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 694	ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 695
 696	/* complete current transfer ... */
 697}
 698
 699static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 700{
 701	u16	reg;
 702	int	status, restart, is_in;
 703	int	dma_channel;
 704
 705	is_in = ep->bEndpointAddress & USB_DIR_IN;
 706	if (is_in)
 707		reg = omap_readw(UDC_TXDMA_CFG);
 708	else
 709		reg = omap_readw(UDC_RXDMA_CFG);
 710	reg |= UDC_DMA_REQ;		/* "pulse" activated */
 711
 712	ep->dma_channel = 0;
 713	ep->lch = -1;
 714	if (channel == 0 || channel > 3) {
 715		if ((reg & 0x0f00) == 0)
 716			channel = 3;
 717		else if ((reg & 0x00f0) == 0)
 718			channel = 2;
 719		else if ((reg & 0x000f) == 0)	/* preferred for ISO */
 720			channel = 1;
 721		else {
 722			status = -EMLINK;
 723			goto just_restart;
 724		}
 725	}
 726	reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 727	ep->dma_channel = channel;
 728
 729	if (is_in) {
 730		dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 731		status = omap_request_dma(dma_channel,
 732			ep->ep.name, dma_error, ep, &ep->lch);
 733		if (status == 0) {
 734			omap_writew(reg, UDC_TXDMA_CFG);
 735			/* EMIFF or SDRC */
 736			omap_set_dma_src_burst_mode(ep->lch,
 737						OMAP_DMA_DATA_BURST_4);
 738			omap_set_dma_src_data_pack(ep->lch, 1);
 739			/* TIPB */
 740			omap_set_dma_dest_params(ep->lch,
 741				OMAP_DMA_PORT_TIPB,
 742				OMAP_DMA_AMODE_CONSTANT,
 743				UDC_DATA_DMA,
 744				0, 0);
 745		}
 746	} else {
 747		dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 748		status = omap_request_dma(dma_channel,
 749			ep->ep.name, dma_error, ep, &ep->lch);
 750		if (status == 0) {
 751			omap_writew(reg, UDC_RXDMA_CFG);
 752			/* TIPB */
 753			omap_set_dma_src_params(ep->lch,
 754				OMAP_DMA_PORT_TIPB,
 755				OMAP_DMA_AMODE_CONSTANT,
 756				UDC_DATA_DMA,
 757				0, 0);
 758			/* EMIFF or SDRC */
 759			omap_set_dma_dest_burst_mode(ep->lch,
 760						OMAP_DMA_DATA_BURST_4);
 761			omap_set_dma_dest_data_pack(ep->lch, 1);
 762		}
 763	}
 764	if (status)
 765		ep->dma_channel = 0;
 766	else {
 767		ep->has_dma = 1;
 768		omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 769
 770		/* channel type P: hw synch (fifo) */
 771		if (!cpu_is_omap15xx())
 772			omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 773	}
 774
 775just_restart:
 776	/* restart any queue, even if the claim failed  */
 777	restart = !ep->stopped && !list_empty(&ep->queue);
 778
 779	if (status)
 780		DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 781			restart ? " (restart)" : "");
 782	else
 783		DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 784			is_in ? 't' : 'r',
 785			ep->dma_channel - 1, ep->lch,
 786			restart ? " (restart)" : "");
 787
 788	if (restart) {
 789		struct omap_req	*req;
 790		req = container_of(ep->queue.next, struct omap_req, queue);
 791		if (ep->has_dma)
 792			(is_in ? next_in_dma : next_out_dma)(ep, req);
 793		else {
 794			use_ep(ep, UDC_EP_SEL);
 795			(is_in ? write_fifo : read_fifo)(ep, req);
 796			deselect_ep();
 797			if (!is_in) {
 798				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 799				ep->ackwait = 1 + ep->double_buf;
 800			}
 801			/* IN: 6 wait states before it'll tx */
 802		}
 803	}
 804}
 805
 806static void dma_channel_release(struct omap_ep *ep)
 807{
 808	int		shift = 4 * (ep->dma_channel - 1);
 809	u16		mask = 0x0f << shift;
 810	struct omap_req	*req;
 811	int		active;
 812
 813	/* abort any active usb transfer request */
 814	if (!list_empty(&ep->queue))
 815		req = container_of(ep->queue.next, struct omap_req, queue);
 816	else
 817		req = NULL;
 818
 819	active = omap_get_dma_active_status(ep->lch);
 820
 821	DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 822			active ? "active" : "idle",
 823			(ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 824			ep->dma_channel - 1, req);
 825
 826	/* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 827	 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 828	 */
 829
 830	/* wait till current packet DMA finishes, and fifo empties */
 831	if (ep->bEndpointAddress & USB_DIR_IN) {
 832		omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 833					UDC_TXDMA_CFG);
 834
 835		if (req) {
 836			finish_in_dma(ep, req, -ECONNRESET);
 837
 838			/* clear FIFO; hosts probably won't empty it */
 839			use_ep(ep, UDC_EP_SEL);
 840			omap_writew(UDC_CLR_EP, UDC_CTRL);
 841			deselect_ep();
 842		}
 843		while (omap_readw(UDC_TXDMA_CFG) & mask)
 844			udelay(10);
 845	} else {
 846		omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 847					UDC_RXDMA_CFG);
 848
 849		/* dma empties the fifo */
 850		while (omap_readw(UDC_RXDMA_CFG) & mask)
 851			udelay(10);
 852		if (req)
 853			finish_out_dma(ep, req, -ECONNRESET, 0);
 854	}
 855	omap_free_dma(ep->lch);
 856	ep->dma_channel = 0;
 857	ep->lch = -1;
 858	/* has_dma still set, till endpoint is fully quiesced */
 859}
 860
 861
 862/*-------------------------------------------------------------------------*/
 863
 864static int
 865omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 866{
 867	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
 868	struct omap_req	*req = container_of(_req, struct omap_req, req);
 869	struct omap_udc	*udc;
 870	unsigned long	flags;
 871	int		is_iso = 0;
 872
 873	/* catch various bogus parameters */
 874	if (!_req || !req->req.complete || !req->req.buf
 875			|| !list_empty(&req->queue)) {
 876		DBG("%s, bad params\n", __func__);
 877		return -EINVAL;
 878	}
 879	if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
 880		DBG("%s, bad ep\n", __func__);
 881		return -EINVAL;
 882	}
 883	if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 884		if (req->req.length > ep->ep.maxpacket)
 885			return -EMSGSIZE;
 886		is_iso = 1;
 887	}
 888
 889	/* this isn't bogus, but OMAP DMA isn't the only hardware to
 890	 * have a hard time with partial packet reads...  reject it.
 891	 */
 892	if (use_dma
 893			&& ep->has_dma
 894			&& ep->bEndpointAddress != 0
 895			&& (ep->bEndpointAddress & USB_DIR_IN) == 0
 896			&& (req->req.length % ep->ep.maxpacket) != 0) {
 897		DBG("%s, no partial packet OUT reads\n", __func__);
 898		return -EMSGSIZE;
 899	}
 900
 901	udc = ep->udc;
 902	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 903		return -ESHUTDOWN;
 904
 905	if (use_dma && ep->has_dma)
 906		usb_gadget_map_request(&udc->gadget, &req->req,
 907				(ep->bEndpointAddress & USB_DIR_IN));
 908
 909	VDBG("%s queue req %p, len %d buf %p\n",
 910		ep->ep.name, _req, _req->length, _req->buf);
 911
 912	spin_lock_irqsave(&udc->lock, flags);
 913
 914	req->req.status = -EINPROGRESS;
 915	req->req.actual = 0;
 916
 917	/* maybe kickstart non-iso i/o queues */
 918	if (is_iso) {
 919		u16 w;
 920
 921		w = omap_readw(UDC_IRQ_EN);
 922		w |= UDC_SOF_IE;
 923		omap_writew(w, UDC_IRQ_EN);
 924	} else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 925		int	is_in;
 926
 927		if (ep->bEndpointAddress == 0) {
 928			if (!udc->ep0_pending || !list_empty(&ep->queue)) {
 929				spin_unlock_irqrestore(&udc->lock, flags);
 930				return -EL2HLT;
 931			}
 932
 933			/* empty DATA stage? */
 934			is_in = udc->ep0_in;
 935			if (!req->req.length) {
 936
 937				/* chip became CONFIGURED or ADDRESSED
 938				 * earlier; drivers may already have queued
 939				 * requests to non-control endpoints
 940				 */
 941				if (udc->ep0_set_config) {
 942					u16	irq_en = omap_readw(UDC_IRQ_EN);
 943
 944					irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 945					if (!udc->ep0_reset_config)
 946						irq_en |= UDC_EPN_RX_IE
 947							| UDC_EPN_TX_IE;
 948					omap_writew(irq_en, UDC_IRQ_EN);
 949				}
 950
 951				/* STATUS for zero length DATA stages is
 952				 * always an IN ... even for IN transfers,
 953				 * a weird case which seem to stall OMAP.
 954				 */
 955				omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 956						UDC_EP_NUM);
 957				omap_writew(UDC_CLR_EP, UDC_CTRL);
 958				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 959				omap_writew(UDC_EP_DIR, UDC_EP_NUM);
 960
 961				/* cleanup */
 962				udc->ep0_pending = 0;
 963				done(ep, req, 0);
 964				req = NULL;
 965
 966			/* non-empty DATA stage */
 967			} else if (is_in) {
 968				omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 969						UDC_EP_NUM);
 970			} else {
 971				if (udc->ep0_setup)
 972					goto irq_wait;
 973				omap_writew(UDC_EP_SEL, UDC_EP_NUM);
 974			}
 975		} else {
 976			is_in = ep->bEndpointAddress & USB_DIR_IN;
 977			if (!ep->has_dma)
 978				use_ep(ep, UDC_EP_SEL);
 979			/* if ISO: SOF IRQs must be enabled/disabled! */
 980		}
 981
 982		if (ep->has_dma)
 983			(is_in ? next_in_dma : next_out_dma)(ep, req);
 984		else if (req) {
 985			if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
 986				req = NULL;
 987			deselect_ep();
 988			if (!is_in) {
 989				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 990				ep->ackwait = 1 + ep->double_buf;
 991			}
 992			/* IN: 6 wait states before it'll tx */
 993		}
 994	}
 995
 996irq_wait:
 997	/* irq handler advances the queue */
 998	if (req != NULL)
 999		list_add_tail(&req->queue, &ep->queue);
1000	spin_unlock_irqrestore(&udc->lock, flags);
1001
1002	return 0;
1003}
1004
1005static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1006{
1007	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
1008	struct omap_req	*req = NULL, *iter;
1009	unsigned long	flags;
1010
1011	if (!_ep || !_req)
1012		return -EINVAL;
1013
1014	spin_lock_irqsave(&ep->udc->lock, flags);
1015
1016	/* make sure it's actually queued on this endpoint */
1017	list_for_each_entry(iter, &ep->queue, queue) {
1018		if (&iter->req != _req)
1019			continue;
1020		req = iter;
1021		break;
1022	}
1023	if (!req) {
1024		spin_unlock_irqrestore(&ep->udc->lock, flags);
1025		return -EINVAL;
1026	}
1027
1028	if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1029		int channel = ep->dma_channel;
1030
1031		/* releasing the channel cancels the request,
1032		 * reclaiming the channel restarts the queue
1033		 */
1034		dma_channel_release(ep);
1035		dma_channel_claim(ep, channel);
1036	} else
1037		done(ep, req, -ECONNRESET);
1038	spin_unlock_irqrestore(&ep->udc->lock, flags);
1039	return 0;
1040}
1041
1042/*-------------------------------------------------------------------------*/
1043
1044static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1045{
1046	struct omap_ep	*ep = container_of(_ep, struct omap_ep, ep);
1047	unsigned long	flags;
1048	int		status = -EOPNOTSUPP;
1049
1050	spin_lock_irqsave(&ep->udc->lock, flags);
1051
1052	/* just use protocol stalls for ep0; real halts are annoying */
1053	if (ep->bEndpointAddress == 0) {
1054		if (!ep->udc->ep0_pending)
1055			status = -EINVAL;
1056		else if (value) {
1057			if (ep->udc->ep0_set_config) {
1058				WARNING("error changing config?\n");
1059				omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1060			}
1061			omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1062			ep->udc->ep0_pending = 0;
1063			status = 0;
1064		} else /* NOP */
1065			status = 0;
1066
1067	/* otherwise, all active non-ISO endpoints can halt */
1068	} else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1069
1070		/* IN endpoints must already be idle */
1071		if ((ep->bEndpointAddress & USB_DIR_IN)
1072				&& !list_empty(&ep->queue)) {
1073			status = -EAGAIN;
1074			goto done;
1075		}
1076
1077		if (value) {
1078			int	channel;
1079
1080			if (use_dma && ep->dma_channel
1081					&& !list_empty(&ep->queue)) {
1082				channel = ep->dma_channel;
1083				dma_channel_release(ep);
1084			} else
1085				channel = 0;
1086
1087			use_ep(ep, UDC_EP_SEL);
1088			if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1089				omap_writew(UDC_SET_HALT, UDC_CTRL);
1090				status = 0;
1091			} else
1092				status = -EAGAIN;
1093			deselect_ep();
1094
1095			if (channel)
1096				dma_channel_claim(ep, channel);
1097		} else {
1098			use_ep(ep, 0);
1099			omap_writew(ep->udc->clr_halt, UDC_CTRL);
1100			ep->ackwait = 0;
1101			if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1102				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1103				ep->ackwait = 1 + ep->double_buf;
1104			}
1105		}
1106	}
1107done:
1108	VDBG("%s %s halt stat %d\n", ep->ep.name,
1109		value ? "set" : "clear", status);
1110
1111	spin_unlock_irqrestore(&ep->udc->lock, flags);
1112	return status;
1113}
1114
1115static const struct usb_ep_ops omap_ep_ops = {
1116	.enable		= omap_ep_enable,
1117	.disable	= omap_ep_disable,
1118
1119	.alloc_request	= omap_alloc_request,
1120	.free_request	= omap_free_request,
1121
1122	.queue		= omap_ep_queue,
1123	.dequeue	= omap_ep_dequeue,
1124
1125	.set_halt	= omap_ep_set_halt,
1126	/* fifo_status ... report bytes in fifo */
1127	/* fifo_flush ... flush fifo */
1128};
1129
1130/*-------------------------------------------------------------------------*/
1131
1132static int omap_get_frame(struct usb_gadget *gadget)
1133{
1134	u16	sof = omap_readw(UDC_SOF);
1135	return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1136}
1137
1138static int omap_wakeup(struct usb_gadget *gadget)
1139{
1140	struct omap_udc	*udc;
1141	unsigned long	flags;
1142	int		retval = -EHOSTUNREACH;
1143
1144	udc = container_of(gadget, struct omap_udc, gadget);
1145
1146	spin_lock_irqsave(&udc->lock, flags);
1147	if (udc->devstat & UDC_SUS) {
1148		/* NOTE:  OTG spec erratum says that OTG devices may
1149		 * issue wakeups without host enable.
1150		 */
1151		if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1152			DBG("remote wakeup...\n");
1153			omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1154			retval = 0;
1155		}
1156
1157	/* NOTE:  non-OTG systems may use SRP TOO... */
1158	} else if (!(udc->devstat & UDC_ATT)) {
1159		if (!IS_ERR_OR_NULL(udc->transceiver))
1160			retval = otg_start_srp(udc->transceiver->otg);
1161	}
1162	spin_unlock_irqrestore(&udc->lock, flags);
1163
1164	return retval;
1165}
1166
1167static int
1168omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1169{
1170	struct omap_udc	*udc;
1171	unsigned long	flags;
1172	u16		syscon1;
1173
1174	gadget->is_selfpowered = (is_selfpowered != 0);
1175	udc = container_of(gadget, struct omap_udc, gadget);
1176	spin_lock_irqsave(&udc->lock, flags);
1177	syscon1 = omap_readw(UDC_SYSCON1);
1178	if (is_selfpowered)
1179		syscon1 |= UDC_SELF_PWR;
1180	else
1181		syscon1 &= ~UDC_SELF_PWR;
1182	omap_writew(syscon1, UDC_SYSCON1);
1183	spin_unlock_irqrestore(&udc->lock, flags);
1184
1185	return 0;
1186}
1187
1188static int can_pullup(struct omap_udc *udc)
1189{
1190	return udc->driver && udc->softconnect && udc->vbus_active;
1191}
1192
1193static void pullup_enable(struct omap_udc *udc)
1194{
1195	u16 w;
1196
1197	w = omap_readw(UDC_SYSCON1);
1198	w |= UDC_PULLUP_EN;
1199	omap_writew(w, UDC_SYSCON1);
1200	if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1201		u32 l;
1202
1203		l = omap_readl(OTG_CTRL);
1204		l |= OTG_BSESSVLD;
1205		omap_writel(l, OTG_CTRL);
1206	}
1207	omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1208}
1209
1210static void pullup_disable(struct omap_udc *udc)
1211{
1212	u16 w;
1213
1214	if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1215		u32 l;
1216
1217		l = omap_readl(OTG_CTRL);
1218		l &= ~OTG_BSESSVLD;
1219		omap_writel(l, OTG_CTRL);
1220	}
1221	omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1222	w = omap_readw(UDC_SYSCON1);
1223	w &= ~UDC_PULLUP_EN;
1224	omap_writew(w, UDC_SYSCON1);
1225}
1226
1227static struct omap_udc *udc;
1228
1229static void omap_udc_enable_clock(int enable)
1230{
1231	if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1232		return;
1233
1234	if (enable) {
1235		clk_enable(udc->dc_clk);
1236		clk_enable(udc->hhc_clk);
1237		udelay(100);
1238	} else {
1239		clk_disable(udc->hhc_clk);
1240		clk_disable(udc->dc_clk);
1241	}
1242}
1243
1244/*
1245 * Called by whatever detects VBUS sessions:  external transceiver
1246 * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1247 */
1248static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1249{
1250	struct omap_udc	*udc;
1251	unsigned long	flags;
1252	u32 l;
1253
1254	udc = container_of(gadget, struct omap_udc, gadget);
1255	spin_lock_irqsave(&udc->lock, flags);
1256	VDBG("VBUS %s\n", str_on_off(is_active));
1257	udc->vbus_active = (is_active != 0);
1258	if (cpu_is_omap15xx()) {
1259		/* "software" detect, ignored if !VBUS_MODE_1510 */
1260		l = omap_readl(FUNC_MUX_CTRL_0);
1261		if (is_active)
1262			l |= VBUS_CTRL_1510;
1263		else
1264			l &= ~VBUS_CTRL_1510;
1265		omap_writel(l, FUNC_MUX_CTRL_0);
1266	}
1267	if (udc->dc_clk != NULL && is_active) {
1268		if (!udc->clk_requested) {
1269			omap_udc_enable_clock(1);
1270			udc->clk_requested = 1;
1271		}
1272	}
1273	if (can_pullup(udc))
1274		pullup_enable(udc);
1275	else
1276		pullup_disable(udc);
1277	if (udc->dc_clk != NULL && !is_active) {
1278		if (udc->clk_requested) {
1279			omap_udc_enable_clock(0);
1280			udc->clk_requested = 0;
1281		}
1282	}
1283	spin_unlock_irqrestore(&udc->lock, flags);
1284	return 0;
1285}
1286
1287static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1288{
1289	struct omap_udc	*udc;
1290
1291	udc = container_of(gadget, struct omap_udc, gadget);
1292	if (!IS_ERR_OR_NULL(udc->transceiver))
1293		return usb_phy_set_power(udc->transceiver, mA);
1294	return -EOPNOTSUPP;
1295}
1296
1297static int omap_pullup(struct usb_gadget *gadget, int is_on)
1298{
1299	struct omap_udc	*udc;
1300	unsigned long	flags;
1301
1302	udc = container_of(gadget, struct omap_udc, gadget);
1303	spin_lock_irqsave(&udc->lock, flags);
1304	udc->softconnect = (is_on != 0);
1305	if (can_pullup(udc))
1306		pullup_enable(udc);
1307	else
1308		pullup_disable(udc);
1309	spin_unlock_irqrestore(&udc->lock, flags);
1310	return 0;
1311}
1312
1313static int omap_udc_start(struct usb_gadget *g,
1314		struct usb_gadget_driver *driver);
1315static int omap_udc_stop(struct usb_gadget *g);
1316
1317static const struct usb_gadget_ops omap_gadget_ops = {
1318	.get_frame		= omap_get_frame,
1319	.wakeup			= omap_wakeup,
1320	.set_selfpowered	= omap_set_selfpowered,
1321	.vbus_session		= omap_vbus_session,
1322	.vbus_draw		= omap_vbus_draw,
1323	.pullup			= omap_pullup,
1324	.udc_start		= omap_udc_start,
1325	.udc_stop		= omap_udc_stop,
1326};
1327
1328/*-------------------------------------------------------------------------*/
1329
1330/* dequeue ALL requests; caller holds udc->lock */
1331static void nuke(struct omap_ep *ep, int status)
1332{
1333	struct omap_req	*req;
1334
1335	ep->stopped = 1;
1336
1337	if (use_dma && ep->dma_channel)
1338		dma_channel_release(ep);
1339
1340	use_ep(ep, 0);
1341	omap_writew(UDC_CLR_EP, UDC_CTRL);
1342	if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1343		omap_writew(UDC_SET_HALT, UDC_CTRL);
1344
1345	while (!list_empty(&ep->queue)) {
1346		req = list_entry(ep->queue.next, struct omap_req, queue);
1347		done(ep, req, status);
1348	}
1349}
1350
1351/* caller holds udc->lock */
1352static void udc_quiesce(struct omap_udc *udc)
1353{
1354	struct omap_ep	*ep;
1355
1356	udc->gadget.speed = USB_SPEED_UNKNOWN;
1357	nuke(&udc->ep[0], -ESHUTDOWN);
1358	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1359		nuke(ep, -ESHUTDOWN);
1360}
1361
1362/*-------------------------------------------------------------------------*/
1363
1364static void update_otg(struct omap_udc *udc)
1365{
1366	u16	devstat;
1367
1368	if (!gadget_is_otg(&udc->gadget))
1369		return;
1370
1371	if (omap_readl(OTG_CTRL) & OTG_ID)
1372		devstat = omap_readw(UDC_DEVSTAT);
1373	else
1374		devstat = 0;
1375
1376	udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1377	udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1378	udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1379
1380	/* Enable HNP early, avoiding races on suspend irq path.
1381	 * ASSUMES OTG state machine B_BUS_REQ input is true.
1382	 */
1383	if (udc->gadget.b_hnp_enable) {
1384		u32 l;
1385
1386		l = omap_readl(OTG_CTRL);
1387		l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1388		l &= ~OTG_PULLUP;
1389		omap_writel(l, OTG_CTRL);
1390	}
1391}
1392
1393static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1394{
1395	struct omap_ep	*ep0 = &udc->ep[0];
1396	struct omap_req	*req = NULL;
1397
1398	ep0->irqs++;
1399
1400	/* Clear any pending requests and then scrub any rx/tx state
1401	 * before starting to handle the SETUP request.
1402	 */
1403	if (irq_src & UDC_SETUP) {
1404		u16	ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1405
1406		nuke(ep0, 0);
1407		if (ack) {
1408			omap_writew(ack, UDC_IRQ_SRC);
1409			irq_src = UDC_SETUP;
1410		}
1411	}
1412
1413	/* IN/OUT packets mean we're in the DATA or STATUS stage.
1414	 * This driver uses only uses protocol stalls (ep0 never halts),
1415	 * and if we got this far the gadget driver already had a
1416	 * chance to stall.  Tries to be forgiving of host oddities.
1417	 *
1418	 * NOTE:  the last chance gadget drivers have to stall control
1419	 * requests is during their request completion callback.
1420	 */
1421	if (!list_empty(&ep0->queue))
1422		req = container_of(ep0->queue.next, struct omap_req, queue);
1423
1424	/* IN == TX to host */
1425	if (irq_src & UDC_EP0_TX) {
1426		int	stat;
1427
1428		omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1429		omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1430		stat = omap_readw(UDC_STAT_FLG);
1431		if (stat & UDC_ACK) {
1432			if (udc->ep0_in) {
1433				/* write next IN packet from response,
1434				 * or set up the status stage.
1435				 */
1436				if (req)
1437					stat = write_fifo(ep0, req);
1438				omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1439				if (!req && udc->ep0_pending) {
1440					omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1441					omap_writew(UDC_CLR_EP, UDC_CTRL);
1442					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1443					omap_writew(0, UDC_EP_NUM);
1444					udc->ep0_pending = 0;
1445				} /* else:  6 wait states before it'll tx */
1446			} else {
1447				/* ack status stage of OUT transfer */
1448				omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1449				if (req)
1450					done(ep0, req, 0);
1451			}
1452			req = NULL;
1453		} else if (stat & UDC_STALL) {
1454			omap_writew(UDC_CLR_HALT, UDC_CTRL);
1455			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1456		} else {
1457			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1458		}
1459	}
1460
1461	/* OUT == RX from host */
1462	if (irq_src & UDC_EP0_RX) {
1463		int	stat;
1464
1465		omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1466		omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1467		stat = omap_readw(UDC_STAT_FLG);
1468		if (stat & UDC_ACK) {
1469			if (!udc->ep0_in) {
1470				stat = 0;
1471				/* read next OUT packet of request, maybe
1472				 * reactivating the fifo; stall on errors.
1473				 */
1474				stat = read_fifo(ep0, req);
1475				if (!req || stat < 0) {
1476					omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1477					udc->ep0_pending = 0;
1478					stat = 0;
1479				} else if (stat == 0)
1480					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1481				omap_writew(0, UDC_EP_NUM);
1482
1483				/* activate status stage */
1484				if (stat == 1) {
1485					done(ep0, req, 0);
1486					/* that may have STALLed ep0... */
1487					omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1488							UDC_EP_NUM);
1489					omap_writew(UDC_CLR_EP, UDC_CTRL);
1490					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1491					omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1492					udc->ep0_pending = 0;
1493				}
1494			} else {
1495				/* ack status stage of IN transfer */
1496				omap_writew(0, UDC_EP_NUM);
1497				if (req)
1498					done(ep0, req, 0);
1499			}
1500		} else if (stat & UDC_STALL) {
1501			omap_writew(UDC_CLR_HALT, UDC_CTRL);
1502			omap_writew(0, UDC_EP_NUM);
1503		} else {
1504			omap_writew(0, UDC_EP_NUM);
1505		}
1506	}
1507
1508	/* SETUP starts all control transfers */
1509	if (irq_src & UDC_SETUP) {
1510		union u {
1511			u16			word[4];
1512			struct usb_ctrlrequest	r;
1513		} u;
1514		int			status = -EINVAL;
1515		struct omap_ep		*ep;
1516
1517		/* read the (latest) SETUP message */
1518		do {
1519			omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1520			/* two bytes at a time */
1521			u.word[0] = omap_readw(UDC_DATA);
1522			u.word[1] = omap_readw(UDC_DATA);
1523			u.word[2] = omap_readw(UDC_DATA);
1524			u.word[3] = omap_readw(UDC_DATA);
1525			omap_writew(0, UDC_EP_NUM);
1526		} while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1527
1528#define	w_value		le16_to_cpu(u.r.wValue)
1529#define	w_index		le16_to_cpu(u.r.wIndex)
1530#define	w_length	le16_to_cpu(u.r.wLength)
1531
1532		/* Delegate almost all control requests to the gadget driver,
1533		 * except for a handful of ch9 status/feature requests that
1534		 * hardware doesn't autodecode _and_ the gadget API hides.
1535		 */
1536		udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1537		udc->ep0_set_config = 0;
1538		udc->ep0_pending = 1;
1539		ep0->stopped = 0;
1540		ep0->ackwait = 0;
1541		switch (u.r.bRequest) {
1542		case USB_REQ_SET_CONFIGURATION:
1543			/* udc needs to know when ep != 0 is valid */
1544			if (u.r.bRequestType != USB_RECIP_DEVICE)
1545				goto delegate;
1546			if (w_length != 0)
1547				goto do_stall;
1548			udc->ep0_set_config = 1;
1549			udc->ep0_reset_config = (w_value == 0);
1550			VDBG("set config %d\n", w_value);
1551
1552			/* update udc NOW since gadget driver may start
1553			 * queueing requests immediately; clear config
1554			 * later if it fails the request.
1555			 */
1556			if (udc->ep0_reset_config)
1557				omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1558			else
1559				omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1560			update_otg(udc);
1561			goto delegate;
1562		case USB_REQ_CLEAR_FEATURE:
1563			/* clear endpoint halt */
1564			if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1565				goto delegate;
1566			if (w_value != USB_ENDPOINT_HALT
1567					|| w_length != 0)
1568				goto do_stall;
1569			ep = &udc->ep[w_index & 0xf];
1570			if (ep != ep0) {
1571				if (w_index & USB_DIR_IN)
1572					ep += 16;
1573				if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1574						|| !ep->ep.desc)
1575					goto do_stall;
1576				use_ep(ep, 0);
1577				omap_writew(udc->clr_halt, UDC_CTRL);
1578				ep->ackwait = 0;
1579				if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1580					omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1581					ep->ackwait = 1 + ep->double_buf;
1582				}
1583				/* NOTE:  assumes the host behaves sanely,
1584				 * only clearing real halts.  Else we may
1585				 * need to kill pending transfers and then
1586				 * restart the queue... very messy for DMA!
1587				 */
1588			}
1589			VDBG("%s halt cleared by host\n", ep->name);
1590			goto ep0out_status_stage;
1591		case USB_REQ_SET_FEATURE:
1592			/* set endpoint halt */
1593			if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1594				goto delegate;
1595			if (w_value != USB_ENDPOINT_HALT
1596					|| w_length != 0)
1597				goto do_stall;
1598			ep = &udc->ep[w_index & 0xf];
1599			if (w_index & USB_DIR_IN)
1600				ep += 16;
1601			if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1602					|| ep == ep0 || !ep->ep.desc)
1603				goto do_stall;
1604			if (use_dma && ep->has_dma) {
1605				/* this has rude side-effects (aborts) and
1606				 * can't really work if DMA-IN is active
1607				 */
1608				DBG("%s host set_halt, NYET\n", ep->name);
1609				goto do_stall;
1610			}
1611			use_ep(ep, 0);
1612			/* can't halt if fifo isn't empty... */
1613			omap_writew(UDC_CLR_EP, UDC_CTRL);
1614			omap_writew(UDC_SET_HALT, UDC_CTRL);
1615			VDBG("%s halted by host\n", ep->name);
1616ep0out_status_stage:
1617			status = 0;
1618			omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1619			omap_writew(UDC_CLR_EP, UDC_CTRL);
1620			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1621			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1622			udc->ep0_pending = 0;
1623			break;
1624		case USB_REQ_GET_STATUS:
1625			/* USB_ENDPOINT_HALT status? */
1626			if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1627				goto intf_status;
1628
1629			/* ep0 never stalls */
1630			if (!(w_index & 0xf))
1631				goto zero_status;
1632
1633			/* only active endpoints count */
1634			ep = &udc->ep[w_index & 0xf];
1635			if (w_index & USB_DIR_IN)
1636				ep += 16;
1637			if (!ep->ep.desc)
1638				goto do_stall;
1639
1640			/* iso never stalls */
1641			if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1642				goto zero_status;
1643
1644			/* FIXME don't assume non-halted endpoints!! */
1645			ERR("%s status, can't report\n", ep->ep.name);
1646			goto do_stall;
1647
1648intf_status:
1649			/* return interface status.  if we were pedantic,
1650			 * we'd detect non-existent interfaces, and stall.
1651			 */
1652			if (u.r.bRequestType
1653					!= (USB_DIR_IN|USB_RECIP_INTERFACE))
1654				goto delegate;
1655
1656zero_status:
1657			/* return two zero bytes */
1658			omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1659			omap_writew(0, UDC_DATA);
1660			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1661			omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1662			status = 0;
1663			VDBG("GET_STATUS, interface %d\n", w_index);
1664			/* next, status stage */
1665			break;
1666		default:
1667delegate:
1668			/* activate the ep0out fifo right away */
1669			if (!udc->ep0_in && w_length) {
1670				omap_writew(0, UDC_EP_NUM);
1671				omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1672			}
1673
1674			/* gadget drivers see class/vendor specific requests,
1675			 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1676			 * and more
1677			 */
1678			VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1679				u.r.bRequestType, u.r.bRequest,
1680				w_value, w_index, w_length);
1681
1682#undef	w_value
1683#undef	w_index
1684#undef	w_length
1685
1686			/* The gadget driver may return an error here,
1687			 * causing an immediate protocol stall.
1688			 *
1689			 * Else it must issue a response, either queueing a
1690			 * response buffer for the DATA stage, or halting ep0
1691			 * (causing a protocol stall, not a real halt).  A
1692			 * zero length buffer means no DATA stage.
1693			 *
1694			 * It's fine to issue that response after the setup()
1695			 * call returns, and this IRQ was handled.
1696			 */
1697			udc->ep0_setup = 1;
1698			spin_unlock(&udc->lock);
1699			status = udc->driver->setup(&udc->gadget, &u.r);
1700			spin_lock(&udc->lock);
1701			udc->ep0_setup = 0;
1702		}
1703
1704		if (status < 0) {
1705do_stall:
1706			VDBG("req %02x.%02x protocol STALL; stat %d\n",
1707					u.r.bRequestType, u.r.bRequest, status);
1708			if (udc->ep0_set_config) {
1709				if (udc->ep0_reset_config)
1710					WARNING("error resetting config?\n");
1711				else
1712					omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1713			}
1714			omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1715			udc->ep0_pending = 0;
1716		}
1717	}
1718}
1719
1720/*-------------------------------------------------------------------------*/
1721
1722#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1723
1724static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1725{
1726	u16	devstat, change;
1727
1728	devstat = omap_readw(UDC_DEVSTAT);
1729	change = devstat ^ udc->devstat;
1730	udc->devstat = devstat;
1731
1732	if (change & (UDC_USB_RESET|UDC_ATT)) {
1733		udc_quiesce(udc);
1734
1735		if (change & UDC_ATT) {
1736			/* driver for any external transceiver will
1737			 * have called omap_vbus_session() already
1738			 */
1739			if (devstat & UDC_ATT) {
1740				udc->gadget.speed = USB_SPEED_FULL;
1741				VDBG("connect\n");
1742				if (IS_ERR_OR_NULL(udc->transceiver))
1743					pullup_enable(udc);
1744				/* if (driver->connect) call it */
1745			} else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1746				udc->gadget.speed = USB_SPEED_UNKNOWN;
1747				if (IS_ERR_OR_NULL(udc->transceiver))
1748					pullup_disable(udc);
1749				DBG("disconnect, gadget %s\n",
1750					udc->driver->driver.name);
1751				if (udc->driver->disconnect) {
1752					spin_unlock(&udc->lock);
1753					udc->driver->disconnect(&udc->gadget);
1754					spin_lock(&udc->lock);
1755				}
1756			}
1757			change &= ~UDC_ATT;
1758		}
1759
1760		if (change & UDC_USB_RESET) {
1761			if (devstat & UDC_USB_RESET) {
1762				VDBG("RESET=1\n");
1763			} else {
1764				udc->gadget.speed = USB_SPEED_FULL;
1765				INFO("USB reset done, gadget %s\n",
1766					udc->driver->driver.name);
1767				/* ep0 traffic is legal from now on */
1768				omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1769						UDC_IRQ_EN);
1770			}
1771			change &= ~UDC_USB_RESET;
1772		}
1773	}
1774	if (change & UDC_SUS) {
1775		if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1776			/* FIXME tell isp1301 to suspend/resume (?) */
1777			if (devstat & UDC_SUS) {
1778				VDBG("suspend\n");
1779				update_otg(udc);
1780				/* HNP could be under way already */
1781				if (udc->gadget.speed == USB_SPEED_FULL
1782						&& udc->driver->suspend) {
1783					spin_unlock(&udc->lock);
1784					udc->driver->suspend(&udc->gadget);
1785					spin_lock(&udc->lock);
1786				}
1787				if (!IS_ERR_OR_NULL(udc->transceiver))
1788					usb_phy_set_suspend(
1789							udc->transceiver, 1);
1790			} else {
1791				VDBG("resume\n");
1792				if (!IS_ERR_OR_NULL(udc->transceiver))
1793					usb_phy_set_suspend(
1794							udc->transceiver, 0);
1795				if (udc->gadget.speed == USB_SPEED_FULL
1796						&& udc->driver->resume) {
1797					spin_unlock(&udc->lock);
1798					udc->driver->resume(&udc->gadget);
1799					spin_lock(&udc->lock);
1800				}
1801			}
1802		}
1803		change &= ~UDC_SUS;
1804	}
1805	if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1806		update_otg(udc);
1807		change &= ~OTG_FLAGS;
1808	}
1809
1810	change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1811	if (change)
1812		VDBG("devstat %03x, ignore change %03x\n",
1813			devstat,  change);
1814
1815	omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1816}
1817
1818static irqreturn_t omap_udc_irq(int irq, void *_udc)
1819{
1820	struct omap_udc	*udc = _udc;
1821	u16		irq_src;
1822	irqreturn_t	status = IRQ_NONE;
1823	unsigned long	flags;
1824
1825	spin_lock_irqsave(&udc->lock, flags);
1826	irq_src = omap_readw(UDC_IRQ_SRC);
1827
1828	/* Device state change (usb ch9 stuff) */
1829	if (irq_src & UDC_DS_CHG) {
1830		devstate_irq(_udc, irq_src);
1831		status = IRQ_HANDLED;
1832		irq_src &= ~UDC_DS_CHG;
1833	}
1834
1835	/* EP0 control transfers */
1836	if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1837		ep0_irq(_udc, irq_src);
1838		status = IRQ_HANDLED;
1839		irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1840	}
1841
1842	/* DMA transfer completion */
1843	if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1844		dma_irq(_udc, irq_src);
1845		status = IRQ_HANDLED;
1846		irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1847	}
1848
1849	irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1850	if (irq_src)
1851		DBG("udc_irq, unhandled %03x\n", irq_src);
1852	spin_unlock_irqrestore(&udc->lock, flags);
1853
1854	return status;
1855}
1856
1857/* workaround for seemingly-lost IRQs for RX ACKs... */
1858#define PIO_OUT_TIMEOUT	(jiffies + HZ/3)
1859#define HALF_FULL(f)	(!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1860
1861static void pio_out_timer(struct timer_list *t)
1862{
1863	struct omap_ep	*ep = timer_container_of(ep, t, timer);
1864	unsigned long	flags;
1865	u16		stat_flg;
1866
1867	spin_lock_irqsave(&ep->udc->lock, flags);
1868	if (!list_empty(&ep->queue) && ep->ackwait) {
1869		use_ep(ep, UDC_EP_SEL);
1870		stat_flg = omap_readw(UDC_STAT_FLG);
1871
1872		if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1873				|| (ep->double_buf && HALF_FULL(stat_flg)))) {
1874			struct omap_req	*req;
1875
1876			VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1877			req = container_of(ep->queue.next,
1878					struct omap_req, queue);
1879			(void) read_fifo(ep, req);
1880			omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1881			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1882			ep->ackwait = 1 + ep->double_buf;
1883		} else
1884			deselect_ep();
1885	}
1886	mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1887	spin_unlock_irqrestore(&ep->udc->lock, flags);
1888}
1889
1890static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1891{
1892	u16		epn_stat, irq_src;
1893	irqreturn_t	status = IRQ_NONE;
1894	struct omap_ep	*ep;
1895	int		epnum;
1896	struct omap_udc	*udc = _dev;
1897	struct omap_req	*req;
1898	unsigned long	flags;
1899
1900	spin_lock_irqsave(&udc->lock, flags);
1901	epn_stat = omap_readw(UDC_EPN_STAT);
1902	irq_src = omap_readw(UDC_IRQ_SRC);
1903
1904	/* handle OUT first, to avoid some wasteful NAKs */
1905	if (irq_src & UDC_EPN_RX) {
1906		epnum = (epn_stat >> 8) & 0x0f;
1907		omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1908		status = IRQ_HANDLED;
1909		ep = &udc->ep[epnum];
1910		ep->irqs++;
1911
1912		omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1913		ep->fnf = 0;
1914		if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1915			ep->ackwait--;
1916			if (!list_empty(&ep->queue)) {
1917				int stat;
1918				req = container_of(ep->queue.next,
1919						struct omap_req, queue);
1920				stat = read_fifo(ep, req);
1921				if (!ep->double_buf)
1922					ep->fnf = 1;
1923			}
1924		}
1925		/* min 6 clock delay before clearing EP_SEL ... */
1926		epn_stat = omap_readw(UDC_EPN_STAT);
1927		epn_stat = omap_readw(UDC_EPN_STAT);
1928		omap_writew(epnum, UDC_EP_NUM);
1929
1930		/* enabling fifo _after_ clearing ACK, contrary to docs,
1931		 * reduces lossage; timer still needed though (sigh).
1932		 */
1933		if (ep->fnf) {
1934			omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1935			ep->ackwait = 1 + ep->double_buf;
1936		}
1937		mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1938	}
1939
1940	/* then IN transfers */
1941	else if (irq_src & UDC_EPN_TX) {
1942		epnum = epn_stat & 0x0f;
1943		omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1944		status = IRQ_HANDLED;
1945		ep = &udc->ep[16 + epnum];
1946		ep->irqs++;
1947
1948		omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1949		if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1950			ep->ackwait = 0;
1951			if (!list_empty(&ep->queue)) {
1952				req = container_of(ep->queue.next,
1953						struct omap_req, queue);
1954				(void) write_fifo(ep, req);
1955			}
1956		}
1957		/* min 6 clock delay before clearing EP_SEL ... */
1958		epn_stat = omap_readw(UDC_EPN_STAT);
1959		epn_stat = omap_readw(UDC_EPN_STAT);
1960		omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1961		/* then 6 clocks before it'd tx */
1962	}
1963
1964	spin_unlock_irqrestore(&udc->lock, flags);
1965	return status;
1966}
1967
1968#ifdef	USE_ISO
1969static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1970{
1971	struct omap_udc	*udc = _dev;
1972	struct omap_ep	*ep;
1973	int		pending = 0;
1974	unsigned long	flags;
1975
1976	spin_lock_irqsave(&udc->lock, flags);
1977
1978	/* handle all non-DMA ISO transfers */
1979	list_for_each_entry(ep, &udc->iso, iso) {
1980		u16		stat;
1981		struct omap_req	*req;
1982
1983		if (ep->has_dma || list_empty(&ep->queue))
1984			continue;
1985		req = list_entry(ep->queue.next, struct omap_req, queue);
1986
1987		use_ep(ep, UDC_EP_SEL);
1988		stat = omap_readw(UDC_STAT_FLG);
1989
1990		/* NOTE: like the other controller drivers, this isn't
1991		 * currently reporting lost or damaged frames.
1992		 */
1993		if (ep->bEndpointAddress & USB_DIR_IN) {
1994			if (stat & UDC_MISS_IN)
1995				/* done(ep, req, -EPROTO) */;
1996			else
1997				write_fifo(ep, req);
1998		} else {
1999			int	status = 0;
2000
2001			if (stat & UDC_NO_RXPACKET)
2002				status = -EREMOTEIO;
2003			else if (stat & UDC_ISO_ERR)
2004				status = -EILSEQ;
2005			else if (stat & UDC_DATA_FLUSH)
2006				status = -ENOSR;
2007
2008			if (status)
2009				/* done(ep, req, status) */;
2010			else
2011				read_fifo(ep, req);
2012		}
2013		deselect_ep();
2014		/* 6 wait states before next EP */
2015
2016		ep->irqs++;
2017		if (!list_empty(&ep->queue))
2018			pending = 1;
2019	}
2020	if (!pending) {
2021		u16 w;
2022
2023		w = omap_readw(UDC_IRQ_EN);
2024		w &= ~UDC_SOF_IE;
2025		omap_writew(w, UDC_IRQ_EN);
2026	}
2027	omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2028
2029	spin_unlock_irqrestore(&udc->lock, flags);
2030	return IRQ_HANDLED;
2031}
2032#endif
2033
2034/*-------------------------------------------------------------------------*/
2035
2036static inline int machine_without_vbus_sense(void)
2037{
2038	return  machine_is_omap_osk() || machine_is_omap_palmte() ||
2039		machine_is_sx1();
2040}
2041
2042static int omap_udc_start(struct usb_gadget *g,
2043		struct usb_gadget_driver *driver)
2044{
2045	int		status;
2046	struct omap_ep	*ep;
2047	unsigned long	flags;
2048
2049
2050	spin_lock_irqsave(&udc->lock, flags);
2051	/* reset state */
2052	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2053		ep->irqs = 0;
2054		if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2055			continue;
2056		use_ep(ep, 0);
2057		omap_writew(UDC_SET_HALT, UDC_CTRL);
2058	}
2059	udc->ep0_pending = 0;
2060	udc->ep[0].irqs = 0;
2061	udc->softconnect = 1;
2062
2063	/* hook up the driver */
2064	udc->driver = driver;
2065	spin_unlock_irqrestore(&udc->lock, flags);
2066
2067	if (udc->dc_clk != NULL)
2068		omap_udc_enable_clock(1);
2069
2070	omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2071
2072	/* connect to bus through transceiver */
2073	if (!IS_ERR_OR_NULL(udc->transceiver)) {
2074		status = otg_set_peripheral(udc->transceiver->otg,
2075						&udc->gadget);
2076		if (status < 0) {
2077			ERR("can't bind to transceiver\n");
2078			udc->driver = NULL;
2079			goto done;
2080		}
2081	} else {
2082		status = 0;
2083		if (can_pullup(udc))
2084			pullup_enable(udc);
2085		else
2086			pullup_disable(udc);
2087	}
2088
2089	/* boards that don't have VBUS sensing can't autogate 48MHz;
2090	 * can't enter deep sleep while a gadget driver is active.
2091	 */
2092	if (machine_without_vbus_sense())
2093		omap_vbus_session(&udc->gadget, 1);
2094
2095done:
2096	if (udc->dc_clk != NULL)
2097		omap_udc_enable_clock(0);
2098
2099	return status;
2100}
2101
2102static int omap_udc_stop(struct usb_gadget *g)
2103{
2104	unsigned long	flags;
2105
2106	if (udc->dc_clk != NULL)
2107		omap_udc_enable_clock(1);
2108
2109	if (machine_without_vbus_sense())
2110		omap_vbus_session(&udc->gadget, 0);
2111
2112	if (!IS_ERR_OR_NULL(udc->transceiver))
2113		(void) otg_set_peripheral(udc->transceiver->otg, NULL);
2114	else
2115		pullup_disable(udc);
2116
2117	spin_lock_irqsave(&udc->lock, flags);
2118	udc_quiesce(udc);
2119	spin_unlock_irqrestore(&udc->lock, flags);
2120
2121	udc->driver = NULL;
2122
2123	if (udc->dc_clk != NULL)
2124		omap_udc_enable_clock(0);
2125
2126	return 0;
2127}
2128
2129/*-------------------------------------------------------------------------*/
2130
2131#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2132
2133#include <linux/seq_file.h>
2134
2135static const char proc_filename[] = "driver/udc";
2136
2137#define FOURBITS "%s%s%s%s"
2138#define EIGHTBITS "%s%s%s%s%s%s%s%s"
2139
2140static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2141{
2142	u16		stat_flg;
2143	struct omap_req	*req;
2144	char		buf[20];
2145
2146	use_ep(ep, 0);
2147
2148	if (use_dma && ep->has_dma)
2149		snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2150			(ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2151			ep->dma_channel - 1, ep->lch);
2152	else
2153		buf[0] = 0;
2154
2155	stat_flg = omap_readw(UDC_STAT_FLG);
2156	seq_printf(s,
2157		"\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2158		ep->name, buf,
2159		ep->double_buf ? "dbuf " : "",
2160		({ char *s;
2161		switch (ep->ackwait) {
2162		case 0:
2163			s = "";
2164			break;
2165		case 1:
2166			s = "(ackw) ";
2167			break;
2168		case 2:
2169			s = "(ackw2) ";
2170			break;
2171		default:
2172			s = "(?) ";
2173			break;
2174		} s; }),
2175		ep->irqs, stat_flg,
2176		(stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2177		(stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2178		(stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2179		(stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2180		(stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2181		(stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2182		(stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2183		(stat_flg & UDC_STALL) ? "STALL " : "",
2184		(stat_flg & UDC_NAK) ? "NAK " : "",
2185		(stat_flg & UDC_ACK) ? "ACK " : "",
2186		(stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2187		(stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2188		(stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2189
2190	if (list_empty(&ep->queue))
2191		seq_printf(s, "\t(queue empty)\n");
2192	else
2193		list_for_each_entry(req, &ep->queue, queue) {
2194			unsigned	length = req->req.actual;
2195
2196			if (use_dma && buf[0]) {
2197				length += ((ep->bEndpointAddress & USB_DIR_IN)
2198						? dma_src_len : dma_dest_len)
2199					(ep, req->req.dma + length);
2200				buf[0] = 0;
2201			}
2202			seq_printf(s, "\treq %p len %d/%d buf %p\n",
2203					&req->req, length,
2204					req->req.length, req->req.buf);
2205		}
2206}
2207
2208static char *trx_mode(unsigned m, int enabled)
2209{
2210	switch (m) {
2211	case 0:
2212		return enabled ? "*6wire" : "unused";
2213	case 1:
2214		return "4wire";
2215	case 2:
2216		return "3wire";
2217	case 3:
2218		return "6wire";
2219	default:
2220		return "unknown";
2221	}
2222}
2223
2224static int proc_otg_show(struct seq_file *s)
2225{
2226	u32		tmp;
2227	u32		trans = 0;
2228	char		*ctrl_name = "(UNKNOWN)";
2229
2230	tmp = omap_readl(OTG_REV);
2231	ctrl_name = "transceiver_ctrl";
2232	trans = omap_readw(USB_TRANSCEIVER_CTRL);
2233	seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2234		tmp >> 4, tmp & 0xf, ctrl_name, trans);
2235	tmp = omap_readw(OTG_SYSCON_1);
2236	seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2237			FOURBITS "\n", tmp,
2238		trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2239		trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2240		(USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2241			? "internal"
2242			: trx_mode(USB0_TRX_MODE(tmp), 1),
2243		(tmp & OTG_IDLE_EN) ? " !otg" : "",
2244		(tmp & HST_IDLE_EN) ? " !host" : "",
2245		(tmp & DEV_IDLE_EN) ? " !dev" : "",
2246		(tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2247	tmp = omap_readl(OTG_SYSCON_2);
2248	seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2249			" b_ase_brst=%d hmc=%d\n", tmp,
2250		(tmp & OTG_EN) ? " otg_en" : "",
2251		(tmp & USBX_SYNCHRO) ? " synchro" : "",
2252		/* much more SRP stuff */
2253		(tmp & SRP_DATA) ? " srp_data" : "",
2254		(tmp & SRP_VBUS) ? " srp_vbus" : "",
2255		(tmp & OTG_PADEN) ? " otg_paden" : "",
2256		(tmp & HMC_PADEN) ? " hmc_paden" : "",
2257		(tmp & UHOST_EN) ? " uhost_en" : "",
2258		(tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2259		(tmp & HMC_TLLATTACH) ? " tllattach" : "",
2260		B_ASE_BRST(tmp),
2261		OTG_HMC(tmp));
2262	tmp = omap_readl(OTG_CTRL);
2263	seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2264		(tmp & OTG_ASESSVLD) ? " asess" : "",
2265		(tmp & OTG_BSESSEND) ? " bsess_end" : "",
2266		(tmp & OTG_BSESSVLD) ? " bsess" : "",
2267		(tmp & OTG_VBUSVLD) ? " vbus" : "",
2268		(tmp & OTG_ID) ? " id" : "",
2269		(tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2270		(tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2271		(tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2272		(tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2273		(tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2274		(tmp & OTG_BUSDROP) ? " busdrop" : "",
2275		(tmp & OTG_PULLDOWN) ? " down" : "",
2276		(tmp & OTG_PULLUP) ? " up" : "",
2277		(tmp & OTG_DRV_VBUS) ? " drv" : "",
2278		(tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2279		(tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2280		(tmp & OTG_PU_ID) ? " pu_id" : ""
2281		);
2282	tmp = omap_readw(OTG_IRQ_EN);
2283	seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2284	tmp = omap_readw(OTG_IRQ_SRC);
2285	seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2286	tmp = omap_readw(OTG_OUTCTRL);
2287	seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2288	tmp = omap_readw(OTG_TEST);
2289	seq_printf(s, "otg_test    %04x" "\n", tmp);
2290	return 0;
2291}
2292
2293static int proc_udc_show(struct seq_file *s, void *_)
2294{
2295	u32		tmp;
2296	struct omap_ep	*ep;
2297	unsigned long	flags;
2298
2299	spin_lock_irqsave(&udc->lock, flags);
2300
2301	seq_printf(s, "OMAP UDC driver, version: " DRIVER_VERSION
2302#ifdef	USE_ISO
2303		" (iso)"
2304#endif
2305		"%s\n", use_dma ?  " (dma)" : "");
2306
2307	tmp = omap_readw(UDC_REV) & 0xff;
2308	seq_printf(s,
2309		"UDC rev %d.%d, fifo mode %d, gadget %s\n"
2310		"hmc %d, transceiver %s\n",
2311		tmp >> 4, tmp & 0xf,
2312		fifo_mode,
2313		udc->driver ? udc->driver->driver.name : "(none)",
2314		HMC,
2315		udc->transceiver
2316			? udc->transceiver->label
2317			: (cpu_is_omap1710()
2318				? "external" : "(none)"));
2319	seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2320		omap_readw(ULPD_CLOCK_CTRL),
2321		omap_readw(ULPD_SOFT_REQ),
2322		omap_readw(ULPD_STATUS_REQ));
2323
2324	/* OTG controller registers */
2325	if (!cpu_is_omap15xx())
2326		proc_otg_show(s);
2327
2328	tmp = omap_readw(UDC_SYSCON1);
2329	seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2330		(tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2331		(tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2332		(tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2333		(tmp & UDC_NAK_EN) ? " nak" : "",
2334		(tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2335		(tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2336		(tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2337		(tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2338	/* syscon2 is write-only */
2339
2340	/* UDC controller registers */
2341	if (!(tmp & UDC_PULLUP_EN)) {
2342		seq_printf(s, "(suspended)\n");
2343		spin_unlock_irqrestore(&udc->lock, flags);
2344		return 0;
2345	}
2346
2347	tmp = omap_readw(UDC_DEVSTAT);
2348	seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2349		(tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2350		(tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2351		(tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2352		(tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2353		(tmp & UDC_USB_RESET) ? " usb_reset" : "",
2354		(tmp & UDC_SUS) ? " SUS" : "",
2355		(tmp & UDC_CFG) ? " CFG" : "",
2356		(tmp & UDC_ADD) ? " ADD" : "",
2357		(tmp & UDC_DEF) ? " DEF" : "",
2358		(tmp & UDC_ATT) ? " ATT" : "");
2359	seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2360	tmp = omap_readw(UDC_IRQ_EN);
2361	seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2362		(tmp & UDC_SOF_IE) ? " sof" : "",
2363		(tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2364		(tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2365		(tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2366		(tmp & UDC_EP0_IE) ? " ep0" : "");
2367	tmp = omap_readw(UDC_IRQ_SRC);
2368	seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2369		(tmp & UDC_TXN_DONE) ? " txn_done" : "",
2370		(tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2371		(tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2372		(tmp & UDC_IRQ_SOF) ? " sof" : "",
2373		(tmp & UDC_EPN_RX) ? " epn_rx" : "",
2374		(tmp & UDC_EPN_TX) ? " epn_tx" : "",
2375		(tmp & UDC_DS_CHG) ? " ds_chg" : "",
2376		(tmp & UDC_SETUP) ? " setup" : "",
2377		(tmp & UDC_EP0_RX) ? " ep0out" : "",
2378		(tmp & UDC_EP0_TX) ? " ep0in" : "");
2379	if (use_dma) {
2380		unsigned i;
2381
2382		tmp = omap_readw(UDC_DMA_IRQ_EN);
2383		seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2384			(tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2385			(tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2386			(tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2387
2388			(tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2389			(tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2390			(tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2391
2392			(tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2393			(tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2394			(tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2395
2396		tmp = omap_readw(UDC_RXDMA_CFG);
2397		seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2398		if (tmp) {
2399			for (i = 0; i < 3; i++) {
2400				if ((tmp & (0x0f << (i * 4))) == 0)
2401					continue;
2402				seq_printf(s, "rxdma[%d]    %04x\n", i,
2403						omap_readw(UDC_RXDMA(i + 1)));
2404			}
2405		}
2406		tmp = omap_readw(UDC_TXDMA_CFG);
2407		seq_printf(s, "txdma_cfg   %04x\n", tmp);
2408		if (tmp) {
2409			for (i = 0; i < 3; i++) {
2410				if (!(tmp & (0x0f << (i * 4))))
2411					continue;
2412				seq_printf(s, "txdma[%d]    %04x\n", i,
2413						omap_readw(UDC_TXDMA(i + 1)));
2414			}
2415		}
2416	}
2417
2418	tmp = omap_readw(UDC_DEVSTAT);
2419	if (tmp & UDC_ATT) {
2420		proc_ep_show(s, &udc->ep[0]);
2421		if (tmp & UDC_ADD) {
2422			list_for_each_entry(ep, &udc->gadget.ep_list,
2423					ep.ep_list) {
2424				if (ep->ep.desc)
2425					proc_ep_show(s, ep);
2426			}
2427		}
2428	}
2429	spin_unlock_irqrestore(&udc->lock, flags);
2430	return 0;
2431}
2432
2433static void create_proc_file(void)
2434{
2435	proc_create_single(proc_filename, 0, NULL, proc_udc_show);
2436}
2437
2438static void remove_proc_file(void)
2439{
2440	remove_proc_entry(proc_filename, NULL);
2441}
2442
2443#else
2444
2445static inline void create_proc_file(void) {}
2446static inline void remove_proc_file(void) {}
2447
2448#endif
2449
2450/*-------------------------------------------------------------------------*/
2451
2452/* Before this controller can enumerate, we need to pick an endpoint
2453 * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2454 * buffer space among the endpoints we'll be operating.
2455 *
2456 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2457 * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2458 * capability yet though.
2459 */
2460static unsigned
2461omap_ep_setup(char *name, u8 addr, u8 type,
2462		unsigned buf, unsigned maxp, int dbuf)
2463{
2464	struct omap_ep	*ep;
2465	u16		epn_rxtx = 0;
2466
2467	/* OUT endpoints first, then IN */
2468	ep = &udc->ep[addr & 0xf];
2469	if (addr & USB_DIR_IN)
2470		ep += 16;
2471
2472	/* in case of ep init table bugs */
2473	BUG_ON(ep->name[0]);
2474
2475	/* chip setup ... bit values are same for IN, OUT */
2476	if (type == USB_ENDPOINT_XFER_ISOC) {
2477		switch (maxp) {
2478		case 8:
2479			epn_rxtx = 0 << 12;
2480			break;
2481		case 16:
2482			epn_rxtx = 1 << 12;
2483			break;
2484		case 32:
2485			epn_rxtx = 2 << 12;
2486			break;
2487		case 64:
2488			epn_rxtx = 3 << 12;
2489			break;
2490		case 128:
2491			epn_rxtx = 4 << 12;
2492			break;
2493		case 256:
2494			epn_rxtx = 5 << 12;
2495			break;
2496		case 512:
2497			epn_rxtx = 6 << 12;
2498			break;
2499		default:
2500			BUG();
2501		}
2502		epn_rxtx |= UDC_EPN_RX_ISO;
2503		dbuf = 1;
2504	} else {
2505		/* double-buffering "not supported" on 15xx,
2506		 * and ignored for PIO-IN on newer chips
2507		 * (for more reliable behavior)
2508		 */
2509		if (!use_dma || cpu_is_omap15xx())
2510			dbuf = 0;
2511
2512		switch (maxp) {
2513		case 8:
2514			epn_rxtx = 0 << 12;
2515			break;
2516		case 16:
2517			epn_rxtx = 1 << 12;
2518			break;
2519		case 32:
2520			epn_rxtx = 2 << 12;
2521			break;
2522		case 64:
2523			epn_rxtx = 3 << 12;
2524			break;
2525		default:
2526			BUG();
2527		}
2528		if (dbuf && addr)
2529			epn_rxtx |= UDC_EPN_RX_DB;
2530		timer_setup(&ep->timer, pio_out_timer, 0);
2531	}
2532	if (addr)
2533		epn_rxtx |= UDC_EPN_RX_VALID;
2534	BUG_ON(buf & 0x07);
2535	epn_rxtx |= buf >> 3;
2536
2537	DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2538		name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2539
2540	if (addr & USB_DIR_IN)
2541		omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2542	else
2543		omap_writew(epn_rxtx, UDC_EP_RX(addr));
2544
2545	/* next endpoint's buffer starts after this one's */
2546	buf += maxp;
2547	if (dbuf)
2548		buf += maxp;
2549	BUG_ON(buf > 2048);
2550
2551	/* set up driver data structures */
2552	BUG_ON(strlen(name) >= sizeof ep->name);
2553	strscpy(ep->name, name, sizeof(ep->name));
2554	INIT_LIST_HEAD(&ep->queue);
2555	INIT_LIST_HEAD(&ep->iso);
2556	ep->bEndpointAddress = addr;
2557	ep->bmAttributes = type;
2558	ep->double_buf = dbuf;
2559	ep->udc = udc;
2560
2561	switch (type) {
2562	case USB_ENDPOINT_XFER_CONTROL:
2563		ep->ep.caps.type_control = true;
2564		ep->ep.caps.dir_in = true;
2565		ep->ep.caps.dir_out = true;
2566		break;
2567	case USB_ENDPOINT_XFER_ISOC:
2568		ep->ep.caps.type_iso = true;
2569		break;
2570	case USB_ENDPOINT_XFER_BULK:
2571		ep->ep.caps.type_bulk = true;
2572		break;
2573	case USB_ENDPOINT_XFER_INT:
2574		ep->ep.caps.type_int = true;
2575		break;
2576	}
2577
2578	if (addr & USB_DIR_IN)
2579		ep->ep.caps.dir_in = true;
2580	else
2581		ep->ep.caps.dir_out = true;
2582
2583	ep->ep.name = ep->name;
2584	ep->ep.ops = &omap_ep_ops;
2585	ep->maxpacket = maxp;
2586	usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
2587	list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2588
2589	return buf;
2590}
2591
2592static void omap_udc_release(struct device *dev)
2593{
2594	pullup_disable(udc);
2595	if (!IS_ERR_OR_NULL(udc->transceiver)) {
2596		usb_put_phy(udc->transceiver);
2597		udc->transceiver = NULL;
2598	}
2599	omap_writew(0, UDC_SYSCON1);
2600	remove_proc_file();
2601	if (udc->dc_clk) {
2602		if (udc->clk_requested)
2603			omap_udc_enable_clock(0);
2604		clk_unprepare(udc->hhc_clk);
2605		clk_unprepare(udc->dc_clk);
2606		clk_put(udc->hhc_clk);
2607		clk_put(udc->dc_clk);
2608	}
2609	if (udc->done)
2610		complete(udc->done);
2611	kfree(udc);
2612}
2613
2614static int
2615omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2616{
2617	unsigned	tmp, buf;
2618
2619	/* abolish any previous hardware state */
2620	omap_writew(0, UDC_SYSCON1);
2621	omap_writew(0, UDC_IRQ_EN);
2622	omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2623	omap_writew(0, UDC_DMA_IRQ_EN);
2624	omap_writew(0, UDC_RXDMA_CFG);
2625	omap_writew(0, UDC_TXDMA_CFG);
2626
2627	/* UDC_PULLUP_EN gates the chip clock */
2628	/* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2629
2630	udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2631	if (!udc)
2632		return -ENOMEM;
2633
2634	spin_lock_init(&udc->lock);
2635
2636	udc->gadget.ops = &omap_gadget_ops;
2637	udc->gadget.ep0 = &udc->ep[0].ep;
2638	INIT_LIST_HEAD(&udc->gadget.ep_list);
2639	INIT_LIST_HEAD(&udc->iso);
2640	udc->gadget.speed = USB_SPEED_UNKNOWN;
2641	udc->gadget.max_speed = USB_SPEED_FULL;
2642	udc->gadget.name = driver_name;
2643	udc->gadget.quirk_ep_out_aligned_size = 1;
2644	udc->transceiver = xceiv;
2645
2646	/* ep0 is special; put it right after the SETUP buffer */
2647	buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2648			8 /* after SETUP */, 64 /* maxpacket */, 0);
2649	list_del_init(&udc->ep[0].ep.ep_list);
2650
2651	/* initially disable all non-ep0 endpoints */
2652	for (tmp = 1; tmp < 15; tmp++) {
2653		omap_writew(0, UDC_EP_RX(tmp));
2654		omap_writew(0, UDC_EP_TX(tmp));
2655	}
2656
2657#define OMAP_BULK_EP(name, addr) \
2658	buf = omap_ep_setup(name "-bulk", addr, \
2659			USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2660#define OMAP_INT_EP(name, addr, maxp) \
2661	buf = omap_ep_setup(name "-int", addr, \
2662			USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2663#define OMAP_ISO_EP(name, addr, maxp) \
2664	buf = omap_ep_setup(name "-iso", addr, \
2665			USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2666
2667	switch (fifo_mode) {
2668	case 0:
2669		OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2670		OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2671		OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2672		break;
2673	case 1:
2674		OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2675		OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2676		OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2677
2678		OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2679		OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2680		OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2681
2682		OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2683		OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2684		OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2685
2686		OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2687		OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2688		OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2689
2690		OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2691		OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2692		OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2693		OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2694
2695		OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2696		OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2697		OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2698		OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2699
2700		OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2701		OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2702
2703		break;
2704
2705#ifdef	USE_ISO
2706	case 2:			/* mixed iso/bulk */
2707		OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2708		OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2709		OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2710		OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2711
2712		OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2713
2714		OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2715		OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2716		OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2717		break;
2718	case 3:			/* mixed bulk/iso */
2719		OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2720		OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2721		OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2722
2723		OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2724		OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2725		OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2726
2727		OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2728		OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2729		OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2730		break;
2731#endif
2732
2733	/* add more modes as needed */
2734
2735	default:
2736		ERR("unsupported fifo_mode #%d\n", fifo_mode);
2737		return -ENODEV;
2738	}
2739	omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2740	INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2741	return 0;
2742}
2743
2744static int omap_udc_probe(struct platform_device *pdev)
2745{
2746	int			status = -ENODEV;
2747	int			hmc;
2748	struct usb_phy		*xceiv = NULL;
2749	const char		*type = NULL;
2750	struct omap_usb_config	*config = dev_get_platdata(&pdev->dev);
2751	struct clk		*dc_clk = NULL;
2752	struct clk		*hhc_clk = NULL;
2753
2754	/* NOTE:  "knows" the order of the resources! */
2755	if (!request_mem_region(pdev->resource[0].start,
2756			resource_size(&pdev->resource[0]),
2757			driver_name)) {
2758		DBG("request_mem_region failed\n");
2759		return -EBUSY;
2760	}
2761
2762	if (cpu_is_omap16xx()) {
2763		dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2764		hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2765		BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2766		/* can't use omap_udc_enable_clock yet */
2767		clk_prepare_enable(dc_clk);
2768		clk_prepare_enable(hhc_clk);
2769		udelay(100);
2770	}
2771
2772	INFO("OMAP UDC rev %d.%d%s\n",
2773		omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2774		config->otg ? ", Mini-AB" : "");
2775
2776	/* use the mode given to us by board init code */
2777	if (cpu_is_omap15xx()) {
2778		hmc = HMC_1510;
2779		type = "(unknown)";
2780
2781		if (machine_without_vbus_sense()) {
2782			/* just set up software VBUS detect, and then
2783			 * later rig it so we always report VBUS.
2784			 * FIXME without really sensing VBUS, we can't
2785			 * know when to turn PULLUP_EN on/off; and that
2786			 * means we always "need" the 48MHz clock.
2787			 */
2788			u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2789			tmp &= ~VBUS_CTRL_1510;
2790			omap_writel(tmp, FUNC_MUX_CTRL_0);
2791			tmp |= VBUS_MODE_1510;
2792			tmp &= ~VBUS_CTRL_1510;
2793			omap_writel(tmp, FUNC_MUX_CTRL_0);
2794		}
2795	} else {
2796		/* The transceiver may package some GPIO logic or handle
2797		 * loopback and/or transceiverless setup; if we find one,
2798		 * use it.  Except for OTG, we don't _need_ to talk to one;
2799		 * but not having one probably means no VBUS detection.
2800		 */
2801		xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2802		if (!IS_ERR_OR_NULL(xceiv))
2803			type = xceiv->label;
2804		else if (config->otg) {
2805			DBG("OTG requires external transceiver!\n");
2806			goto cleanup0;
2807		}
2808
2809		hmc = HMC_1610;
2810
2811		switch (hmc) {
2812		case 0:			/* POWERUP DEFAULT == 0 */
2813		case 4:
2814		case 12:
2815		case 20:
2816			if (!cpu_is_omap1710()) {
2817				type = "integrated";
2818				break;
2819			}
2820			fallthrough;
2821		case 3:
2822		case 11:
2823		case 16:
2824		case 19:
2825		case 25:
2826			if (IS_ERR_OR_NULL(xceiv)) {
2827				DBG("external transceiver not registered!\n");
2828				type = "unknown";
2829			}
2830			break;
2831		case 21:			/* internal loopback */
2832			type = "loopback";
2833			break;
2834		case 14:			/* transceiverless */
2835			if (cpu_is_omap1710())
2836				goto bad_on_1710;
2837			fallthrough;
2838		case 13:
2839		case 15:
2840			type = "no";
2841			break;
2842
2843		default:
2844bad_on_1710:
2845			ERR("unrecognized UDC HMC mode %d\n", hmc);
2846			goto cleanup0;
2847		}
2848	}
2849
2850	INFO("hmc mode %d, %s transceiver\n", hmc, type);
2851
2852	/* a "gadget" abstracts/virtualizes the controller */
2853	status = omap_udc_setup(pdev, xceiv);
2854	if (status)
2855		goto cleanup0;
2856
2857	xceiv = NULL;
2858	/* "udc" is now valid */
2859	pullup_disable(udc);
2860#if	IS_ENABLED(CONFIG_USB_OHCI_HCD)
2861	udc->gadget.is_otg = (config->otg != 0);
2862#endif
2863
2864	/* starting with omap1710 es2.0, clear toggle is a separate bit */
2865	if (omap_readw(UDC_REV) >= 0x61)
2866		udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2867	else
2868		udc->clr_halt = UDC_RESET_EP;
2869
2870	/* USB general purpose IRQ:  ep0, state changes, dma, etc */
2871	status = devm_request_irq(&pdev->dev, pdev->resource[1].start,
2872				  omap_udc_irq, 0, driver_name, udc);
2873	if (status != 0) {
2874		ERR("can't get irq %d, err %d\n",
2875			(int) pdev->resource[1].start, status);
2876		goto cleanup1;
2877	}
2878
2879	/* USB "non-iso" IRQ (PIO for all but ep0) */
2880	status = devm_request_irq(&pdev->dev, pdev->resource[2].start,
2881				  omap_udc_pio_irq, 0, "omap_udc pio", udc);
2882	if (status != 0) {
2883		ERR("can't get irq %d, err %d\n",
2884			(int) pdev->resource[2].start, status);
2885		goto cleanup1;
2886	}
2887#ifdef	USE_ISO
2888	status = devm_request_irq(&pdev->dev, pdev->resource[3].start,
2889				  omap_udc_iso_irq, 0, "omap_udc iso", udc);
2890	if (status != 0) {
2891		ERR("can't get irq %d, err %d\n",
2892			(int) pdev->resource[3].start, status);
2893		goto cleanup1;
2894	}
2895#endif
2896	if (cpu_is_omap16xx()) {
2897		udc->dc_clk = dc_clk;
2898		udc->hhc_clk = hhc_clk;
2899		clk_disable(hhc_clk);
2900		clk_disable(dc_clk);
2901	}
2902
2903	create_proc_file();
2904	return usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2905					  omap_udc_release);
2906
2907cleanup1:
2908	kfree(udc);
2909	udc = NULL;
2910
2911cleanup0:
2912	if (!IS_ERR_OR_NULL(xceiv))
2913		usb_put_phy(xceiv);
2914
2915	if (cpu_is_omap16xx()) {
2916		clk_disable_unprepare(hhc_clk);
2917		clk_disable_unprepare(dc_clk);
2918		clk_put(hhc_clk);
2919		clk_put(dc_clk);
2920	}
2921
2922	release_mem_region(pdev->resource[0].start,
2923			   resource_size(&pdev->resource[0]));
2924
2925	return status;
2926}
2927
2928static void omap_udc_remove(struct platform_device *pdev)
2929{
2930	DECLARE_COMPLETION_ONSTACK(done);
2931
2932	udc->done = &done;
2933
2934	usb_del_gadget_udc(&udc->gadget);
2935
2936	wait_for_completion(&done);
2937
2938	release_mem_region(pdev->resource[0].start,
2939			   resource_size(&pdev->resource[0]));
2940}
2941
2942/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2943 * system is forced into deep sleep
2944 *
2945 * REVISIT we should probably reject suspend requests when there's a host
2946 * session active, rather than disconnecting, at least on boards that can
2947 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
2948 * make host resumes and VBUS detection trigger OMAP wakeup events; that
2949 * may involve talking to an external transceiver (e.g. isp1301).
2950 */
2951
2952static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2953{
2954	u32	devstat;
2955
2956	devstat = omap_readw(UDC_DEVSTAT);
2957
2958	/* we're requesting 48 MHz clock if the pullup is enabled
2959	 * (== we're attached to the host) and we're not suspended,
2960	 * which would prevent entry to deep sleep...
2961	 */
2962	if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
2963		WARNING("session active; suspend requires disconnect\n");
2964		omap_pullup(&udc->gadget, 0);
2965	}
2966
2967	return 0;
2968}
2969
2970static int omap_udc_resume(struct platform_device *dev)
2971{
2972	DBG("resume + wakeup/SRP\n");
2973	omap_pullup(&udc->gadget, 1);
2974
2975	/* maybe the host would enumerate us if we nudged it */
2976	msleep(100);
2977	return omap_wakeup(&udc->gadget);
2978}
2979
2980/*-------------------------------------------------------------------------*/
2981
2982static struct platform_driver udc_driver = {
2983	.probe		= omap_udc_probe,
2984	.remove		= omap_udc_remove,
2985	.suspend	= omap_udc_suspend,
2986	.resume		= omap_udc_resume,
2987	.driver		= {
2988		.name	= driver_name,
2989	},
2990};
2991
2992module_platform_driver(udc_driver);
2993
2994MODULE_DESCRIPTION("OMAP UDC driver");
2995MODULE_LICENSE("GPL");
2996MODULE_ALIAS("platform:omap_udc");