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lpc32xx_udc.c
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linux-6.19.14/drivers/usb/gadget/udc/lpc32xx_udc.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * USB Gadget driver for LPC32xx 4 * 5 * Authors: 6 * Kevin Wells <kevin.wells@nxp.com> 7 * Mike James 8 * Roland Stigge <stigge@antcom.de> 9 * 10 * Copyright (C) 2006 Philips Semiconductors 11 * Copyright (C) 2009 NXP Semiconductors 12 * Copyright (C) 2012 Roland Stigge 13 * 14 * Note: This driver is based on original work done by Mike James for 15 * the LPC3180. 16 */ 17 18#include <linux/clk.h> 19#include <linux/delay.h> 20#include <linux/dma-mapping.h> 21#include <linux/dmapool.h> 22#include <linux/i2c.h> 23#include <linux/interrupt.h> 24#include <linux/module.h> 25#include <linux/of.h> 26#include <linux/platform_device.h> 27#include <linux/prefetch.h> 28#include <linux/proc_fs.h> 29#include <linux/slab.h> 30#include <linux/usb/ch9.h> 31#include <linux/usb/gadget.h> 32#include <linux/usb/isp1301.h> 33 34#ifdef CONFIG_USB_GADGET_DEBUG_FILES 35#include <linux/debugfs.h> 36#include <linux/seq_file.h> 37#endif 38 39/* 40 * USB device configuration structure 41 */ 42typedef void (*usc_chg_event)(int); 43struct lpc32xx_usbd_cfg { 44 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */ 45 usc_chg_event conn_chgb; /* Connection change event (optional) */ 46 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */ 47 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */ 48}; 49 50/* 51 * controller driver data structures 52 */ 53 54/* 16 endpoints (not to be confused with 32 hardware endpoints) */ 55#define NUM_ENDPOINTS 16 56 57/* 58 * IRQ indices make reading the code a little easier 59 */ 60#define IRQ_USB_LP 0 61#define IRQ_USB_HP 1 62#define IRQ_USB_DEVDMA 2 63#define IRQ_USB_ATX 3 64 65#define EP_OUT 0 /* RX (from host) */ 66#define EP_IN 1 /* TX (to host) */ 67 68/* Returns the interrupt mask for the selected hardware endpoint */ 69#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir)) 70 71#define EP_INT_TYPE 0 72#define EP_ISO_TYPE 1 73#define EP_BLK_TYPE 2 74#define EP_CTL_TYPE 3 75 76/* EP0 states */ 77#define WAIT_FOR_SETUP 0 /* Wait for setup packet */ 78#define DATA_IN 1 /* Expect dev->host transfer */ 79#define DATA_OUT 2 /* Expect host->dev transfer */ 80 81/* DD (DMA Descriptor) structure, requires word alignment, this is already 82 * defined in the LPC32XX USB device header file, but this version is slightly 83 * modified to tag some work data with each DMA descriptor. */ 84struct lpc32xx_usbd_dd_gad { 85 u32 dd_next_phy; 86 u32 dd_setup; 87 u32 dd_buffer_addr; 88 u32 dd_status; 89 u32 dd_iso_ps_mem_addr; 90 u32 this_dma; 91 u32 iso_status[6]; /* 5 spare */ 92 u32 dd_next_v; 93}; 94 95/* 96 * Logical endpoint structure 97 */ 98struct lpc32xx_ep { 99 struct usb_ep ep; 100 struct list_head queue; 101 struct lpc32xx_udc *udc; 102 103 u32 hwep_num_base; /* Physical hardware EP */ 104 u32 hwep_num; /* Maps to hardware endpoint */ 105 u32 maxpacket; 106 u32 lep; 107 108 bool is_in; 109 bool req_pending; 110 u32 eptype; 111 112 u32 totalints; 113 114 bool wedge; 115}; 116 117enum atx_type { 118 ISP1301, 119 STOTG04, 120}; 121 122/* 123 * Common UDC structure 124 */ 125struct lpc32xx_udc { 126 struct usb_gadget gadget; 127 struct usb_gadget_driver *driver; 128 struct platform_device *pdev; 129 struct device *dev; 130 spinlock_t lock; 131 struct i2c_client *isp1301_i2c_client; 132 133 /* Board and device specific */ 134 struct lpc32xx_usbd_cfg *board; 135 void __iomem *udp_baseaddr; 136 int udp_irq[4]; 137 struct clk *usb_slv_clk; 138 139 /* DMA support */ 140 u32 *udca_v_base; 141 u32 udca_p_base; 142 struct dma_pool *dd_cache; 143 144 /* Common EP and control data */ 145 u32 enabled_devints; 146 u32 enabled_hwepints; 147 u32 dev_status; 148 u32 realized_eps; 149 150 /* VBUS detection, pullup, and power flags */ 151 u8 vbus; 152 u8 last_vbus; 153 int pullup; 154 int poweron; 155 enum atx_type atx; 156 157 /* Work queues related to I2C support */ 158 struct work_struct pullup_job; 159 struct work_struct power_job; 160 161 /* USB device peripheral - various */ 162 struct lpc32xx_ep ep[NUM_ENDPOINTS]; 163 bool enabled; 164 bool clocked; 165 bool suspended; 166 int ep0state; 167 atomic_t enabled_ep_cnt; 168 wait_queue_head_t ep_disable_wait_queue; 169}; 170 171/* 172 * Endpoint request 173 */ 174struct lpc32xx_request { 175 struct usb_request req; 176 struct list_head queue; 177 struct lpc32xx_usbd_dd_gad *dd_desc_ptr; 178 bool mapped; 179 bool send_zlp; 180}; 181 182static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g) 183{ 184 return container_of(g, struct lpc32xx_udc, gadget); 185} 186 187#define ep_dbg(epp, fmt, arg...) \ 188 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg) 189#define ep_err(epp, fmt, arg...) \ 190 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg) 191#define ep_info(epp, fmt, arg...) \ 192 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg) 193#define ep_warn(epp, fmt, arg...) \ 194 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg) 195 196#define UDCA_BUFF_SIZE (128) 197 198/********************************************************************** 199 * USB device controller register offsets 200 **********************************************************************/ 201 202#define USBD_DEVINTST(x) ((x) + 0x200) 203#define USBD_DEVINTEN(x) ((x) + 0x204) 204#define USBD_DEVINTCLR(x) ((x) + 0x208) 205#define USBD_DEVINTSET(x) ((x) + 0x20C) 206#define USBD_CMDCODE(x) ((x) + 0x210) 207#define USBD_CMDDATA(x) ((x) + 0x214) 208#define USBD_RXDATA(x) ((x) + 0x218) 209#define USBD_TXDATA(x) ((x) + 0x21C) 210#define USBD_RXPLEN(x) ((x) + 0x220) 211#define USBD_TXPLEN(x) ((x) + 0x224) 212#define USBD_CTRL(x) ((x) + 0x228) 213#define USBD_DEVINTPRI(x) ((x) + 0x22C) 214#define USBD_EPINTST(x) ((x) + 0x230) 215#define USBD_EPINTEN(x) ((x) + 0x234) 216#define USBD_EPINTCLR(x) ((x) + 0x238) 217#define USBD_EPINTSET(x) ((x) + 0x23C) 218#define USBD_EPINTPRI(x) ((x) + 0x240) 219#define USBD_REEP(x) ((x) + 0x244) 220#define USBD_EPIND(x) ((x) + 0x248) 221#define USBD_EPMAXPSIZE(x) ((x) + 0x24C) 222/* DMA support registers only below */ 223/* Set, clear, or get enabled state of the DMA request status. If 224 * enabled, an IN or OUT token will start a DMA transfer for the EP */ 225#define USBD_DMARST(x) ((x) + 0x250) 226#define USBD_DMARCLR(x) ((x) + 0x254) 227#define USBD_DMARSET(x) ((x) + 0x258) 228/* DMA UDCA head pointer */ 229#define USBD_UDCAH(x) ((x) + 0x280) 230/* EP DMA status, enable, and disable. This is used to specifically 231 * enabled or disable DMA for a specific EP */ 232#define USBD_EPDMAST(x) ((x) + 0x284) 233#define USBD_EPDMAEN(x) ((x) + 0x288) 234#define USBD_EPDMADIS(x) ((x) + 0x28C) 235/* DMA master interrupts enable and pending interrupts */ 236#define USBD_DMAINTST(x) ((x) + 0x290) 237#define USBD_DMAINTEN(x) ((x) + 0x294) 238/* DMA end of transfer interrupt enable, disable, status */ 239#define USBD_EOTINTST(x) ((x) + 0x2A0) 240#define USBD_EOTINTCLR(x) ((x) + 0x2A4) 241#define USBD_EOTINTSET(x) ((x) + 0x2A8) 242/* New DD request interrupt enable, disable, status */ 243#define USBD_NDDRTINTST(x) ((x) + 0x2AC) 244#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0) 245#define USBD_NDDRTINTSET(x) ((x) + 0x2B4) 246/* DMA error interrupt enable, disable, status */ 247#define USBD_SYSERRTINTST(x) ((x) + 0x2B8) 248#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC) 249#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0) 250 251/********************************************************************** 252 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/ 253 * USBD_DEVINTPRI register definitions 254 **********************************************************************/ 255#define USBD_ERR_INT (1 << 9) 256#define USBD_EP_RLZED (1 << 8) 257#define USBD_TXENDPKT (1 << 7) 258#define USBD_RXENDPKT (1 << 6) 259#define USBD_CDFULL (1 << 5) 260#define USBD_CCEMPTY (1 << 4) 261#define USBD_DEV_STAT (1 << 3) 262#define USBD_EP_SLOW (1 << 2) 263#define USBD_EP_FAST (1 << 1) 264#define USBD_FRAME (1 << 0) 265 266/********************************************************************** 267 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/ 268 * USBD_EPINTPRI register definitions 269 **********************************************************************/ 270/* End point selection macro (RX) */ 271#define USBD_RX_EP_SEL(e) (1 << ((e) << 1)) 272 273/* End point selection macro (TX) */ 274#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1)) 275 276/********************************************************************** 277 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/ 278 * USBD_EPDMAEN/USBD_EPDMADIS/ 279 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/ 280 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/ 281 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET 282 * register definitions 283 **********************************************************************/ 284/* Endpoint selection macro */ 285#define USBD_EP_SEL(e) (1 << (e)) 286 287/********************************************************************** 288 * SBD_DMAINTST/USBD_DMAINTEN 289 **********************************************************************/ 290#define USBD_SYS_ERR_INT (1 << 2) 291#define USBD_NEW_DD_INT (1 << 1) 292#define USBD_EOT_INT (1 << 0) 293 294/********************************************************************** 295 * USBD_RXPLEN register definitions 296 **********************************************************************/ 297#define USBD_PKT_RDY (1 << 11) 298#define USBD_DV (1 << 10) 299#define USBD_PK_LEN_MASK 0x3FF 300 301/********************************************************************** 302 * USBD_CTRL register definitions 303 **********************************************************************/ 304#define USBD_LOG_ENDPOINT(e) ((e) << 2) 305#define USBD_WR_EN (1 << 1) 306#define USBD_RD_EN (1 << 0) 307 308/********************************************************************** 309 * USBD_CMDCODE register definitions 310 **********************************************************************/ 311#define USBD_CMD_CODE(c) ((c) << 16) 312#define USBD_CMD_PHASE(p) ((p) << 8) 313 314/********************************************************************** 315 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions 316 **********************************************************************/ 317#define USBD_DMAEP(e) (1 << (e)) 318 319/* DD (DMA Descriptor) structure, requires word alignment */ 320struct lpc32xx_usbd_dd { 321 u32 *dd_next; 322 u32 dd_setup; 323 u32 dd_buffer_addr; 324 u32 dd_status; 325 u32 dd_iso_ps_mem_addr; 326}; 327 328/* dd_setup bit defines */ 329#define DD_SETUP_ATLE_DMA_MODE 0x01 330#define DD_SETUP_NEXT_DD_VALID 0x04 331#define DD_SETUP_ISO_EP 0x10 332#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5) 333#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16) 334 335/* dd_status bit defines */ 336#define DD_STATUS_DD_RETIRED 0x01 337#define DD_STATUS_STS_MASK 0x1E 338#define DD_STATUS_STS_NS 0x00 /* Not serviced */ 339#define DD_STATUS_STS_BS 0x02 /* Being serviced */ 340#define DD_STATUS_STS_NC 0x04 /* Normal completion */ 341#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */ 342#define DD_STATUS_STS_DOR 0x08 /* Data overrun */ 343#define DD_STATUS_STS_SE 0x12 /* System error */ 344#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */ 345#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */ 346#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */ 347#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F) 348#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF) 349 350/* 351 * 352 * Protocol engine bits below 353 * 354 */ 355/* Device Interrupt Bit Definitions */ 356#define FRAME_INT 0x00000001 357#define EP_FAST_INT 0x00000002 358#define EP_SLOW_INT 0x00000004 359#define DEV_STAT_INT 0x00000008 360#define CCEMTY_INT 0x00000010 361#define CDFULL_INT 0x00000020 362#define RxENDPKT_INT 0x00000040 363#define TxENDPKT_INT 0x00000080 364#define EP_RLZED_INT 0x00000100 365#define ERR_INT 0x00000200 366 367/* Rx & Tx Packet Length Definitions */ 368#define PKT_LNGTH_MASK 0x000003FF 369#define PKT_DV 0x00000400 370#define PKT_RDY 0x00000800 371 372/* USB Control Definitions */ 373#define CTRL_RD_EN 0x00000001 374#define CTRL_WR_EN 0x00000002 375 376/* Command Codes */ 377#define CMD_SET_ADDR 0x00D00500 378#define CMD_CFG_DEV 0x00D80500 379#define CMD_SET_MODE 0x00F30500 380#define CMD_RD_FRAME 0x00F50500 381#define DAT_RD_FRAME 0x00F50200 382#define CMD_RD_TEST 0x00FD0500 383#define DAT_RD_TEST 0x00FD0200 384#define CMD_SET_DEV_STAT 0x00FE0500 385#define CMD_GET_DEV_STAT 0x00FE0500 386#define DAT_GET_DEV_STAT 0x00FE0200 387#define CMD_GET_ERR_CODE 0x00FF0500 388#define DAT_GET_ERR_CODE 0x00FF0200 389#define CMD_RD_ERR_STAT 0x00FB0500 390#define DAT_RD_ERR_STAT 0x00FB0200 391#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) 392#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) 393#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) 394#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) 395#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) 396#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) 397#define CMD_CLR_BUF 0x00F20500 398#define DAT_CLR_BUF 0x00F20200 399#define CMD_VALID_BUF 0x00FA0500 400 401/* Device Address Register Definitions */ 402#define DEV_ADDR_MASK 0x7F 403#define DEV_EN 0x80 404 405/* Device Configure Register Definitions */ 406#define CONF_DVICE 0x01 407 408/* Device Mode Register Definitions */ 409#define AP_CLK 0x01 410#define INAK_CI 0x02 411#define INAK_CO 0x04 412#define INAK_II 0x08 413#define INAK_IO 0x10 414#define INAK_BI 0x20 415#define INAK_BO 0x40 416 417/* Device Status Register Definitions */ 418#define DEV_CON 0x01 419#define DEV_CON_CH 0x02 420#define DEV_SUS 0x04 421#define DEV_SUS_CH 0x08 422#define DEV_RST 0x10 423 424/* Error Code Register Definitions */ 425#define ERR_EC_MASK 0x0F 426#define ERR_EA 0x10 427 428/* Error Status Register Definitions */ 429#define ERR_PID 0x01 430#define ERR_UEPKT 0x02 431#define ERR_DCRC 0x04 432#define ERR_TIMOUT 0x08 433#define ERR_EOP 0x10 434#define ERR_B_OVRN 0x20 435#define ERR_BTSTF 0x40 436#define ERR_TGL 0x80 437 438/* Endpoint Select Register Definitions */ 439#define EP_SEL_F 0x01 440#define EP_SEL_ST 0x02 441#define EP_SEL_STP 0x04 442#define EP_SEL_PO 0x08 443#define EP_SEL_EPN 0x10 444#define EP_SEL_B_1_FULL 0x20 445#define EP_SEL_B_2_FULL 0x40 446 447/* Endpoint Status Register Definitions */ 448#define EP_STAT_ST 0x01 449#define EP_STAT_DA 0x20 450#define EP_STAT_RF_MO 0x40 451#define EP_STAT_CND_ST 0x80 452 453/* Clear Buffer Register Definitions */ 454#define CLR_BUF_PO 0x01 455 456/* DMA Interrupt Bit Definitions */ 457#define EOT_INT 0x01 458#define NDD_REQ_INT 0x02 459#define SYS_ERR_INT 0x04 460 461#define DRIVER_VERSION "1.03" 462static const char driver_name[] = "lpc32xx_udc"; 463 464/* 465 * 466 * proc interface support 467 * 468 */ 469#ifdef CONFIG_USB_GADGET_DEBUG_FILES 470static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"}; 471static const char debug_filename[] = "driver/udc"; 472 473static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep) 474{ 475 struct lpc32xx_request *req; 476 477 seq_printf(s, "\n"); 478 seq_printf(s, "%12s, maxpacket %4d %3s", 479 ep->ep.name, ep->ep.maxpacket, 480 ep->is_in ? "in" : "out"); 481 seq_printf(s, " type %4s", epnames[ep->eptype]); 482 seq_printf(s, " ints: %12d", ep->totalints); 483 484 if (list_empty(&ep->queue)) 485 seq_printf(s, "\t(queue empty)\n"); 486 else { 487 list_for_each_entry(req, &ep->queue, queue) { 488 u32 length = req->req.actual; 489 490 seq_printf(s, "\treq %p len %d/%d buf %p\n", 491 &req->req, length, 492 req->req.length, req->req.buf); 493 } 494 } 495} 496 497static int udc_show(struct seq_file *s, void *unused) 498{ 499 struct lpc32xx_udc *udc = s->private; 500 struct lpc32xx_ep *ep; 501 unsigned long flags; 502 503 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); 504 505 spin_lock_irqsave(&udc->lock, flags); 506 507 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", 508 udc->vbus ? "present" : "off", 509 udc->enabled ? (udc->vbus ? "active" : "enabled") : 510 "disabled", 511 udc->gadget.is_selfpowered ? "self" : "VBUS", 512 udc->suspended ? ", suspended" : "", 513 udc->driver ? udc->driver->driver.name : "(none)"); 514 515 if (udc->enabled && udc->vbus) { 516 proc_ep_show(s, &udc->ep[0]); 517 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) 518 proc_ep_show(s, ep); 519 } 520 521 spin_unlock_irqrestore(&udc->lock, flags); 522 523 return 0; 524} 525 526DEFINE_SHOW_ATTRIBUTE(udc); 527 528static void create_debug_file(struct lpc32xx_udc *udc) 529{ 530 debugfs_create_file(debug_filename, 0, NULL, udc, &udc_fops); 531} 532 533static void remove_debug_file(struct lpc32xx_udc *udc) 534{ 535 debugfs_lookup_and_remove(debug_filename, NULL); 536} 537 538#else 539static inline void create_debug_file(struct lpc32xx_udc *udc) {} 540static inline void remove_debug_file(struct lpc32xx_udc *udc) {} 541#endif 542 543/* Primary initialization sequence for the ISP1301 transceiver */ 544static void isp1301_udc_configure(struct lpc32xx_udc *udc) 545{ 546 u8 value; 547 s32 vendor, product; 548 549 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00); 550 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02); 551 552 if (vendor == 0x0483 && product == 0xa0c4) 553 udc->atx = STOTG04; 554 555 /* LPC32XX only supports DAT_SE0 USB mode */ 556 /* This sequence is important */ 557 558 /* Disable transparent UART mode first */ 559 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 560 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 561 MC1_UART_EN); 562 563 /* Set full speed and SE0 mode */ 564 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 565 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 566 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 567 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0)); 568 569 /* 570 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide 571 */ 572 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 573 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 574 575 value = MC2_BI_DI; 576 if (udc->atx != STOTG04) 577 value |= MC2_SPD_SUSP_CTRL; 578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 579 ISP1301_I2C_MODE_CONTROL_2, value); 580 581 /* Driver VBUS_DRV high or low depending on board setup */ 582 if (udc->board->vbus_drv_pol != 0) 583 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 584 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV); 585 else 586 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 587 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 588 OTG1_VBUS_DRV); 589 590 /* Bi-directional mode with suspend control 591 * Enable both pulldowns for now - the pullup will be enable when VBUS 592 * is detected */ 593 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 594 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 595 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 596 ISP1301_I2C_OTG_CONTROL_1, 597 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); 598 599 /* Discharge VBUS (just in case) */ 600 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 601 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 602 msleep(1); 603 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 604 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 605 OTG1_VBUS_DISCHRG); 606 607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 608 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 609 610 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 611 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 613 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 614 615 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor); 616 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product); 617 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n", 618 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14)); 619 620} 621 622/* Enables or disables the USB device pullup via the ISP1301 transceiver */ 623static void isp1301_pullup_set(struct lpc32xx_udc *udc) 624{ 625 if (udc->pullup) 626 /* Enable pullup for bus signalling */ 627 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 628 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP); 629 else 630 /* Enable pullup for bus signalling */ 631 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 632 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 633 OTG1_DP_PULLUP); 634} 635 636static void pullup_work(struct work_struct *work) 637{ 638 struct lpc32xx_udc *udc = 639 container_of(work, struct lpc32xx_udc, pullup_job); 640 641 isp1301_pullup_set(udc); 642} 643 644static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup, 645 int block) 646{ 647 if (en_pullup == udc->pullup) 648 return; 649 650 udc->pullup = en_pullup; 651 if (block) 652 isp1301_pullup_set(udc); 653 else 654 /* defer slow i2c pull up setting */ 655 schedule_work(&udc->pullup_job); 656} 657 658#ifdef CONFIG_PM 659/* Powers up or down the ISP1301 transceiver */ 660static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable) 661{ 662 /* There is no "global power down" register for stotg04 */ 663 if (udc->atx == STOTG04) 664 return; 665 666 if (enable != 0) 667 /* Power up ISP1301 - this ISP1301 will automatically wakeup 668 when VBUS is detected */ 669 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 670 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, 671 MC2_GLOBAL_PWR_DN); 672 else 673 /* Power down ISP1301 */ 674 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 675 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); 676} 677 678static void power_work(struct work_struct *work) 679{ 680 struct lpc32xx_udc *udc = 681 container_of(work, struct lpc32xx_udc, power_job); 682 683 isp1301_set_powerstate(udc, udc->poweron); 684} 685#endif 686 687/* 688 * 689 * USB protocol engine command/data read/write helper functions 690 * 691 */ 692/* Issues a single command to the USB device state machine */ 693static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd) 694{ 695 u32 pass = 0; 696 int to; 697 698 /* EP may lock on CLRI if this read isn't done */ 699 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); 700 (void) tmp; 701 702 while (pass == 0) { 703 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr)); 704 705 /* Write command code */ 706 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr)); 707 to = 10000; 708 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) & 709 USBD_CCEMPTY) == 0) && (to > 0)) { 710 to--; 711 } 712 713 if (to > 0) 714 pass = 1; 715 716 cpu_relax(); 717 } 718} 719 720/* Issues 2 commands (or command and data) to the USB device state machine */ 721static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd, 722 u32 data) 723{ 724 udc_protocol_cmd_w(udc, cmd); 725 udc_protocol_cmd_w(udc, data); 726} 727 728/* Issues a single command to the USB device state machine and reads 729 * response data */ 730static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd) 731{ 732 int to = 1000; 733 734 /* Write a command and read data from the protocol engine */ 735 writel((USBD_CDFULL | USBD_CCEMPTY), 736 USBD_DEVINTCLR(udc->udp_baseaddr)); 737 738 /* Write command code */ 739 udc_protocol_cmd_w(udc, cmd); 740 741 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL)) 742 && (to > 0)) 743 to--; 744 if (!to) 745 dev_dbg(udc->dev, 746 "Protocol engine didn't receive response (CDFULL)\n"); 747 748 return readl(USBD_CMDDATA(udc->udp_baseaddr)); 749} 750 751/* 752 * 753 * USB device interrupt mask support functions 754 * 755 */ 756/* Enable one or more USB device interrupts */ 757static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask) 758{ 759 udc->enabled_devints |= devmask; 760 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 761} 762 763/* Disable one or more USB device interrupts */ 764static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask) 765{ 766 udc->enabled_devints &= ~mask; 767 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 768} 769 770/* Clear one or more USB device interrupts */ 771static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask) 772{ 773 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr)); 774} 775 776/* 777 * 778 * Endpoint interrupt disable/enable functions 779 * 780 */ 781/* Enable one or more USB endpoint interrupts */ 782static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 783{ 784 udc->enabled_hwepints |= (1 << hwep); 785 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 786} 787 788/* Disable one or more USB endpoint interrupts */ 789static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 790{ 791 udc->enabled_hwepints &= ~(1 << hwep); 792 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 793} 794 795/* Clear one or more USB endpoint interrupts */ 796static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep) 797{ 798 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr)); 799} 800 801/* Enable DMA for the HW channel */ 802static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep) 803{ 804 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr)); 805} 806 807/* Disable DMA for the HW channel */ 808static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep) 809{ 810 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr)); 811} 812 813/* 814 * 815 * Endpoint realize/unrealize functions 816 * 817 */ 818/* Before an endpoint can be used, it needs to be realized 819 * in the USB protocol engine - this realizes the endpoint. 820 * The interrupt (FIFO or DMA) is not enabled with this function */ 821static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep, 822 u32 maxpacket) 823{ 824 int to = 1000; 825 826 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 827 writel(hwep, USBD_EPIND(udc->udp_baseaddr)); 828 udc->realized_eps |= (1 << hwep); 829 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 830 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr)); 831 832 /* Wait until endpoint is realized in hardware */ 833 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & 834 USBD_EP_RLZED)) && (to > 0)) 835 to--; 836 if (!to) 837 dev_dbg(udc->dev, "EP not correctly realized in hardware\n"); 838 839 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 840} 841 842/* Unrealize an EP */ 843static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep) 844{ 845 udc->realized_eps &= ~(1 << hwep); 846 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 847} 848 849/* 850 * 851 * Endpoint support functions 852 * 853 */ 854/* Select and clear endpoint interrupt */ 855static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep) 856{ 857 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep)); 858 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep)); 859} 860 861/* Disables the endpoint in the USB protocol engine */ 862static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep) 863{ 864 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 865 DAT_WR_BYTE(EP_STAT_DA)); 866} 867 868/* Stalls the endpoint - endpoint will return STALL */ 869static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep) 870{ 871 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 872 DAT_WR_BYTE(EP_STAT_ST)); 873} 874 875/* Clear stall or reset endpoint */ 876static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep) 877{ 878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 879 DAT_WR_BYTE(0)); 880} 881 882/* Select an endpoint for endpoint status, clear, validate */ 883static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep) 884{ 885 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep)); 886} 887 888/* 889 * 890 * Endpoint buffer management functions 891 * 892 */ 893/* Clear the current endpoint's buffer */ 894static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 895{ 896 udc_select_hwep(udc, hwep); 897 udc_protocol_cmd_w(udc, CMD_CLR_BUF); 898} 899 900/* Validate the current endpoint's buffer */ 901static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 902{ 903 udc_select_hwep(udc, hwep); 904 udc_protocol_cmd_w(udc, CMD_VALID_BUF); 905} 906 907static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep) 908{ 909 /* Clear EP interrupt */ 910 uda_clear_hwepint(udc, hwep); 911 return udc_selep_clrint(udc, hwep); 912} 913 914/* 915 * 916 * USB EP DMA support 917 * 918 */ 919/* Allocate a DMA Descriptor */ 920static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc) 921{ 922 dma_addr_t dma; 923 struct lpc32xx_usbd_dd_gad *dd; 924 925 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma); 926 if (dd) 927 dd->this_dma = dma; 928 929 return dd; 930} 931 932/* Free a DMA Descriptor */ 933static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd) 934{ 935 dma_pool_free(udc->dd_cache, dd, dd->this_dma); 936} 937 938/* 939 * 940 * USB setup and shutdown functions 941 * 942 */ 943/* Enables or disables most of the USB system clocks when low power mode is 944 * needed. Clocks are typically started on a connection event, and disabled 945 * when a cable is disconnected */ 946static void udc_clk_set(struct lpc32xx_udc *udc, int enable) 947{ 948 if (enable != 0) { 949 if (udc->clocked) 950 return; 951 952 udc->clocked = 1; 953 clk_prepare_enable(udc->usb_slv_clk); 954 } else { 955 if (!udc->clocked) 956 return; 957 958 udc->clocked = 0; 959 clk_disable_unprepare(udc->usb_slv_clk); 960 } 961} 962 963/* Set/reset USB device address */ 964static void udc_set_address(struct lpc32xx_udc *udc, u32 addr) 965{ 966 /* Address will be latched at the end of the status phase, or 967 latched immediately if function is called twice */ 968 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR, 969 DAT_WR_BYTE(DEV_EN | addr)); 970} 971 972/* Setup up a IN request for DMA transfer - this consists of determining the 973 * list of DMA addresses for the transfer, allocating DMA Descriptors, 974 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 975static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 976{ 977 struct lpc32xx_request *req; 978 u32 hwep = ep->hwep_num; 979 980 ep->req_pending = 1; 981 982 /* There will always be a request waiting here */ 983 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 984 985 /* Place the DD Descriptor into the UDCA */ 986 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 987 988 /* Enable DMA and interrupt for the HW EP */ 989 udc_ep_dma_enable(udc, hwep); 990 991 /* Clear ZLP if last packet is not of MAXP size */ 992 if (req->req.length % ep->ep.maxpacket) 993 req->send_zlp = 0; 994 995 return 0; 996} 997 998/* Setup up a OUT request for DMA transfer - this consists of determining the 999 * list of DMA addresses for the transfer, allocating DMA Descriptors, 1000 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 1001static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1002{ 1003 struct lpc32xx_request *req; 1004 u32 hwep = ep->hwep_num; 1005 1006 ep->req_pending = 1; 1007 1008 /* There will always be a request waiting here */ 1009 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1010 1011 /* Place the DD Descriptor into the UDCA */ 1012 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 1013 1014 /* Enable DMA and interrupt for the HW EP */ 1015 udc_ep_dma_enable(udc, hwep); 1016 return 0; 1017} 1018 1019static void udc_disable(struct lpc32xx_udc *udc) 1020{ 1021 u32 i; 1022 1023 /* Disable device */ 1024 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1025 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0)); 1026 1027 /* Disable all device interrupts (including EP0) */ 1028 uda_disable_devint(udc, 0x3FF); 1029 1030 /* Disable and reset all endpoint interrupts */ 1031 for (i = 0; i < 32; i++) { 1032 uda_disable_hwepint(udc, i); 1033 uda_clear_hwepint(udc, i); 1034 udc_disable_hwep(udc, i); 1035 udc_unrealize_hwep(udc, i); 1036 udc->udca_v_base[i] = 0; 1037 1038 /* Disable and clear all interrupts and DMA */ 1039 udc_ep_dma_disable(udc, i); 1040 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr)); 1041 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1042 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1043 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr)); 1044 } 1045 1046 /* Disable DMA interrupts */ 1047 writel(0, USBD_DMAINTEN(udc->udp_baseaddr)); 1048 1049 writel(0, USBD_UDCAH(udc->udp_baseaddr)); 1050} 1051 1052static void udc_enable(struct lpc32xx_udc *udc) 1053{ 1054 u32 i; 1055 struct lpc32xx_ep *ep = &udc->ep[0]; 1056 1057 /* Start with known state */ 1058 udc_disable(udc); 1059 1060 /* Enable device */ 1061 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); 1062 1063 /* EP interrupts on high priority, FRAME interrupt on low priority */ 1064 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr)); 1065 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr)); 1066 1067 /* Clear any pending device interrupts */ 1068 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr)); 1069 1070 /* Setup UDCA - not yet used (DMA) */ 1071 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr)); 1072 1073 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */ 1074 for (i = 0; i <= 1; i++) { 1075 udc_realize_hwep(udc, i, ep->ep.maxpacket); 1076 uda_enable_hwepint(udc, i); 1077 udc_select_hwep(udc, i); 1078 udc_clrstall_hwep(udc, i); 1079 udc_clr_buffer_hwep(udc, i); 1080 } 1081 1082 /* Device interrupt setup */ 1083 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1084 USBD_EP_FAST)); 1085 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1086 USBD_EP_FAST)); 1087 1088 /* Set device address to 0 - called twice to force a latch in the USB 1089 engine without the need of a setup packet status closure */ 1090 udc_set_address(udc, 0); 1091 udc_set_address(udc, 0); 1092 1093 /* Enable master DMA interrupts */ 1094 writel((USBD_SYS_ERR_INT | USBD_EOT_INT), 1095 USBD_DMAINTEN(udc->udp_baseaddr)); 1096 1097 udc->dev_status = 0; 1098} 1099 1100/* 1101 * 1102 * USB device board specific events handled via callbacks 1103 * 1104 */ 1105/* Connection change event - notify board function of change */ 1106static void uda_power_event(struct lpc32xx_udc *udc, u32 conn) 1107{ 1108 /* Just notify of a connection change event (optional) */ 1109 if (udc->board->conn_chgb != NULL) 1110 udc->board->conn_chgb(conn); 1111} 1112 1113/* Suspend/resume event - notify board function of change */ 1114static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn) 1115{ 1116 /* Just notify of a Suspend/resume change event (optional) */ 1117 if (udc->board->susp_chgb != NULL) 1118 udc->board->susp_chgb(conn); 1119 1120 if (conn) 1121 udc->suspended = 0; 1122 else 1123 udc->suspended = 1; 1124} 1125 1126/* Remote wakeup enable/disable - notify board function of change */ 1127static void uda_remwkp_cgh(struct lpc32xx_udc *udc) 1128{ 1129 if (udc->board->rmwk_chgb != NULL) 1130 udc->board->rmwk_chgb(udc->dev_status & 1131 (1 << USB_DEVICE_REMOTE_WAKEUP)); 1132} 1133 1134/* Reads data from FIFO, adjusts for alignment and data size */ 1135static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1136{ 1137 int n, i, bl; 1138 u16 *p16; 1139 u32 *p32, tmp, cbytes; 1140 1141 /* Use optimal data transfer method based on source address and size */ 1142 switch (((uintptr_t) data) & 0x3) { 1143 case 0: /* 32-bit aligned */ 1144 p32 = (u32 *) data; 1145 cbytes = (bytes & ~0x3); 1146 1147 /* Copy 32-bit aligned data first */ 1148 for (n = 0; n < cbytes; n += 4) 1149 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr)); 1150 1151 /* Handle any remaining bytes */ 1152 bl = bytes - cbytes; 1153 if (bl) { 1154 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1155 for (n = 0; n < bl; n++) 1156 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1157 1158 } 1159 break; 1160 1161 case 1: /* 8-bit aligned */ 1162 case 3: 1163 /* Each byte has to be handled independently */ 1164 for (n = 0; n < bytes; n += 4) { 1165 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1166 1167 bl = bytes - n; 1168 if (bl > 4) 1169 bl = 4; 1170 1171 for (i = 0; i < bl; i++) 1172 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF); 1173 } 1174 break; 1175 1176 case 2: /* 16-bit aligned */ 1177 p16 = (u16 *) data; 1178 cbytes = (bytes & ~0x3); 1179 1180 /* Copy 32-bit sized objects first with 16-bit alignment */ 1181 for (n = 0; n < cbytes; n += 4) { 1182 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1183 *p16++ = (u16)(tmp & 0xFFFF); 1184 *p16++ = (u16)((tmp >> 16) & 0xFFFF); 1185 } 1186 1187 /* Handle any remaining bytes */ 1188 bl = bytes - cbytes; 1189 if (bl) { 1190 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1191 for (n = 0; n < bl; n++) 1192 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1193 } 1194 break; 1195 } 1196} 1197 1198/* Read data from the FIFO for an endpoint. This function is for endpoints (such 1199 * as EP0) that don't use DMA. This function should only be called if a packet 1200 * is known to be ready to read for the endpoint. Note that the endpoint must 1201 * be selected in the protocol engine prior to this call. */ 1202static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1203 u32 bytes) 1204{ 1205 u32 tmpv; 1206 int to = 1000; 1207 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN; 1208 1209 /* Setup read of endpoint */ 1210 writel(hwrep, USBD_CTRL(udc->udp_baseaddr)); 1211 1212 /* Wait until packet is ready */ 1213 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) & 1214 PKT_RDY) == 0) && (to > 0)) 1215 to--; 1216 if (!to) 1217 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n"); 1218 1219 /* Mask out count */ 1220 tmp = tmpv & PKT_LNGTH_MASK; 1221 if (bytes < tmp) 1222 tmp = bytes; 1223 1224 if ((tmp > 0) && (data != NULL)) 1225 udc_pop_fifo(udc, (u8 *) data, tmp); 1226 1227 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1228 1229 /* Clear the buffer */ 1230 udc_clr_buffer_hwep(udc, hwep); 1231 1232 return tmp; 1233} 1234 1235/* Stuffs data into the FIFO, adjusts for alignment and data size */ 1236static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1237{ 1238 int n, i, bl; 1239 u16 *p16; 1240 u32 *p32, tmp, cbytes; 1241 1242 /* Use optimal data transfer method based on source address and size */ 1243 switch (((uintptr_t) data) & 0x3) { 1244 case 0: /* 32-bit aligned */ 1245 p32 = (u32 *) data; 1246 cbytes = (bytes & ~0x3); 1247 1248 /* Copy 32-bit aligned data first */ 1249 for (n = 0; n < cbytes; n += 4) 1250 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr)); 1251 1252 /* Handle any remaining bytes */ 1253 bl = bytes - cbytes; 1254 if (bl) { 1255 tmp = 0; 1256 for (n = 0; n < bl; n++) 1257 tmp |= data[cbytes + n] << (n * 8); 1258 1259 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1260 } 1261 break; 1262 1263 case 1: /* 8-bit aligned */ 1264 case 3: 1265 /* Each byte has to be handled independently */ 1266 for (n = 0; n < bytes; n += 4) { 1267 bl = bytes - n; 1268 if (bl > 4) 1269 bl = 4; 1270 1271 tmp = 0; 1272 for (i = 0; i < bl; i++) 1273 tmp |= data[n + i] << (i * 8); 1274 1275 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1276 } 1277 break; 1278 1279 case 2: /* 16-bit aligned */ 1280 p16 = (u16 *) data; 1281 cbytes = (bytes & ~0x3); 1282 1283 /* Copy 32-bit aligned data first */ 1284 for (n = 0; n < cbytes; n += 4) { 1285 tmp = *p16++ & 0xFFFF; 1286 tmp |= (*p16++ & 0xFFFF) << 16; 1287 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1288 } 1289 1290 /* Handle any remaining bytes */ 1291 bl = bytes - cbytes; 1292 if (bl) { 1293 tmp = 0; 1294 for (n = 0; n < bl; n++) 1295 tmp |= data[cbytes + n] << (n * 8); 1296 1297 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1298 } 1299 break; 1300 } 1301} 1302 1303/* Write data to the FIFO for an endpoint. This function is for endpoints (such 1304 * as EP0) that don't use DMA. Note that the endpoint must be selected in the 1305 * protocol engine prior to this call. */ 1306static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1307 u32 bytes) 1308{ 1309 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN; 1310 1311 if ((bytes > 0) && (data == NULL)) 1312 return; 1313 1314 /* Setup write of endpoint */ 1315 writel(hwwep, USBD_CTRL(udc->udp_baseaddr)); 1316 1317 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr)); 1318 1319 /* Need at least 1 byte to trigger TX */ 1320 if (bytes == 0) 1321 writel(0, USBD_TXDATA(udc->udp_baseaddr)); 1322 else 1323 udc_stuff_fifo(udc, (u8 *) data, bytes); 1324 1325 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1326 1327 udc_val_buffer_hwep(udc, hwep); 1328} 1329 1330/* USB device reset - resets USB to a default state with just EP0 1331 enabled */ 1332static void uda_usb_reset(struct lpc32xx_udc *udc) 1333{ 1334 u32 i = 0; 1335 /* Re-init device controller and EP0 */ 1336 udc_enable(udc); 1337 udc->gadget.speed = USB_SPEED_FULL; 1338 1339 for (i = 1; i < NUM_ENDPOINTS; i++) { 1340 struct lpc32xx_ep *ep = &udc->ep[i]; 1341 ep->req_pending = 0; 1342 } 1343} 1344 1345/* Send a ZLP on EP0 */ 1346static void udc_ep0_send_zlp(struct lpc32xx_udc *udc) 1347{ 1348 udc_write_hwep(udc, EP_IN, NULL, 0); 1349} 1350 1351/* Get current frame number */ 1352static u16 udc_get_current_frame(struct lpc32xx_udc *udc) 1353{ 1354 u16 flo, fhi; 1355 1356 udc_protocol_cmd_w(udc, CMD_RD_FRAME); 1357 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1358 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1359 1360 return (fhi << 8) | flo; 1361} 1362 1363/* Set the device as configured - enables all endpoints */ 1364static inline void udc_set_device_configured(struct lpc32xx_udc *udc) 1365{ 1366 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE)); 1367} 1368 1369/* Set the device as unconfigured - disables all endpoints */ 1370static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc) 1371{ 1372 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1373} 1374 1375/* reinit == restore initial software state */ 1376static void udc_reinit(struct lpc32xx_udc *udc) 1377{ 1378 u32 i; 1379 1380 INIT_LIST_HEAD(&udc->gadget.ep_list); 1381 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); 1382 1383 for (i = 0; i < NUM_ENDPOINTS; i++) { 1384 struct lpc32xx_ep *ep = &udc->ep[i]; 1385 1386 if (i != 0) 1387 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 1388 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); 1389 INIT_LIST_HEAD(&ep->queue); 1390 ep->req_pending = 0; 1391 } 1392 1393 udc->ep0state = WAIT_FOR_SETUP; 1394} 1395 1396/* Must be called with lock */ 1397static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status) 1398{ 1399 struct lpc32xx_udc *udc = ep->udc; 1400 1401 list_del_init(&req->queue); 1402 if (req->req.status == -EINPROGRESS) 1403 req->req.status = status; 1404 else 1405 status = req->req.status; 1406 1407 if (ep->lep) { 1408 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in); 1409 1410 /* Free DDs */ 1411 udc_dd_free(udc, req->dd_desc_ptr); 1412 } 1413 1414 if (status && status != -ESHUTDOWN) 1415 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status); 1416 1417 ep->req_pending = 0; 1418 spin_unlock(&udc->lock); 1419 usb_gadget_giveback_request(&ep->ep, &req->req); 1420 spin_lock(&udc->lock); 1421} 1422 1423/* Must be called with lock */ 1424static void nuke(struct lpc32xx_ep *ep, int status) 1425{ 1426 struct lpc32xx_request *req; 1427 1428 while (!list_empty(&ep->queue)) { 1429 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1430 done(ep, req, status); 1431 } 1432 1433 if (status == -ESHUTDOWN) { 1434 uda_disable_hwepint(ep->udc, ep->hwep_num); 1435 udc_disable_hwep(ep->udc, ep->hwep_num); 1436 } 1437} 1438 1439/* IN endpoint 0 transfer */ 1440static int udc_ep0_in_req(struct lpc32xx_udc *udc) 1441{ 1442 struct lpc32xx_request *req; 1443 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1444 u32 tsend, ts = 0; 1445 1446 if (list_empty(&ep0->queue)) 1447 /* Nothing to send */ 1448 return 0; 1449 else 1450 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1451 queue); 1452 1453 tsend = ts = req->req.length - req->req.actual; 1454 if (ts == 0) { 1455 /* Send a ZLP */ 1456 udc_ep0_send_zlp(udc); 1457 done(ep0, req, 0); 1458 return 1; 1459 } else if (ts > ep0->ep.maxpacket) 1460 ts = ep0->ep.maxpacket; /* Just send what we can */ 1461 1462 /* Write data to the EP0 FIFO and start transfer */ 1463 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts); 1464 1465 /* Increment data pointer */ 1466 req->req.actual += ts; 1467 1468 if (tsend >= ep0->ep.maxpacket) 1469 return 0; /* Stay in data transfer state */ 1470 1471 /* Transfer request is complete */ 1472 udc->ep0state = WAIT_FOR_SETUP; 1473 done(ep0, req, 0); 1474 return 1; 1475} 1476 1477/* OUT endpoint 0 transfer */ 1478static int udc_ep0_out_req(struct lpc32xx_udc *udc) 1479{ 1480 struct lpc32xx_request *req; 1481 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1482 u32 tr, bufferspace; 1483 1484 if (list_empty(&ep0->queue)) 1485 return 0; 1486 else 1487 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1488 queue); 1489 1490 if (req->req.length == 0) { 1491 /* Just dequeue request */ 1492 done(ep0, req, 0); 1493 udc->ep0state = WAIT_FOR_SETUP; 1494 return 1; 1495 } 1496 1497 /* Get data from FIFO */ 1498 bufferspace = req->req.length - req->req.actual; 1499 if (bufferspace > ep0->ep.maxpacket) 1500 bufferspace = ep0->ep.maxpacket; 1501 1502 /* Copy data to buffer */ 1503 prefetchw(req->req.buf + req->req.actual); 1504 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual, 1505 bufferspace); 1506 req->req.actual += bufferspace; 1507 1508 if (tr < ep0->ep.maxpacket) { 1509 /* This is the last packet */ 1510 done(ep0, req, 0); 1511 udc->ep0state = WAIT_FOR_SETUP; 1512 return 1; 1513 } 1514 1515 return 0; 1516} 1517 1518/* Must be called with lock */ 1519static void stop_activity(struct lpc32xx_udc *udc) 1520{ 1521 struct usb_gadget_driver *driver = udc->driver; 1522 int i; 1523 1524 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1525 driver = NULL; 1526 1527 udc->gadget.speed = USB_SPEED_UNKNOWN; 1528 udc->suspended = 0; 1529 1530 for (i = 0; i < NUM_ENDPOINTS; i++) { 1531 struct lpc32xx_ep *ep = &udc->ep[i]; 1532 nuke(ep, -ESHUTDOWN); 1533 } 1534 if (driver) { 1535 spin_unlock(&udc->lock); 1536 driver->disconnect(&udc->gadget); 1537 spin_lock(&udc->lock); 1538 } 1539 1540 isp1301_pullup_enable(udc, 0, 0); 1541 udc_disable(udc); 1542 udc_reinit(udc); 1543} 1544 1545/* 1546 * Activate or kill host pullup 1547 * Can be called with or without lock 1548 */ 1549static void pullup(struct lpc32xx_udc *udc, int is_on) 1550{ 1551 if (!udc->clocked) 1552 return; 1553 1554 if (!udc->enabled || !udc->vbus) 1555 is_on = 0; 1556 1557 if (is_on != udc->pullup) 1558 isp1301_pullup_enable(udc, is_on, 0); 1559} 1560 1561/* Must be called without lock */ 1562static int lpc32xx_ep_disable(struct usb_ep *_ep) 1563{ 1564 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1565 struct lpc32xx_udc *udc = ep->udc; 1566 unsigned long flags; 1567 1568 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0)) 1569 return -EINVAL; 1570 spin_lock_irqsave(&udc->lock, flags); 1571 1572 nuke(ep, -ESHUTDOWN); 1573 1574 /* Clear all DMA statuses for this EP */ 1575 udc_ep_dma_disable(udc, ep->hwep_num); 1576 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1577 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1578 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1579 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1580 1581 /* Remove the DD pointer in the UDCA */ 1582 udc->udca_v_base[ep->hwep_num] = 0; 1583 1584 /* Disable and reset endpoint and interrupt */ 1585 uda_clear_hwepint(udc, ep->hwep_num); 1586 udc_unrealize_hwep(udc, ep->hwep_num); 1587 1588 ep->hwep_num = 0; 1589 1590 spin_unlock_irqrestore(&udc->lock, flags); 1591 1592 atomic_dec(&udc->enabled_ep_cnt); 1593 wake_up(&udc->ep_disable_wait_queue); 1594 1595 return 0; 1596} 1597 1598/* Must be called without lock */ 1599static int lpc32xx_ep_enable(struct usb_ep *_ep, 1600 const struct usb_endpoint_descriptor *desc) 1601{ 1602 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1603 struct lpc32xx_udc *udc; 1604 u16 maxpacket; 1605 u32 tmp; 1606 unsigned long flags; 1607 1608 /* Verify EP data */ 1609 if ((!_ep) || (!ep) || (!desc) || 1610 (desc->bDescriptorType != USB_DT_ENDPOINT)) 1611 return -EINVAL; 1612 1613 udc = ep->udc; 1614 maxpacket = usb_endpoint_maxp(desc); 1615 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) { 1616 dev_dbg(udc->dev, "bad ep descriptor's packet size\n"); 1617 return -EINVAL; 1618 } 1619 1620 /* Don't touch EP0 */ 1621 if (ep->hwep_num_base == 0) { 1622 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n"); 1623 return -EINVAL; 1624 } 1625 1626 /* Is driver ready? */ 1627 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { 1628 dev_dbg(udc->dev, "bogus device state\n"); 1629 return -ESHUTDOWN; 1630 } 1631 1632 tmp = usb_endpoint_type(desc); 1633 switch (tmp) { 1634 case USB_ENDPOINT_XFER_CONTROL: 1635 return -EINVAL; 1636 1637 case USB_ENDPOINT_XFER_INT: 1638 if (maxpacket > ep->maxpacket) { 1639 dev_dbg(udc->dev, 1640 "Bad INT endpoint maxpacket %d\n", maxpacket); 1641 return -EINVAL; 1642 } 1643 break; 1644 1645 case USB_ENDPOINT_XFER_BULK: 1646 switch (maxpacket) { 1647 case 8: 1648 case 16: 1649 case 32: 1650 case 64: 1651 break; 1652 1653 default: 1654 dev_dbg(udc->dev, 1655 "Bad BULK endpoint maxpacket %d\n", maxpacket); 1656 return -EINVAL; 1657 } 1658 break; 1659 1660 case USB_ENDPOINT_XFER_ISOC: 1661 break; 1662 } 1663 spin_lock_irqsave(&udc->lock, flags); 1664 1665 /* Initialize endpoint to match the selected descriptor */ 1666 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0; 1667 ep->ep.maxpacket = maxpacket; 1668 1669 /* Map hardware endpoint from base and direction */ 1670 if (ep->is_in) 1671 /* IN endpoints are offset 1 from the OUT endpoint */ 1672 ep->hwep_num = ep->hwep_num_base + EP_IN; 1673 else 1674 ep->hwep_num = ep->hwep_num_base; 1675 1676 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name, 1677 ep->hwep_num, maxpacket, (ep->is_in == 1)); 1678 1679 /* Realize the endpoint, interrupt is enabled later when 1680 * buffers are queued, IN EPs will NAK until buffers are ready */ 1681 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket); 1682 udc_clr_buffer_hwep(udc, ep->hwep_num); 1683 uda_disable_hwepint(udc, ep->hwep_num); 1684 udc_clrstall_hwep(udc, ep->hwep_num); 1685 1686 /* Clear all DMA statuses for this EP */ 1687 udc_ep_dma_disable(udc, ep->hwep_num); 1688 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1689 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1690 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1691 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1692 1693 spin_unlock_irqrestore(&udc->lock, flags); 1694 1695 atomic_inc(&udc->enabled_ep_cnt); 1696 return 0; 1697} 1698 1699/* 1700 * Allocate a USB request list 1701 * Can be called with or without lock 1702 */ 1703static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep, 1704 gfp_t gfp_flags) 1705{ 1706 struct lpc32xx_request *req; 1707 1708 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags); 1709 if (!req) 1710 return NULL; 1711 1712 INIT_LIST_HEAD(&req->queue); 1713 return &req->req; 1714} 1715 1716/* 1717 * De-allocate a USB request list 1718 * Can be called with or without lock 1719 */ 1720static void lpc32xx_ep_free_request(struct usb_ep *_ep, 1721 struct usb_request *_req) 1722{ 1723 struct lpc32xx_request *req; 1724 1725 req = container_of(_req, struct lpc32xx_request, req); 1726 BUG_ON(!list_empty(&req->queue)); 1727 kfree(req); 1728} 1729 1730/* Must be called without lock */ 1731static int lpc32xx_ep_queue(struct usb_ep *_ep, 1732 struct usb_request *_req, gfp_t gfp_flags) 1733{ 1734 struct lpc32xx_request *req; 1735 struct lpc32xx_ep *ep; 1736 struct lpc32xx_udc *udc; 1737 unsigned long flags; 1738 int status = 0; 1739 1740 req = container_of(_req, struct lpc32xx_request, req); 1741 ep = container_of(_ep, struct lpc32xx_ep, ep); 1742 1743 if (!_ep || !_req || !_req->complete || !_req->buf || 1744 !list_empty(&req->queue)) 1745 return -EINVAL; 1746 1747 udc = ep->udc; 1748 1749 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1750 return -EPIPE; 1751 1752 if (ep->lep) { 1753 struct lpc32xx_usbd_dd_gad *dd; 1754 1755 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in); 1756 if (status) 1757 return status; 1758 1759 /* For the request, build a list of DDs */ 1760 dd = udc_dd_alloc(udc); 1761 if (!dd) { 1762 /* Error allocating DD */ 1763 return -ENOMEM; 1764 } 1765 req->dd_desc_ptr = dd; 1766 1767 /* Setup the DMA descriptor */ 1768 dd->dd_next_phy = dd->dd_next_v = 0; 1769 dd->dd_buffer_addr = req->req.dma; 1770 dd->dd_status = 0; 1771 1772 /* Special handling for ISO EPs */ 1773 if (ep->eptype == EP_ISO_TYPE) { 1774 dd->dd_setup = DD_SETUP_ISO_EP | 1775 DD_SETUP_PACKETLEN(0) | 1776 DD_SETUP_DMALENBYTES(1); 1777 dd->dd_iso_ps_mem_addr = dd->this_dma + 24; 1778 if (ep->is_in) 1779 dd->iso_status[0] = req->req.length; 1780 else 1781 dd->iso_status[0] = 0; 1782 } else 1783 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) | 1784 DD_SETUP_DMALENBYTES(req->req.length); 1785 } 1786 1787 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name, 1788 _req, _req->length, _req->buf, ep->is_in, _req->zero); 1789 1790 spin_lock_irqsave(&udc->lock, flags); 1791 1792 _req->status = -EINPROGRESS; 1793 _req->actual = 0; 1794 req->send_zlp = _req->zero; 1795 1796 /* Kickstart empty queues */ 1797 if (list_empty(&ep->queue)) { 1798 list_add_tail(&req->queue, &ep->queue); 1799 1800 if (ep->hwep_num_base == 0) { 1801 /* Handle expected data direction */ 1802 if (ep->is_in) { 1803 /* IN packet to host */ 1804 udc->ep0state = DATA_IN; 1805 status = udc_ep0_in_req(udc); 1806 } else { 1807 /* OUT packet from host */ 1808 udc->ep0state = DATA_OUT; 1809 status = udc_ep0_out_req(udc); 1810 } 1811 } else if (ep->is_in) { 1812 /* IN packet to host and kick off transfer */ 1813 if (!ep->req_pending) 1814 udc_ep_in_req_dma(udc, ep); 1815 } else 1816 /* OUT packet from host and kick off list */ 1817 if (!ep->req_pending) 1818 udc_ep_out_req_dma(udc, ep); 1819 } else 1820 list_add_tail(&req->queue, &ep->queue); 1821 1822 spin_unlock_irqrestore(&udc->lock, flags); 1823 1824 return (status < 0) ? status : 0; 1825} 1826 1827/* Must be called without lock */ 1828static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1829{ 1830 struct lpc32xx_ep *ep; 1831 struct lpc32xx_request *req = NULL, *iter; 1832 unsigned long flags; 1833 1834 ep = container_of(_ep, struct lpc32xx_ep, ep); 1835 if (!_ep || ep->hwep_num_base == 0) 1836 return -EINVAL; 1837 1838 spin_lock_irqsave(&ep->udc->lock, flags); 1839 1840 /* make sure it's actually queued on this endpoint */ 1841 list_for_each_entry(iter, &ep->queue, queue) { 1842 if (&iter->req != _req) 1843 continue; 1844 req = iter; 1845 break; 1846 } 1847 if (!req) { 1848 spin_unlock_irqrestore(&ep->udc->lock, flags); 1849 return -EINVAL; 1850 } 1851 1852 done(ep, req, -ECONNRESET); 1853 1854 spin_unlock_irqrestore(&ep->udc->lock, flags); 1855 1856 return 0; 1857} 1858 1859/* Must be called without lock */ 1860static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value) 1861{ 1862 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1863 struct lpc32xx_udc *udc; 1864 unsigned long flags; 1865 1866 if ((!ep) || (ep->hwep_num <= 1)) 1867 return -EINVAL; 1868 1869 /* Don't halt an IN EP */ 1870 if (ep->is_in) 1871 return -EAGAIN; 1872 1873 udc = ep->udc; 1874 spin_lock_irqsave(&udc->lock, flags); 1875 1876 if (value == 1) { 1877 /* stall */ 1878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1879 DAT_WR_BYTE(EP_STAT_ST)); 1880 } else { 1881 /* End stall */ 1882 ep->wedge = 0; 1883 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1884 DAT_WR_BYTE(0)); 1885 } 1886 1887 spin_unlock_irqrestore(&udc->lock, flags); 1888 1889 return 0; 1890} 1891 1892/* set the halt feature and ignores clear requests */ 1893static int lpc32xx_ep_set_wedge(struct usb_ep *_ep) 1894{ 1895 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1896 1897 if (!_ep || !ep->udc) 1898 return -EINVAL; 1899 1900 ep->wedge = 1; 1901 1902 return usb_ep_set_halt(_ep); 1903} 1904 1905static const struct usb_ep_ops lpc32xx_ep_ops = { 1906 .enable = lpc32xx_ep_enable, 1907 .disable = lpc32xx_ep_disable, 1908 .alloc_request = lpc32xx_ep_alloc_request, 1909 .free_request = lpc32xx_ep_free_request, 1910 .queue = lpc32xx_ep_queue, 1911 .dequeue = lpc32xx_ep_dequeue, 1912 .set_halt = lpc32xx_ep_set_halt, 1913 .set_wedge = lpc32xx_ep_set_wedge, 1914}; 1915 1916/* Send a ZLP on a non-0 IN EP */ 1917static void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1918{ 1919 /* Clear EP status */ 1920 udc_clearep_getsts(udc, ep->hwep_num); 1921 1922 /* Send ZLP via FIFO mechanism */ 1923 udc_write_hwep(udc, ep->hwep_num, NULL, 0); 1924} 1925 1926/* 1927 * Handle EP completion for ZLP 1928 * This function will only be called when a delayed ZLP needs to be sent out 1929 * after a DMA transfer has filled both buffers. 1930 */ 1931static void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1932{ 1933 u32 epstatus; 1934 struct lpc32xx_request *req; 1935 1936 if (ep->hwep_num <= 0) 1937 return; 1938 1939 uda_clear_hwepint(udc, ep->hwep_num); 1940 1941 /* If this interrupt isn't enabled, return now */ 1942 if (!(udc->enabled_hwepints & (1 << ep->hwep_num))) 1943 return; 1944 1945 /* Get endpoint status */ 1946 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 1947 1948 /* 1949 * This should never happen, but protect against writing to the 1950 * buffer when full. 1951 */ 1952 if (epstatus & EP_SEL_F) 1953 return; 1954 1955 if (ep->is_in) { 1956 udc_send_in_zlp(udc, ep); 1957 uda_disable_hwepint(udc, ep->hwep_num); 1958 } else 1959 return; 1960 1961 /* If there isn't a request waiting, something went wrong */ 1962 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1963 1964 done(ep, req, 0); 1965 1966 /* Start another request if ready */ 1967 if (!list_empty(&ep->queue)) { 1968 if (ep->is_in) 1969 udc_ep_in_req_dma(udc, ep); 1970 else 1971 udc_ep_out_req_dma(udc, ep); 1972 } else 1973 ep->req_pending = 0; 1974} 1975 1976 1977/* DMA end of transfer completion */ 1978static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1979{ 1980 u32 status; 1981 struct lpc32xx_request *req; 1982 struct lpc32xx_usbd_dd_gad *dd; 1983 1984#ifdef CONFIG_USB_GADGET_DEBUG_FILES 1985 ep->totalints++; 1986#endif 1987 1988 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1989 dd = req->dd_desc_ptr; 1990 1991 /* DMA descriptor should always be retired for this call */ 1992 if (!(dd->dd_status & DD_STATUS_DD_RETIRED)) 1993 ep_warn(ep, "DMA descriptor did not retire\n"); 1994 1995 /* Disable DMA */ 1996 udc_ep_dma_disable(udc, ep->hwep_num); 1997 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr)); 1998 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1999 2000 /* System error? */ 2001 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) & 2002 (1 << ep->hwep_num)) { 2003 writel((1 << ep->hwep_num), 2004 USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 2005 ep_err(ep, "AHB critical error!\n"); 2006 ep->req_pending = 0; 2007 2008 /* The error could have occurred on a packet of a multipacket 2009 * transfer, so recovering the transfer is not possible. Close 2010 * the request with an error */ 2011 done(ep, req, -ECONNABORTED); 2012 return; 2013 } 2014 2015 /* Handle the current DD's status */ 2016 status = dd->dd_status; 2017 switch (status & DD_STATUS_STS_MASK) { 2018 case DD_STATUS_STS_NS: 2019 /* DD not serviced? This shouldn't happen! */ 2020 ep->req_pending = 0; 2021 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n", 2022 status); 2023 2024 done(ep, req, -ECONNABORTED); 2025 return; 2026 2027 case DD_STATUS_STS_BS: 2028 /* Interrupt only fires on EOT - This shouldn't happen! */ 2029 ep->req_pending = 0; 2030 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n", 2031 status); 2032 done(ep, req, -ECONNABORTED); 2033 return; 2034 2035 case DD_STATUS_STS_NC: 2036 case DD_STATUS_STS_DUR: 2037 /* Really just a short packet, not an underrun */ 2038 /* This is a good status and what we expect */ 2039 break; 2040 2041 default: 2042 /* Data overrun, system error, or unknown */ 2043 ep->req_pending = 0; 2044 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n", 2045 status); 2046 done(ep, req, -ECONNABORTED); 2047 return; 2048 } 2049 2050 /* ISO endpoints are handled differently */ 2051 if (ep->eptype == EP_ISO_TYPE) { 2052 if (ep->is_in) 2053 req->req.actual = req->req.length; 2054 else 2055 req->req.actual = dd->iso_status[0] & 0xFFFF; 2056 } else 2057 req->req.actual += DD_STATUS_CURDMACNT(status); 2058 2059 /* Send a ZLP if necessary. This will be done for non-int 2060 * packets which have a size that is a divisor of MAXP */ 2061 if (req->send_zlp) { 2062 /* 2063 * If at least 1 buffer is available, send the ZLP now. 2064 * Otherwise, the ZLP send needs to be deferred until a 2065 * buffer is available. 2066 */ 2067 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) { 2068 udc_clearep_getsts(udc, ep->hwep_num); 2069 uda_enable_hwepint(udc, ep->hwep_num); 2070 udc_clearep_getsts(udc, ep->hwep_num); 2071 2072 /* Let the EP interrupt handle the ZLP */ 2073 return; 2074 } else 2075 udc_send_in_zlp(udc, ep); 2076 } 2077 2078 /* Transfer request is complete */ 2079 done(ep, req, 0); 2080 2081 /* Start another request if ready */ 2082 udc_clearep_getsts(udc, ep->hwep_num); 2083 if (!list_empty((&ep->queue))) { 2084 if (ep->is_in) 2085 udc_ep_in_req_dma(udc, ep); 2086 else 2087 udc_ep_out_req_dma(udc, ep); 2088 } else 2089 ep->req_pending = 0; 2090 2091} 2092 2093/* 2094 * 2095 * Endpoint 0 functions 2096 * 2097 */ 2098static void udc_handle_dev(struct lpc32xx_udc *udc) 2099{ 2100 u32 tmp; 2101 2102 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT); 2103 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT); 2104 2105 if (tmp & DEV_RST) 2106 uda_usb_reset(udc); 2107 else if (tmp & DEV_CON_CH) 2108 uda_power_event(udc, (tmp & DEV_CON)); 2109 else if (tmp & DEV_SUS_CH) { 2110 if (tmp & DEV_SUS) { 2111 if (udc->vbus == 0) 2112 stop_activity(udc); 2113 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2114 udc->driver) { 2115 /* Power down transceiver */ 2116 udc->poweron = 0; 2117 schedule_work(&udc->pullup_job); 2118 uda_resm_susp_event(udc, 1); 2119 } 2120 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2121 udc->driver && udc->vbus) { 2122 uda_resm_susp_event(udc, 0); 2123 /* Power up transceiver */ 2124 udc->poweron = 1; 2125 schedule_work(&udc->pullup_job); 2126 } 2127 } 2128} 2129 2130static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex) 2131{ 2132 struct lpc32xx_ep *ep; 2133 u32 ep0buff = 0, tmp; 2134 2135 switch (reqtype & USB_RECIP_MASK) { 2136 case USB_RECIP_INTERFACE: 2137 break; /* Not supported */ 2138 2139 case USB_RECIP_DEVICE: 2140 ep0buff = udc->gadget.is_selfpowered; 2141 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP)) 2142 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP); 2143 break; 2144 2145 case USB_RECIP_ENDPOINT: 2146 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2147 ep = &udc->ep[tmp]; 2148 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS)) 2149 return -EOPNOTSUPP; 2150 2151 if (wIndex & USB_DIR_IN) { 2152 if (!ep->is_in) 2153 return -EOPNOTSUPP; /* Something's wrong */ 2154 } else if (ep->is_in) 2155 return -EOPNOTSUPP; /* Not an IN endpoint */ 2156 2157 /* Get status of the endpoint */ 2158 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num)); 2159 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num)); 2160 2161 if (tmp & EP_SEL_ST) 2162 ep0buff = (1 << USB_ENDPOINT_HALT); 2163 else 2164 ep0buff = 0; 2165 break; 2166 2167 default: 2168 break; 2169 } 2170 2171 /* Return data */ 2172 udc_write_hwep(udc, EP_IN, &ep0buff, 2); 2173 2174 return 0; 2175} 2176 2177static void udc_handle_ep0_setup(struct lpc32xx_udc *udc) 2178{ 2179 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0]; 2180 struct usb_ctrlrequest ctrlpkt; 2181 int i, bytes; 2182 u16 wIndex, wValue, reqtype, req, tmp; 2183 2184 /* Nuke previous transfers */ 2185 nuke(ep0, -EPROTO); 2186 2187 /* Get setup packet */ 2188 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8); 2189 if (bytes != 8) { 2190 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n", 2191 bytes); 2192 return; 2193 } 2194 2195 /* Native endianness */ 2196 wIndex = le16_to_cpu(ctrlpkt.wIndex); 2197 wValue = le16_to_cpu(ctrlpkt.wValue); 2198 reqtype = le16_to_cpu(ctrlpkt.bRequestType); 2199 2200 /* Set direction of EP0 */ 2201 if (likely(reqtype & USB_DIR_IN)) 2202 ep0->is_in = 1; 2203 else 2204 ep0->is_in = 0; 2205 2206 /* Handle SETUP packet */ 2207 req = le16_to_cpu(ctrlpkt.bRequest); 2208 switch (req) { 2209 case USB_REQ_CLEAR_FEATURE: 2210 case USB_REQ_SET_FEATURE: 2211 switch (reqtype) { 2212 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE): 2213 if (wValue != USB_DEVICE_REMOTE_WAKEUP) 2214 goto stall; /* Nothing else handled */ 2215 2216 /* Tell board about event */ 2217 if (req == USB_REQ_CLEAR_FEATURE) 2218 udc->dev_status &= 2219 ~(1 << USB_DEVICE_REMOTE_WAKEUP); 2220 else 2221 udc->dev_status |= 2222 (1 << USB_DEVICE_REMOTE_WAKEUP); 2223 uda_remwkp_cgh(udc); 2224 goto zlp_send; 2225 2226 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT): 2227 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2228 if ((wValue != USB_ENDPOINT_HALT) || 2229 (tmp >= NUM_ENDPOINTS)) 2230 break; 2231 2232 /* Find hardware endpoint from logical endpoint */ 2233 ep = &udc->ep[tmp]; 2234 tmp = ep->hwep_num; 2235 if (tmp == 0) 2236 break; 2237 2238 if (req == USB_REQ_SET_FEATURE) 2239 udc_stall_hwep(udc, tmp); 2240 else if (!ep->wedge) 2241 udc_clrstall_hwep(udc, tmp); 2242 2243 goto zlp_send; 2244 2245 default: 2246 break; 2247 } 2248 break; 2249 2250 case USB_REQ_SET_ADDRESS: 2251 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) { 2252 udc_set_address(udc, wValue); 2253 goto zlp_send; 2254 } 2255 break; 2256 2257 case USB_REQ_GET_STATUS: 2258 udc_get_status(udc, reqtype, wIndex); 2259 return; 2260 2261 default: 2262 break; /* Let GadgetFS handle the descriptor instead */ 2263 } 2264 2265 if (likely(udc->driver)) { 2266 /* device-2-host (IN) or no data setup command, process 2267 * immediately */ 2268 spin_unlock(&udc->lock); 2269 i = udc->driver->setup(&udc->gadget, &ctrlpkt); 2270 2271 spin_lock(&udc->lock); 2272 if (req == USB_REQ_SET_CONFIGURATION) { 2273 /* Configuration is set after endpoints are realized */ 2274 if (wValue) { 2275 /* Set configuration */ 2276 udc_set_device_configured(udc); 2277 2278 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2279 DAT_WR_BYTE(AP_CLK | 2280 INAK_BI | INAK_II)); 2281 } else { 2282 /* Clear configuration */ 2283 udc_set_device_unconfigured(udc); 2284 2285 /* Disable NAK interrupts */ 2286 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2287 DAT_WR_BYTE(AP_CLK)); 2288 } 2289 } 2290 2291 if (i < 0) { 2292 /* setup processing failed, force stall */ 2293 dev_dbg(udc->dev, 2294 "req %02x.%02x protocol STALL; stat %d\n", 2295 reqtype, req, i); 2296 udc->ep0state = WAIT_FOR_SETUP; 2297 goto stall; 2298 } 2299 } 2300 2301 if (!ep0->is_in) 2302 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */ 2303 2304 return; 2305 2306stall: 2307 udc_stall_hwep(udc, EP_IN); 2308 return; 2309 2310zlp_send: 2311 udc_ep0_send_zlp(udc); 2312 return; 2313} 2314 2315/* IN endpoint 0 transfer */ 2316static void udc_handle_ep0_in(struct lpc32xx_udc *udc) 2317{ 2318 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2319 u32 epstatus; 2320 2321 /* Clear EP interrupt */ 2322 epstatus = udc_clearep_getsts(udc, EP_IN); 2323 2324#ifdef CONFIG_USB_GADGET_DEBUG_FILES 2325 ep0->totalints++; 2326#endif 2327 2328 /* Stalled? Clear stall and reset buffers */ 2329 if (epstatus & EP_SEL_ST) { 2330 udc_clrstall_hwep(udc, EP_IN); 2331 nuke(ep0, -ECONNABORTED); 2332 udc->ep0state = WAIT_FOR_SETUP; 2333 return; 2334 } 2335 2336 /* Is a buffer available? */ 2337 if (!(epstatus & EP_SEL_F)) { 2338 /* Handle based on current state */ 2339 if (udc->ep0state == DATA_IN) 2340 udc_ep0_in_req(udc); 2341 else { 2342 /* Unknown state for EP0 oe end of DATA IN phase */ 2343 nuke(ep0, -ECONNABORTED); 2344 udc->ep0state = WAIT_FOR_SETUP; 2345 } 2346 } 2347} 2348 2349/* OUT endpoint 0 transfer */ 2350static void udc_handle_ep0_out(struct lpc32xx_udc *udc) 2351{ 2352 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2353 u32 epstatus; 2354 2355 /* Clear EP interrupt */ 2356 epstatus = udc_clearep_getsts(udc, EP_OUT); 2357 2358 2359#ifdef CONFIG_USB_GADGET_DEBUG_FILES 2360 ep0->totalints++; 2361#endif 2362 2363 /* Stalled? */ 2364 if (epstatus & EP_SEL_ST) { 2365 udc_clrstall_hwep(udc, EP_OUT); 2366 nuke(ep0, -ECONNABORTED); 2367 udc->ep0state = WAIT_FOR_SETUP; 2368 return; 2369 } 2370 2371 /* A NAK may occur if a packet couldn't be received yet */ 2372 if (epstatus & EP_SEL_EPN) 2373 return; 2374 /* Setup packet incoming? */ 2375 if (epstatus & EP_SEL_STP) { 2376 nuke(ep0, 0); 2377 udc->ep0state = WAIT_FOR_SETUP; 2378 } 2379 2380 /* Data available? */ 2381 if (epstatus & EP_SEL_F) 2382 /* Handle based on current state */ 2383 switch (udc->ep0state) { 2384 case WAIT_FOR_SETUP: 2385 udc_handle_ep0_setup(udc); 2386 break; 2387 2388 case DATA_OUT: 2389 udc_ep0_out_req(udc); 2390 break; 2391 2392 default: 2393 /* Unknown state for EP0 */ 2394 nuke(ep0, -ECONNABORTED); 2395 udc->ep0state = WAIT_FOR_SETUP; 2396 } 2397} 2398 2399/* Must be called without lock */ 2400static int lpc32xx_get_frame(struct usb_gadget *gadget) 2401{ 2402 int frame; 2403 unsigned long flags; 2404 struct lpc32xx_udc *udc = to_udc(gadget); 2405 2406 if (!udc->clocked) 2407 return -EINVAL; 2408 2409 spin_lock_irqsave(&udc->lock, flags); 2410 2411 frame = (int) udc_get_current_frame(udc); 2412 2413 spin_unlock_irqrestore(&udc->lock, flags); 2414 2415 return frame; 2416} 2417 2418static int lpc32xx_wakeup(struct usb_gadget *gadget) 2419{ 2420 return -ENOTSUPP; 2421} 2422 2423static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on) 2424{ 2425 gadget->is_selfpowered = (is_on != 0); 2426 2427 return 0; 2428} 2429 2430/* 2431 * vbus is here! turn everything on that's ready 2432 * Must be called without lock 2433 */ 2434static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active) 2435{ 2436 unsigned long flags; 2437 struct lpc32xx_udc *udc = to_udc(gadget); 2438 2439 spin_lock_irqsave(&udc->lock, flags); 2440 2441 /* Doesn't need lock */ 2442 if (udc->driver) { 2443 udc_clk_set(udc, 1); 2444 udc_enable(udc); 2445 pullup(udc, is_active); 2446 } else { 2447 stop_activity(udc); 2448 pullup(udc, 0); 2449 2450 spin_unlock_irqrestore(&udc->lock, flags); 2451 /* 2452 * Wait for all the endpoints to disable, 2453 * before disabling clocks. Don't wait if 2454 * endpoints are not enabled. 2455 */ 2456 if (atomic_read(&udc->enabled_ep_cnt)) 2457 wait_event_interruptible(udc->ep_disable_wait_queue, 2458 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2459 2460 spin_lock_irqsave(&udc->lock, flags); 2461 2462 udc_clk_set(udc, 0); 2463 } 2464 2465 spin_unlock_irqrestore(&udc->lock, flags); 2466 2467 return 0; 2468} 2469 2470/* Can be called with or without lock */ 2471static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on) 2472{ 2473 struct lpc32xx_udc *udc = to_udc(gadget); 2474 2475 /* Doesn't need lock */ 2476 pullup(udc, is_on); 2477 2478 return 0; 2479} 2480 2481static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *); 2482static int lpc32xx_stop(struct usb_gadget *); 2483 2484static const struct usb_gadget_ops lpc32xx_udc_ops = { 2485 .get_frame = lpc32xx_get_frame, 2486 .wakeup = lpc32xx_wakeup, 2487 .set_selfpowered = lpc32xx_set_selfpowered, 2488 .vbus_session = lpc32xx_vbus_session, 2489 .pullup = lpc32xx_pullup, 2490 .udc_start = lpc32xx_start, 2491 .udc_stop = lpc32xx_stop, 2492}; 2493 2494static void nop_release(struct device *dev) 2495{ 2496 /* nothing to free */ 2497} 2498 2499static const struct lpc32xx_udc controller_template = { 2500 .gadget = { 2501 .ops = &lpc32xx_udc_ops, 2502 .name = driver_name, 2503 .dev = { 2504 .init_name = "gadget", 2505 .release = nop_release, 2506 } 2507 }, 2508 .ep[0] = { 2509 .ep = { 2510 .name = "ep0", 2511 .ops = &lpc32xx_ep_ops, 2512 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, 2513 USB_EP_CAPS_DIR_ALL), 2514 }, 2515 .maxpacket = 64, 2516 .hwep_num_base = 0, 2517 .hwep_num = 0, /* Can be 0 or 1, has special handling */ 2518 .lep = 0, 2519 .eptype = EP_CTL_TYPE, 2520 }, 2521 .ep[1] = { 2522 .ep = { 2523 .name = "ep1-int", 2524 .ops = &lpc32xx_ep_ops, 2525 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2526 USB_EP_CAPS_DIR_ALL), 2527 }, 2528 .maxpacket = 64, 2529 .hwep_num_base = 2, 2530 .hwep_num = 0, /* 2 or 3, will be set later */ 2531 .lep = 1, 2532 .eptype = EP_INT_TYPE, 2533 }, 2534 .ep[2] = { 2535 .ep = { 2536 .name = "ep2-bulk", 2537 .ops = &lpc32xx_ep_ops, 2538 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2539 USB_EP_CAPS_DIR_ALL), 2540 }, 2541 .maxpacket = 64, 2542 .hwep_num_base = 4, 2543 .hwep_num = 0, /* 4 or 5, will be set later */ 2544 .lep = 2, 2545 .eptype = EP_BLK_TYPE, 2546 }, 2547 .ep[3] = { 2548 .ep = { 2549 .name = "ep3-iso", 2550 .ops = &lpc32xx_ep_ops, 2551 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2552 USB_EP_CAPS_DIR_ALL), 2553 }, 2554 .maxpacket = 1023, 2555 .hwep_num_base = 6, 2556 .hwep_num = 0, /* 6 or 7, will be set later */ 2557 .lep = 3, 2558 .eptype = EP_ISO_TYPE, 2559 }, 2560 .ep[4] = { 2561 .ep = { 2562 .name = "ep4-int", 2563 .ops = &lpc32xx_ep_ops, 2564 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2565 USB_EP_CAPS_DIR_ALL), 2566 }, 2567 .maxpacket = 64, 2568 .hwep_num_base = 8, 2569 .hwep_num = 0, /* 8 or 9, will be set later */ 2570 .lep = 4, 2571 .eptype = EP_INT_TYPE, 2572 }, 2573 .ep[5] = { 2574 .ep = { 2575 .name = "ep5-bulk", 2576 .ops = &lpc32xx_ep_ops, 2577 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2578 USB_EP_CAPS_DIR_ALL), 2579 }, 2580 .maxpacket = 64, 2581 .hwep_num_base = 10, 2582 .hwep_num = 0, /* 10 or 11, will be set later */ 2583 .lep = 5, 2584 .eptype = EP_BLK_TYPE, 2585 }, 2586 .ep[6] = { 2587 .ep = { 2588 .name = "ep6-iso", 2589 .ops = &lpc32xx_ep_ops, 2590 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2591 USB_EP_CAPS_DIR_ALL), 2592 }, 2593 .maxpacket = 1023, 2594 .hwep_num_base = 12, 2595 .hwep_num = 0, /* 12 or 13, will be set later */ 2596 .lep = 6, 2597 .eptype = EP_ISO_TYPE, 2598 }, 2599 .ep[7] = { 2600 .ep = { 2601 .name = "ep7-int", 2602 .ops = &lpc32xx_ep_ops, 2603 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2604 USB_EP_CAPS_DIR_ALL), 2605 }, 2606 .maxpacket = 64, 2607 .hwep_num_base = 14, 2608 .hwep_num = 0, 2609 .lep = 7, 2610 .eptype = EP_INT_TYPE, 2611 }, 2612 .ep[8] = { 2613 .ep = { 2614 .name = "ep8-bulk", 2615 .ops = &lpc32xx_ep_ops, 2616 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2617 USB_EP_CAPS_DIR_ALL), 2618 }, 2619 .maxpacket = 64, 2620 .hwep_num_base = 16, 2621 .hwep_num = 0, 2622 .lep = 8, 2623 .eptype = EP_BLK_TYPE, 2624 }, 2625 .ep[9] = { 2626 .ep = { 2627 .name = "ep9-iso", 2628 .ops = &lpc32xx_ep_ops, 2629 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2630 USB_EP_CAPS_DIR_ALL), 2631 }, 2632 .maxpacket = 1023, 2633 .hwep_num_base = 18, 2634 .hwep_num = 0, 2635 .lep = 9, 2636 .eptype = EP_ISO_TYPE, 2637 }, 2638 .ep[10] = { 2639 .ep = { 2640 .name = "ep10-int", 2641 .ops = &lpc32xx_ep_ops, 2642 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2643 USB_EP_CAPS_DIR_ALL), 2644 }, 2645 .maxpacket = 64, 2646 .hwep_num_base = 20, 2647 .hwep_num = 0, 2648 .lep = 10, 2649 .eptype = EP_INT_TYPE, 2650 }, 2651 .ep[11] = { 2652 .ep = { 2653 .name = "ep11-bulk", 2654 .ops = &lpc32xx_ep_ops, 2655 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2656 USB_EP_CAPS_DIR_ALL), 2657 }, 2658 .maxpacket = 64, 2659 .hwep_num_base = 22, 2660 .hwep_num = 0, 2661 .lep = 11, 2662 .eptype = EP_BLK_TYPE, 2663 }, 2664 .ep[12] = { 2665 .ep = { 2666 .name = "ep12-iso", 2667 .ops = &lpc32xx_ep_ops, 2668 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2669 USB_EP_CAPS_DIR_ALL), 2670 }, 2671 .maxpacket = 1023, 2672 .hwep_num_base = 24, 2673 .hwep_num = 0, 2674 .lep = 12, 2675 .eptype = EP_ISO_TYPE, 2676 }, 2677 .ep[13] = { 2678 .ep = { 2679 .name = "ep13-int", 2680 .ops = &lpc32xx_ep_ops, 2681 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2682 USB_EP_CAPS_DIR_ALL), 2683 }, 2684 .maxpacket = 64, 2685 .hwep_num_base = 26, 2686 .hwep_num = 0, 2687 .lep = 13, 2688 .eptype = EP_INT_TYPE, 2689 }, 2690 .ep[14] = { 2691 .ep = { 2692 .name = "ep14-bulk", 2693 .ops = &lpc32xx_ep_ops, 2694 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2695 USB_EP_CAPS_DIR_ALL), 2696 }, 2697 .maxpacket = 64, 2698 .hwep_num_base = 28, 2699 .hwep_num = 0, 2700 .lep = 14, 2701 .eptype = EP_BLK_TYPE, 2702 }, 2703 .ep[15] = { 2704 .ep = { 2705 .name = "ep15-bulk", 2706 .ops = &lpc32xx_ep_ops, 2707 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2708 USB_EP_CAPS_DIR_ALL), 2709 }, 2710 .maxpacket = 1023, 2711 .hwep_num_base = 30, 2712 .hwep_num = 0, 2713 .lep = 15, 2714 .eptype = EP_BLK_TYPE, 2715 }, 2716}; 2717 2718/* ISO and status interrupts */ 2719static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc) 2720{ 2721 u32 tmp, devstat; 2722 struct lpc32xx_udc *udc = _udc; 2723 2724 spin_lock(&udc->lock); 2725 2726 /* Read the device status register */ 2727 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr)); 2728 2729 devstat &= ~USBD_EP_FAST; 2730 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr)); 2731 devstat = devstat & udc->enabled_devints; 2732 2733 /* Device specific handling needed? */ 2734 if (devstat & USBD_DEV_STAT) 2735 udc_handle_dev(udc); 2736 2737 /* Start of frame? (devstat & FRAME_INT): 2738 * The frame interrupt isn't really needed for ISO support, 2739 * as the driver will queue the necessary packets */ 2740 2741 /* Error? */ 2742 if (devstat & ERR_INT) { 2743 /* All types of errors, from cable removal during transfer to 2744 * misc protocol and bit errors. These are mostly for just info, 2745 * as the USB hardware will work around these. If these errors 2746 * happen alot, something is wrong. */ 2747 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT); 2748 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT); 2749 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp); 2750 } 2751 2752 spin_unlock(&udc->lock); 2753 2754 return IRQ_HANDLED; 2755} 2756 2757/* EP interrupts */ 2758static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc) 2759{ 2760 u32 tmp; 2761 struct lpc32xx_udc *udc = _udc; 2762 2763 spin_lock(&udc->lock); 2764 2765 /* Read the device status register */ 2766 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr)); 2767 2768 /* Endpoints */ 2769 tmp = readl(USBD_EPINTST(udc->udp_baseaddr)); 2770 2771 /* Special handling for EP0 */ 2772 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2773 /* Handle EP0 IN */ 2774 if (tmp & (EP_MASK_SEL(0, EP_IN))) 2775 udc_handle_ep0_in(udc); 2776 2777 /* Handle EP0 OUT */ 2778 if (tmp & (EP_MASK_SEL(0, EP_OUT))) 2779 udc_handle_ep0_out(udc); 2780 } 2781 2782 /* All other EPs */ 2783 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2784 int i; 2785 2786 /* Handle other EP interrupts */ 2787 for (i = 1; i < NUM_ENDPOINTS; i++) { 2788 if (tmp & (1 << udc->ep[i].hwep_num)) 2789 udc_handle_eps(udc, &udc->ep[i]); 2790 } 2791 } 2792 2793 spin_unlock(&udc->lock); 2794 2795 return IRQ_HANDLED; 2796} 2797 2798static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc) 2799{ 2800 struct lpc32xx_udc *udc = _udc; 2801 2802 int i; 2803 u32 tmp; 2804 2805 spin_lock(&udc->lock); 2806 2807 /* Handle EP DMA EOT interrupts */ 2808 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) | 2809 (readl(USBD_EPDMAST(udc->udp_baseaddr)) & 2810 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) | 2811 readl(USBD_SYSERRTINTST(udc->udp_baseaddr)); 2812 for (i = 1; i < NUM_ENDPOINTS; i++) { 2813 if (tmp & (1 << udc->ep[i].hwep_num)) 2814 udc_handle_dma_ep(udc, &udc->ep[i]); 2815 } 2816 2817 spin_unlock(&udc->lock); 2818 2819 return IRQ_HANDLED; 2820} 2821 2822/* 2823 * 2824 * VBUS detection, pullup handler, and Gadget cable state notification 2825 * 2826 */ 2827static void vbus_work(struct lpc32xx_udc *udc) 2828{ 2829 u8 value; 2830 2831 if (udc->enabled != 0) { 2832 /* Discharge VBUS real quick */ 2833 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2834 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 2835 2836 /* Give VBUS some time (100mS) to discharge */ 2837 msleep(100); 2838 2839 /* Disable VBUS discharge resistor */ 2840 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2841 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 2842 OTG1_VBUS_DISCHRG); 2843 2844 /* Clear interrupt */ 2845 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2846 ISP1301_I2C_INTERRUPT_LATCH | 2847 ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2848 2849 /* Get the VBUS status from the transceiver */ 2850 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client, 2851 ISP1301_I2C_INTERRUPT_SOURCE); 2852 2853 /* VBUS on or off? */ 2854 if (value & INT_SESS_VLD) 2855 udc->vbus = 1; 2856 else 2857 udc->vbus = 0; 2858 2859 /* VBUS changed? */ 2860 if (udc->last_vbus != udc->vbus) { 2861 udc->last_vbus = udc->vbus; 2862 lpc32xx_vbus_session(&udc->gadget, udc->vbus); 2863 } 2864 } 2865} 2866 2867static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc) 2868{ 2869 struct lpc32xx_udc *udc = _udc; 2870 2871 vbus_work(udc); 2872 2873 return IRQ_HANDLED; 2874} 2875 2876static int lpc32xx_start(struct usb_gadget *gadget, 2877 struct usb_gadget_driver *driver) 2878{ 2879 struct lpc32xx_udc *udc = to_udc(gadget); 2880 2881 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) { 2882 dev_err(udc->dev, "bad parameter.\n"); 2883 return -EINVAL; 2884 } 2885 2886 if (udc->driver) { 2887 dev_err(udc->dev, "UDC already has a gadget driver\n"); 2888 return -EBUSY; 2889 } 2890 2891 udc->driver = driver; 2892 udc->gadget.dev.of_node = udc->dev->of_node; 2893 udc->enabled = 1; 2894 udc->gadget.is_selfpowered = 1; 2895 udc->vbus = 0; 2896 2897 /* Force VBUS process once to check for cable insertion */ 2898 udc->last_vbus = udc->vbus = 0; 2899 vbus_work(udc); 2900 2901 /* enable interrupts */ 2902 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2903 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD); 2904 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2905 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD); 2906 2907 return 0; 2908} 2909 2910static int lpc32xx_stop(struct usb_gadget *gadget) 2911{ 2912 struct lpc32xx_udc *udc = to_udc(gadget); 2913 2914 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2915 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2916 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2917 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2918 2919 if (udc->clocked) { 2920 spin_lock(&udc->lock); 2921 stop_activity(udc); 2922 spin_unlock(&udc->lock); 2923 2924 /* 2925 * Wait for all the endpoints to disable, 2926 * before disabling clocks. Don't wait if 2927 * endpoints are not enabled. 2928 */ 2929 if (atomic_read(&udc->enabled_ep_cnt)) 2930 wait_event_interruptible(udc->ep_disable_wait_queue, 2931 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2932 2933 spin_lock(&udc->lock); 2934 udc_clk_set(udc, 0); 2935 spin_unlock(&udc->lock); 2936 } 2937 2938 udc->enabled = 0; 2939 udc->driver = NULL; 2940 2941 return 0; 2942} 2943 2944static void lpc32xx_udc_shutdown(struct platform_device *dev) 2945{ 2946 /* Force disconnect on reboot */ 2947 struct lpc32xx_udc *udc = platform_get_drvdata(dev); 2948 2949 pullup(udc, 0); 2950} 2951 2952/* 2953 * Callbacks to be overridden by options passed via OF (TODO) 2954 */ 2955 2956static void lpc32xx_usbd_conn_chg(int conn) 2957{ 2958 /* Do nothing, it might be nice to enable an LED 2959 * based on conn state being !0 */ 2960} 2961 2962static void lpc32xx_usbd_susp_chg(int susp) 2963{ 2964 /* Device suspend if susp != 0 */ 2965} 2966 2967static void lpc32xx_rmwkup_chg(int remote_wakup_enable) 2968{ 2969 /* Enable or disable USB remote wakeup */ 2970} 2971 2972static struct lpc32xx_usbd_cfg lpc32xx_usbddata = { 2973 .vbus_drv_pol = 0, 2974 .conn_chgb = &lpc32xx_usbd_conn_chg, 2975 .susp_chgb = &lpc32xx_usbd_susp_chg, 2976 .rmwk_chgb = &lpc32xx_rmwkup_chg, 2977}; 2978 2979 2980static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F; 2981 2982static int lpc32xx_udc_probe(struct platform_device *pdev) 2983{ 2984 struct device *dev = &pdev->dev; 2985 struct lpc32xx_udc *udc; 2986 int retval, i; 2987 dma_addr_t dma_handle; 2988 struct device_node *isp1301_node; 2989 2990 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL); 2991 if (!udc) 2992 return -ENOMEM; 2993 2994 for (i = 0; i <= 15; i++) 2995 udc->ep[i].udc = udc; 2996 udc->gadget.ep0 = &udc->ep[0].ep; 2997 2998 /* init software state */ 2999 udc->gadget.dev.parent = dev; 3000 udc->pdev = pdev; 3001 udc->dev = &pdev->dev; 3002 udc->enabled = 0; 3003 3004 if (pdev->dev.of_node) { 3005 isp1301_node = of_parse_phandle(pdev->dev.of_node, 3006 "transceiver", 0); 3007 } else { 3008 isp1301_node = NULL; 3009 } 3010 3011 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node); 3012 of_node_put(isp1301_node); 3013 if (!udc->isp1301_i2c_client) { 3014 return -EPROBE_DEFER; 3015 } 3016 3017 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n", 3018 udc->isp1301_i2c_client->addr); 3019 3020 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask; 3021 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 3022 if (retval) 3023 goto err_put_client; 3024 3025 udc->board = &lpc32xx_usbddata; 3026 3027 /* 3028 * Resources are mapped as follows: 3029 * IORESOURCE_MEM, base address and size of USB space 3030 * IORESOURCE_IRQ, USB device low priority interrupt number 3031 * IORESOURCE_IRQ, USB device high priority interrupt number 3032 * IORESOURCE_IRQ, USB device interrupt number 3033 * IORESOURCE_IRQ, USB transceiver interrupt number 3034 */ 3035 3036 spin_lock_init(&udc->lock); 3037 3038 /* Get IRQs */ 3039 for (i = 0; i < 4; i++) { 3040 udc->udp_irq[i] = platform_get_irq(pdev, i); 3041 if (udc->udp_irq[i] < 0) { 3042 retval = udc->udp_irq[i]; 3043 goto err_put_client; 3044 } 3045 } 3046 3047 udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, 0); 3048 if (IS_ERR(udc->udp_baseaddr)) { 3049 dev_err(udc->dev, "IO map failure\n"); 3050 retval = PTR_ERR(udc->udp_baseaddr); 3051 goto err_put_client; 3052 } 3053 3054 /* Get USB device clock */ 3055 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL); 3056 if (IS_ERR(udc->usb_slv_clk)) { 3057 dev_err(udc->dev, "failed to acquire USB device clock\n"); 3058 retval = PTR_ERR(udc->usb_slv_clk); 3059 goto err_put_client; 3060 } 3061 3062 /* Enable USB device clock */ 3063 retval = clk_prepare_enable(udc->usb_slv_clk); 3064 if (retval < 0) { 3065 dev_err(udc->dev, "failed to start USB device clock\n"); 3066 goto err_put_client; 3067 } 3068 3069 /* Setup deferred workqueue data */ 3070 udc->poweron = udc->pullup = 0; 3071 INIT_WORK(&udc->pullup_job, pullup_work); 3072#ifdef CONFIG_PM 3073 INIT_WORK(&udc->power_job, power_work); 3074#endif 3075 3076 /* All clocks are now on */ 3077 udc->clocked = 1; 3078 3079 isp1301_udc_configure(udc); 3080 /* Allocate memory for the UDCA */ 3081 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3082 &dma_handle, 3083 (GFP_KERNEL | GFP_DMA)); 3084 if (!udc->udca_v_base) { 3085 dev_err(udc->dev, "error getting UDCA region\n"); 3086 retval = -ENOMEM; 3087 goto err_disable_clk; 3088 } 3089 udc->udca_p_base = dma_handle; 3090 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n", 3091 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base); 3092 3093 /* Setup the DD DMA memory pool */ 3094 udc->dd_cache = dma_pool_create("udc_dd", udc->dev, 3095 sizeof(struct lpc32xx_usbd_dd_gad), 3096 sizeof(u32), 0); 3097 if (!udc->dd_cache) { 3098 dev_err(udc->dev, "error getting DD DMA region\n"); 3099 retval = -ENOMEM; 3100 goto err_free_dma; 3101 } 3102 3103 /* Clear USB peripheral and initialize gadget endpoints */ 3104 udc_disable(udc); 3105 udc_reinit(udc); 3106 3107 /* Request IRQs - low and high priority USB device IRQs are routed to 3108 * the same handler, while the DMA interrupt is routed elsewhere */ 3109 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP], 3110 lpc32xx_usb_lp_irq, 0, "udc_lp", udc); 3111 if (retval < 0) { 3112 dev_err(udc->dev, "LP request irq %d failed\n", 3113 udc->udp_irq[IRQ_USB_LP]); 3114 goto err_destroy_pool; 3115 } 3116 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP], 3117 lpc32xx_usb_hp_irq, 0, "udc_hp", udc); 3118 if (retval < 0) { 3119 dev_err(udc->dev, "HP request irq %d failed\n", 3120 udc->udp_irq[IRQ_USB_HP]); 3121 goto err_destroy_pool; 3122 } 3123 3124 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA], 3125 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc); 3126 if (retval < 0) { 3127 dev_err(udc->dev, "DEV request irq %d failed\n", 3128 udc->udp_irq[IRQ_USB_DEVDMA]); 3129 goto err_destroy_pool; 3130 } 3131 3132 /* The transceiver interrupt is used for VBUS detection and will 3133 kick off the VBUS handler function */ 3134 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL, 3135 lpc32xx_usb_vbus_irq, IRQF_ONESHOT, 3136 "udc_otg", udc); 3137 if (retval < 0) { 3138 dev_err(udc->dev, "VBUS request irq %d failed\n", 3139 udc->udp_irq[IRQ_USB_ATX]); 3140 goto err_destroy_pool; 3141 } 3142 3143 /* Initialize wait queue */ 3144 init_waitqueue_head(&udc->ep_disable_wait_queue); 3145 atomic_set(&udc->enabled_ep_cnt, 0); 3146 3147 retval = usb_add_gadget_udc(dev, &udc->gadget); 3148 if (retval < 0) 3149 goto err_destroy_pool; 3150 3151 dev_set_drvdata(dev, udc); 3152 device_init_wakeup(dev, 1); 3153 create_debug_file(udc); 3154 3155 /* Disable clocks for now */ 3156 udc_clk_set(udc, 0); 3157 3158 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION); 3159 return 0; 3160 3161err_destroy_pool: 3162 dma_pool_destroy(udc->dd_cache); 3163err_free_dma: 3164 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3165 udc->udca_v_base, udc->udca_p_base); 3166err_disable_clk: 3167 clk_disable_unprepare(udc->usb_slv_clk); 3168err_put_client: 3169 put_device(&udc->isp1301_i2c_client->dev); 3170 3171 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval); 3172 3173 return retval; 3174} 3175 3176static void lpc32xx_udc_remove(struct platform_device *pdev) 3177{ 3178 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3179 3180 usb_del_gadget_udc(&udc->gadget); 3181 if (udc->driver) { 3182 dev_err(&pdev->dev, 3183 "Driver still in use but removing anyhow\n"); 3184 return; 3185 } 3186 3187 udc_clk_set(udc, 1); 3188 udc_disable(udc); 3189 pullup(udc, 0); 3190 3191 device_init_wakeup(&pdev->dev, 0); 3192 remove_debug_file(udc); 3193 3194 dma_pool_destroy(udc->dd_cache); 3195 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3196 udc->udca_v_base, udc->udca_p_base); 3197 3198 clk_disable_unprepare(udc->usb_slv_clk); 3199 3200 put_device(&udc->isp1301_i2c_client->dev); 3201} 3202 3203#ifdef CONFIG_PM 3204static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg) 3205{ 3206 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3207 3208 if (udc->clocked) { 3209 /* Power down ISP */ 3210 udc->poweron = 0; 3211 isp1301_set_powerstate(udc, 0); 3212 3213 /* Disable clocking */ 3214 udc_clk_set(udc, 0); 3215 3216 /* Keep clock flag on, so we know to re-enable clocks 3217 on resume */ 3218 udc->clocked = 1; 3219 3220 /* Kill global USB clock */ 3221 clk_disable_unprepare(udc->usb_slv_clk); 3222 } 3223 3224 return 0; 3225} 3226 3227static int lpc32xx_udc_resume(struct platform_device *pdev) 3228{ 3229 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3230 3231 if (udc->clocked) { 3232 /* Enable global USB clock */ 3233 clk_prepare_enable(udc->usb_slv_clk); 3234 3235 /* Enable clocking */ 3236 udc_clk_set(udc, 1); 3237 3238 /* ISP back to normal power mode */ 3239 udc->poweron = 1; 3240 isp1301_set_powerstate(udc, 1); 3241 } 3242 3243 return 0; 3244} 3245#else 3246#define lpc32xx_udc_suspend NULL 3247#define lpc32xx_udc_resume NULL 3248#endif 3249 3250#ifdef CONFIG_OF 3251static const struct of_device_id lpc32xx_udc_of_match[] = { 3252 { .compatible = "nxp,lpc3220-udc", }, 3253 { }, 3254}; 3255MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match); 3256#endif 3257 3258static struct platform_driver lpc32xx_udc_driver = { 3259 .probe = lpc32xx_udc_probe, 3260 .remove = lpc32xx_udc_remove, 3261 .shutdown = lpc32xx_udc_shutdown, 3262 .suspend = lpc32xx_udc_suspend, 3263 .resume = lpc32xx_udc_resume, 3264 .driver = { 3265 .name = driver_name, 3266 .of_match_table = of_match_ptr(lpc32xx_udc_of_match), 3267 }, 3268}; 3269 3270module_platform_driver(lpc32xx_udc_driver); 3271 3272MODULE_DESCRIPTION("LPC32XX udc driver"); 3273MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 3274MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 3275MODULE_LICENSE("GPL"); 3276MODULE_ALIAS("platform:lpc32xx_udc");
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