dwc3-am62.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
  4 *
  5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
  6 */
  7
  8#include <linux/init.h>
  9#include <linux/kernel.h>
 10#include <linux/module.h>
 11#include <linux/platform_device.h>
 12#include <linux/mfd/syscon.h>
 13#include <linux/of.h>
 14#include <linux/of_platform.h>
 15#include <linux/pm_runtime.h>
 16#include <linux/clk.h>
 17#include <linux/regmap.h>
 18#include <linux/pinctrl/consumer.h>
 19
 20#include "core.h"
 21
 22/* USB WRAPPER register offsets */
 23#define USBSS_PID			0x0
 24#define USBSS_OVERCURRENT_CTRL		0x4
 25#define USBSS_PHY_CONFIG		0x8
 26#define USBSS_PHY_TEST			0xc
 27#define USBSS_CORE_STAT			0x14
 28#define USBSS_HOST_VBUS_CTRL		0x18
 29#define USBSS_MODE_CONTROL		0x1c
 30#define USBSS_WAKEUP_CONFIG		0x30
 31#define USBSS_WAKEUP_STAT		0x34
 32#define USBSS_OVERRIDE_CONFIG		0x38
 33#define USBSS_IRQ_MISC_STATUS_RAW	0x430
 34#define USBSS_IRQ_MISC_STATUS		0x434
 35#define USBSS_IRQ_MISC_ENABLE_SET	0x438
 36#define USBSS_IRQ_MISC_ENABLE_CLR	0x43c
 37#define USBSS_IRQ_MISC_EOI		0x440
 38#define USBSS_INTR_TEST			0x490
 39#define USBSS_VBUS_FILTER		0x614
 40#define USBSS_VBUS_STAT			0x618
 41#define USBSS_DEBUG_CFG			0x708
 42#define USBSS_DEBUG_DATA		0x70c
 43#define USBSS_HOST_HUB_CTRL		0x714
 44
 45/* PHY CONFIG register bits */
 46#define USBSS_PHY_VBUS_SEL_MASK		GENMASK(2, 1)
 47#define USBSS_PHY_VBUS_SEL_SHIFT	1
 48#define USBSS_PHY_LANE_REVERSE		BIT(0)
 49
 50/* CORE STAT register bits */
 51#define USBSS_CORE_OPERATIONAL_MODE_MASK	GENMASK(13, 12)
 52#define USBSS_CORE_OPERATIONAL_MODE_SHIFT	12
 53
 54/* MODE CONTROL register bits */
 55#define USBSS_MODE_VALID	BIT(0)
 56
 57/* WAKEUP CONFIG register bits */
 58#define USBSS_WAKEUP_CFG_OVERCURRENT_EN	BIT(3)
 59#define USBSS_WAKEUP_CFG_LINESTATE_EN	BIT(2)
 60#define USBSS_WAKEUP_CFG_SESSVALID_EN	BIT(1)
 61#define USBSS_WAKEUP_CFG_VBUSVALID_EN	BIT(0)
 62
 63#define USBSS_WAKEUP_CFG_ALL	(USBSS_WAKEUP_CFG_VBUSVALID_EN | \
 64				 USBSS_WAKEUP_CFG_SESSVALID_EN | \
 65				 USBSS_WAKEUP_CFG_LINESTATE_EN | \
 66				 USBSS_WAKEUP_CFG_OVERCURRENT_EN)
 67
 68#define USBSS_WAKEUP_CFG_NONE	0
 69
 70/* WAKEUP STAT register bits */
 71#define USBSS_WAKEUP_STAT_OVERCURRENT	BIT(4)
 72#define USBSS_WAKEUP_STAT_LINESTATE	BIT(3)
 73#define USBSS_WAKEUP_STAT_SESSVALID	BIT(2)
 74#define USBSS_WAKEUP_STAT_VBUSVALID	BIT(1)
 75#define USBSS_WAKEUP_STAT_CLR		BIT(0)
 76
 77/* IRQ_MISC_STATUS_RAW register bits */
 78#define USBSS_IRQ_MISC_RAW_VBUSVALID	BIT(22)
 79#define USBSS_IRQ_MISC_RAW_SESSVALID	BIT(20)
 80
 81/* IRQ_MISC_STATUS register bits */
 82#define USBSS_IRQ_MISC_VBUSVALID	BIT(22)
 83#define USBSS_IRQ_MISC_SESSVALID	BIT(20)
 84
 85/* IRQ_MISC_ENABLE_SET register bits */
 86#define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALID	BIT(22)
 87#define USBSS_IRQ_MISC_ENABLE_SET_SESSVALID	BIT(20)
 88
 89/* IRQ_MISC_ENABLE_CLR register bits */
 90#define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALID	BIT(22)
 91#define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALID	BIT(20)
 92
 93/* IRQ_MISC_EOI register bits */
 94#define USBSS_IRQ_MISC_EOI_VECTOR	BIT(0)
 95
 96/* VBUS_STAT register bits */
 97#define USBSS_VBUS_STAT_SESSVALID	BIT(2)
 98#define USBSS_VBUS_STAT_VBUSVALID	BIT(0)
 99
100/* USB_PHY_CTRL register bits in CTRL_MMR */
101#define PHY_CORE_VOLTAGE_MASK	BIT(31)
102#define PHY_PLL_REFCLK_MASK	GENMASK(3, 0)
103
104/* USB PHY2 register offsets */
105#define	USB_PHY_PLL_REG12		0x130
106#define	USB_PHY_PLL_LDO_REF_EN		BIT(5)
107#define	USB_PHY_PLL_LDO_REF_EN_EN	BIT(4)
108
109#define DWC3_AM62_AUTOSUSPEND_DELAY	100
110
111#define USBSS_DEBUG_CFG_OFF		0x0
112#define USBSS_DEBUG_CFG_DISABLED	0x7
113
114struct dwc3_am62 {
115	struct device *dev;
116	void __iomem *usbss;
117	struct clk *usb2_refclk;
118	int rate_code;
119	struct regmap *syscon;
120	unsigned int offset;
121	unsigned int vbus_divider;
122	u32 wakeup_stat;
123	void __iomem *phy_regs;
124};
125
126static const int dwc3_ti_rate_table[] = {	/* in KHZ */
127	9600,
128	10000,
129	12000,
130	19200,
131	20000,
132	24000,
133	25000,
134	26000,
135	38400,
136	40000,
137	58000,
138	50000,
139	52000,
140};
141
142static inline u32 dwc3_ti_readl(struct dwc3_am62 *am62, u32 offset)
143{
144	return readl((am62->usbss) + offset);
145}
146
147static inline void dwc3_ti_writel(struct dwc3_am62 *am62, u32 offset, u32 value)
148{
149	writel(value, (am62->usbss) + offset);
150}
151
152static int phy_syscon_pll_refclk(struct dwc3_am62 *am62)
153{
154	struct device *dev = am62->dev;
155	struct device_node *node = dev->of_node;
156	struct regmap *syscon;
157	int ret;
158
159	syscon = syscon_regmap_lookup_by_phandle_args(node, "ti,syscon-phy-pll-refclk",
160						      1, &am62->offset);
161	if (IS_ERR(syscon)) {
162		dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n");
163		return PTR_ERR(syscon);
164	}
165
166	am62->syscon = syscon;
167
168	/* Core voltage. PHY_CORE_VOLTAGE bit Recommended to be 0 always */
169	ret = regmap_update_bits(am62->syscon, am62->offset, PHY_CORE_VOLTAGE_MASK, 0);
170	if (ret) {
171		dev_err(dev, "failed to set phy core voltage\n");
172		return ret;
173	}
174
175	ret = regmap_update_bits(am62->syscon, am62->offset, PHY_PLL_REFCLK_MASK, am62->rate_code);
176	if (ret) {
177		dev_err(dev, "failed to set phy pll reference clock rate\n");
178		return ret;
179	}
180
181	return 0;
182}
183
184static int dwc3_ti_init(struct dwc3_am62 *am62)
185{
186	int ret;
187	u32 reg;
188
189	/* Read the syscon property and set the rate code */
190	ret = phy_syscon_pll_refclk(am62);
191	if (ret)
192		return ret;
193
194	/* Workaround Errata i2409 */
195	if (am62->phy_regs) {
196		reg = readl(am62->phy_regs + USB_PHY_PLL_REG12);
197		reg |= USB_PHY_PLL_LDO_REF_EN | USB_PHY_PLL_LDO_REF_EN_EN;
198		writel(reg, am62->phy_regs + USB_PHY_PLL_REG12);
199	}
200
201	/* VBUS divider select */
202	reg = dwc3_ti_readl(am62, USBSS_PHY_CONFIG);
203	if (am62->vbus_divider)
204		reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT;
205
206	dwc3_ti_writel(am62, USBSS_PHY_CONFIG, reg);
207
208	clk_prepare_enable(am62->usb2_refclk);
209
210	/* Set mode valid bit to indicate role is valid */
211	reg = dwc3_ti_readl(am62, USBSS_MODE_CONTROL);
212	reg |= USBSS_MODE_VALID;
213	dwc3_ti_writel(am62, USBSS_MODE_CONTROL, reg);
214
215	return 0;
216}
217
218static int dwc3_ti_probe(struct platform_device *pdev)
219{
220	struct device *dev = &pdev->dev;
221	struct device_node *node = pdev->dev.of_node;
222	struct dwc3_am62 *am62;
223	unsigned long rate;
224	int i, ret;
225
226	am62 = devm_kzalloc(dev, sizeof(*am62), GFP_KERNEL);
227	if (!am62)
228		return -ENOMEM;
229
230	am62->dev = dev;
231	platform_set_drvdata(pdev, am62);
232
233	am62->usbss = devm_platform_ioremap_resource(pdev, 0);
234	if (IS_ERR(am62->usbss)) {
235		dev_err(dev, "can't map IOMEM resource\n");
236		return PTR_ERR(am62->usbss);
237	}
238
239	am62->usb2_refclk = devm_clk_get(dev, "ref");
240	if (IS_ERR(am62->usb2_refclk)) {
241		dev_err(dev, "can't get usb2_refclk\n");
242		return PTR_ERR(am62->usb2_refclk);
243	}
244
245	/* Calculate the rate code */
246	rate = clk_get_rate(am62->usb2_refclk);
247	rate /= 1000;	// To KHz
248	for (i = 0; i < ARRAY_SIZE(dwc3_ti_rate_table); i++) {
249		if (dwc3_ti_rate_table[i] == rate)
250			break;
251	}
252
253	if (i == ARRAY_SIZE(dwc3_ti_rate_table)) {
254		dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate);
255		return -EINVAL;
256	}
257
258	am62->rate_code = i;
259
260	am62->phy_regs = devm_platform_ioremap_resource(pdev, 1);
261	if (IS_ERR(am62->phy_regs)) {
262		dev_err(dev, "can't map PHY IOMEM resource. Won't apply i2409 fix.\n");
263		am62->phy_regs = NULL;
264	}
265
266	am62->vbus_divider = device_property_read_bool(dev, "ti,vbus-divider");
267
268	ret = dwc3_ti_init(am62);
269	if (ret)
270		return ret;
271
272	pm_runtime_set_active(dev);
273	pm_runtime_enable(dev);
274	/*
275	 * Don't ignore its dependencies with its children
276	 */
277	pm_suspend_ignore_children(dev, false);
278	pm_runtime_get_noresume(dev);
279
280	ret = of_platform_populate(node, NULL, NULL, dev);
281	if (ret) {
282		dev_err(dev, "failed to create dwc3 core: %d\n", ret);
283		goto err_pm_disable;
284	}
285
286	/* Device has capability to wakeup system from sleep */
287	device_set_wakeup_capable(dev, true);
288	ret = device_wakeup_enable(dev);
289	if (ret)
290		dev_err(dev, "couldn't enable device as a wakeup source: %d\n", ret);
291
292	/* Setting up autosuspend */
293	pm_runtime_set_autosuspend_delay(dev, DWC3_AM62_AUTOSUSPEND_DELAY);
294	pm_runtime_use_autosuspend(dev);
295	pm_runtime_put_autosuspend(dev);
296	return 0;
297
298err_pm_disable:
299	clk_disable_unprepare(am62->usb2_refclk);
300	pm_runtime_disable(dev);
301	pm_runtime_set_suspended(dev);
302	return ret;
303}
304
305static void dwc3_ti_remove(struct platform_device *pdev)
306{
307	struct device *dev = &pdev->dev;
308	struct dwc3_am62 *am62 = platform_get_drvdata(pdev);
309	u32 reg;
310
311	pm_runtime_get_sync(dev);
312	device_init_wakeup(dev, false);
313	of_platform_depopulate(dev);
314
315	/* Clear mode valid bit */
316	reg = dwc3_ti_readl(am62, USBSS_MODE_CONTROL);
317	reg &= ~USBSS_MODE_VALID;
318	dwc3_ti_writel(am62, USBSS_MODE_CONTROL, reg);
319
320	pm_runtime_put_sync(dev);
321	pm_runtime_disable(dev);
322	pm_runtime_dont_use_autosuspend(dev);
323	pm_runtime_set_suspended(dev);
324}
325
326#ifdef CONFIG_PM
327static int dwc3_ti_suspend_common(struct device *dev)
328{
329	struct dwc3_am62 *am62 = dev_get_drvdata(dev);
330	u32 reg, current_prtcap_dir;
331
332	if (device_may_wakeup(dev)) {
333		reg = dwc3_ti_readl(am62, USBSS_CORE_STAT);
334		current_prtcap_dir = (reg & USBSS_CORE_OPERATIONAL_MODE_MASK)
335				     >> USBSS_CORE_OPERATIONAL_MODE_SHIFT;
336		/* Set wakeup config enable bits */
337		reg = dwc3_ti_readl(am62, USBSS_WAKEUP_CONFIG);
338		if (current_prtcap_dir == DWC3_GCTL_PRTCAP_HOST) {
339			reg = USBSS_WAKEUP_CFG_LINESTATE_EN | USBSS_WAKEUP_CFG_OVERCURRENT_EN;
340		} else {
341			reg = USBSS_WAKEUP_CFG_VBUSVALID_EN | USBSS_WAKEUP_CFG_SESSVALID_EN;
342			/*
343			 * Enable LINESTATE wake up only if connected to bus
344			 * and in U2/L3 state else it causes spurious wake-up.
345			 */
346		}
347		dwc3_ti_writel(am62, USBSS_WAKEUP_CONFIG, reg);
348		/* clear wakeup status so we know what caused the wake up */
349		dwc3_ti_writel(am62, USBSS_WAKEUP_STAT, USBSS_WAKEUP_STAT_CLR);
350	}
351
352	/* just to track if module resets on suspend */
353	dwc3_ti_writel(am62, USBSS_DEBUG_CFG, USBSS_DEBUG_CFG_DISABLED);
354
355	clk_disable_unprepare(am62->usb2_refclk);
356
357	return 0;
358}
359
360static int dwc3_ti_resume_common(struct device *dev)
361{
362	struct dwc3_am62 *am62 = dev_get_drvdata(dev);
363	u32 reg;
364
365	reg = dwc3_ti_readl(am62, USBSS_DEBUG_CFG);
366	if (reg != USBSS_DEBUG_CFG_DISABLED) {
367		/* lost power/context */
368		dwc3_ti_init(am62);
369	} else {
370		dwc3_ti_writel(am62, USBSS_DEBUG_CFG, USBSS_DEBUG_CFG_OFF);
371		clk_prepare_enable(am62->usb2_refclk);
372	}
373
374	if (device_may_wakeup(dev)) {
375		/* Clear wakeup config enable bits */
376		dwc3_ti_writel(am62, USBSS_WAKEUP_CONFIG, USBSS_WAKEUP_CFG_NONE);
377	}
378
379	reg = dwc3_ti_readl(am62, USBSS_WAKEUP_STAT);
380	am62->wakeup_stat = reg;
381
382	return 0;
383}
384
385static UNIVERSAL_DEV_PM_OPS(dwc3_ti_pm_ops, dwc3_ti_suspend_common,
386			    dwc3_ti_resume_common, NULL);
387
388#define DEV_PM_OPS	(&dwc3_ti_pm_ops)
389#else
390#define DEV_PM_OPS	NULL
391#endif /* CONFIG_PM */
392
393static const struct of_device_id dwc3_ti_of_match[] = {
394	{ .compatible = "ti,am62-usb"},
395	{},
396};
397MODULE_DEVICE_TABLE(of, dwc3_ti_of_match);
398
399static struct platform_driver dwc3_ti_driver = {
400	.probe		= dwc3_ti_probe,
401	.remove		= dwc3_ti_remove,
402	.driver		= {
403		.name	= "dwc3-am62",
404		.pm	= DEV_PM_OPS,
405		.of_match_table = dwc3_ti_of_match,
406	},
407};
408
409module_platform_driver(dwc3_ti_driver);
410
411MODULE_ALIAS("platform:dwc3-am62");
412MODULE_AUTHOR("Aswath Govindraju <a-govindraju@ti.com>");
413MODULE_LICENSE("GPL");
414MODULE_DESCRIPTION("DesignWare USB3 TI Glue Layer");