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core.c
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linux-6.19.14/drivers/usb/dwc2/core.c
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * core.c - DesignWare HS OTG Controller common routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 */ 7 8/* 9 * The Core code provides basic services for accessing and managing the 10 * DWC_otg hardware. These services are used by both the Host Controller 11 * Driver and the Peripheral Controller Driver. 12 */ 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/moduleparam.h> 16#include <linux/spinlock.h> 17#include <linux/interrupt.h> 18#include <linux/dma-mapping.h> 19#include <linux/delay.h> 20#include <linux/io.h> 21#include <linux/slab.h> 22#include <linux/usb.h> 23 24#include <linux/usb/hcd.h> 25#include <linux/usb/ch11.h> 26 27#include "core.h" 28#include "hcd.h" 29 30/** 31 * dwc2_backup_global_registers() - Backup global controller registers. 32 * When suspending usb bus, registers needs to be backuped 33 * if controller power is disabled once suspended. 34 * 35 * @hsotg: Programming view of the DWC_otg controller 36 */ 37int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 38{ 39 struct dwc2_gregs_backup *gr; 40 41 dev_dbg(hsotg->dev, "%s\n", __func__); 42 43 /* Backup global regs */ 44 gr = &hsotg->gr_backup; 45 46 gr->gintsts = dwc2_readl(hsotg, GINTSTS); 47 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); 48 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); 49 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); 50 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG); 51 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 52 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 53 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG); 54 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); 55 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG); 56 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL); 57 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL); 58 59 gr->valid = true; 60 return 0; 61} 62 63/** 64 * dwc2_restore_global_registers() - Restore controller global registers. 65 * When resuming usb bus, device registers needs to be restored 66 * if controller power were disabled. 67 * 68 * @hsotg: Programming view of the DWC_otg controller 69 */ 70int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 71{ 72 struct dwc2_gregs_backup *gr; 73 74 dev_dbg(hsotg->dev, "%s\n", __func__); 75 76 /* Restore global regs */ 77 gr = &hsotg->gr_backup; 78 if (!gr->valid) { 79 dev_err(hsotg->dev, "%s: no global registers to restore\n", 80 __func__); 81 return -EINVAL; 82 } 83 gr->valid = false; 84 85 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 86 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL); 87 dwc2_writel(hsotg, gr->gintmsk, GINTMSK); 88 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 89 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG); 90 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ); 91 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ); 92 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG); 93 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1); 94 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG); 95 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL); 96 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL); 97 98 return 0; 99} 100 101/** 102 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down. 103 * 104 * @hsotg: Programming view of the DWC_otg controller 105 * @rem_wakeup: indicates whether resume is initiated by Reset. 106 * @restore: Controller registers need to be restored 107 */ 108int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 109 bool restore) 110{ 111 struct dwc2_gregs_backup *gr; 112 113 gr = &hsotg->gr_backup; 114 115 /* 116 * Restore host or device regisers with the same mode core enterted 117 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup 118 * value of the "gotgctl" register. 119 */ 120 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 121 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup, 122 restore); 123 else 124 return dwc2_gadget_exit_partial_power_down(hsotg, restore); 125} 126 127/** 128 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down. 129 * 130 * @hsotg: Programming view of the DWC_otg controller 131 */ 132int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg) 133{ 134 if (dwc2_is_host_mode(hsotg)) 135 return dwc2_host_enter_partial_power_down(hsotg); 136 else 137 return dwc2_gadget_enter_partial_power_down(hsotg); 138} 139 140/** 141 * dwc2_restore_essential_regs() - Restore essiential regs of core. 142 * 143 * @hsotg: Programming view of the DWC_otg controller 144 * @rmode: Restore mode, enabled in case of remote-wakeup. 145 * @is_host: Host or device mode. 146 */ 147static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode, 148 int is_host) 149{ 150 u32 pcgcctl; 151 struct dwc2_gregs_backup *gr; 152 struct dwc2_dregs_backup *dr; 153 struct dwc2_hregs_backup *hr; 154 155 gr = &hsotg->gr_backup; 156 dr = &hsotg->dr_backup; 157 hr = &hsotg->hr_backup; 158 159 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__); 160 161 /* Load restore values for [31:14] bits */ 162 pcgcctl = (gr->pcgcctl & 0xffffc000); 163 /* If High Speed */ 164 if (is_host) { 165 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK)) 166 pcgcctl |= BIT(17); 167 } else { 168 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK)) 169 pcgcctl |= BIT(17); 170 } 171 dwc2_writel(hsotg, pcgcctl, PCGCTL); 172 173 /* Umnask global Interrupt in GAHBCFG and restore it */ 174 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG); 175 176 /* Clear all pending interupts */ 177 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 178 179 /* Unmask restore done interrupt */ 180 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK); 181 182 /* Restore GUSBCFG and HCFG/DCFG */ 183 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 184 185 if (is_host) { 186 dwc2_writel(hsotg, hr->hcfg, HCFG); 187 if (rmode) 188 pcgcctl |= PCGCTL_RESTOREMODE; 189 dwc2_writel(hsotg, pcgcctl, PCGCTL); 190 udelay(10); 191 192 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 193 dwc2_writel(hsotg, pcgcctl, PCGCTL); 194 udelay(10); 195 } else { 196 dwc2_writel(hsotg, dr->dcfg, DCFG); 197 if (!rmode) 198 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE; 199 dwc2_writel(hsotg, pcgcctl, PCGCTL); 200 udelay(10); 201 202 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 203 dwc2_writel(hsotg, pcgcctl, PCGCTL); 204 udelay(10); 205 } 206} 207 208/** 209 * dwc2_hib_restore_common() - Common part of restore routine. 210 * 211 * @hsotg: Programming view of the DWC_otg controller 212 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 213 * @is_host: Host or device mode. 214 */ 215void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 216 int is_host) 217{ 218 u32 gpwrdn; 219 220 /* Switch-on voltage to the core */ 221 gpwrdn = dwc2_readl(hsotg, GPWRDN); 222 gpwrdn &= ~GPWRDN_PWRDNSWTCH; 223 dwc2_writel(hsotg, gpwrdn, GPWRDN); 224 udelay(10); 225 226 /* Reset core */ 227 gpwrdn = dwc2_readl(hsotg, GPWRDN); 228 gpwrdn &= ~GPWRDN_PWRDNRSTN; 229 dwc2_writel(hsotg, gpwrdn, GPWRDN); 230 udelay(10); 231 232 /* Enable restore from PMU */ 233 gpwrdn = dwc2_readl(hsotg, GPWRDN); 234 gpwrdn |= GPWRDN_RESTORE; 235 dwc2_writel(hsotg, gpwrdn, GPWRDN); 236 udelay(10); 237 238 /* Disable Power Down Clamp */ 239 gpwrdn = dwc2_readl(hsotg, GPWRDN); 240 gpwrdn &= ~GPWRDN_PWRDNCLMP; 241 dwc2_writel(hsotg, gpwrdn, GPWRDN); 242 udelay(50); 243 244 if (!is_host && rem_wakeup) 245 udelay(70); 246 247 /* Deassert reset core */ 248 gpwrdn = dwc2_readl(hsotg, GPWRDN); 249 gpwrdn |= GPWRDN_PWRDNRSTN; 250 dwc2_writel(hsotg, gpwrdn, GPWRDN); 251 udelay(10); 252 253 /* Reset ULPI latch */ 254 gpwrdn = dwc2_readl(hsotg, GPWRDN); 255 gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY; 256 dwc2_writel(hsotg, gpwrdn, GPWRDN); 257 258 /* Disable PMU interrupt */ 259 gpwrdn = dwc2_readl(hsotg, GPWRDN); 260 gpwrdn &= ~GPWRDN_PMUINTSEL; 261 dwc2_writel(hsotg, gpwrdn, GPWRDN); 262 udelay(10); 263 264 /* Set Restore Essential Regs bit in PCGCCTL register */ 265 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host); 266 267 /* 268 * Wait For Restore_done Interrupt. This mechanism of polling the 269 * interrupt is introduced to avoid any possible race conditions 270 */ 271 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE, 272 20000)) { 273 dev_dbg(hsotg->dev, 274 "%s: Restore Done wasn't generated here\n", 275 __func__); 276 } else { 277 dev_dbg(hsotg->dev, "restore done generated here\n"); 278 279 /* 280 * To avoid restore done interrupt storm after restore is 281 * generated clear GINTSTS_RESTOREDONE bit. 282 */ 283 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS); 284 } 285} 286 287/** 288 * dwc2_wait_for_mode() - Waits for the controller mode. 289 * @hsotg: Programming view of the DWC_otg controller. 290 * @host_mode: If true, waits for host mode, otherwise device mode. 291 */ 292static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, 293 bool host_mode) 294{ 295 ktime_t start; 296 ktime_t end; 297 unsigned int timeout = 110; 298 299 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", 300 host_mode ? "host" : "device"); 301 302 start = ktime_get(); 303 304 while (1) { 305 s64 ms; 306 307 if (dwc2_is_host_mode(hsotg) == host_mode) { 308 dev_vdbg(hsotg->dev, "%s mode set\n", 309 host_mode ? "Host" : "Device"); 310 break; 311 } 312 313 end = ktime_get(); 314 ms = ktime_to_ms(ktime_sub(end, start)); 315 316 if (ms >= (s64)timeout) { 317 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", 318 __func__, host_mode ? "host" : "device"); 319 break; 320 } 321 322 usleep_range(1000, 2000); 323 } 324} 325 326/** 327 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce 328 * filter is enabled. 329 * 330 * @hsotg: Programming view of DWC_otg controller 331 */ 332static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 333{ 334 u32 gsnpsid; 335 u32 ghwcfg4; 336 337 if (!dwc2_hw_is_otg(hsotg)) 338 return false; 339 340 /* Check if core configuration includes the IDDIG filter. */ 341 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4); 342 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 343 return false; 344 345 /* 346 * Check if the IDDIG debounce filter is bypassed. Available 347 * in core version >= 3.10a. 348 */ 349 gsnpsid = dwc2_readl(hsotg, GSNPSID); 350 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 351 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); 352 353 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 354 return false; 355 } 356 357 return true; 358} 359 360/* 361 * dwc2_enter_hibernation() - Common function to enter hibernation. 362 * 363 * @hsotg: Programming view of the DWC_otg controller 364 * @is_host: True if core is in host mode. 365 * 366 * Return: 0 if successful, negative error code otherwise 367 */ 368int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host) 369{ 370 if (is_host) 371 return dwc2_host_enter_hibernation(hsotg); 372 else 373 return dwc2_gadget_enter_hibernation(hsotg); 374} 375 376/* 377 * dwc2_exit_hibernation() - Common function to exit from hibernation. 378 * 379 * @hsotg: Programming view of the DWC_otg controller 380 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 381 * @reset: Enabled in case of restore with reset. 382 * @is_host: True if core is in host mode. 383 * 384 * Return: 0 if successful, negative error code otherwise 385 */ 386int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 387 int reset, int is_host) 388{ 389 if (is_host) 390 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset); 391 else 392 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset); 393} 394 395/* 396 * Do core a soft reset of the core. Be careful with this because it 397 * resets all the internal state machines of the core. 398 */ 399int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) 400{ 401 u32 greset; 402 bool wait_for_host_mode = false; 403 404 dev_vdbg(hsotg->dev, "%s()\n", __func__); 405 406 /* 407 * If the current mode is host, either due to the force mode 408 * bit being set (which persists after core reset) or the 409 * connector id pin, a core soft reset will temporarily reset 410 * the mode to device. A delay from the IDDIG debounce filter 411 * will occur before going back to host mode. 412 * 413 * Determine whether we will go back into host mode after a 414 * reset and account for this delay after the reset. 415 */ 416 if (dwc2_iddig_filter_enabled(hsotg)) { 417 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); 418 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 419 420 if (!(gotgctl & GOTGCTL_CONID_B) || 421 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 422 wait_for_host_mode = true; 423 } 424 } 425 426 /* Core Soft Reset */ 427 greset = dwc2_readl(hsotg, GRSTCTL); 428 greset |= GRSTCTL_CSFTRST; 429 dwc2_writel(hsotg, greset, GRSTCTL); 430 431 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) < 432 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { 433 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, 434 GRSTCTL_CSFTRST, 10000)) { 435 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n", 436 __func__); 437 return -EBUSY; 438 } 439 } else { 440 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, 441 GRSTCTL_CSFTRST_DONE, 10000)) { 442 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n", 443 __func__); 444 return -EBUSY; 445 } 446 greset = dwc2_readl(hsotg, GRSTCTL); 447 greset &= ~GRSTCTL_CSFTRST; 448 greset |= GRSTCTL_CSFTRST_DONE; 449 dwc2_writel(hsotg, greset, GRSTCTL); 450 } 451 452 /* 453 * Switching from device mode to host mode by disconnecting 454 * device cable core enters and exits form hibernation. 455 * However, the fifo map remains not cleared. It results 456 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/ 457 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2]) 458 * if in host mode we disconnect the micro a to b host 459 * cable. Because core reset occurs. 460 * To avoid the WARNING, fifo_map should be cleared 461 * in dwc2_core_reset() function by taking into account configs. 462 * fifo_map must be cleared only if driver is configured in 463 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE" 464 * mode. 465 */ 466 dwc2_clear_fifo_map(hsotg); 467 468 /* Wait for AHB master IDLE state */ 469 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) { 470 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n", 471 __func__); 472 return -EBUSY; 473 } 474 475 if (wait_for_host_mode && !skip_wait) 476 dwc2_wait_for_mode(hsotg, true); 477 478 return 0; 479} 480 481/** 482 * dwc2_force_mode() - Force the mode of the controller. 483 * 484 * Forcing the mode is needed for two cases: 485 * 486 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 487 * controller to stay in a particular mode regardless of ID pin 488 * changes. We do this once during probe. 489 * 490 * 2) During probe we want to read reset values of the hw 491 * configuration registers that are only available in either host or 492 * device mode. We may need to force the mode if the current mode does 493 * not allow us to access the register in the mode that we want. 494 * 495 * In either case it only makes sense to force the mode if the 496 * controller hardware is OTG capable. 497 * 498 * Checks are done in this function to determine whether doing a force 499 * would be valid or not. 500 * 501 * If a force is done, it requires a IDDIG debounce filter delay if 502 * the filter is configured and enabled. We poll the current mode of 503 * the controller to account for this delay. 504 * 505 * @hsotg: Programming view of DWC_otg controller 506 * @host: Host mode flag 507 */ 508void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 509{ 510 u32 gusbcfg; 511 u32 set; 512 u32 clear; 513 514 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 515 516 /* 517 * Force mode has no effect if the hardware is not OTG. 518 */ 519 if (!dwc2_hw_is_otg(hsotg)) 520 return; 521 522 /* 523 * If dr_mode is either peripheral or host only, there is no 524 * need to ever force the mode to the opposite mode. 525 */ 526 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) 527 return; 528 529 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 530 return; 531 532 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 533 534 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 535 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 536 537 gusbcfg &= ~clear; 538 gusbcfg |= set; 539 dwc2_writel(hsotg, gusbcfg, GUSBCFG); 540 541 dwc2_wait_for_mode(hsotg, host); 542 return; 543} 544 545/** 546 * dwc2_clear_force_mode() - Clears the force mode bits. 547 * 548 * After clearing the bits, wait up to 100 ms to account for any 549 * potential IDDIG filter delay. We can't know if we expect this delay 550 * or not because the value of the connector ID status is affected by 551 * the force mode. We only need to call this once during probe if 552 * dr_mode == OTG. 553 * 554 * @hsotg: Programming view of DWC_otg controller 555 */ 556static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 557{ 558 u32 gusbcfg; 559 560 if (!dwc2_hw_is_otg(hsotg)) 561 return; 562 563 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); 564 565 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 566 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 567 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 568 dwc2_writel(hsotg, gusbcfg, GUSBCFG); 569 570 if (dwc2_iddig_filter_enabled(hsotg)) 571 msleep(100); 572} 573 574/* 575 * Sets or clears force mode based on the dr_mode parameter. 576 */ 577void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 578{ 579 switch (hsotg->dr_mode) { 580 case USB_DR_MODE_HOST: 581 dwc2_force_mode(hsotg, true); 582 /* 583 * NOTE: This is required for some rockchip soc based 584 * platforms on their host-only dwc2. 585 */ 586 if (!dwc2_hw_is_otg(hsotg)) 587 msleep(50); 588 589 break; 590 case USB_DR_MODE_PERIPHERAL: 591 dwc2_force_mode(hsotg, false); 592 break; 593 case USB_DR_MODE_OTG: 594 dwc2_clear_force_mode(hsotg); 595 break; 596 default: 597 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 598 __func__, hsotg->dr_mode); 599 break; 600 } 601} 602 603/* 604 * dwc2_enable_acg - enable active clock gating feature 605 */ 606void dwc2_enable_acg(struct dwc2_hsotg *hsotg) 607{ 608 if (hsotg->params.acg_enable) { 609 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); 610 611 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); 612 pcgcctl1 |= PCGCCTL1_GATEEN; 613 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1); 614 } 615} 616 617/** 618 * dwc2_dump_host_registers() - Prints the host registers 619 * 620 * @hsotg: Programming view of DWC_otg controller 621 * 622 * NOTE: This function will be removed once the peripheral controller code 623 * is integrated and the driver is stable 624 */ 625void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 626{ 627#ifdef DEBUG 628 u32 __iomem *addr; 629 int i; 630 631 dev_dbg(hsotg->dev, "Host Global Registers\n"); 632 addr = hsotg->regs + HCFG; 633 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 634 (unsigned long)addr, dwc2_readl(hsotg, HCFG)); 635 addr = hsotg->regs + HFIR; 636 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 637 (unsigned long)addr, dwc2_readl(hsotg, HFIR)); 638 addr = hsotg->regs + HFNUM; 639 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 640 (unsigned long)addr, dwc2_readl(hsotg, HFNUM)); 641 addr = hsotg->regs + HPTXSTS; 642 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 643 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS)); 644 addr = hsotg->regs + HAINT; 645 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 646 (unsigned long)addr, dwc2_readl(hsotg, HAINT)); 647 addr = hsotg->regs + HAINTMSK; 648 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 649 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK)); 650 if (hsotg->params.dma_desc_enable) { 651 addr = hsotg->regs + HFLBADDR; 652 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 653 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR)); 654 } 655 656 addr = hsotg->regs + HPRT0; 657 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 658 (unsigned long)addr, dwc2_readl(hsotg, HPRT0)); 659 660 for (i = 0; i < hsotg->params.host_channels; i++) { 661 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 662 addr = hsotg->regs + HCCHAR(i); 663 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 664 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i))); 665 addr = hsotg->regs + HCSPLT(i); 666 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 667 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i))); 668 addr = hsotg->regs + HCINT(i); 669 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 670 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i))); 671 addr = hsotg->regs + HCINTMSK(i); 672 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 673 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i))); 674 addr = hsotg->regs + HCTSIZ(i); 675 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 676 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i))); 677 addr = hsotg->regs + HCDMA(i); 678 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 679 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i))); 680 if (hsotg->params.dma_desc_enable) { 681 addr = hsotg->regs + HCDMAB(i); 682 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 683 (unsigned long)addr, dwc2_readl(hsotg, 684 HCDMAB(i))); 685 } 686 } 687#endif 688} 689 690/** 691 * dwc2_dump_global_registers() - Prints the core global registers 692 * 693 * @hsotg: Programming view of DWC_otg controller 694 * 695 * NOTE: This function will be removed once the peripheral controller code 696 * is integrated and the driver is stable 697 */ 698void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 699{ 700#ifdef DEBUG 701 u32 __iomem *addr; 702 703 dev_dbg(hsotg->dev, "Core Global Registers\n"); 704 addr = hsotg->regs + GOTGCTL; 705 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 706 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL)); 707 addr = hsotg->regs + GOTGINT; 708 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 709 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT)); 710 addr = hsotg->regs + GAHBCFG; 711 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 712 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG)); 713 addr = hsotg->regs + GUSBCFG; 714 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 715 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG)); 716 addr = hsotg->regs + GRSTCTL; 717 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 718 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL)); 719 addr = hsotg->regs + GINTSTS; 720 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 721 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS)); 722 addr = hsotg->regs + GINTMSK; 723 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 724 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK)); 725 addr = hsotg->regs + GRXSTSR; 726 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 727 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR)); 728 addr = hsotg->regs + GRXFSIZ; 729 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 730 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ)); 731 addr = hsotg->regs + GNPTXFSIZ; 732 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 733 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ)); 734 addr = hsotg->regs + GNPTXSTS; 735 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 736 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS)); 737 addr = hsotg->regs + GI2CCTL; 738 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 739 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL)); 740 addr = hsotg->regs + GPVNDCTL; 741 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 742 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL)); 743 addr = hsotg->regs + GGPIO; 744 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 745 (unsigned long)addr, dwc2_readl(hsotg, GGPIO)); 746 addr = hsotg->regs + GUID; 747 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 748 (unsigned long)addr, dwc2_readl(hsotg, GUID)); 749 addr = hsotg->regs + GSNPSID; 750 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 751 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID)); 752 addr = hsotg->regs + GHWCFG1; 753 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 754 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1)); 755 addr = hsotg->regs + GHWCFG2; 756 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 757 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2)); 758 addr = hsotg->regs + GHWCFG3; 759 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 760 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3)); 761 addr = hsotg->regs + GHWCFG4; 762 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 763 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4)); 764 addr = hsotg->regs + GLPMCFG; 765 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 766 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG)); 767 addr = hsotg->regs + GPWRDN; 768 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 769 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN)); 770 addr = hsotg->regs + GDFIFOCFG; 771 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 772 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG)); 773 addr = hsotg->regs + HPTXFSIZ; 774 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 775 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ)); 776 777 addr = hsotg->regs + PCGCTL; 778 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 779 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL)); 780#endif 781} 782 783/** 784 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 785 * 786 * @hsotg: Programming view of DWC_otg controller 787 * @num: Tx FIFO to flush 788 */ 789void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 790{ 791 u32 greset; 792 793 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 794 795 /* Wait for AHB master IDLE state */ 796 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 797 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 798 __func__); 799 800 greset = GRSTCTL_TXFFLSH; 801 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 802 dwc2_writel(hsotg, greset, GRSTCTL); 803 804 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) 805 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", 806 __func__); 807 808 /* Wait for at least 3 PHY Clocks */ 809 udelay(1); 810} 811 812/** 813 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 814 * 815 * @hsotg: Programming view of DWC_otg controller 816 */ 817void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 818{ 819 u32 greset; 820 821 dev_vdbg(hsotg->dev, "%s()\n", __func__); 822 823 /* Wait for AHB master IDLE state */ 824 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 825 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 826 __func__); 827 828 greset = GRSTCTL_RXFFLSH; 829 dwc2_writel(hsotg, greset, GRSTCTL); 830 831 /* Wait for RxFIFO flush done */ 832 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000)) 833 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n", 834 __func__); 835 836 /* Wait for at least 3 PHY Clocks */ 837 udelay(1); 838} 839 840bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 841{ 842 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff) 843 return false; 844 else 845 return true; 846} 847 848/** 849 * dwc2_enable_global_interrupts() - Enables the controller's Global 850 * Interrupt in the AHB Config register 851 * 852 * @hsotg: Programming view of DWC_otg controller 853 */ 854void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 855{ 856 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 857 858 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 859 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 860} 861 862/** 863 * dwc2_disable_global_interrupts() - Disables the controller's Global 864 * Interrupt in the AHB Config register 865 * 866 * @hsotg: Programming view of DWC_otg controller 867 */ 868void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 869{ 870 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 871 872 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 873 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 874} 875 876/* Returns the controller's GHWCFG2.OTG_MODE. */ 877unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) 878{ 879 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2); 880 881 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 882 GHWCFG2_OP_MODE_SHIFT; 883} 884 885/* Returns true if the controller is capable of DRD. */ 886bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 887{ 888 unsigned int op_mode = dwc2_op_mode(hsotg); 889 890 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 891 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 892 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 893} 894 895/* Returns true if the controller is host-only. */ 896bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 897{ 898 unsigned int op_mode = dwc2_op_mode(hsotg); 899 900 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 901 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 902} 903 904/* Returns true if the controller is device-only. */ 905bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 906{ 907 unsigned int op_mode = dwc2_op_mode(hsotg); 908 909 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 910 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 911} 912 913/** 914 * dwc2_hsotg_wait_bit_set - Waits for bit to be set. 915 * @hsotg: Programming view of DWC_otg controller. 916 * @offset: Register's offset where bit/bits must be set. 917 * @mask: Mask of the bit/bits which must be set. 918 * @timeout: Timeout to wait. 919 * 920 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 921 */ 922int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 923 u32 timeout) 924{ 925 u32 i; 926 927 for (i = 0; i < timeout; i++) { 928 if (dwc2_readl(hsotg, offset) & mask) 929 return 0; 930 udelay(1); 931 } 932 933 return -ETIMEDOUT; 934} 935 936/** 937 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear. 938 * @hsotg: Programming view of DWC_otg controller. 939 * @offset: Register's offset where bit/bits must be set. 940 * @mask: Mask of the bit/bits which must be set. 941 * @timeout: Timeout to wait. 942 * 943 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 944 */ 945int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 946 u32 timeout) 947{ 948 u32 i; 949 950 for (i = 0; i < timeout; i++) { 951 if (!(dwc2_readl(hsotg, offset) & mask)) 952 return 0; 953 udelay(1); 954 } 955 956 return -ETIMEDOUT; 957} 958 959/* 960 * Initializes the FSLSPClkSel field of the HCFG register depending on the 961 * PHY type 962 */ 963void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 964{ 965 u32 hcfg, val; 966 967 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 968 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 969 hsotg->params.ulpi_fs_ls) || 970 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 971 /* Full speed PHY */ 972 val = HCFG_FSLSPCLKSEL_48_MHZ; 973 } else { 974 /* High speed PHY running at full speed or high speed */ 975 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 976 } 977 978 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 979 hcfg = dwc2_readl(hsotg, HCFG); 980 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 981 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 982 dwc2_writel(hsotg, hcfg, HCFG); 983} 984 985static void dwc2_set_clock_switch_timer(struct dwc2_hsotg *hsotg) 986{ 987 u32 grstctl, gsnpsid, val = 0; 988 989 gsnpsid = dwc2_readl(hsotg, GSNPSID); 990 991 /* 992 * Applicable only to HSOTG core v5.00a or higher. 993 * Not applicable to HS/FS IOT devices. 994 */ 995 if ((gsnpsid & ~DWC2_CORE_REV_MASK) != DWC2_OTG_ID || 996 gsnpsid < DWC2_CORE_REV_5_00a) 997 return; 998 999 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI && 1000 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) || 1001 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 1002 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) || 1003 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED && 1004 hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED)) { 1005 val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_DIS; 1006 } 1007 1008 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW && 1009 hsotg->hw_params.hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED && 1010 hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) { 1011 val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_147; 1012 } 1013 1014 grstctl = dwc2_readl(hsotg, GRSTCTL); 1015 grstctl &= ~GRSTCTL_CLOCK_SWITH_TIMER_MASK; 1016 grstctl |= GRSTCTL_CLOCK_SWITH_TIMER(val); 1017 dwc2_writel(hsotg, grstctl, GRSTCTL); 1018} 1019 1020static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1021{ 1022 u32 usbcfg, ggpio, i2cctl; 1023 int retval = 0; 1024 1025 /* 1026 * core_init() is now called on every switch so only call the 1027 * following for the first time through 1028 */ 1029 if (select_phy) { 1030 dev_dbg(hsotg->dev, "FS PHY selected\n"); 1031 1032 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1033 if (!(usbcfg & GUSBCFG_PHYSEL)) { 1034 usbcfg |= GUSBCFG_PHYSEL; 1035 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1036 1037 dwc2_set_clock_switch_timer(hsotg); 1038 1039 /* Reset after a PHY select */ 1040 retval = dwc2_core_reset(hsotg, false); 1041 1042 if (retval) { 1043 dev_err(hsotg->dev, 1044 "%s: Reset failed, aborting", __func__); 1045 return retval; 1046 } 1047 } 1048 1049 if (hsotg->params.activate_stm_fs_transceiver) { 1050 ggpio = dwc2_readl(hsotg, GGPIO); 1051 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 1052 dev_dbg(hsotg->dev, "Activating transceiver\n"); 1053 /* 1054 * STM32F4x9 uses the GGPIO register as general 1055 * core configuration register. 1056 */ 1057 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 1058 dwc2_writel(hsotg, ggpio, GGPIO); 1059 } 1060 } 1061 } 1062 1063 /* 1064 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 1065 * do this on HNP Dev/Host mode switches (done in dev_init and 1066 * host_init). 1067 */ 1068 if (dwc2_is_host_mode(hsotg)) 1069 dwc2_init_fs_ls_pclk_sel(hsotg); 1070 1071 if (hsotg->params.i2c_enable) { 1072 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 1073 1074 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 1075 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1076 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 1077 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1078 1079 /* Program GI2CCTL.I2CEn */ 1080 i2cctl = dwc2_readl(hsotg, GI2CCTL); 1081 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 1082 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 1083 i2cctl &= ~GI2CCTL_I2CEN; 1084 dwc2_writel(hsotg, i2cctl, GI2CCTL); 1085 i2cctl |= GI2CCTL_I2CEN; 1086 dwc2_writel(hsotg, i2cctl, GI2CCTL); 1087 } 1088 1089 return retval; 1090} 1091 1092static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1093{ 1094 u32 usbcfg, usbcfg_old; 1095 int retval = 0; 1096 1097 if (!select_phy) 1098 return 0; 1099 1100 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1101 usbcfg_old = usbcfg; 1102 1103 /* 1104 * HS PHY parameters. These parameters are preserved during soft reset 1105 * so only program the first time. Do a soft reset immediately after 1106 * setting phyif. 1107 */ 1108 switch (hsotg->params.phy_type) { 1109 case DWC2_PHY_TYPE_PARAM_ULPI: 1110 /* ULPI interface */ 1111 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 1112 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 1113 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 1114 if (hsotg->params.phy_ulpi_ddr) 1115 usbcfg |= GUSBCFG_DDRSEL; 1116 1117 /* Set external VBUS indicator as needed. */ 1118 if (hsotg->params.oc_disable) 1119 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | 1120 GUSBCFG_INDICATORPASSTHROUGH); 1121 break; 1122 case DWC2_PHY_TYPE_PARAM_UTMI: 1123 /* UTMI+ interface */ 1124 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 1125 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 1126 if (hsotg->params.phy_utmi_width == 16) 1127 usbcfg |= GUSBCFG_PHYIF16; 1128 break; 1129 default: 1130 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 1131 break; 1132 } 1133 1134 if (usbcfg != usbcfg_old) { 1135 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1136 1137 /* Reset after setting the PHY parameters */ 1138 retval = dwc2_core_reset(hsotg, false); 1139 if (retval) { 1140 dev_err(hsotg->dev, 1141 "%s: Reset failed, aborting", __func__); 1142 return retval; 1143 } 1144 } 1145 1146 return retval; 1147} 1148 1149static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg) 1150{ 1151 u32 usbcfg; 1152 1153 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI) 1154 return; 1155 1156 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1157 1158 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK; 1159 if (hsotg->params.phy_utmi_width == 16) 1160 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT; 1161 else 1162 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT; 1163 1164 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1165} 1166 1167int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1168{ 1169 u32 usbcfg; 1170 u32 otgctl; 1171 int retval = 0; 1172 1173 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 1174 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 1175 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 1176 /* If FS/LS mode with FS/LS PHY */ 1177 retval = dwc2_fs_phy_init(hsotg, select_phy); 1178 if (retval) 1179 return retval; 1180 } else { 1181 /* High speed PHY */ 1182 retval = dwc2_hs_phy_init(hsotg, select_phy); 1183 if (retval) 1184 return retval; 1185 1186 if (dwc2_is_device_mode(hsotg)) 1187 dwc2_set_turnaround_time(hsotg); 1188 } 1189 1190 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 1191 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 1192 hsotg->params.ulpi_fs_ls) { 1193 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 1194 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1195 usbcfg |= GUSBCFG_ULPI_FS_LS; 1196 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 1197 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1198 } else { 1199 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1200 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 1201 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 1202 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1203 } 1204 1205 if (!hsotg->params.activate_ingenic_overcurrent_detection) { 1206 if (dwc2_is_host_mode(hsotg)) { 1207 otgctl = readl(hsotg->regs + GOTGCTL); 1208 otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL; 1209 writel(otgctl, hsotg->regs + GOTGCTL); 1210 } 1211 } 1212 1213 return retval; 1214} 1215 1216MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); 1217MODULE_AUTHOR("Synopsys, Inc."); 1218MODULE_LICENSE("Dual BSD/GPL");
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