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cdnsp-gadget.h
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linux-6.19.14/drivers/usb/cdns3/cdnsp-gadget.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Cadence CDNSP DRD Driver. 4 * 5 * Copyright (C) 2020 Cadence. 6 * 7 * Author: Pawel Laszczak <pawell@cadence.com> 8 * 9 * Code based on Linux XHCI driver. 10 * Origin: Copyright (C) 2008 Intel Corp. 11 */ 12#ifndef __LINUX_CDNSP_GADGET_H 13#define __LINUX_CDNSP_GADGET_H 14 15#include <linux/io-64-nonatomic-lo-hi.h> 16#include <linux/usb/gadget.h> 17#include <linux/irq.h> 18 19/* Max number slots - only 1 is allowed. */ 20#define CDNSP_DEV_MAX_SLOTS 1 21 22#define CDNSP_EP0_SETUP_SIZE 512 23 24/* One control and 15 for in and 15 for out endpoints. */ 25#define CDNSP_ENDPOINTS_NUM 31 26 27/* Best Effort Service Latency. */ 28#define CDNSP_DEFAULT_BESL 0 29 30/* Device Controller command default timeout value in us */ 31#define CDNSP_CMD_TIMEOUT (15 * 1000) 32 33/* Up to 16 ms to halt an device controller */ 34#define CDNSP_MAX_HALT_USEC (16 * 1000) 35 36#define CDNSP_CTX_SIZE 2112 37 38/* 39 * Controller register interface. 40 */ 41 42/** 43 * struct cdnsp_cap_regs - CDNSP Registers. 44 * @hc_capbase: Length of the capabilities register and controller 45 * version number 46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 49 * @hcc_params: HCCPARAMS - Capability Parameters 50 * @db_off: DBOFF - Doorbell array offset 51 * @run_regs_off: RTSOFF - Runtime register space offset 52 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, 53 */ 54struct cdnsp_cap_regs { 55 __le32 hc_capbase; 56 __le32 hcs_params1; 57 __le32 hcs_params2; 58 __le32 hcs_params3; 59 __le32 hcc_params; 60 __le32 db_off; 61 __le32 run_regs_off; 62 __le32 hcc_params2; 63 /* Reserved up to (CAPLENGTH - 0x1C) */ 64}; 65 66/* hc_capbase bitmasks. */ 67/* bits 7:0 - how long is the Capabilities register. */ 68#define HC_LENGTH(p) (((p) >> 00) & GENMASK(7, 0)) 69/* bits 31:16 */ 70#define HC_VERSION(p) (((p) >> 16) & GENMASK(15, 1)) 71 72/* HCSPARAMS1 - hcs_params1 - bitmasks */ 73/* bits 0:7, Max Device Endpoints */ 74#define HCS_ENDPOINTS_MASK GENMASK(7, 0) 75#define HCS_ENDPOINTS(p) (((p) & HCS_ENDPOINTS_MASK) >> 0) 76 77/* HCCPARAMS offset from PCI base address */ 78#define HCC_PARAMS_OFFSET 0x10 79 80/* HCCPARAMS - hcc_params - bitmasks */ 81/* 1: device controller can use 64-bit address pointers. */ 82#define HCC_64BIT_ADDR(p) ((p) & BIT(0)) 83/* 1: device controller uses 64-byte Device Context structures. */ 84#define HCC_64BYTE_CONTEXT(p) ((p) & BIT(2)) 85/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */ 86#define HCC_MAX_PSA(p) ((((p) >> 12) & 0xf) + 1) 87/* Extended Capabilities pointer from PCI base. */ 88#define HCC_EXT_CAPS(p) (((p) & GENMASK(31, 16)) >> 16) 89 90#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 91 92/* db_off bitmask - bits 0:1 reserved. */ 93#define DBOFF_MASK GENMASK(31, 2) 94 95/* run_regs_off bitmask - bits 0:4 reserved. */ 96#define RTSOFF_MASK GENMASK(31, 5) 97 98/** 99 * struct cdnsp_op_regs - Device Controller Operational Registers. 100 * @command: USBCMD - Controller command register. 101 * @status: USBSTS - Controller status register. 102 * @page_size: This indicates the page size that the device controller supports. 103 * If bit n is set, the controller supports a page size of 2^(n+12), 104 * up to a 128MB page size. 4K is the minimum page size. 105 * @dnctrl: DNCTRL - Device notification control register. 106 * @cmd_ring: CRP - 64-bit Command Ring Pointer. 107 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer. 108 * @config_reg: CONFIG - Configure Register 109 * @port_reg_base: PORTSCn - base address for Port Status and Control 110 * Each port has a Port Status and Control register, 111 * followed by a Port Power Management Status and Control 112 * register, a Port Link Info register, and a reserved 113 * register. 114 */ 115struct cdnsp_op_regs { 116 __le32 command; 117 __le32 status; 118 __le32 page_size; 119 __le32 reserved1; 120 __le32 reserved2; 121 __le32 dnctrl; 122 __le64 cmd_ring; 123 /* rsvd: offset 0x20-2F. */ 124 __le32 reserved3[4]; 125 __le64 dcbaa_ptr; 126 __le32 config_reg; 127 /* rsvd: offset 0x3C-3FF. */ 128 __le32 reserved4[241]; 129 /* port 1 registers, which serve as a base address for other ports. */ 130 __le32 port_reg_base; 131}; 132 133/* Number of registers per port. */ 134#define NUM_PORT_REGS 4 135 136/** 137 * struct cdnsp_port_regs - Port Registers. 138 * @portsc: PORTSC - Port Status and Control Register. 139 * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register. 140 * @portli: PORTLI - Port Link Info register. 141 */ 142struct cdnsp_port_regs { 143 __le32 portsc; 144 __le32 portpmsc; 145 __le32 portli; 146 __le32 reserved; 147}; 148 149/* 150 * These bits are Read Only (RO) and should be saved and written to the 151 * registers: 0 (connect status) and 10:13 (port speed). 152 * These bits are also sticky - meaning they're in the AUX well and they aren't 153 * changed by a hot and warm. 154 */ 155#define CDNSP_PORT_RO (PORT_CONNECT | DEV_SPEED_MASK) 156 157/* 158 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 159 * bits 5:8 (link state), 25:26 ("wake on" enable state) 160 */ 161#define CDNSP_PORT_RWS (PORT_PLS_MASK | PORT_WKCONN_E | PORT_WKDISC_E) 162 163/* 164 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 165 * bits 1 (port enable/disable), 17 ( connect changed), 166 * 21 (port reset changed) , 22 (Port Link State Change), 167 */ 168#define CDNSP_PORT_RW1CS (PORT_PED | PORT_CSC | PORT_RC | PORT_PLC) 169 170/* USBCMD - USB command - bitmasks. */ 171/* Run/Stop, controller execution - do not write unless controller is halted.*/ 172#define CMD_R_S BIT(0) 173/* 174 * Reset device controller - resets internal controller state machine and all 175 * registers (except PCI config regs). 176 */ 177#define CMD_RESET BIT(1) 178/* Event Interrupt Enable - a '1' allows interrupts from the controller. */ 179#define CMD_INTE BIT(2) 180/* 181 * Device System Error Interrupt Enable - get out-of-band signal for 182 * controller errors. 183 */ 184#define CMD_DSEIE BIT(3) 185/* device controller save/restore state. */ 186#define CMD_CSS BIT(8) 187#define CMD_CRS BIT(9) 188/* 189 * Enable Wrap Event - '1' means device controller generates an event 190 * when MFINDEX wraps. 191 */ 192#define CMD_EWE BIT(10) 193/* 1: device enabled */ 194#define CMD_DEVEN BIT(17) 195/* bits 18:31 are reserved (and should be preserved on writes). */ 196 197/* Command register values to disable interrupts. */ 198#define CDNSP_IRQS (CMD_INTE | CMD_DSEIE | CMD_EWE) 199 200/* USBSTS - USB status - bitmasks */ 201/* controller not running - set to 1 when run/stop bit is cleared. */ 202#define STS_HALT BIT(0) 203/* 204 * serious error, e.g. PCI parity error. The controller will clear 205 * the run/stop bit. 206 */ 207#define STS_FATAL BIT(2) 208/* event interrupt - clear this prior to clearing any IP flags in IR set.*/ 209#define STS_EINT BIT(3) 210/* port change detect */ 211#define STS_PCD BIT(4) 212/* save state status - '1' means device controller is saving state. */ 213#define STS_SSS BIT(8) 214/* restore state status - '1' means controllers is restoring state. */ 215#define STS_RSS BIT(9) 216/* 1: save or restore error */ 217#define STS_SRE BIT(10) 218/* 1: device Not Ready to accept doorbell or op reg writes after reset. */ 219#define STS_CNR BIT(11) 220/* 1: internal Device Controller Error.*/ 221#define STS_HCE BIT(12) 222 223/* CRCR - Command Ring Control Register - cmd_ring bitmasks. */ 224/* bit 0 is the command ring cycle state. */ 225#define CMD_RING_CS BIT(0) 226/* stop ring immediately - abort the currently executing command. */ 227#define CMD_RING_ABORT BIT(2) 228/* 229 * Command Ring Busy. 230 * Set when Doorbell register is written with DB for command and cleared when 231 * the controller reached end of CR. 232 */ 233#define CMD_RING_BUSY(p) ((p) & BIT(4)) 234/* 1: command ring is running */ 235#define CMD_RING_RUNNING BIT(3) 236/* Command Ring pointer - bit mask for the lower 32 bits. */ 237#define CMD_RING_RSVD_BITS GENMASK(5, 0) 238 239/* CONFIG - Configure Register - config_reg bitmasks. */ 240/* bits 0:7 - maximum number of device slots enabled. */ 241#define MAX_DEVS GENMASK(7, 0) 242/* bit 8: U3 Entry Enabled, assert PLC when controller enters U3. */ 243#define CONFIG_U3E BIT(8) 244 245/* PORTSC - Port Status and Control Register - port_reg_base bitmasks */ 246/* 1: device connected. */ 247#define PORT_CONNECT BIT(0) 248/* 1: port enabled. */ 249#define PORT_PED BIT(1) 250/* 1: port reset signaling asserted. */ 251#define PORT_RESET BIT(4) 252/* 253 * Port Link State - bits 5:8 254 * A read gives the current link PM state of the port, 255 * a write with Link State Write Strobe sets the link state. 256 */ 257#define PORT_PLS_MASK GENMASK(8, 5) 258#define XDEV_U0 (0x0 << 5) 259#define XDEV_U1 (0x1 << 5) 260#define XDEV_U2 (0x2 << 5) 261#define XDEV_U3 (0x3 << 5) 262#define XDEV_DISABLED (0x4 << 5) 263#define XDEV_RXDETECT (0x5 << 5) 264#define XDEV_INACTIVE (0x6 << 5) 265#define XDEV_POLLING (0x7 << 5) 266#define XDEV_RECOVERY (0x8 << 5) 267#define XDEV_HOT_RESET (0x9 << 5) 268#define XDEV_COMP_MODE (0xa << 5) 269#define XDEV_TEST_MODE (0xb << 5) 270#define XDEV_RESUME (0xf << 5) 271/* 1: port has power. */ 272#define PORT_POWER BIT(9) 273/* 274 * bits 10:13 indicate device speed: 275 * 0 - undefined speed - port hasn't be initialized by a reset yet 276 * 1 - full speed 277 * 2 - Reserved (Low Speed not supported 278 * 3 - high speed 279 * 4 - super speed 280 * 5 - super speed 281 * 6-15 reserved 282 */ 283#define DEV_SPEED_MASK GENMASK(13, 10) 284#define XDEV_FS (0x1 << 10) 285#define XDEV_HS (0x3 << 10) 286#define XDEV_SS (0x4 << 10) 287#define XDEV_SSP (0x5 << 10) 288#define XDEV_SSP1x2 (0x6 << 10) 289#define XDEV_SSP2x2 (0x7 << 10) 290#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0 << 10)) 291#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 292#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 293#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 294#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 295#define DEV_SSP_GEN1x2(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP1x2) 296#define DEV_SSP_GEN2x2(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP2x2) 297#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 298#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 299/* Port Link State Write Strobe - set this when changing link state */ 300#define PORT_LINK_STROBE BIT(16) 301/* 1: connect status change */ 302#define PORT_CSC BIT(17) 303/* 1: warm reset for a USB 3.0 device is done. */ 304#define PORT_WRC BIT(19) 305/* 1: reset change - 1 to 0 transition of PORT_RESET */ 306#define PORT_RC BIT(21) 307/* 308 * port link status change - set on some port link state transitions: 309 * Transition Reason 310 * ---------------------------------------------------------------------------- 311 * - U3 to Resume Wakeup signaling from a device 312 * - Resume to Recovery to U0 USB 3.0 device resume 313 * - Resume to U0 USB 2.0 device resume 314 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 315 * - U3 to U0 Software resume of USB 2.0 device complete 316 * - U2 to U0 L1 resume of USB 2.1 device complete 317 * - U0 to U0 L1 entry rejection by USB 2.1 device 318 * - U0 to disabled L1 entry error with USB 2.1 device 319 * - Any state to inactive Error on USB 3.0 port 320 */ 321#define PORT_PLC BIT(22) 322/* Port configure error change - port failed to configure its link partner. */ 323#define PORT_CEC BIT(23) 324/* Wake on connect (enable). */ 325#define PORT_WKCONN_E BIT(25) 326/* Wake on disconnect (enable). */ 327#define PORT_WKDISC_E BIT(26) 328/* Indicates if Warm Reset is being received. */ 329#define PORT_WR BIT(31) 330 331#define PORT_CHANGE_BITS (PORT_CSC | PORT_WRC | PORT_RC | PORT_PLC | PORT_CEC) 332 333/* PORTPMSCUSB3 - Port Power Management Status and Control - bitmasks. */ 334/* Enables U1 entry. */ 335#define PORT_U1_TIMEOUT_MASK GENMASK(7, 0) 336#define PORT_U1_TIMEOUT(p) ((p) & PORT_U1_TIMEOUT_MASK) 337/* Enables U2 entry .*/ 338#define PORT_U2_TIMEOUT_MASK GENMASK(14, 8) 339#define PORT_U2_TIMEOUT(p) (((p) << 8) & PORT_U2_TIMEOUT_MASK) 340 341/* PORTPMSCUSB2 - Port Power Management Status and Control - bitmasks. */ 342#define PORT_L1S_MASK GENMASK(2, 0) 343#define PORT_L1S(p) ((p) & PORT_L1S_MASK) 344#define PORT_L1S_ACK PORT_L1S(1) 345#define PORT_L1S_NYET PORT_L1S(2) 346#define PORT_L1S_STALL PORT_L1S(3) 347#define PORT_L1S_TIMEOUT PORT_L1S(4) 348/* Remote Wake Enable. */ 349#define PORT_RWE BIT(3) 350/* Best Effort Service Latency (BESL). */ 351#define PORT_BESL(p) (((p) << 4) & GENMASK(7, 4)) 352/* Hardware LPM Enable (HLE). */ 353#define PORT_HLE BIT(16) 354/* Received Best Effort Service Latency (BESL). */ 355#define PORT_RRBESL(p) (((p) & GENMASK(20, 17)) >> 17) 356/* Port Test Control. */ 357#define PORT_TEST_MODE_MASK GENMASK(31, 28) 358#define PORT_TEST_MODE(p) (((p) << 28) & PORT_TEST_MODE_MASK) 359 360/** 361 * struct cdnsp_intr_reg - Interrupt Register Set. 362 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 363 * interrupts and check for pending interrupts. 364 * @irq_control: IMOD - Interrupt Moderation Register. 365 * Used to throttle interrupts. 366 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 367 * @erst_base: ERST base address. 368 * @erst_dequeue: Event ring dequeue pointer. 369 * 370 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 371 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 372 * multiple segments of the same size. The controller places events on the ring 373 * and "updates the Cycle bit in the TRBs to indicate to software the current 374 * position of the Enqueue Pointer." The driver processes those events and 375 * updates the dequeue pointer. 376 */ 377struct cdnsp_intr_reg { 378 __le32 irq_pending; 379 __le32 irq_control; 380 __le32 erst_size; 381 __le32 rsvd; 382 __le64 erst_base; 383 __le64 erst_dequeue; 384}; 385 386/* IMAN - Interrupt Management Register - irq_pending bitmasks l. */ 387#define IMAN_IE BIT(1) 388#define IMAN_IP BIT(0) 389/* bits 2:31 need to be preserved */ 390#define IMAN_IE_SET(p) ((p) | IMAN_IE) 391#define IMAN_IE_CLEAR(p) ((p) & ~IMAN_IE) 392 393/* IMOD - Interrupter Moderation Register - irq_control bitmasks. */ 394/* 395 * Minimum interval between interrupts (in 250ns intervals). The interval 396 * between interrupts will be longer if there are no events on the event ring. 397 * Default is 4000 (1 ms). 398 */ 399#define IMOD_INTERVAL_MASK GENMASK(15, 0) 400/* Counter used to count down the time to the next interrupt - HW use only */ 401#define IMOD_COUNTER_MASK GENMASK(31, 16) 402#define IMOD_DEFAULT_INTERVAL 0 403 404/* erst_size bitmasks. */ 405/* Preserve bits 16:31 of erst_size. */ 406#define ERST_SIZE_MASK GENMASK(31, 16) 407 408/* erst_dequeue bitmasks. */ 409/* 410 * Dequeue ERST Segment Index (DESI) - Segment number (or alias) 411 * where the current dequeue pointer lies. This is an optional HW hint. 412 */ 413#define ERST_DESI_MASK GENMASK(2, 0) 414/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced. */ 415#define ERST_EHB BIT(3) 416#define ERST_PTR_MASK GENMASK(3, 0) 417 418/** 419 * struct cdnsp_run_regs 420 * @microframe_index: MFINDEX - current microframe number. 421 * @ir_set: Array of Interrupter registers. 422 * 423 * Device Controller Runtime Registers: 424 * "Software should read and write these registers using only Dword (32 bit) 425 * or larger accesses" 426 */ 427struct cdnsp_run_regs { 428 __le32 microframe_index; 429 __le32 rsvd[7]; 430 struct cdnsp_intr_reg ir_set[128]; 431}; 432 433/** 434 * USB2.0 Port Peripheral Configuration Registers. 435 * @ext_cap: Header register for Extended Capability. 436 * @port_reg1: Timer Configuration Register. 437 * @port_reg2: Timer Configuration Register. 438 * @port_reg3: Timer Configuration Register. 439 * @port_reg4: Timer Configuration Register. 440 * @port_reg5: Timer Configuration Register. 441 * @port_reg6: Chicken bits for USB20PPP. 442 */ 443struct cdnsp_20port_cap { 444 __le32 ext_cap; 445 __le32 port_reg1; 446 __le32 port_reg2; 447 __le32 port_reg3; 448 __le32 port_reg4; 449 __le32 port_reg5; 450 __le32 port_reg6; 451}; 452 453/* Extended capability register fields */ 454#define EXT_CAPS_ID(p) (((p) >> 0) & GENMASK(7, 0)) 455#define EXT_CAPS_NEXT(p) (((p) >> 8) & GENMASK(7, 0)) 456/* Extended capability IDs - ID 0 reserved */ 457#define EXT_CAPS_PROTOCOL 2 458 459/* USB 2.0 Port Peripheral Configuration Extended Capability */ 460#define EXT_CAP_CFG_DEV_20PORT_CAP_ID 0xC1 461/* 462 * Setting this bit to '1' enables automatic wakeup from L1 state on transfer 463 * TRB prepared when USBSSP operates in USB2.0 mode. 464 */ 465#define PORT_REG6_L1_L0_HW_EN BIT(1) 466/* 467 * Setting this bit to '1' forces Full Speed when USBSSP operates in USB2.0 468 * mode (disables High Speed). 469 */ 470#define PORT_REG6_FORCE_FS BIT(0) 471 472/** 473 * USB3.x Port Peripheral Configuration Registers. 474 * @ext_cap: Header register for Extended Capability. 475 * @mode_addr: Miscellaneous 3xPORT operation mode configuration register. 476 * @mode_2: 3x Port Control Register 2. 477 */ 478struct cdnsp_3xport_cap { 479 __le32 ext_cap; 480 __le32 mode_addr; 481 __le32 reserved[52]; 482 __le32 mode_2; 483}; 484 485/* Extended Capability Header for 3XPort Configuration Registers. */ 486#define D_XEC_CFG_3XPORT_CAP 0xC0 487#define CFG_3XPORT_SSP_SUPPORT BIT(31) 488#define CFG_3XPORT_U1_PIPE_CLK_GATE_EN BIT(0) 489 490/* Revision Extended Capability ID */ 491#define RTL_REV_CAP 0xC4 492#define RTL_REV_CAP_RX_BUFF_CMD_SIZE BITMASK(31, 24) 493#define RTL_REV_CAP_RX_BUFF_SIZE BITMASK(15, 0) 494#define RTL_REV_CAP_TX_BUFF_CMD_SIZE BITMASK(31, 24) 495#define RTL_REV_CAP_TX_BUFF_SIZE BITMASK(15, 0) 496 497#define CDNSP_VER_1 0x00000000 498#define CDNSP_VER_2 0x10000000 499 500#define CDNSP_IF_EP_EXIST(pdev, ep_num, dir) \ 501 (readl(&(pdev)->rev_cap->ep_supported) & \ 502 (BIT(ep_num) << ((dir) ? 0 : 16))) 503 504/** 505 * struct cdnsp_rev_cap - controller capabilities. 506 * @ext_cap: Header for RTL Revision Extended Capability. 507 * @rtl_revision: RTL revision. 508 * @rx_buff_size: Rx buffer sizes. 509 * @tx_buff_size: Tx buffer sizes. 510 * @ep_supported: Supported endpoints. 511 * @ctrl_revision: Controller revision ID. 512 */ 513struct cdnsp_rev_cap { 514 __le32 ext_cap; 515 __le32 rtl_revision; 516 __le32 rx_buff_size; 517 __le32 tx_buff_size; 518 __le32 ep_supported; 519 __le32 ctrl_revision; 520}; 521 522/* USB2.0 Port Peripheral Configuration Registers. */ 523#define D_XEC_PRE_REGS_CAP 0xC8 524#define REG_CHICKEN_BITS_2_OFFSET 0x48 525#define CHICKEN_XDMA_2_TP_CACHE_DIS BIT(28) 526 527#define REG_CHICKEN_BITS_3_OFFSET 0x4C 528#define CHICKEN_APB_TIMEOUT_SET(p, val) (((p) & ~GENMASK(21, 0)) | (val)) 529 530/* XBUF Extended Capability ID. */ 531#define XBUF_CAP_ID 0xCB 532#define XBUF_RX_TAG_MASK_0_OFFSET 0x1C 533#define XBUF_RX_TAG_MASK_1_OFFSET 0x24 534#define XBUF_TX_CMD_OFFSET 0x2C 535 536/** 537 * struct cdnsp_doorbell_array. 538 * @cmd_db: Command ring doorbell register. 539 * @ep_db: Endpoint ring doorbell register. 540 * Bits 0 - 7: Endpoint target. 541 * Bits 8 - 15: RsvdZ. 542 * Bits 16 - 31: Stream ID. 543 */ 544struct cdnsp_doorbell_array { 545 __le32 cmd_db; 546 __le32 ep_db; 547}; 548 549#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 550#define DB_VALUE_EP0_OUT(ep, stream) ((ep) & 0xff) 551#define DB_VALUE_CMD 0x00000000 552 553/** 554 * struct cdnsp_container_ctx. 555 * @type: Type of context. Used to calculated offsets to contained contexts. 556 * @size: Size of the context data. 557 * @ctx_size: context data structure size - 64 or 32 bits. 558 * @dma: dma address of the bytes. 559 * @bytes: The raw context data given to HW. 560 * 561 * Represents either a Device or Input context. Holds a pointer to the raw 562 * memory used for the context (bytes) and dma address of it (dma). 563 */ 564struct cdnsp_container_ctx { 565 unsigned int type; 566#define CDNSP_CTX_TYPE_DEVICE 0x1 567#define CDNSP_CTX_TYPE_INPUT 0x2 568 int size; 569 int ctx_size; 570 dma_addr_t dma; 571 u8 *bytes; 572}; 573 574/** 575 * struct cdnsp_slot_ctx 576 * @dev_info: Device speed, and last valid endpoint. 577 * @dev_port: Device port number that is needed to access the USB device. 578 * @int_target: Interrupter target number. 579 * @dev_state: Slot state and device address. 580 * 581 * Slot Context - This assumes the controller uses 32-byte context 582 * structures. If the controller uses 64-byte contexts, there is an additional 583 * 32 bytes reserved at the end of the slot context for controller internal use. 584 */ 585struct cdnsp_slot_ctx { 586 __le32 dev_info; 587 __le32 dev_port; 588 __le32 int_target; 589 __le32 dev_state; 590 /* offset 0x10 to 0x1f reserved for controller internal use. */ 591 __le32 reserved[4]; 592}; 593 594/* Bits 20:23 in the Slot Context are the speed for the device. */ 595#define SLOT_SPEED_FS (XDEV_FS << 10) 596#define SLOT_SPEED_HS (XDEV_HS << 10) 597#define SLOT_SPEED_SS (XDEV_SS << 10) 598#define SLOT_SPEED_SSP (XDEV_SSP << 10) 599 600/* dev_info bitmasks. */ 601/* Device speed - values defined by PORTSC Device Speed field - 20:23. */ 602#define DEV_SPEED GENMASK(23, 20) 603#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 604/* Index of the last valid endpoint context in this device context - 27:31. */ 605#define LAST_CTX_MASK ((unsigned int)GENMASK(31, 27)) 606#define LAST_CTX(p) ((p) << 27) 607#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 608#define SLOT_FLAG BIT(0) 609#define EP0_FLAG BIT(1) 610 611/* dev_port bitmasks */ 612/* Device port number that is needed to access the USB device. */ 613#define DEV_PORT(p) (((p) & 0xff) << 16) 614 615/* dev_state bitmasks */ 616/* USB device address - assigned by the controller. */ 617#define DEV_ADDR_MASK GENMASK(7, 0) 618/* Slot state */ 619#define SLOT_STATE GENMASK(31, 27) 620#define GET_SLOT_STATE(p) (((p) & SLOT_STATE) >> 27) 621 622#define SLOT_STATE_DISABLED 0 623#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 624#define SLOT_STATE_DEFAULT 1 625#define SLOT_STATE_ADDRESSED 2 626#define SLOT_STATE_CONFIGURED 3 627 628/** 629 * struct cdnsp_ep_ctx. 630 * @ep_info: Endpoint state, streams, mult, and interval information. 631 * @ep_info2: Information on endpoint type, max packet size, max burst size, 632 * error count, and whether the controller will force an event for 633 * all transactions. 634 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 635 * defines one stream, this points to the endpoint transfer ring. 636 * Otherwise, it points to a stream context array, which has a 637 * ring pointer for each flow. 638 * @tx_info: Average TRB lengths for the endpoint ring and 639 * max payload within an Endpoint Service Interval Time (ESIT). 640 * 641 * Endpoint Context - This assumes the controller uses 32-byte context 642 * structures. If the controller uses 64-byte contexts, there is an additional 643 * 32 bytes reserved at the end of the endpoint context for controller internal 644 * use. 645 */ 646struct cdnsp_ep_ctx { 647 __le32 ep_info; 648 __le32 ep_info2; 649 __le64 deq; 650 __le32 tx_info; 651 /* offset 0x14 - 0x1f reserved for controller internal use. */ 652 __le32 reserved[3]; 653}; 654 655/* ep_info bitmasks. */ 656/* 657 * Endpoint State - bits 0:2: 658 * 0 - disabled 659 * 1 - running 660 * 2 - halted due to halt condition 661 * 3 - stopped 662 * 4 - TRB error 663 * 5-7 - reserved 664 */ 665#define EP_STATE_MASK GENMASK(3, 0) 666#define EP_STATE_DISABLED 0 667#define EP_STATE_RUNNING 1 668#define EP_STATE_HALTED 2 669#define EP_STATE_STOPPED 3 670#define EP_STATE_ERROR 4 671#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 672 673/* Mult - Max number of burst within an interval, in EP companion desc. */ 674#define EP_MULT(p) (((p) << 8) & GENMASK(9, 8)) 675#define CTX_TO_EP_MULT(p) (((p) & GENMASK(9, 8)) >> 8) 676/* bits 10:14 are Max Primary Streams. */ 677/* bit 15 is Linear Stream Array. */ 678/* Interval - period between requests to an endpoint - 125u increments. */ 679#define EP_INTERVAL(p) (((p) << 16) & GENMASK(23, 16)) 680#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) & GENMASK(23, 16)) >> 16)) 681#define CTX_TO_EP_INTERVAL(p) (((p) & GENMASK(23, 16)) >> 16) 682#define EP_MAXPSTREAMS_MASK GENMASK(14, 10) 683#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 684#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 685/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 686#define EP_HAS_LSA BIT(15) 687 688/* ep_info2 bitmasks */ 689#define ERROR_COUNT(p) (((p) & 0x3) << 1) 690#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 691#define EP_TYPE(p) ((p) << 3) 692#define ISOC_OUT_EP 1 693#define BULK_OUT_EP 2 694#define INT_OUT_EP 3 695#define CTRL_EP 4 696#define ISOC_IN_EP 5 697#define BULK_IN_EP 6 698#define INT_IN_EP 7 699/* bit 6 reserved. */ 700/* bit 7 is Device Initiate Disable - for disabling stream selection. */ 701#define MAX_BURST(p) (((p) << 8) & GENMASK(15, 8)) 702#define CTX_TO_MAX_BURST(p) (((p) & GENMASK(15, 8)) >> 8) 703#define MAX_PACKET(p) (((p) << 16) & GENMASK(31, 16)) 704#define MAX_PACKET_MASK GENMASK(31, 16) 705#define MAX_PACKET_DECODED(p) (((p) & GENMASK(31, 16)) >> 16) 706 707/* tx_info bitmasks. */ 708#define EP_AVG_TRB_LENGTH(p) ((p) & GENMASK(15, 0)) 709#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) << 16) & GENMASK(31, 16)) 710#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) & GENMASK(23, 16)) >> 16) << 24) 711#define CTX_TO_MAX_ESIT_PAYLOAD_LO(p) (((p) & GENMASK(31, 16)) >> 16) 712#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) & GENMASK(31, 24)) >> 24) 713 714/* deq bitmasks. */ 715#define EP_CTX_CYCLE_MASK BIT(0) 716#define CTX_DEQ_MASK (~0xfL) 717 718/** 719 * struct cdnsp_input_control_context 720 * Input control context; 721 * 722 * @drop_context: Set the bit of the endpoint context you want to disable. 723 * @add_context: Set the bit of the endpoint context you want to enable. 724 */ 725struct cdnsp_input_control_ctx { 726 __le32 drop_flags; 727 __le32 add_flags; 728 __le32 rsvd2[6]; 729}; 730 731/** 732 * Represents everything that is needed to issue a command on the command ring. 733 * 734 * @in_ctx: Pointer to input context structure. 735 * @status: Command Completion Code for last command. 736 * @command_trb: Pointer to command TRB. 737 */ 738struct cdnsp_command { 739 /* Input context for changing device state. */ 740 struct cdnsp_container_ctx *in_ctx; 741 u32 status; 742 union cdnsp_trb *command_trb; 743}; 744 745/** 746 * Stream context structure. 747 * 748 * @stream_ring: 64-bit stream ring address, cycle state, and stream type. 749 * @reserved: offset 0x14 - 0x1f reserved for controller internal use. 750 */ 751struct cdnsp_stream_ctx { 752 __le64 stream_ring; 753 __le32 reserved[2]; 754}; 755 756/* Stream Context Types - bits 3:1 of stream ctx deq ptr. */ 757#define SCT_FOR_CTX(p) (((p) << 1) & GENMASK(3, 1)) 758/* Secondary stream array type, dequeue pointer is to a transfer ring. */ 759#define SCT_SEC_TR 0 760/* Primary stream array type, dequeue pointer is to a transfer ring. */ 761#define SCT_PRI_TR 1 762 763/** 764 * struct cdnsp_stream_info: Representing everything that is needed to 765 * supports stream capable endpoints. 766 * @stream_rings: Array of pointers containing Transfer rings for all 767 * supported streams. 768 * @num_streams: Number of streams, including stream 0. 769 * @stream_ctx_array: The stream context array may be bigger than the number 770 * of streams the driver asked for. 771 * @num_stream_ctxs: Number of streams. 772 * @ctx_array_dma: Dma address of Context Stream Array. 773 * @trb_address_map: For mapping physical TRB addresses to segments in 774 * stream rings. 775 * @td_count: Number of TDs associated with endpoint. 776 * @first_prime_det: First PRIME packet detected. 777 * @drbls_count: Number of allowed doorbells. 778 */ 779struct cdnsp_stream_info { 780 struct cdnsp_ring **stream_rings; 781 unsigned int num_streams; 782 struct cdnsp_stream_ctx *stream_ctx_array; 783 unsigned int num_stream_ctxs; 784 dma_addr_t ctx_array_dma; 785 struct radix_tree_root trb_address_map; 786 int td_count; 787 u8 first_prime_det; 788#define STREAM_DRBL_FIFO_DEPTH 2 789 u8 drbls_count; 790}; 791 792#define STREAM_LOG_STREAMS 4 793#define STREAM_NUM_STREAMS BIT(STREAM_LOG_STREAMS) 794 795#if STREAM_LOG_STREAMS > 16 && STREAM_LOG_STREAMS < 1 796#error "Not suupported stream value" 797#endif 798 799/** 800 * struct cdnsp_ep - extended device side representation of USB endpoint. 801 * @endpoint: usb endpoint 802 * @pending_req_list: List of requests queuing on transfer ring. 803 * @pdev: Device associated with this endpoint. 804 * @number: Endpoint number (1 - 15). 805 * idx: The device context index (DCI). 806 * interval: Interval between packets used for ISOC endpoint. 807 * @name: A human readable name e.g. ep1out. 808 * @direction: Endpoint direction. 809 * @buffering: Number of on-chip buffers related to endpoint. 810 * @buffering_period; Number of on-chip buffers related to periodic endpoint. 811 * @in_ctx: Pointer to input endpoint context structure. 812 * @out_ctx: Pointer to output endpoint context structure. 813 * @ring: Pointer to transfer ring. 814 * @stream_info: Hold stream information. 815 * @ep_state: Current state of endpoint. 816 * @skip: Sometimes the controller can not process isochronous endpoint ring 817 * quickly enough, and it will miss some isoc tds on the ring and 818 * generate Missed Service Error Event. 819 * Set skip flag when receive a Missed Service Error Event and 820 * process the missed tds on the endpoint ring. 821 * @wa1_nop_trb: hold pointer to NOP trb. 822 */ 823struct cdnsp_ep { 824 struct usb_ep endpoint; 825 struct list_head pending_list; 826 struct cdnsp_device *pdev; 827 u8 number; 828 u8 idx; 829 u32 interval; 830 char name[20]; 831 u8 direction; 832 u8 buffering; 833 u8 buffering_period; 834 struct cdnsp_ep_ctx *in_ctx; 835 struct cdnsp_ep_ctx *out_ctx; 836 struct cdnsp_ring *ring; 837 struct cdnsp_stream_info stream_info; 838 unsigned int ep_state; 839#define EP_ENABLED BIT(0) 840#define EP_DIS_IN_RROGRESS BIT(1) 841#define EP_HALTED BIT(2) 842#define EP_STOPPED BIT(3) 843#define EP_WEDGE BIT(4) 844#define EP0_HALTED_STATUS BIT(5) 845#define EP_HAS_STREAMS BIT(6) 846#define EP_UNCONFIGURED BIT(7) 847 848 bool skip; 849 union cdnsp_trb *wa1_nop_trb; 850 851}; 852 853/** 854 * struct cdnsp_device_context_array 855 * @dev_context_ptr: Array of 64-bit DMA addresses for device contexts. 856 * @dma: DMA address for device contexts structure. 857 */ 858struct cdnsp_device_context_array { 859 __le64 dev_context_ptrs[CDNSP_DEV_MAX_SLOTS + 1]; 860 dma_addr_t dma; 861}; 862 863/** 864 * struct cdnsp_transfer_event. 865 * @buffer: 64-bit buffer address, or immediate data. 866 * @transfer_len: Data length transferred. 867 * @flags: Field is interpreted differently based on the type of TRB. 868 */ 869struct cdnsp_transfer_event { 870 __le64 buffer; 871 __le32 transfer_len; 872 __le32 flags; 873}; 874 875/* Invalidate event after disabling endpoint. */ 876#define TRB_EVENT_INVALIDATE 8 877 878/* Transfer event TRB length bit mask. */ 879/* bits 0:23 */ 880#define EVENT_TRB_LEN(p) ((p) & GENMASK(23, 0)) 881/* Completion Code - only applicable for some types of TRBs */ 882#define COMP_CODE_MASK (0xff << 24) 883#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 884#define COMP_INVALID 0 885#define COMP_SUCCESS 1 886#define COMP_DATA_BUFFER_ERROR 2 887#define COMP_BABBLE_DETECTED_ERROR 3 888#define COMP_TRB_ERROR 5 889#define COMP_RESOURCE_ERROR 7 890#define COMP_NO_SLOTS_AVAILABLE_ERROR 9 891#define COMP_INVALID_STREAM_TYPE_ERROR 10 892#define COMP_SLOT_NOT_ENABLED_ERROR 11 893#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 894#define COMP_SHORT_PACKET 13 895#define COMP_RING_UNDERRUN 14 896#define COMP_RING_OVERRUN 15 897#define COMP_VF_EVENT_RING_FULL_ERROR 16 898#define COMP_PARAMETER_ERROR 17 899#define COMP_CONTEXT_STATE_ERROR 19 900#define COMP_EVENT_RING_FULL_ERROR 21 901#define COMP_INCOMPATIBLE_DEVICE_ERROR 22 902#define COMP_MISSED_SERVICE_ERROR 23 903#define COMP_COMMAND_RING_STOPPED 24 904#define COMP_COMMAND_ABORTED 25 905#define COMP_STOPPED 26 906#define COMP_STOPPED_LENGTH_INVALID 27 907#define COMP_STOPPED_SHORT_PACKET 28 908#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 909#define COMP_ISOCH_BUFFER_OVERRUN 31 910#define COMP_EVENT_LOST_ERROR 32 911#define COMP_UNDEFINED_ERROR 33 912#define COMP_INVALID_STREAM_ID_ERROR 34 913 914/*Transfer Event NRDY bit fields */ 915#define TRB_TO_DEV_STREAM(p) ((p) & GENMASK(16, 0)) 916#define TRB_TO_HOST_STREAM(p) ((p) & GENMASK(16, 0)) 917#define STREAM_PRIME_ACK 0xFFFE 918#define STREAM_REJECTED 0xFFFF 919 920/** Transfer Event bit fields **/ 921#define TRB_TO_EP_ID(p) (((p) & GENMASK(20, 16)) >> 16) 922 923/** 924 * struct cdnsp_link_trb 925 * @segment_ptr: 64-bit segment pointer. 926 * @intr_target: Interrupter target. 927 * @control: Flags. 928 */ 929struct cdnsp_link_trb { 930 __le64 segment_ptr; 931 __le32 intr_target; 932 __le32 control; 933}; 934 935/* control bitfields */ 936#define LINK_TOGGLE BIT(1) 937 938/** 939 * struct cdnsp_event_cmd - Command completion event TRB. 940 * cmd_trb: Pointer to command TRB, or the value passed by the event data trb 941 * status: Command completion parameters and error code. 942 * flags: Flags. 943 */ 944struct cdnsp_event_cmd { 945 __le64 cmd_trb; 946 __le32 status; 947 __le32 flags; 948}; 949 950/* flags bitmasks */ 951 952/* Address device - disable SetAddress. */ 953#define TRB_BSR BIT(9) 954 955/* Configure Endpoint - Deconfigure. */ 956#define TRB_DC BIT(9) 957 958/* Force Header */ 959#define TRB_FH_TO_PACKET_TYPE(p) ((p) & GENMASK(4, 0)) 960#define TRB_FH_TR_PACKET 0x4 961#define TRB_FH_TO_DEVICE_ADDRESS(p) (((p) << 25) & GENMASK(31, 25)) 962#define TRB_FH_TR_PACKET_DEV_NOT 0x6 963#define TRB_FH_TO_NOT_TYPE(p) (((p) << 4) & GENMASK(7, 4)) 964#define TRB_FH_TR_PACKET_FUNCTION_WAKE 0x1 965#define TRB_FH_TO_INTERFACE(p) (((p) << 8) & GENMASK(15, 8)) 966 967enum cdnsp_setup_dev { 968 SETUP_CONTEXT_ONLY, 969 SETUP_CONTEXT_ADDRESS, 970}; 971 972/* bits 24:31 are the slot ID. */ 973#define TRB_TO_SLOT_ID(p) (((p) & GENMASK(31, 24)) >> 24) 974#define SLOT_ID_FOR_TRB(p) (((p) << 24) & GENMASK(31, 24)) 975 976/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB. */ 977#define TRB_TO_EP_INDEX(p) (((p) >> 16) & 0x1f) 978 979#define EP_ID_FOR_TRB(p) ((((p) + 1) << 16) & GENMASK(20, 16)) 980 981#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 982#define TRB_TO_SUSPEND_PORT(p) (((p) >> 23) & 0x1) 983#define LAST_EP_INDEX 30 984 985/* Set TR Dequeue Pointer command TRB fields. */ 986#define TRB_TO_STREAM_ID(p) ((((p) & GENMASK(31, 16)) >> 16)) 987#define STREAM_ID_FOR_TRB(p) ((((p)) << 16) & GENMASK(31, 16)) 988#define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 989 990/* 991 * Halt Endpoint Command TRB field. 992 * The ESP bit only exists in the SSP2 controller. 993 */ 994#define TRB_ESP BIT(9) 995 996/* Link TRB specific fields. */ 997#define TRB_TC BIT(1) 998 999/* Port Status Change Event TRB fields. */ 1000/* Port ID - bits 31:24. */ 1001#define GET_PORT_ID(p) (((p) & GENMASK(31, 24)) >> 24) 1002#define SET_PORT_ID(p) (((p) << 24) & GENMASK(31, 24)) 1003#define EVENT_DATA BIT(2) 1004 1005/* Normal TRB fields. */ 1006/* transfer_len bitmasks - bits 0:16. */ 1007#define TRB_LEN(p) ((p) & GENMASK(16, 0)) 1008/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31). */ 1009#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1010#define GET_TD_SIZE(p) (((p) & GENMASK(21, 17)) >> 17) 1011/* 1012 * Controller uses the TD_SIZE field for TBC if Extended TBC 1013 * is enabled (ETE). 1014 */ 1015#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1016/* Interrupter Target - which MSI-X vector to target the completion event at. */ 1017#define TRB_INTR_TARGET(p) (((p) << 22) & GENMASK(31, 22)) 1018#define GET_INTR_TARGET(p) (((p) & GENMASK(31, 22)) >> 22) 1019/* 1020 * Total burst count field, Rsvdz on controller with Extended TBC 1021 * enabled (ETE). 1022 */ 1023#define TRB_TBC(p) (((p) & 0x3) << 7) 1024#define TRB_TLBPC(p) (((p) & 0xf) << 16) 1025 1026/* Cycle bit - indicates TRB ownership by driver or driver.*/ 1027#define TRB_CYCLE BIT(0) 1028/* 1029 * Force next event data TRB to be evaluated before task switch. 1030 * Used to pass OS data back after a TD completes. 1031 */ 1032#define TRB_ENT BIT(1) 1033/* Interrupt on short packet. */ 1034#define TRB_ISP BIT(2) 1035/* Set PCIe no snoop attribute. */ 1036#define TRB_NO_SNOOP BIT(3) 1037/* Chain multiple TRBs into a TD. */ 1038#define TRB_CHAIN BIT(4) 1039/* Interrupt on completion. */ 1040#define TRB_IOC BIT(5) 1041/* The buffer pointer contains immediate data. */ 1042#define TRB_IDT BIT(6) 1043/* 0 - NRDY during data stage, 1 - NRDY during status stage (only control). */ 1044#define TRB_STAT BIT(7) 1045/* Block Event Interrupt. */ 1046#define TRB_BEI BIT(9) 1047 1048/* Control transfer TRB specific fields. */ 1049#define TRB_DIR_IN BIT(16) 1050 1051/* TRB bit mask in Data Stage TRB */ 1052#define TRB_SETUPID_BITMASK GENMASK(9, 8) 1053#define TRB_SETUPID(p) ((p) << 8) 1054#define TRB_SETUPID_TO_TYPE(p) (((p) & TRB_SETUPID_BITMASK) >> 8) 1055 1056#define TRB_SETUP_SPEEDID_USB3 0x1 1057#define TRB_SETUP_SPEEDID_USB2 0x0 1058#define TRB_SETUP_SPEEDID(p) ((p) & (1 << 7)) 1059 1060#define TRB_SETUPSTAT_ACK 0x1 1061#define TRB_SETUPSTAT_STALL 0x0 1062#define TRB_SETUPSTAT(p) ((p) << 6) 1063 1064/* Isochronous TRB specific fields */ 1065#define TRB_SIA BIT(31) 1066#define TRB_FRAME_ID(p) (((p) << 20) & GENMASK(30, 20)) 1067 1068struct cdnsp_generic_trb { 1069 __le32 field[4]; 1070}; 1071 1072union cdnsp_trb { 1073 struct cdnsp_link_trb link; 1074 struct cdnsp_transfer_event trans_event; 1075 struct cdnsp_event_cmd event_cmd; 1076 struct cdnsp_generic_trb generic; 1077}; 1078 1079/* TRB bit mask. */ 1080#define TRB_TYPE_BITMASK GENMASK(15, 10) 1081#define TRB_TYPE(p) ((p) << 10) 1082#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1083 1084/* TRB type IDs. */ 1085/* bulk, interrupt, isoc scatter/gather, and control data stage. */ 1086#define TRB_NORMAL 1 1087/* Setup Stage for control transfers. */ 1088#define TRB_SETUP 2 1089/* Data Stage for control transfers. */ 1090#define TRB_DATA 3 1091/* Status Stage for control transfers. */ 1092#define TRB_STATUS 4 1093/* ISOC transfers. */ 1094#define TRB_ISOC 5 1095/* TRB for linking ring segments. */ 1096#define TRB_LINK 6 1097#define TRB_EVENT_DATA 7 1098/* Transfer Ring No-op (not for the command ring). */ 1099#define TRB_TR_NOOP 8 1100 1101/* Command TRBs */ 1102/* Enable Slot Command. */ 1103#define TRB_ENABLE_SLOT 9 1104/* Disable Slot Command. */ 1105#define TRB_DISABLE_SLOT 10 1106/* Address Device Command. */ 1107#define TRB_ADDR_DEV 11 1108/* Configure Endpoint Command. */ 1109#define TRB_CONFIG_EP 12 1110/* Evaluate Context Command. */ 1111#define TRB_EVAL_CONTEXT 13 1112/* Reset Endpoint Command. */ 1113#define TRB_RESET_EP 14 1114/* Stop Transfer Ring Command. */ 1115#define TRB_STOP_RING 15 1116/* Set Transfer Ring Dequeue Pointer Command. */ 1117#define TRB_SET_DEQ 16 1118/* Reset Device Command. */ 1119#define TRB_RESET_DEV 17 1120/* Force Event Command (opt). */ 1121#define TRB_FORCE_EVENT 18 1122/* Force Header Command - generate a transaction or link management packet. */ 1123#define TRB_FORCE_HEADER 22 1124/* No-op Command - not for transfer rings. */ 1125#define TRB_CMD_NOOP 23 1126/* TRB IDs 24-31 reserved. */ 1127 1128/* Event TRBS. */ 1129/* Transfer Event. */ 1130#define TRB_TRANSFER 32 1131/* Command Completion Event. */ 1132#define TRB_COMPLETION 33 1133/* Port Status Change Event. */ 1134#define TRB_PORT_STATUS 34 1135/* Device Controller Event. */ 1136#define TRB_HC_EVENT 37 1137/* MFINDEX Wrap Event - microframe counter wrapped. */ 1138#define TRB_MFINDEX_WRAP 39 1139/* TRB IDs 40-47 reserved. */ 1140/* Endpoint Not Ready Event. */ 1141#define TRB_ENDPOINT_NRDY 48 1142/* TRB IDs 49-53 reserved. */ 1143/* Halt Endpoint Command. */ 1144#define TRB_HALT_ENDPOINT 54 1145/* Doorbell Overflow Event. */ 1146#define TRB_DRB_OVERFLOW 57 1147 1148#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1149#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1150 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1151#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1152 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1153 1154/* 1155 * TRBS_PER_SEGMENT must be a multiple of 4. 1156 * The command ring is 64-byte aligned, so it must also be greater than 16. 1157 */ 1158#define TRBS_PER_SEGMENT 256 1159#define TRBS_PER_EVENT_SEGMENT 256 1160#define TRBS_PER_EV_DEQ_UPDATE 100 1161#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT * 16) 1162#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1163/* TRB buffer pointers can't cross 64KB boundaries. */ 1164#define TRB_MAX_BUFF_SHIFT 16 1165#define TRB_MAX_BUFF_SIZE BIT(TRB_MAX_BUFF_SHIFT) 1166/* How much data is left before the 64KB boundary? */ 1167#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1168 ((addr) & (TRB_MAX_BUFF_SIZE - 1))) 1169 1170/** 1171 * struct cdnsp_segment - segment related data. 1172 * @trbs: Array of Transfer Request Blocks. 1173 * @next: Pointer to the next segment. 1174 * @dma: DMA address of current segment. 1175 * @bounce_dma: Bounce buffer DMA address . 1176 * @bounce_buf: Bounce buffer virtual address. 1177 * bounce_offs: Bounce buffer offset. 1178 * bounce_len: Bounce buffer length. 1179 */ 1180struct cdnsp_segment { 1181 union cdnsp_trb *trbs; 1182 struct cdnsp_segment *next; 1183 dma_addr_t dma; 1184 /* Max packet sized bounce buffer for td-fragmant alignment */ 1185 dma_addr_t bounce_dma; 1186 void *bounce_buf; 1187 unsigned int bounce_offs; 1188 unsigned int bounce_len; 1189}; 1190 1191/** 1192 * struct cdnsp_td - Transfer Descriptor object. 1193 * @td_list: Used for binding TD with ep_ring->td_list. 1194 * @preq: Request associated with this TD 1195 * @start_seg: Segment containing the first_trb in TD. 1196 * @first_trb: First TRB for this TD. 1197 * @last_trb: Last TRB related with TD. 1198 * @bounce_seg: Bounce segment for this TD. 1199 * @request_length_set: actual_length of the request has already been set. 1200 * @drbl - TD has been added to HW scheduler - only for stream capable 1201 * endpoints. 1202 */ 1203struct cdnsp_td { 1204 struct list_head td_list; 1205 struct cdnsp_request *preq; 1206 struct cdnsp_segment *start_seg; 1207 union cdnsp_trb *first_trb; 1208 union cdnsp_trb *last_trb; 1209 struct cdnsp_segment *bounce_seg; 1210 bool request_length_set; 1211 bool drbl; 1212}; 1213 1214/** 1215 * struct cdnsp_dequeue_state - New dequeue pointer for Transfer Ring. 1216 * @new_deq_seg: New dequeue segment. 1217 * @new_deq_ptr: New dequeue pointer. 1218 * @new_cycle_state: New cycle state. 1219 * @stream_id: stream id for which new dequeue pointer has been selected. 1220 */ 1221struct cdnsp_dequeue_state { 1222 struct cdnsp_segment *new_deq_seg; 1223 union cdnsp_trb *new_deq_ptr; 1224 int new_cycle_state; 1225 unsigned int stream_id; 1226}; 1227 1228enum cdnsp_ring_type { 1229 TYPE_CTRL = 0, 1230 TYPE_ISOC, 1231 TYPE_BULK, 1232 TYPE_INTR, 1233 TYPE_STREAM, 1234 TYPE_COMMAND, 1235 TYPE_EVENT, 1236}; 1237 1238/** 1239 * struct cdnsp_ring - information describing transfer, command or event ring. 1240 * @first_seg: First segment on transfer ring. 1241 * @last_seg: Last segment on transfer ring. 1242 * @enqueue: SW enqueue pointer address. 1243 * @enq_seg: SW enqueue segment address. 1244 * @dequeue: SW dequeue pointer address. 1245 * @deq_seg: SW dequeue segment address. 1246 * @td_list: transfer descriptor list associated with this ring. 1247 * @cycle_state: Current cycle bit. Write the cycle state into the TRB cycle 1248 * field to give ownership of the TRB to the device controller 1249 * (if we are the producer) or to check if we own the TRB 1250 * (if we are the consumer). 1251 * @stream_id: Stream id 1252 * @stream_active: Stream is active - PRIME packet has been detected. 1253 * @stream_rejected: This ring has been rejected by host. 1254 * @num_tds: Number of TDs associated with ring. 1255 * @num_segs: Number of segments. 1256 * @num_trbs_free: Number of free TRBs on the ring. 1257 * @bounce_buf_len: Length of bounce buffer. 1258 * @type: Ring type - event, transfer, or command ring. 1259 * @last_td_was_short - TD is short TD. 1260 * @trb_address_map: For mapping physical TRB addresses to segments in 1261 * stream rings. 1262 */ 1263struct cdnsp_ring { 1264 struct cdnsp_segment *first_seg; 1265 struct cdnsp_segment *last_seg; 1266 union cdnsp_trb *enqueue; 1267 struct cdnsp_segment *enq_seg; 1268 union cdnsp_trb *dequeue; 1269 struct cdnsp_segment *deq_seg; 1270 struct list_head td_list; 1271 u32 cycle_state; 1272 unsigned int stream_id; 1273 unsigned int stream_active; 1274 unsigned int stream_rejected; 1275 int num_tds; 1276 unsigned int num_segs; 1277 unsigned int num_trbs_free; 1278 unsigned int bounce_buf_len; 1279 enum cdnsp_ring_type type; 1280 bool last_td_was_short; 1281 struct radix_tree_root *trb_address_map; 1282}; 1283 1284/** 1285 * struct cdnsp_erst_entry - even ring segment table entry object. 1286 * @seg_addr: 64-bit event ring segment address. 1287 * seg_size: Number of TRBs in segment.; 1288 */ 1289struct cdnsp_erst_entry { 1290 __le64 seg_addr; 1291 __le32 seg_size; 1292 /* Set to zero */ 1293 __le32 rsvd; 1294}; 1295 1296/** 1297 * struct cdnsp_erst - even ring segment table for event ring. 1298 * @entries: Array of event ring segments 1299 * @num_entries: Number of segments in entries array. 1300 * @erst_dma_addr: DMA address for entries array. 1301 */ 1302struct cdnsp_erst { 1303 struct cdnsp_erst_entry *entries; 1304 unsigned int num_entries; 1305 dma_addr_t erst_dma_addr; 1306}; 1307 1308/** 1309 * struct cdnsp_request - extended device side representation of usb_request 1310 * object . 1311 * @td: Transfer descriptor associated with this request. 1312 * @request: Generic usb_request object describing single I/O request. 1313 * @list: Used to adding request to endpoint pending_list. 1314 * @pep: Extended representation of usb_ep object 1315 * @epnum: Endpoint number associated with usb request. 1316 * @direction: Endpoint direction for usb request. 1317 */ 1318struct cdnsp_request { 1319 struct cdnsp_td td; 1320 struct usb_request request; 1321 struct list_head list; 1322 struct cdnsp_ep *pep; 1323 u8 epnum; 1324 unsigned direction:1; 1325}; 1326 1327#define ERST_NUM_SEGS 1 1328 1329/* Stages used during enumeration process.*/ 1330enum cdnsp_ep0_stage { 1331 CDNSP_SETUP_STAGE, 1332 CDNSP_DATA_STAGE, 1333 CDNSP_STATUS_STAGE, 1334}; 1335 1336/** 1337 * struct cdnsp_port - holds information about detected ports. 1338 * @port_num: Port number. 1339 * @exist: Indicate if port exist. 1340 * maj_rev: Major revision. 1341 * min_rev: Minor revision. 1342 */ 1343struct cdnsp_port { 1344 struct cdnsp_port_regs __iomem *regs; 1345 u8 port_num; 1346 u8 exist; 1347 u8 maj_rev; 1348 u8 min_rev; 1349}; 1350 1351#define CDNSP_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 1352#define CDNSP_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 1353#define CDNSP_EXT_PORT_OFF(x) ((x) & 0xff) 1354#define CDNSP_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 1355 1356/** 1357 * struct cdnsp_device - represent USB device. 1358 * @dev: Pointer to device structure associated whit this controller. 1359 * @gadget: Device side representation of the peripheral controller. 1360 * @gadget_driver: Pointer to the gadget driver. 1361 * @irq: IRQ line number used by device side. 1362 * @regs:IO device memory. 1363 * @cap_regs: Capability registers. 1364 * @op_regs: Operational registers. 1365 * @run_regs: Runtime registers. 1366 * @dba: Device base address register. 1367 * @ir_set: Current interrupter register set. 1368 * @port20_regs: Port 2.0 Peripheral Configuration Registers. 1369 * @port3x_regs: USB3.x Port Peripheral Configuration Registers. 1370 * @rev_cap: Controller Capabilities Registers. 1371 * @hcs_params1: Cached register copies of read-only HCSPARAMS1 1372 * @hcc_params: Cached register copies of read-only HCCPARAMS1 1373 * @rtl_revision: Cached controller rtl revision. 1374 * @setup: Temporary buffer for setup packet. 1375 * @ep0_preq: Internal allocated request used during enumeration. 1376 * @ep0_stage: ep0 stage during enumeration process. 1377 * @three_stage_setup: Three state or two state setup. 1378 * @ep0_expect_in: Data IN expected for control transfer. 1379 * @setup_id: Setup identifier. 1380 * @setup_speed - Speed detected for current SETUP packet. 1381 * @setup_buf: Buffer for SETUP packet. 1382 * @device_address: Current device address. 1383 * @may_wakeup: remote wakeup enabled/disabled. 1384 * @lock: Lock used in interrupt thread context. 1385 * @hci_version: device controller version. 1386 * @dcbaa: Device context base address array. 1387 * @cmd_ring: Command ring. 1388 * @cmd: Represent all what is needed to issue command on Command Ring. 1389 * @event_ring: Event ring. 1390 * @erst: Event Ring Segment table 1391 * @slot_id: Current Slot ID. Should be 0 or 1. 1392 * @out_ctx: Output context. 1393 * @in_ctx: Input context. 1394 * @eps: array of endpoints object associated with device. 1395 * @usb2_hw_lpm_capable: hardware lpm is enabled; 1396 * @u1_allowed: Allow device transition to U1 state. 1397 * @u2_allowed: Allow device transition to U2 state 1398 * @device_pool: DMA pool for allocating input and output context. 1399 * @segment_pool: DMA pool for allocating new segments. 1400 * @cdnsp_state: Current state of controller. 1401 * @link_state: Current link state. 1402 * @usb2_port - Port USB 2.0. 1403 * @usb3_port - Port USB 3.0. 1404 * @active_port - Current selected Port. 1405 * @test_mode: selected Test Mode. 1406 */ 1407struct cdnsp_device { 1408 struct device *dev; 1409 struct usb_gadget gadget; 1410 struct usb_gadget_driver *gadget_driver; 1411 unsigned int irq; 1412 void __iomem *regs; 1413 1414 /* Registers map */ 1415 struct cdnsp_cap_regs __iomem *cap_regs; 1416 struct cdnsp_op_regs __iomem *op_regs; 1417 struct cdnsp_run_regs __iomem *run_regs; 1418 struct cdnsp_doorbell_array __iomem *dba; 1419 struct cdnsp_intr_reg __iomem *ir_set; 1420 struct cdnsp_20port_cap __iomem *port20_regs; 1421 struct cdnsp_3xport_cap __iomem *port3x_regs; 1422 struct cdnsp_rev_cap __iomem *rev_cap; 1423 1424 /* Cached register copies of read-only CDNSP data */ 1425 __u32 hcs_params1; 1426 __u32 hcs_params3; 1427 __u32 hcc_params; 1428 #define RTL_REVISION_NEW_LPM 0x2700 1429 __u32 rtl_revision; 1430 /* Lock used in interrupt thread context. */ 1431 spinlock_t lock; 1432 struct usb_ctrlrequest setup; 1433 struct cdnsp_request ep0_preq; 1434 enum cdnsp_ep0_stage ep0_stage; 1435 u8 three_stage_setup; 1436 u8 ep0_expect_in; 1437 u8 setup_id; 1438 u8 setup_speed; 1439 void *setup_buf; 1440 u8 device_address; 1441 int may_wakeup; 1442 u16 hci_version; 1443 1444 /* data structures */ 1445 struct cdnsp_device_context_array *dcbaa; 1446 struct cdnsp_ring *cmd_ring; 1447 struct cdnsp_command cmd; 1448 struct cdnsp_ring *event_ring; 1449 struct cdnsp_erst erst; 1450 int slot_id; 1451 1452 /* 1453 * Commands to the hardware are passed an "input context" that 1454 * tells the hardware what to change in its data structures. 1455 * The hardware will return changes in an "output context" that 1456 * software must allocate for the hardware. . 1457 */ 1458 struct cdnsp_container_ctx out_ctx; 1459 struct cdnsp_container_ctx in_ctx; 1460 struct cdnsp_ep eps[CDNSP_ENDPOINTS_NUM]; 1461 u8 usb2_hw_lpm_capable:1; 1462 u8 u1_allowed:1; 1463 u8 u2_allowed:1; 1464 1465 /* DMA pools */ 1466 struct dma_pool *device_pool; 1467 struct dma_pool *segment_pool; 1468 1469#define CDNSP_STATE_HALTED BIT(1) 1470#define CDNSP_STATE_DYING BIT(2) 1471#define CDNSP_STATE_DISCONNECT_PENDING BIT(3) 1472#define CDNSP_WAKEUP_PENDING BIT(4) 1473 unsigned int cdnsp_state; 1474 unsigned int link_state; 1475 1476 struct cdnsp_port usb2_port; 1477 struct cdnsp_port usb3_port; 1478 struct cdnsp_port *active_port; 1479 u16 test_mode; 1480}; 1481 1482/* 1483 * Registers should always be accessed with double word or quad word accesses. 1484 * 1485 * Registers with 64-bit address pointers should be written to with 1486 * dword accesses by writing the low dword first (ptr[0]), then the high dword 1487 * (ptr[1]) second. controller implementations that do not support 64-bit 1488 * address pointers will ignore the high dword, and write order is irrelevant. 1489 */ 1490static inline u64 cdnsp_read_64(__le64 __iomem *regs) 1491{ 1492 return lo_hi_readq(regs); 1493} 1494 1495static inline void cdnsp_write_64(const u64 val, __le64 __iomem *regs) 1496{ 1497 lo_hi_writeq(val, regs); 1498} 1499 1500/* CDNSP memory management functions. */ 1501void cdnsp_mem_cleanup(struct cdnsp_device *pdev); 1502int cdnsp_mem_init(struct cdnsp_device *pdev); 1503int cdnsp_setup_addressable_priv_dev(struct cdnsp_device *pdev); 1504void cdnsp_copy_ep0_dequeue_into_input_ctx(struct cdnsp_device *pdev); 1505void cdnsp_endpoint_zero(struct cdnsp_device *pdev, struct cdnsp_ep *ep); 1506int cdnsp_endpoint_init(struct cdnsp_device *pdev, 1507 struct cdnsp_ep *pep, 1508 gfp_t mem_flags); 1509int cdnsp_ring_expansion(struct cdnsp_device *pdev, 1510 struct cdnsp_ring *ring, 1511 unsigned int num_trbs, gfp_t flags); 1512struct cdnsp_ring *cdnsp_dma_to_transfer_ring(struct cdnsp_ep *ep, u64 address); 1513int cdnsp_alloc_stream_info(struct cdnsp_device *pdev, 1514 struct cdnsp_ep *pep, 1515 unsigned int num_stream_ctxs, 1516 unsigned int num_streams); 1517int cdnsp_alloc_streams(struct cdnsp_device *pdev, struct cdnsp_ep *pep); 1518void cdnsp_free_endpoint_rings(struct cdnsp_device *pdev, struct cdnsp_ep *pep); 1519 1520/* Device controller glue. */ 1521int cdnsp_find_next_ext_cap(void __iomem *base, u32 start, int id); 1522int cdnsp_halt(struct cdnsp_device *pdev); 1523void cdnsp_died(struct cdnsp_device *pdev); 1524int cdnsp_reset(struct cdnsp_device *pdev); 1525irqreturn_t cdnsp_irq_handler(int irq, void *priv); 1526int cdnsp_setup_device(struct cdnsp_device *pdev, enum cdnsp_setup_dev setup); 1527void cdnsp_set_usb2_hardware_lpm(struct cdnsp_device *usbsssp_data, 1528 struct usb_request *req, int enable); 1529irqreturn_t cdnsp_thread_irq_handler(int irq, void *data); 1530 1531/* Ring, segment, TRB, and TD functions. */ 1532dma_addr_t cdnsp_trb_virt_to_dma(struct cdnsp_segment *seg, 1533 union cdnsp_trb *trb); 1534bool cdnsp_last_trb_on_seg(struct cdnsp_segment *seg, union cdnsp_trb *trb); 1535bool cdnsp_last_trb_on_ring(struct cdnsp_ring *ring, 1536 struct cdnsp_segment *seg, 1537 union cdnsp_trb *trb); 1538int cdnsp_wait_for_cmd_compl(struct cdnsp_device *pdev); 1539void cdnsp_update_erst_dequeue(struct cdnsp_device *pdev, 1540 union cdnsp_trb *event_ring_deq, 1541 u8 clear_ehb); 1542void cdnsp_initialize_ring_info(struct cdnsp_ring *ring); 1543void cdnsp_ring_cmd_db(struct cdnsp_device *pdev); 1544void cdnsp_queue_slot_control(struct cdnsp_device *pdev, u32 trb_type); 1545void cdnsp_queue_address_device(struct cdnsp_device *pdev, 1546 dma_addr_t in_ctx_ptr, 1547 enum cdnsp_setup_dev setup); 1548void cdnsp_queue_stop_endpoint(struct cdnsp_device *pdev, 1549 unsigned int ep_index); 1550int cdnsp_queue_ctrl_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq); 1551int cdnsp_queue_bulk_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq); 1552int cdnsp_queue_isoc_tx(struct cdnsp_device *pdev, 1553 struct cdnsp_request *preq); 1554void cdnsp_queue_configure_endpoint(struct cdnsp_device *pdev, 1555 dma_addr_t in_ctx_ptr); 1556void cdnsp_queue_reset_ep(struct cdnsp_device *pdev, unsigned int ep_index); 1557void cdnsp_queue_halt_endpoint(struct cdnsp_device *pdev, 1558 unsigned int ep_index); 1559void cdnsp_force_header_wakeup(struct cdnsp_device *pdev, int intf_num); 1560void cdnsp_queue_reset_device(struct cdnsp_device *pdev); 1561void cdnsp_queue_new_dequeue_state(struct cdnsp_device *pdev, 1562 struct cdnsp_ep *pep, 1563 struct cdnsp_dequeue_state *deq_state); 1564void cdnsp_ring_doorbell_for_active_rings(struct cdnsp_device *pdev, 1565 struct cdnsp_ep *pep); 1566void cdnsp_inc_deq(struct cdnsp_device *pdev, struct cdnsp_ring *ring); 1567void cdnsp_set_link_state(struct cdnsp_device *pdev, 1568 __le32 __iomem *port_regs, u32 link_state); 1569u32 cdnsp_port_state_to_neutral(u32 state); 1570 1571/* CDNSP device controller contexts. */ 1572int cdnsp_enable_slot(struct cdnsp_device *pdev); 1573int cdnsp_disable_slot(struct cdnsp_device *pdev); 1574struct cdnsp_input_control_ctx 1575 *cdnsp_get_input_control_ctx(struct cdnsp_container_ctx *ctx); 1576struct cdnsp_slot_ctx *cdnsp_get_slot_ctx(struct cdnsp_container_ctx *ctx); 1577struct cdnsp_ep_ctx *cdnsp_get_ep_ctx(struct cdnsp_container_ctx *ctx, 1578 unsigned int ep_index); 1579/* CDNSP gadget interface. */ 1580void cdnsp_suspend_gadget(struct cdnsp_device *pdev); 1581void cdnsp_resume_gadget(struct cdnsp_device *pdev); 1582void cdnsp_disconnect_gadget(struct cdnsp_device *pdev); 1583void cdnsp_gadget_giveback(struct cdnsp_ep *pep, struct cdnsp_request *preq, 1584 int status); 1585int cdnsp_ep_enqueue(struct cdnsp_ep *pep, struct cdnsp_request *preq); 1586int cdnsp_ep_dequeue(struct cdnsp_ep *pep, struct cdnsp_request *preq); 1587unsigned int cdnsp_port_speed(unsigned int port_status); 1588void cdnsp_irq_reset(struct cdnsp_device *pdev); 1589int cdnsp_halt_endpoint(struct cdnsp_device *pdev, 1590 struct cdnsp_ep *pep, int value); 1591int cdnsp_cmd_stop_ep(struct cdnsp_device *pdev, struct cdnsp_ep *pep); 1592void cdnsp_setup_analyze(struct cdnsp_device *pdev); 1593int cdnsp_status_stage(struct cdnsp_device *pdev); 1594int cdnsp_reset_device(struct cdnsp_device *pdev); 1595 1596/** 1597 * next_request - gets the next request on the given list 1598 * @list: the request list to operate on 1599 * 1600 * Caller should take care of locking. This function return NULL or the first 1601 * request available on list. 1602 */ 1603static inline struct cdnsp_request *next_request(struct list_head *list) 1604{ 1605 return list_first_entry_or_null(list, struct cdnsp_request, list); 1606} 1607 1608#define to_cdnsp_ep(ep) (container_of(ep, struct cdnsp_ep, endpoint)) 1609#define gadget_to_cdnsp(g) (container_of(g, struct cdnsp_device, gadget)) 1610#define request_to_cdnsp_request(r) (container_of(r, struct cdnsp_request, \ 1611 request)) 1612#define to_cdnsp_request(r) (container_of(r, struct cdnsp_request, request)) 1613int cdnsp_remove_request(struct cdnsp_device *pdev, struct cdnsp_request *preq, 1614 struct cdnsp_ep *pep); 1615 1616#endif /* __LINUX_CDNSP_GADGET_H */
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