ufshcd-dwc.h

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * UFS Host driver for Synopsys Designware Core
 4 *
 5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
 6 *
 7 * Authors: Joao Pinto <jpinto@synopsys.com>
 8 */
 9
10#ifndef _UFSHCD_DWC_H
11#define _UFSHCD_DWC_H
12
13#include <ufs/ufshcd.h>
14
15/* RMMI Attributes */
16#define CBREFCLKCTRL2		0x8132
17#define CBCRCTRL		0x811F
18#define CBC10DIRECTCONF2	0x810E
19#define CBRATESEL		0x8114
20#define CBCREGADDRLSB		0x8116
21#define CBCREGADDRMSB		0x8117
22#define CBCREGWRLSB		0x8118
23#define CBCREGWRMSB		0x8119
24#define CBCREGRDLSB		0x811A
25#define CBCREGRDMSB		0x811B
26#define CBCREGRDWRSEL		0x811C
27
28#define CBREFREFCLK_GATE_OVR_EN		BIT(7)
29
30/* M-PHY Attributes */
31#define MTX_FSM_STATE		0x41
32#define MRX_FSM_STATE		0xC1
33
34/* M-PHY registers */
35#define RX_OVRD_IN_1(n)		(0x3006 + ((n) * 0x100))
36#define RX_PCS_OUT(n)		(0x300F + ((n) * 0x100))
37#define FAST_FLAGS(n)		(0x401C + ((n) * 0x100))
38#define RX_AFE_ATT_IDAC(n)	(0x4000 + ((n) * 0x100))
39#define RX_AFE_CTLE_IDAC(n)	(0x4001 + ((n) * 0x100))
40#define FW_CALIB_CCFG(n)	(0x404D + ((n) * 0x100))
41
42/* Tx/Rx FSM state */
43enum rx_fsm_state {
44	RX_STATE_DISABLED = 0,
45	RX_STATE_HIBERN8 = 1,
46	RX_STATE_SLEEP = 2,
47	RX_STATE_STALL = 3,
48	RX_STATE_LSBURST = 4,
49	RX_STATE_HSBURST = 5,
50};
51
52enum tx_fsm_state {
53	TX_STATE_DISABLED = 0,
54	TX_STATE_HIBERN8 = 1,
55	TX_STATE_SLEEP = 2,
56	TX_STATE_STALL = 3,
57	TX_STATE_LSBURST = 4,
58	TX_STATE_HSBURST = 5,
59};
60
61struct ufshcd_dme_attr_val {
62	u32 attr_sel;
63	u32 mib_val;
64	u8 peer;
65};
66
67int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
68					enum ufs_notify_change_status status);
69int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
70				const struct ufshcd_dme_attr_val *v, int n);
71#endif /* End of Header */