ufs-rockchip.h

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Rockchip UFS Host Controller driver
 4 *
 5 * Copyright (C) 2025 Rockchip Electronics Co., Ltd.
 6 */
 7
 8#ifndef _UFS_ROCKCHIP_H_
 9#define _UFS_ROCKCHIP_H_
10
11#define SEL_TX_LANE0 0x0
12#define SEL_TX_LANE1 0x1
13#define SEL_TX_LANE2 0x2
14#define SEL_TX_LANE3 0x3
15#define SEL_RX_LANE0 0x4
16#define SEL_RX_LANE1 0x5
17#define SEL_RX_LANE2 0x6
18#define SEL_RX_LANE3 0x7
19
20#define VND_TX_CLK_PRD                  0xAA
21#define VND_TX_CLK_PRD_EN               0xA9
22#define VND_TX_LINERESET_PVALUE2        0xAB
23#define VND_TX_LINERESET_PVALUE1        0xAC
24#define VND_TX_LINERESET_VALUE          0xAD
25#define VND_TX_BASE_NVALUE              0x93
26#define VND_TX_TASE_VALUE               0x94
27#define VND_TX_POWER_SAVING_CTRL        0x7F
28#define VND_RX_CLK_PRD                  0x12
29#define VND_RX_CLK_PRD_EN               0x11
30#define VND_RX_LINERESET_PVALUE2        0x1B
31#define VND_RX_LINERESET_PVALUE1        0x1C
32#define VND_RX_LINERESET_VALUE          0x1D
33#define VND_RX_LINERESET_OPTION         0x25
34#define VND_RX_POWER_SAVING_CTRL        0x2F
35#define VND_RX_SAVE_DET_CTRL            0x1E
36
37#define CMN_REG23                       0x8C
38#define CMN_REG25                       0x94
39#define TRSV0_REG08                     0xE0
40#define TRSV1_REG08                     0x220
41#define TRSV0_REG14                     0x110
42#define TRSV1_REG14                     0x250
43#define TRSV0_REG15                     0x134
44#define TRSV1_REG15                     0x274
45#define TRSV0_REG16                     0x128
46#define TRSV1_REG16                     0x268
47#define TRSV0_REG17                     0x12C
48#define TRSV1_REG17                     0x26c
49#define TRSV0_REG18                     0x120
50#define TRSV1_REG18                     0x260
51#define TRSV0_REG29                     0x164
52#define TRSV1_REG29                     0x2A4
53#define TRSV0_REG2E                     0x178
54#define TRSV1_REG2E                     0x2B8
55#define TRSV0_REG3C                     0x1B0
56#define TRSV1_REG3C                     0x2F0
57#define TRSV0_REG3D                     0x1B4
58#define TRSV1_REG3D                     0x2F4
59
60#define MPHY_CFG                        0x200
61#define MPHY_CFG_ENABLE                 0x40
62#define MPHY_CFG_DISABLE                0x0
63
64#define MIB_T_DBG_CPORT_TX_ENDIAN       0xc022
65#define MIB_T_DBG_CPORT_RX_ENDIAN       0xc023
66
67struct ufs_rockchip_host {
68	struct ufs_hba *hba;
69	void __iomem *ufs_phy_ctrl;
70	void __iomem *ufs_sys_ctrl;
71	void __iomem *mphy_base;
72	struct gpio_desc *rst_gpio;
73	struct reset_control *rst;
74	struct clk *ref_out_clk;
75	struct clk_bulk_data *clks;
76	uint64_t caps;
77};
78
79#define ufs_sys_writel(base, val, reg)                                    \
80	writel((val), (base) + (reg))
81#define ufs_sys_readl(base, reg) readl((base) + (reg))
82#define ufs_sys_set_bits(base, mask, reg)                                 \
83	ufs_sys_writel(                                                   \
84		(base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg))
85#define ufs_sys_ctrl_clr_bits(base, mask, reg)                                 \
86	ufs_sys_writel((base),                                            \
87			    ((~(mask)) & (ufs_sys_readl((base), (reg)))), \
88			    (reg))
89
90#endif /* _UFS_ROCKCHIP_H_ */