ufs-rockchip.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Rockchip UFS Host Controller driver
  4 *
  5 * Copyright (C) 2025 Rockchip Electronics Co., Ltd.
  6 */
  7
  8#include <linux/clk.h>
  9#include <linux/gpio.h>
 10#include <linux/gpio/consumer.h>
 11#include <linux/mfd/syscon.h>
 12#include <linux/of.h>
 13#include <linux/platform_device.h>
 14#include <linux/pm_domain.h>
 15#include <linux/pm_wakeup.h>
 16#include <linux/regmap.h>
 17#include <linux/reset.h>
 18
 19#include <ufs/ufshcd.h>
 20#include <ufs/unipro.h>
 21#include "ufshcd-pltfrm.h"
 22#include "ufs-rockchip.h"
 23
 24static void ufs_rockchip_controller_reset(struct ufs_rockchip_host *host)
 25{
 26	reset_control_assert(host->rst);
 27	udelay(1);
 28	reset_control_deassert(host->rst);
 29}
 30
 31static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
 32					 enum ufs_notify_change_status status)
 33{
 34	struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
 35	int err = 0;
 36
 37	if (status == POST_CHANGE) {
 38		err = ufshcd_dme_reset(hba);
 39		if (err)
 40			return err;
 41
 42		err = ufshcd_dme_enable(hba);
 43		if (err)
 44			return err;
 45
 46		return ufshcd_vops_phy_initialization(hba);
 47	}
 48
 49	/* PRE_CHANGE */
 50	ufs_rockchip_controller_reset(host);
 51
 52	return 0;
 53}
 54
 55static void ufs_rockchip_set_pm_lvl(struct ufs_hba *hba)
 56{
 57	hba->rpm_lvl = UFS_PM_LVL_5;
 58	hba->spm_lvl = UFS_PM_LVL_5;
 59}
 60
 61static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
 62{
 63	struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
 64
 65	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
 66	/* enable the mphy DME_SET cfg */
 67	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_ENABLE);
 68	for (int i = 0; i < 2; i++) {
 69		/* Configuration M - TX */
 70		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, SEL_TX_LANE0 + i), 0x06);
 71		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, SEL_TX_LANE0 + i), 0x02);
 72		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_VALUE, SEL_TX_LANE0 + i), 0x44);
 73		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, SEL_TX_LANE0 + i), 0xe6);
 74		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, SEL_TX_LANE0 + i), 0x07);
 75		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_TASE_VALUE, SEL_TX_LANE0 + i), 0x93);
 76		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_BASE_NVALUE, SEL_TX_LANE0 + i), 0xc9);
 77		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_POWER_SAVING_CTRL, SEL_TX_LANE0 + i), 0x00);
 78		/* Configuration M - RX */
 79		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, SEL_RX_LANE0 + i), 0x06);
 80		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, SEL_RX_LANE0 + i), 0x00);
 81		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE, SEL_RX_LANE0 + i), 0x58);
 82		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE1, SEL_RX_LANE0 + i), 0x8c);
 83		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE2, SEL_RX_LANE0 + i), 0x02);
 84		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_OPTION, SEL_RX_LANE0 + i), 0xf6);
 85		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_POWER_SAVING_CTRL, SEL_RX_LANE0 + i), 0x69);
 86	}
 87
 88	/* disable the mphy DME_SET cfg */
 89	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_DISABLE);
 90
 91	ufs_sys_writel(host->mphy_base, 0x80, CMN_REG23);
 92	ufs_sys_writel(host->mphy_base, 0xB5, TRSV0_REG14);
 93	ufs_sys_writel(host->mphy_base, 0xB5, TRSV1_REG14);
 94
 95	ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG15);
 96	ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG15);
 97
 98	ufs_sys_writel(host->mphy_base, 0x38, TRSV0_REG08);
 99	ufs_sys_writel(host->mphy_base, 0x38, TRSV1_REG08);
100
101	ufs_sys_writel(host->mphy_base, 0x50, TRSV0_REG29);
102	ufs_sys_writel(host->mphy_base, 0x50, TRSV1_REG29);
103
104	ufs_sys_writel(host->mphy_base, 0x80, TRSV0_REG2E);
105	ufs_sys_writel(host->mphy_base, 0x80, TRSV1_REG2E);
106
107	ufs_sys_writel(host->mphy_base, 0x18, TRSV0_REG3C);
108	ufs_sys_writel(host->mphy_base, 0x18, TRSV1_REG3C);
109
110	ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG16);
111	ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG16);
112
113	ufs_sys_writel(host->mphy_base, 0x20, TRSV0_REG17);
114	ufs_sys_writel(host->mphy_base, 0x20, TRSV1_REG17);
115
116	ufs_sys_writel(host->mphy_base, 0xC0, TRSV0_REG18);
117	ufs_sys_writel(host->mphy_base, 0xC0, TRSV1_REG18);
118
119	ufs_sys_writel(host->mphy_base, 0x03, CMN_REG25);
120
121	ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG3D);
122	ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG3D);
123
124	ufs_sys_writel(host->mphy_base, 0xC0, CMN_REG23);
125	udelay(1);
126	ufs_sys_writel(host->mphy_base, 0x00, CMN_REG23);
127
128	usleep_range(200, 250);
129	/* start link up */
130	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
131	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
132	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
133	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
134	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
135	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
136
137	return 0;
138}
139
140static int ufs_rockchip_common_init(struct ufs_hba *hba)
141{
142	struct device *dev = hba->dev;
143	struct platform_device *pdev = to_platform_device(dev);
144	struct ufs_rockchip_host *host;
145	int err;
146
147	host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
148	if (!host)
149		return -ENOMEM;
150
151	host->ufs_sys_ctrl = devm_platform_ioremap_resource_byname(pdev, "hci_grf");
152	if (IS_ERR(host->ufs_sys_ctrl))
153		return dev_err_probe(dev, PTR_ERR(host->ufs_sys_ctrl),
154				"Failed to map HCI system control registers\n");
155
156	host->ufs_phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "mphy_grf");
157	if (IS_ERR(host->ufs_phy_ctrl))
158		return dev_err_probe(dev, PTR_ERR(host->ufs_phy_ctrl),
159				"Failed to map mphy system control registers\n");
160
161	host->mphy_base = devm_platform_ioremap_resource_byname(pdev, "mphy");
162	if (IS_ERR(host->mphy_base))
163		return dev_err_probe(dev, PTR_ERR(host->mphy_base),
164				"Failed to map mphy base registers\n");
165
166	host->rst = devm_reset_control_array_get_exclusive(dev);
167	if (IS_ERR(host->rst))
168		return dev_err_probe(dev, PTR_ERR(host->rst),
169				"failed to get reset control\n");
170
171	ufs_rockchip_controller_reset(host);
172
173	host->ref_out_clk = devm_clk_get_enabled(dev, "ref_out");
174	if (IS_ERR(host->ref_out_clk))
175		return dev_err_probe(dev, PTR_ERR(host->ref_out_clk),
176				"ref_out clock unavailable\n");
177
178	host->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
179	if (IS_ERR(host->rst_gpio))
180		return dev_err_probe(dev, PTR_ERR(host->rst_gpio),
181				"failed to get reset gpio\n");
182
183	err = devm_clk_bulk_get_all_enabled(dev, &host->clks);
184	if (err < 0)
185		return dev_err_probe(dev, err, "failed to enable clocks\n");
186
187	host->hba = hba;
188
189	ufshcd_set_variant(hba, host);
190
191	return 0;
192}
193
194static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
195{
196	struct device *dev = hba->dev;
197	int ret;
198
199	hba->quirks = UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;
200
201	/* Enable BKOPS when suspend */
202	hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
203	/* Enable putting device into deep sleep */
204	hba->caps |= UFSHCD_CAP_DEEPSLEEP;
205	/* Enable devfreq of UFS */
206	hba->caps |= UFSHCD_CAP_CLK_SCALING;
207	/* Enable WriteBooster */
208	hba->caps |= UFSHCD_CAP_WB_EN;
209
210	/* Set the default desired pm level in case no users set via sysfs */
211	ufs_rockchip_set_pm_lvl(hba);
212
213	ret = ufs_rockchip_common_init(hba);
214	if (ret)
215		return dev_err_probe(dev, ret, "ufs common init fail\n");
216
217	return 0;
218}
219
220static int ufs_rockchip_device_reset(struct ufs_hba *hba)
221{
222	struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
223
224	gpiod_set_value_cansleep(host->rst_gpio, 1);
225	usleep_range(20, 25);
226
227	gpiod_set_value_cansleep(host->rst_gpio, 0);
228	usleep_range(20, 25);
229
230	return 0;
231}
232
233static const struct ufs_hba_variant_ops ufs_hba_rk3576_vops = {
234	.name = "rk3576",
235	.init = ufs_rockchip_rk3576_init,
236	.device_reset = ufs_rockchip_device_reset,
237	.hce_enable_notify = ufs_rockchip_hce_enable_notify,
238	.phy_initialization = ufs_rockchip_rk3576_phy_init,
239};
240
241static const struct of_device_id ufs_rockchip_of_match[] = {
242	{ .compatible = "rockchip,rk3576-ufshc", .data = &ufs_hba_rk3576_vops },
243	{ },
244};
245MODULE_DEVICE_TABLE(of, ufs_rockchip_of_match);
246
247static int ufs_rockchip_probe(struct platform_device *pdev)
248{
249	struct device *dev = &pdev->dev;
250	const struct ufs_hba_variant_ops *vops;
251	int err;
252
253	vops = device_get_match_data(dev);
254	if (!vops)
255		return dev_err_probe(dev, -ENODATA, "ufs_hba_variant_ops not defined.\n");
256
257	err = ufshcd_pltfrm_init(pdev, vops);
258	if (err)
259		return dev_err_probe(dev, err, "ufshcd_pltfrm_init failed\n");
260
261	return 0;
262}
263
264static void ufs_rockchip_remove(struct platform_device *pdev)
265{
266	ufshcd_pltfrm_remove(pdev);
267}
268
269#ifdef CONFIG_PM
270static int ufs_rockchip_runtime_suspend(struct device *dev)
271{
272	struct ufs_hba *hba = dev_get_drvdata(dev);
273	struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
274
275	clk_disable_unprepare(host->ref_out_clk);
276
277	/* Do not power down the genpd if rpm_lvl is less than level 5 */
278	dev_pm_genpd_rpm_always_on(dev, hba->rpm_lvl < UFS_PM_LVL_5);
279
280	return ufshcd_runtime_suspend(dev);
281}
282
283static int ufs_rockchip_runtime_resume(struct device *dev)
284{
285	struct ufs_hba *hba = dev_get_drvdata(dev);
286	struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
287	int err;
288
289	err = clk_prepare_enable(host->ref_out_clk);
290	if (err) {
291		dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
292		return err;
293	}
294
295	ufs_rockchip_controller_reset(host);
296
297	return ufshcd_runtime_resume(dev);
298}
299#endif
300
301#ifdef CONFIG_PM_SLEEP
302static int ufs_rockchip_system_suspend(struct device *dev)
303{
304	struct ufs_hba *hba = dev_get_drvdata(dev);
305	struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
306	int err;
307
308	/*
309	 * If spm_lvl is less than level 5, it means we need to keep the host
310	 * controller in powered-on state. So device_set_awake_path() is
311	 * calling pm core to notify the genpd provider to meet this requirement
312	 */
313	if (hba->spm_lvl < UFS_PM_LVL_5)
314		device_set_awake_path(dev);
315
316	err = ufshcd_system_suspend(dev);
317	if (err) {
318		dev_err(hba->dev, "UFSHCD system suspend failed %d\n", err);
319		return err;
320	}
321
322	clk_disable_unprepare(host->ref_out_clk);
323
324	return 0;
325}
326
327static int ufs_rockchip_system_resume(struct device *dev)
328{
329	struct ufs_hba *hba = dev_get_drvdata(dev);
330	struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
331	int err;
332
333	err = clk_prepare_enable(host->ref_out_clk);
334	if (err) {
335		dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
336		return err;
337	}
338
339	return ufshcd_system_resume(dev);
340}
341#endif
342
343static const struct dev_pm_ops ufs_rockchip_pm_ops = {
344	SET_SYSTEM_SLEEP_PM_OPS(ufs_rockchip_system_suspend, ufs_rockchip_system_resume)
345	SET_RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL)
346	.prepare	 = ufshcd_suspend_prepare,
347	.complete	 = ufshcd_resume_complete,
348};
349
350static struct platform_driver ufs_rockchip_pltform = {
351	.probe = ufs_rockchip_probe,
352	.remove = ufs_rockchip_remove,
353	.driver = {
354		.name = "ufshcd-rockchip",
355		.pm = &ufs_rockchip_pm_ops,
356		.of_match_table = ufs_rockchip_of_match,
357	},
358};
359module_platform_driver(ufs_rockchip_pltform);
360
361MODULE_LICENSE("GPL");
362MODULE_DESCRIPTION("Rockchip UFS Host Driver");