ufs-mediatek.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2019 MediaTek Inc.
  4 */
  5
  6#ifndef _UFS_MEDIATEK_H
  7#define _UFS_MEDIATEK_H
  8
  9#include <linux/bitops.h>
 10
 11/*
 12 * MCQ define and struct
 13 */
 14#define UFSHCD_MAX_Q_NR 8
 15#define MTK_MCQ_INVALID_IRQ	0xFFFF
 16
 17/* REG_UFS_MMIO_OPT_CTRL_0 160h */
 18#define EHS_EN                  BIT(0)
 19#define PFM_IMPV                BIT(1)
 20#define MCQ_MULTI_INTR_EN       BIT(2)
 21#define MCQ_CMB_INTR_EN         BIT(3)
 22#define MCQ_AH8                 BIT(4)
 23#define MON_EN                  BIT(5)
 24#define MRTT_EN                 BIT(25)
 25#define RDN_PFM_IMPV_DIS        BIT(28)
 26
 27#define MCQ_INTR_EN_MSK         (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN)
 28
 29/*
 30 * Vendor specific UFSHCI Registers
 31 */
 32#define REG_UFS_XOUFS_CTRL          0x140
 33#define REG_UFS_REFCLK_CTRL         0x144
 34#define REG_UFS_UFS_MMIO_OTSD_CTRL  0x14C
 35#define REG_UFS_MMIO_OPT_CTRL_0     0x160
 36#define REG_UFS_EXTREG              0x2100
 37#define REG_UFS_MPHYCTRL            0x2200
 38#define REG_UFS_MTK_IP_VER          0x2240
 39#define REG_UFS_REJECT_MON          0x22AC
 40#define REG_UFS_DEBUG_SEL           0x22C0
 41#define REG_UFS_PROBE               0x22C8
 42#define REG_UFS_DEBUG_SEL_B0        0x22D0
 43#define REG_UFS_DEBUG_SEL_B1        0x22D4
 44#define REG_UFS_DEBUG_SEL_B2        0x22D8
 45#define REG_UFS_DEBUG_SEL_B3        0x22DC
 46
 47#define REG_UFS_MTK_SQD             0x2800
 48#define REG_UFS_MTK_SQIS            0x2814
 49#define REG_UFS_MTK_CQD             0x281C
 50#define REG_UFS_MTK_CQIS            0x2824
 51
 52#define REG_UFS_MCQ_STRIDE          0x30
 53
 54/*
 55 * Ref-clk control
 56 *
 57 * Values for register REG_UFS_REFCLK_CTRL
 58 */
 59#define REFCLK_RELEASE              0x0
 60#define REFCLK_REQUEST              BIT(0)
 61#define REFCLK_ACK                  BIT(1)
 62
 63#define REFCLK_REQ_TIMEOUT_US       3000
 64#define REFCLK_DEFAULT_WAIT_US      32
 65
 66/*
 67 * Other attributes
 68 */
 69#define VS_DEBUGCLOCKENABLE         0xD0A1
 70#define VS_SAVEPOWERCONTROL         0xD0A6
 71#define VS_UNIPROPOWERDOWNCONTROL   0xD0A8
 72
 73/*
 74 * Vendor specific link state
 75 */
 76enum {
 77	VS_LINK_DISABLED            = 0,
 78	VS_LINK_DOWN                = 1,
 79	VS_LINK_UP                  = 2,
 80	VS_LINK_HIBERN8             = 3,
 81	VS_LINK_LOST                = 4,
 82	VS_LINK_CFG                 = 5,
 83};
 84
 85/*
 86 * Vendor specific host controller state
 87 */
 88enum {
 89	VS_HCE_RESET                = 0,
 90	VS_HCE_BASE                 = 1,
 91	VS_HCE_OOCPR_WAIT           = 2,
 92	VS_HCE_DME_RESET            = 3,
 93	VS_HCE_MIDDLE               = 4,
 94	VS_HCE_DME_ENABLE           = 5,
 95	VS_HCE_DEFAULTS             = 6,
 96	VS_HIB_IDLEEN               = 7,
 97	VS_HIB_ENTER                = 8,
 98	VS_HIB_ENTER_CONF           = 9,
 99	VS_HIB_MIDDLE               = 10,
100	VS_HIB_WAITTIMER            = 11,
101	VS_HIB_EXIT_CONF            = 12,
102	VS_HIB_EXIT                 = 13,
103};
104
105/*
106 * VS_DEBUGCLOCKENABLE
107 */
108enum {
109	TX_SYMBOL_CLK_REQ_FORCE = 5,
110};
111
112/*
113 * VS_SAVEPOWERCONTROL
114 */
115enum {
116	RX_SYMBOL_CLK_GATE_EN   = 0,
117	SYS_CLK_GATE_EN         = 2,
118	TX_CLK_GATE_EN          = 3,
119};
120
121/*
122 * Host capability
123 */
124enum ufs_mtk_host_caps {
125	UFS_MTK_CAP_BOOST_CRYPT_ENGINE         = 1 << 0,
126	UFS_MTK_CAP_VA09_PWR_CTRL              = 1 << 1,
127	UFS_MTK_CAP_DISABLE_AH8                = 1 << 2,
128	UFS_MTK_CAP_BROKEN_VCC                 = 1 << 3,
129
130	/*
131	 * Override UFS_MTK_CAP_BROKEN_VCC's behavior to
132	 * allow vccqx upstream to enter LPM
133	 */
134	UFS_MTK_CAP_ALLOW_VCCQX_LPM            = 1 << 5,
135	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
136	UFS_MTK_CAP_TX_SKEW_FIX                = 1 << 7,
137	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
138	/* Control MTCMOS with RTFF */
139	UFS_MTK_CAP_RTFF_MTCMOS                = 1 << 9,
140
141	UFS_MTK_CAP_MCQ_BROKEN_RTC             = 1 << 10,
142};
143
144struct ufs_mtk_crypt_cfg {
145	struct regulator *reg_vcore;
146	struct clk *clk_crypt_perf;
147	struct clk *clk_crypt_mux;
148	struct clk *clk_crypt_lp;
149	int vcore_volt;
150};
151
152struct ufs_mtk_clk {
153	struct ufs_clk_info *ufs_sel_clki; /* Mux */
154	struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
155	struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
156	struct ufs_clk_info *ufs_fde_clki; /* Mux */
157	struct ufs_clk_info *ufs_fde_max_clki; /* Max src */
158	struct ufs_clk_info *ufs_fde_min_clki; /* Min src */
159	struct regulator *reg_vcore;
160	int vcore_volt;
161};
162
163struct ufs_mtk_hw_ver {
164	u8 step;
165	u8 minor;
166	u8 major;
167};
168
169struct ufs_mtk_mcq_intr_info {
170	struct ufs_hba *hba;
171	u32 irq;
172	u8 qid;
173};
174
175struct ufs_mtk_host {
176	struct phy *mphy;
177	struct regulator *reg_va09;
178	struct reset_control *hci_reset;
179	struct reset_control *unipro_reset;
180	struct reset_control *crypto_reset;
181	struct reset_control *mphy_reset;
182	struct ufs_hba *hba;
183	struct ufs_mtk_crypt_cfg *crypt;
184	struct ufs_mtk_clk mclk;
185	struct ufs_mtk_hw_ver hw_ver;
186	enum ufs_mtk_host_caps caps;
187	bool mphy_powered_on;
188	bool unipro_lpm;
189	bool ref_clk_enabled;
190	bool clk_scale_up;
191	u16 ref_clk_ungating_wait_us;
192	u16 ref_clk_gating_wait_us;
193	u32 ip_ver;
194	bool legacy_ip_ver;
195
196	bool mcq_set_intr;
197	bool is_mcq_intr_enabled;
198	int mcq_nr_intr;
199	struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
200	struct device *phy_dev;
201};
202
203/* MTK delay of autosuspend: 500 ms */
204#define MTK_RPM_AUTOSUSPEND_DELAY_MS 500
205
206/* MTK RTT support number */
207#define MTK_MAX_NUM_RTT 2
208
209/* UFSHCI MTK ip version value */
210enum {
211	/* UFSHCI 3.1 */
212	IP_VER_MT6983    = 0x10360000,
213	IP_VER_MT6878    = 0x10420200,
214
215	/* UFSHCI 4.0 */
216	IP_VER_MT6897    = 0x10440000,
217	IP_VER_MT6989    = 0x10450000,
218	IP_VER_MT6899    = 0x10450100,
219	IP_VER_MT6991_A0 = 0x10460000,
220	IP_VER_MT6991_B0 = 0x10470000,
221	IP_VER_MT6993    = 0x10480000,
222
223	IP_VER_NONE      = 0xFFFFFFFF
224};
225
226enum ip_ver_legacy {
227	IP_LEGACY_VER_MT6781 = 0x10380000,
228	IP_LEGACY_VER_MT6879 = 0x10360000,
229	IP_LEGACY_VER_MT6893 = 0x20160706
230};
231
232#endif /* !_UFS_MEDIATEK_H */