ufs-hisi.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2017, HiSilicon. All rights reserved.
  4 */
  5
  6#ifndef UFS_HISI_H_
  7#define UFS_HISI_H_
  8
  9#define HBRN8_POLL_TOUT_MS	1000
 10
 11/*
 12 * ufs sysctrl specific define
 13 */
 14#define PSW_POWER_CTRL	(0x04)
 15#define PHY_ISO_EN	(0x08)
 16#define HC_LP_CTRL	(0x0C)
 17#define PHY_CLK_CTRL	(0x10)
 18#define PSW_CLK_CTRL	(0x14)
 19#define CLOCK_GATE_BYPASS	(0x18)
 20#define RESET_CTRL_EN	(0x1C)
 21#define UFS_SYSCTRL	(0x5C)
 22#define UFS_DEVICE_RESET_CTRL	(0x60)
 23
 24#define BIT_UFS_PSW_ISO_CTRL		(1 << 16)
 25#define BIT_UFS_PSW_MTCMOS_EN		(1 << 0)
 26#define BIT_UFS_REFCLK_ISO_EN		(1 << 16)
 27#define BIT_UFS_PHY_ISO_CTRL		(1 << 0)
 28#define BIT_SYSCTRL_LP_ISOL_EN		(1 << 16)
 29#define BIT_SYSCTRL_PWR_READY		(1 << 8)
 30#define BIT_SYSCTRL_REF_CLOCK_EN	(1 << 24)
 31#define MASK_SYSCTRL_REF_CLOCK_SEL	(0x3 << 8)
 32#define MASK_SYSCTRL_CFG_CLOCK_FREQ	(0xFF)
 33#define UFS_FREQ_CFG_CLK                (0x39)
 34#define BIT_SYSCTRL_PSW_CLK_EN		(1 << 4)
 35#define MASK_UFS_CLK_GATE_BYPASS	(0x3F)
 36#define BIT_SYSCTRL_LP_RESET_N		(1 << 0)
 37#define BIT_UFS_REFCLK_SRC_SEl		(1 << 0)
 38#define MASK_UFS_SYSCRTL_BYPASS		(0x3F << 16)
 39#define MASK_UFS_DEVICE_RESET		(0x1 << 16)
 40#define BIT_UFS_DEVICE_RESET		(0x1)
 41
 42/*
 43 * M-TX Configuration Attributes for Hixxxx
 44 */
 45#define MPHY_TX_FSM_STATE	0x41
 46#define TX_FSM_HIBERN8	0x1
 47
 48/*
 49 * Hixxxx UFS HC specific Registers
 50 */
 51enum {
 52	UFS_REG_OCPTHRTL = 0xc0,
 53	UFS_REG_OOCPR    = 0xc4,
 54
 55	UFS_REG_CDACFG   = 0xd0,
 56	UFS_REG_CDATX1   = 0xd4,
 57	UFS_REG_CDATX2   = 0xd8,
 58	UFS_REG_CDARX1   = 0xdc,
 59	UFS_REG_CDARX2   = 0xe0,
 60	UFS_REG_CDASTA   = 0xe4,
 61
 62	UFS_REG_LBMCFG   = 0xf0,
 63	UFS_REG_LBMSTA   = 0xf4,
 64	UFS_REG_UFSMODE  = 0xf8,
 65
 66	UFS_REG_HCLKDIV  = 0xfc,
 67};
 68
 69/* AHIT - Auto-Hibernate Idle Timer */
 70#define UFS_AHIT_AH8ITV_MASK	0x3FF
 71
 72/* REG UFS_REG_OCPTHRTL definition */
 73#define UFS_HCLKDIV_NORMAL_VALUE	0xE4
 74
 75/* vendor specific pre-defined parameters */
 76#define SLOW	1
 77#define FAST	2
 78
 79#define UFS_HISI_CAP_RESERVED		BIT(0)
 80#define UFS_HISI_CAP_PHY10nm		BIT(1)
 81
 82struct ufs_hisi_host {
 83	struct ufs_hba *hba;
 84	void __iomem *ufs_sys_ctrl;
 85
 86	struct reset_control	*rst;
 87
 88	uint64_t caps;
 89
 90	bool in_suspend;
 91};
 92
 93#define ufs_sys_ctrl_writel(host, val, reg)                                    \
 94	writel((val), (host)->ufs_sys_ctrl + (reg))
 95#define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg))
 96#define ufs_sys_ctrl_set_bits(host, mask, reg)                                 \
 97	ufs_sys_ctrl_writel(                                                   \
 98		(host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg))
 99#define ufs_sys_ctrl_clr_bits(host, mask, reg)                                 \
100	ufs_sys_ctrl_writel((host),                                            \
101			    ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \
102			    (reg))
103
104#endif /* UFS_HISI_H_ */