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ufs-exynos.c
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linux-6.19.14/drivers/ufs/host/ufs-exynos.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * UFS Host Controller driver for Exynos specific extensions 4 * 5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. 6 * Author: Seungwon Jeon <essuuj@gmail.com> 7 * Author: Alim Akhtar <alim.akhtar@samsung.com> 8 * 9 */ 10 11#include <linux/unaligned.h> 12#include <crypto/aes.h> 13#include <linux/arm-smccc.h> 14#include <linux/clk.h> 15#include <linux/delay.h> 16#include <linux/module.h> 17#include <linux/of.h> 18#include <linux/of_address.h> 19#include <linux/mfd/syscon.h> 20#include <linux/phy/phy.h> 21#include <linux/platform_device.h> 22#include <linux/regmap.h> 23 24#include <ufs/ufshcd.h> 25#include "ufshcd-pltfrm.h" 26#include <ufs/ufshci.h> 27#include <ufs/unipro.h> 28 29#include "ufs-exynos.h" 30 31#define DATA_UNIT_SIZE 4096 32 33/* 34 * Exynos's Vendor specific registers for UFSHCI 35 */ 36#define HCI_TXPRDT_ENTRY_SIZE 0x00 37#define PRDT_PREFETCH_EN BIT(31) 38#define HCI_RXPRDT_ENTRY_SIZE 0x04 39#define HCI_1US_TO_CNT_VAL 0x0C 40#define CNT_VAL_1US_MASK 0x3FF 41#define HCI_UTRL_NEXUS_TYPE 0x40 42#define HCI_UTMRL_NEXUS_TYPE 0x44 43#define HCI_SW_RST 0x50 44#define UFS_LINK_SW_RST BIT(0) 45#define UFS_UNIPRO_SW_RST BIT(1) 46#define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST) 47#define HCI_DATA_REORDER 0x60 48#define HCI_UNIPRO_APB_CLK_CTRL 0x68 49#define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) 50#define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C 51#define WLU_EN BIT(31) 52#define WLU_BURST_LEN(x) ((x) << 27 | ((x) & 0xF)) 53#define HCI_GPIO_OUT 0x70 54#define HCI_ERR_EN_PA_LAYER 0x78 55#define HCI_ERR_EN_DL_LAYER 0x7C 56#define HCI_ERR_EN_N_LAYER 0x80 57#define HCI_ERR_EN_T_LAYER 0x84 58#define HCI_ERR_EN_DME_LAYER 0x88 59#define HCI_V2P1_CTRL 0x8C 60#define IA_TICK_SEL BIT(16) 61#define HCI_CLKSTOP_CTRL 0xB0 62#define REFCLKOUT_STOP BIT(4) 63#define MPHY_APBCLK_STOP BIT(3) 64#define REFCLK_STOP BIT(2) 65#define UNIPRO_MCLK_STOP BIT(1) 66#define UNIPRO_PCLK_STOP BIT(0) 67#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\ 68 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\ 69 UNIPRO_PCLK_STOP) 70/* HCI_MISC is also known as HCI_FORCE_HCS */ 71#define HCI_MISC 0xB4 72#define REFCLK_CTRL_EN BIT(7) 73#define UNIPRO_PCLK_CTRL_EN BIT(6) 74#define UNIPRO_MCLK_CTRL_EN BIT(5) 75#define HCI_CORECLK_CTRL_EN BIT(4) 76#define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ 77 UNIPRO_PCLK_CTRL_EN |\ 78 UNIPRO_MCLK_CTRL_EN) 79 80#define HCI_IOP_ACG_DISABLE 0x100 81#define HCI_IOP_ACG_DISABLE_EN BIT(0) 82 83/* Device fatal error */ 84#define DFES_ERR_EN BIT(31) 85#define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ 86 UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 87#define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\ 88 UIC_NETWORK_BAD_DEVICEID_ENC |\ 89 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING) 90#define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\ 91 UIC_TRANSPORT_UNKNOWN_CPORTID |\ 92 UIC_TRANSPORT_NO_CONNECTION_RX |\ 93 UIC_TRANSPORT_BAD_TC) 94 95/* UFS Shareability */ 96#define UFS_EXYNOSAUTO_WR_SHARABLE BIT(2) 97#define UFS_EXYNOSAUTO_RD_SHARABLE BIT(1) 98#define UFS_EXYNOSAUTO_SHARABLE (UFS_EXYNOSAUTO_WR_SHARABLE | \ 99 UFS_EXYNOSAUTO_RD_SHARABLE) 100#define UFS_GS101_WR_SHARABLE BIT(1) 101#define UFS_GS101_RD_SHARABLE BIT(0) 102#define UFS_GS101_SHARABLE (UFS_GS101_WR_SHARABLE | \ 103 UFS_GS101_RD_SHARABLE) 104#define UFS_SHAREABILITY_OFFSET 0x710 105 106/* Multi-host registers */ 107#define MHCTRL 0xC4 108#define MHCTRL_EN_VH_MASK (0xE) 109#define MHCTRL_EN_VH(vh) (vh << 1) 110#define PH2VH_MBOX 0xD8 111 112#define MH_MSG_MASK (0xFF) 113 114#define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF)) 115#define MH_MSG_PH_READY 0x1 116#define MH_MSG_VH_READY 0x2 117 118#define ALLOW_INQUIRY BIT(25) 119#define ALLOW_MODE_SELECT BIT(24) 120#define ALLOW_MODE_SENSE BIT(23) 121#define ALLOW_PRE_FETCH GENMASK(22, 21) 122#define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */ 123#define ALLOW_READ_BUFFER BIT(17) 124#define ALLOW_READ_CAPACITY GENMASK(16, 15) 125#define ALLOW_REPORT_LUNS BIT(14) 126#define ALLOW_REQUEST_SENSE BIT(13) 127#define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7) 128#define ALLOW_TEST_UNIT_READY BIT(6) 129#define ALLOW_UNMAP BIT(5) 130#define ALLOW_VERIFY BIT(4) 131#define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */ 132 133#define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \ 134 ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \ 135 ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \ 136 ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \ 137 ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \ 138 ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \ 139 ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL) 140 141#define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C 142#define HCI_MH_IID_IN_TASK_TAG 0X308 143 144#define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC) 145 146enum { 147 UNIPRO_L1_5 = 0,/* PHY Adapter */ 148 UNIPRO_L2, /* Data Link */ 149 UNIPRO_L3, /* Network */ 150 UNIPRO_L4, /* Transport */ 151 UNIPRO_DME, /* DME */ 152}; 153 154/* 155 * UNIPRO registers 156 */ 157#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888 158#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c 159#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890 160#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8 161#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC 162#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0 163 164/* 165 * UFS Protector registers 166 */ 167#define UFSPRSECURITY 0x010 168#define NSSMU BIT(14) 169#define UFSPSBEGIN0 0x200 170#define UFSPSEND0 0x204 171#define UFSPSLUN0 0x208 172#define UFSPSCTRL0 0x20C 173 174#define CNTR_DIV_VAL 40 175 176static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en); 177static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en); 178 179static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs) 180{ 181 exynos_ufs_auto_ctrl_hcc(ufs, true); 182} 183 184static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs) 185{ 186 exynos_ufs_auto_ctrl_hcc(ufs, false); 187} 188 189static inline void exynos_ufs_disable_auto_ctrl_hcc_save( 190 struct exynos_ufs *ufs, u32 *val) 191{ 192 *val = hci_readl(ufs, HCI_MISC); 193 exynos_ufs_auto_ctrl_hcc(ufs, false); 194} 195 196static inline void exynos_ufs_auto_ctrl_hcc_restore( 197 struct exynos_ufs *ufs, u32 *val) 198{ 199 hci_writel(ufs, *val, HCI_MISC); 200} 201 202static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs) 203{ 204 exynos_ufs_ctrl_clkstop(ufs, true); 205} 206 207static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs) 208{ 209 exynos_ufs_ctrl_clkstop(ufs, false); 210} 211 212static int exynos_ufs_shareability(struct exynos_ufs *ufs) 213{ 214 /* IO Coherency setting */ 215 if (ufs->sysreg) { 216 return regmap_update_bits(ufs->sysreg, 217 ufs->iocc_offset, 218 ufs->iocc_mask, ufs->iocc_val); 219 } 220 221 return 0; 222} 223 224static int gs101_ufs_drv_init(struct exynos_ufs *ufs) 225{ 226 struct ufs_hba *hba = ufs->hba; 227 u32 reg; 228 229 /* Enable WriteBooster */ 230 hba->caps |= UFSHCD_CAP_WB_EN; 231 232 /* Enable clock gating and hibern8 */ 233 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 234 235 /* set ACG to be controlled by UFS_ACG_DISABLE */ 236 reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE); 237 hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE); 238 239 return exynos_ufs_shareability(ufs); 240} 241 242static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs) 243{ 244 return exynos_ufs_shareability(ufs); 245} 246 247static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) 248{ 249 struct ufs_hba *hba = ufs->hba; 250 251 /* Enable Virtual Host #1 */ 252 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); 253 /* Default VH Transfer permissions */ 254 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH); 255 /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */ 256 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG); 257 258 return 0; 259} 260 261static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) 262{ 263 struct ufs_hba *hba = ufs->hba; 264 int i; 265 u32 tx_line_reset_period, rx_line_reset_period; 266 267 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 268 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 269 270 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 271 for_each_ufs_rx_lane(ufs, i) { 272 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 273 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 275 276 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 277 (rx_line_reset_period >> 16) & 0xFF); 278 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 279 (rx_line_reset_period >> 8) & 0xFF); 280 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 281 (rx_line_reset_period) & 0xFF); 282 283 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); 284 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 285 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 286 } 287 288 for_each_ufs_tx_lane(ufs, i) { 289 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 290 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 291 /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */ 292 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 293 0x02); 294 295 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 296 (tx_line_reset_period >> 16) & 0xFF); 297 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 298 (tx_line_reset_period >> 8) & 0xFF); 299 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 300 (tx_line_reset_period) & 0xFF); 301 302 /* TX PWM Gear Capability / PWM_G1_ONLY */ 303 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); 304 } 305 306 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 307 308 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 309 310 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); 311 312 return 0; 313} 314 315static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs, 316 struct ufs_pa_layer_attr *pwr) 317{ 318 struct ufs_hba *hba = ufs->hba; 319 320 /* PACP_PWR_req and delivered to the remote DME */ 321 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 322 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 323 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 324 325 return 0; 326} 327 328static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, 329 const struct ufs_pa_layer_attr *pwr) 330{ 331 struct ufs_hba *hba = ufs->hba; 332 u32 enabled_vh; 333 334 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; 335 336 /* Send physical host ready message to virtual hosts */ 337 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); 338 339 return 0; 340} 341 342static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) 343{ 344 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 345 u32 val = attr->pa_dbg_opt_suite1_val; 346 struct ufs_hba *hba = ufs->hba; 347 int i; 348 349 exynos_ufs_enable_ov_tm(hba); 350 for_each_ufs_tx_lane(ufs, i) 351 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); 352 for_each_ufs_rx_lane(ufs, i) { 353 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); 354 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); 355 } 356 exynos_ufs_disable_ov_tm(hba); 357 358 for_each_ufs_tx_lane(ufs, i) 359 ufshcd_dme_set(hba, 360 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); 361 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); 362 udelay(1); 363 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 364 val | (1 << 12)); 365 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); 366 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); 367 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); 368 udelay(1600); 369 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); 370 371 return 0; 372} 373 374static int exynos7_ufs_post_link(struct exynos_ufs *ufs) 375{ 376 struct ufs_hba *hba = ufs->hba; 377 int i; 378 379 exynos_ufs_enable_ov_tm(hba); 380 for_each_ufs_tx_lane(ufs, i) { 381 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); 382 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); 383 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), 384 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000))); 385 } 386 exynos_ufs_disable_ov_tm(hba); 387 388 exynos_ufs_enable_dbg_mode(hba); 389 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); 390 exynos_ufs_disable_dbg_mode(hba); 391 392 return 0; 393} 394 395static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs, 396 struct ufs_pa_layer_attr *pwr) 397{ 398 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE); 399 400 return 0; 401} 402 403static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs, 404 const struct ufs_pa_layer_attr *pwr) 405{ 406 struct ufs_hba *hba = ufs->hba; 407 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); 408 409 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); 410 411 if (lanes == 1) { 412 exynos_ufs_enable_dbg_mode(hba); 413 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); 414 exynos_ufs_disable_dbg_mode(hba); 415 } 416 417 return 0; 418} 419 420/* 421 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w 422 * Control should be disabled in the below cases 423 * - Before host controller S/W reset 424 * - Access to UFS protector's register 425 */ 426static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en) 427{ 428 u32 misc = hci_readl(ufs, HCI_MISC); 429 430 if (en) 431 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC); 432 else 433 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC); 434} 435 436static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en) 437{ 438 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL); 439 u32 misc = hci_readl(ufs, HCI_MISC); 440 441 if (en) { 442 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC); 443 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 444 } else { 445 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 446 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC); 447 } 448} 449 450static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs) 451{ 452 struct ufs_hba *hba = ufs->hba; 453 struct list_head *head = &hba->clk_list_head; 454 struct ufs_clk_info *clki; 455 unsigned long pclk_rate; 456 u32 f_min, f_max; 457 u8 div = 0; 458 int ret = 0; 459 460 if (list_empty(head)) 461 goto out; 462 463 list_for_each_entry(clki, head, list) { 464 if (!IS_ERR(clki->clk)) { 465 if (!strcmp(clki->name, "core_clk")) 466 ufs->clk_hci_core = clki->clk; 467 else if (!strcmp(clki->name, "sclk_unipro_main")) 468 ufs->clk_unipro_main = clki->clk; 469 } 470 } 471 472 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { 473 dev_err(hba->dev, "failed to get clk info\n"); 474 ret = -EINVAL; 475 goto out; 476 } 477 478 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); 479 pclk_rate = clk_get_rate(ufs->clk_hci_core); 480 f_min = ufs->pclk_avail_min; 481 f_max = ufs->pclk_avail_max; 482 483 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 484 do { 485 pclk_rate /= (div + 1); 486 487 if (pclk_rate <= f_max) 488 break; 489 div++; 490 } while (pclk_rate >= f_min); 491 } 492 493 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) { 494 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); 495 ret = -EINVAL; 496 goto out; 497 } 498 499 ufs->pclk_rate = pclk_rate; 500 ufs->pclk_div = div; 501 502out: 503 return ret; 504} 505 506static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs) 507{ 508 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 509 u32 val; 510 511 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL); 512 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), 513 HCI_UNIPRO_APB_CLK_CTRL); 514 } 515} 516 517static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs) 518{ 519 struct ufs_hba *hba = ufs->hba; 520 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 521 522 ufshcd_dme_set(hba, 523 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); 524} 525 526static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs) 527{ 528 struct ufs_hba *hba = ufs->hba; 529 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 530 const unsigned int div = 30, mult = 20; 531 const unsigned long pwm_min = 3 * 1000 * 1000; 532 const unsigned long pwm_max = 9 * 1000 * 1000; 533 const int divs[] = {32, 16, 8, 4}; 534 unsigned long clk = 0, _clk, clk_period; 535 int i = 0, clk_idx = -1; 536 537 clk_period = UNIPRO_PCLK_PERIOD(ufs); 538 for (i = 0; i < ARRAY_SIZE(divs); i++) { 539 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); 540 if (_clk >= pwm_min && _clk <= pwm_max) { 541 if (_clk > clk) { 542 clk_idx = i; 543 clk = _clk; 544 } 545 } 546 } 547 548 if (clk_idx == -1) { 549 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); 550 dev_err(hba->dev, 551 "failed to decide pwm clock divider, will not change\n"); 552 } 553 554 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; 555} 556 557long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period) 558{ 559 const int precise = 10; 560 long pclk_rate = ufs->pclk_rate; 561 long clk_period, fraction; 562 563 clk_period = UNIPRO_PCLK_PERIOD(ufs); 564 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate; 565 566 return (period * precise) / ((clk_period * precise) + fraction); 567} 568 569static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) 570{ 571 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 572 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 573 574 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR) 575 return; 576 577 t_cfg->tx_linereset_p = 578 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); 579 t_cfg->tx_linereset_n = 580 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); 581 t_cfg->tx_high_z_cnt = 582 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); 583 t_cfg->tx_base_n_val = 584 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); 585 t_cfg->tx_gran_n_val = 586 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); 587 t_cfg->tx_sleep_cnt = 588 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); 589 590 t_cfg->rx_linereset = 591 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); 592 t_cfg->rx_hibern8_wait = 593 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); 594 t_cfg->rx_base_n_val = 595 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); 596 t_cfg->rx_gran_n_val = 597 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); 598 t_cfg->rx_sleep_cnt = 599 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); 600 t_cfg->rx_stall_cnt = 601 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); 602} 603 604static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs) 605{ 606 struct ufs_hba *hba = ufs->hba; 607 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 608 int i; 609 610 exynos_ufs_set_pwm_clk_div(ufs); 611 612 exynos_ufs_enable_ov_tm(hba); 613 614 for_each_ufs_rx_lane(ufs, i) { 615 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), 616 ufs->drv_data->uic_attr->rx_filler_enable); 617 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), 618 RX_LINERESET(t_cfg->rx_linereset)); 619 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), 620 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); 621 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), 622 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); 623 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), 624 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); 625 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), 626 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); 627 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), 628 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); 629 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), 630 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); 631 } 632 633 for_each_ufs_tx_lane(ufs, i) { 634 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), 635 TX_LINERESET_P(t_cfg->tx_linereset_p)); 636 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), 637 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); 638 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), 639 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); 640 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), 641 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); 642 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), 643 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); 644 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), 645 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); 646 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), 647 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); 648 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), 649 TX_OV_H8_ENTER_EN | 650 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); 651 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), 652 ufs->drv_data->uic_attr->tx_min_activatetime); 653 } 654 655 exynos_ufs_disable_ov_tm(hba); 656} 657 658static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs) 659{ 660 struct ufs_hba *hba = ufs->hba; 661 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 662 int i; 663 664 exynos_ufs_enable_ov_tm(hba); 665 666 for_each_ufs_rx_lane(ufs, i) { 667 ufshcd_dme_set(hba, 668 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), 669 attr->rx_hs_g1_sync_len_cap); 670 ufshcd_dme_set(hba, 671 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), 672 attr->rx_hs_g2_sync_len_cap); 673 ufshcd_dme_set(hba, 674 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), 675 attr->rx_hs_g3_sync_len_cap); 676 ufshcd_dme_set(hba, 677 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), 678 attr->rx_hs_g1_prep_sync_len_cap); 679 ufshcd_dme_set(hba, 680 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i), 681 attr->rx_hs_g2_prep_sync_len_cap); 682 ufshcd_dme_set(hba, 683 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i), 684 attr->rx_hs_g3_prep_sync_len_cap); 685 } 686 687 if (attr->rx_adv_fine_gran_sup_en == 0) { 688 for_each_ufs_rx_lane(ufs, i) { 689 ufshcd_dme_set(hba, 690 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0); 691 692 if (attr->rx_min_actv_time_cap) 693 ufshcd_dme_set(hba, 694 UIC_ARG_MIB_SEL( 695 RX_MIN_ACTIVATETIME_CAPABILITY, i), 696 attr->rx_min_actv_time_cap); 697 698 if (attr->rx_hibern8_time_cap) 699 ufshcd_dme_set(hba, 700 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), 701 attr->rx_hibern8_time_cap); 702 } 703 } else if (attr->rx_adv_fine_gran_sup_en == 1) { 704 for_each_ufs_rx_lane(ufs, i) { 705 if (attr->rx_adv_fine_gran_step) 706 ufshcd_dme_set(hba, 707 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, 708 i), RX_ADV_FINE_GRAN_STEP( 709 attr->rx_adv_fine_gran_step)); 710 711 if (attr->rx_adv_min_actv_time_cap) 712 ufshcd_dme_set(hba, 713 UIC_ARG_MIB_SEL( 714 RX_ADV_MIN_ACTIVATETIME_CAP, i), 715 attr->rx_adv_min_actv_time_cap); 716 717 if (attr->rx_adv_hibern8_time_cap) 718 ufshcd_dme_set(hba, 719 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP, 720 i), 721 attr->rx_adv_hibern8_time_cap); 722 } 723 } 724 725 exynos_ufs_disable_ov_tm(hba); 726} 727 728static void exynos_ufs_establish_connt(struct exynos_ufs *ufs) 729{ 730 struct ufs_hba *hba = ufs->hba; 731 enum { 732 DEV_ID = 0x00, 733 PEER_DEV_ID = 0x01, 734 PEER_CPORT_ID = 0x00, 735 TRAFFIC_CLASS = 0x00, 736 }; 737 738 /* allow cport attributes to be set */ 739 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); 740 741 /* local unipro attributes */ 742 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); 743 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true); 744 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); 745 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); 746 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); 747 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); 748 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 749} 750 751static void exynos_ufs_config_smu(struct exynos_ufs *ufs) 752{ 753 u32 reg, val; 754 755 if (ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE) 756 return; 757 758 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 759 760 /* make encryption disabled by default */ 761 reg = ufsp_readl(ufs, UFSPRSECURITY); 762 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY); 763 ufsp_writel(ufs, 0x0, UFSPSBEGIN0); 764 ufsp_writel(ufs, 0xffffffff, UFSPSEND0); 765 ufsp_writel(ufs, 0xff, UFSPSLUN0); 766 ufsp_writel(ufs, 0xf1, UFSPSCTRL0); 767 768 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 769} 770 771static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs, 772 struct ufs_pa_layer_attr *pwr) 773{ 774 struct ufs_hba *hba = ufs->hba; 775 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); 776 u32 mask, sync_len; 777 enum { 778 SYNC_LEN_G1 = 80 * 1000, /* 80us */ 779 SYNC_LEN_G2 = 40 * 1000, /* 40us */ 780 SYNC_LEN_G3 = 20 * 1000, /* 20us */ 781 }; 782 int i; 783 784 if (g == 1) 785 sync_len = SYNC_LEN_G1; 786 else if (g == 2) 787 sync_len = SYNC_LEN_G2; 788 else if (g == 3) 789 sync_len = SYNC_LEN_G3; 790 else 791 return; 792 793 mask = exynos_ufs_calc_time_cntr(ufs, sync_len); 794 mask = (mask >> 8) & 0xff; 795 796 exynos_ufs_enable_ov_tm(hba); 797 798 for_each_ufs_rx_lane(ufs, i) 799 ufshcd_dme_set(hba, 800 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask); 801 802 exynos_ufs_disable_ov_tm(hba); 803} 804 805#define UFS_HW_VER_MAJOR_MASK GENMASK(15, 8) 806 807static u32 exynos_ufs_get_hs_gear(struct ufs_hba *hba) 808{ 809 u8 major; 810 811 major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, hba->ufs_version); 812 813 if (major >= 3) 814 return UFS_HS_G4; 815 816 /* Default is HS-G3 */ 817 return UFS_HS_G3; 818} 819 820static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, 821 const struct ufs_pa_layer_attr *dev_max_params, 822 struct ufs_pa_layer_attr *dev_req_params) 823{ 824 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 825 struct phy *generic_phy = ufs->phy; 826 struct ufs_host_params host_params; 827 int ret; 828 829 if (!dev_req_params) { 830 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 831 ret = -EINVAL; 832 goto out; 833 } 834 835 ufshcd_init_host_params(&host_params); 836 837 /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */ 838 host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba); 839 host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); 840 841 ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); 842 if (ret) { 843 pr_err("%s: failed to determine capabilities\n", __func__); 844 goto out; 845 } 846 847 if (ufs->drv_data->pre_pwr_change) 848 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); 849 850 if (ufshcd_is_hs_mode(dev_req_params)) { 851 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params); 852 853 switch (dev_req_params->hs_rate) { 854 case PA_HS_MODE_A: 855 case PA_HS_MODE_B: 856 phy_calibrate(generic_phy); 857 break; 858 } 859 } 860 861 /* setting for three timeout values for traffic class #0 */ 862 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); 863 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); 864 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); 865 866 return 0; 867out: 868 return ret; 869} 870 871#define PWR_MODE_STR_LEN 64 872static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, 873 const struct ufs_pa_layer_attr *pwr_req) 874{ 875 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 876 struct phy *generic_phy = ufs->phy; 877 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); 878 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); 879 char pwr_str[PWR_MODE_STR_LEN] = ""; 880 881 /* let default be PWM Gear 1, Lane 1 */ 882 if (!gear) 883 gear = 1; 884 885 if (!lanes) 886 lanes = 1; 887 888 if (ufs->drv_data->post_pwr_change) 889 ufs->drv_data->post_pwr_change(ufs, pwr_req); 890 891 if ((ufshcd_is_hs_mode(pwr_req))) { 892 switch (pwr_req->hs_rate) { 893 case PA_HS_MODE_A: 894 case PA_HS_MODE_B: 895 phy_calibrate(generic_phy); 896 break; 897 } 898 899 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d", 900 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", 901 gear, lanes); 902 } else { 903 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d", 904 "SLOW", gear, lanes); 905 } 906 907 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); 908 909 return 0; 910} 911 912static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, 913 int tag, bool is_scsi_cmd) 914{ 915 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 916 u32 type; 917 918 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE); 919 920 if (is_scsi_cmd) 921 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE); 922 else 923 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE); 924} 925 926static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, 927 int tag, u8 func) 928{ 929 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 930 u32 type; 931 932 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE); 933 934 switch (func) { 935 case UFS_ABORT_TASK: 936 case UFS_QUERY_TASK: 937 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE); 938 break; 939 case UFS_ABORT_TASK_SET: 940 case UFS_CLEAR_TASK_SET: 941 case UFS_LOGICAL_RESET: 942 case UFS_QUERY_TASK_SET: 943 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE); 944 break; 945 } 946} 947 948static int exynos_ufs_phy_init(struct exynos_ufs *ufs) 949{ 950 struct ufs_hba *hba = ufs->hba; 951 struct phy *generic_phy = ufs->phy; 952 int ret = 0; 953 954 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { 955 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), 956 &ufs->avail_ln_rx); 957 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), 958 &ufs->avail_ln_tx); 959 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, 960 "available data lane is not equal(rx:%d, tx:%d)\n", 961 ufs->avail_ln_rx, ufs->avail_ln_tx); 962 } 963 964 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); 965 966 if (generic_phy->power_count) { 967 phy_power_off(generic_phy); 968 phy_exit(generic_phy); 969 } 970 971 ret = phy_init(generic_phy); 972 if (ret) { 973 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 974 __func__, ret); 975 return ret; 976 } 977 978 ret = phy_power_on(generic_phy); 979 if (ret) 980 goto out_exit_phy; 981 982 return 0; 983 984out_exit_phy: 985 phy_exit(generic_phy); 986 987 return ret; 988} 989 990static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) 991{ 992 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 993 struct ufs_hba *hba = ufs->hba; 994 995 if (attr->pa_dbg_clk_period_off) 996 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 997 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 998 999 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), 1000 ufs->drv_data->uic_attr->tx_trailingclks); 1001 1002 if (attr->pa_dbg_opt_suite1_off) 1003 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 1004 attr->pa_dbg_opt_suite1_val); 1005 1006 if (attr->pa_dbg_opt_suite2_off) 1007 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), 1008 attr->pa_dbg_opt_suite2_val); 1009} 1010 1011static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) 1012{ 1013 switch (index) { 1014 case UNIPRO_L1_5: 1015 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER); 1016 break; 1017 case UNIPRO_L2: 1018 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER); 1019 break; 1020 case UNIPRO_L3: 1021 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER); 1022 break; 1023 case UNIPRO_L4: 1024 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER); 1025 break; 1026 case UNIPRO_DME: 1027 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER); 1028 break; 1029 } 1030} 1031 1032static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on, 1033 enum ufs_notify_change_status status) 1034{ 1035 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1036 1037 if (!ufs) 1038 return 0; 1039 1040 if (on && status == PRE_CHANGE) { 1041 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1042 exynos_ufs_disable_auto_ctrl_hcc(ufs); 1043 exynos_ufs_ungate_clks(ufs); 1044 } else if (!on && status == POST_CHANGE) { 1045 exynos_ufs_gate_clks(ufs); 1046 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1047 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1048 } 1049 1050 return 0; 1051} 1052 1053static int exynos_ufs_pre_link(struct ufs_hba *hba) 1054{ 1055 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1056 1057 /* hci */ 1058 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2); 1059 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3); 1060 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4); 1061 exynos_ufs_set_unipro_pclk_div(ufs); 1062 1063 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); 1064 1065 /* unipro */ 1066 exynos_ufs_config_unipro(ufs); 1067 1068 if (ufs->drv_data->pre_link) 1069 ufs->drv_data->pre_link(ufs); 1070 1071 /* m-phy */ 1072 exynos_ufs_phy_init(ufs); 1073 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { 1074 exynos_ufs_config_phy_time_attr(ufs); 1075 exynos_ufs_config_phy_cap_attr(ufs); 1076 } 1077 1078 return 0; 1079} 1080 1081static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) 1082{ 1083 u32 val; 1084 1085 /* Select function clock (mclk) for timer tick */ 1086 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { 1087 val = hci_readl(ufs, HCI_V2P1_CTRL); 1088 val |= IA_TICK_SEL; 1089 hci_writel(ufs, val, HCI_V2P1_CTRL); 1090 } 1091 1092 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); 1093 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); 1094} 1095 1096static int exynos_ufs_post_link(struct ufs_hba *hba) 1097{ 1098 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1099 struct phy *generic_phy = ufs->phy; 1100 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1101 u32 val = ilog2(DATA_UNIT_SIZE); 1102 1103 exynos_ufs_establish_connt(ufs); 1104 exynos_ufs_fit_aggr_timeout(ufs); 1105 1106 hci_writel(ufs, 0xa, HCI_DATA_REORDER); 1107 1108 if (hba->caps & UFSHCD_CAP_CRYPTO) 1109 val |= PRDT_PREFETCH_EN; 1110 hci_writel(ufs, val, HCI_TXPRDT_ENTRY_SIZE); 1111 1112 hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_RXPRDT_ENTRY_SIZE); 1113 hci_writel(ufs, BIT(hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); 1114 hci_writel(ufs, BIT(hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); 1115 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); 1116 1117 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) 1118 ufshcd_dme_set(hba, 1119 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true); 1120 1121 if (attr->pa_granularity) { 1122 exynos_ufs_enable_dbg_mode(hba); 1123 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), 1124 attr->pa_granularity); 1125 exynos_ufs_disable_dbg_mode(hba); 1126 1127 if (attr->pa_tactivate) 1128 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1129 attr->pa_tactivate); 1130 if (attr->pa_hibern8time && 1131 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) 1132 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1133 attr->pa_hibern8time); 1134 } 1135 1136 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1137 if (!attr->pa_granularity) 1138 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 1139 &attr->pa_granularity); 1140 if (!attr->pa_hibern8time) 1141 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1142 &attr->pa_hibern8time); 1143 /* 1144 * not wait for HIBERN8 time to exit hibernation 1145 */ 1146 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); 1147 1148 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { 1149 /* Valid range for granularity: 1 ~ 6 */ 1150 dev_warn(hba->dev, 1151 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n", 1152 __func__, 1153 attr->pa_granularity); 1154 attr->pa_granularity = 6; 1155 } 1156 } 1157 1158 phy_calibrate(generic_phy); 1159 1160 if (ufs->drv_data->post_link) 1161 ufs->drv_data->post_link(ufs); 1162 1163 return 0; 1164} 1165 1166static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs) 1167{ 1168 struct device_node *np = dev->of_node; 1169 struct exynos_ufs_uic_attr *attr; 1170 int ret = 0; 1171 1172 ufs->drv_data = device_get_match_data(dev); 1173 1174 if (ufs->drv_data && ufs->drv_data->uic_attr) { 1175 attr = ufs->drv_data->uic_attr; 1176 } else { 1177 dev_err(dev, "failed to get uic attributes\n"); 1178 ret = -EINVAL; 1179 goto out; 1180 } 1181 1182 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); 1183 if (IS_ERR(ufs->sysreg)) 1184 ufs->sysreg = NULL; 1185 else { 1186 if (of_property_read_u32_index(np, "samsung,sysreg", 1, 1187 &ufs->iocc_offset)) { 1188 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n"); 1189 ufs->iocc_offset = UFS_SHAREABILITY_OFFSET; 1190 } 1191 } 1192 1193 ufs->iocc_mask = ufs->drv_data->iocc_mask; 1194 /* 1195 * no 'dma-coherent' property means the descriptors are 1196 * non-cacheable so iocc shareability should be disabled. 1197 */ 1198 if (of_dma_is_coherent(dev->of_node)) 1199 ufs->iocc_val = ufs->iocc_mask; 1200 else 1201 ufs->iocc_val = 0; 1202 1203 ufs->pclk_avail_min = PCLK_AVAIL_MIN; 1204 ufs->pclk_avail_max = PCLK_AVAIL_MAX; 1205 1206 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; 1207 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; 1208 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; 1209 attr->pa_granularity = PA_GRANULARITY_VAL; 1210 attr->pa_tactivate = PA_TACTIVATE_VAL; 1211 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; 1212 1213out: 1214 return ret; 1215} 1216 1217static inline void exynos_ufs_priv_init(struct ufs_hba *hba, 1218 struct exynos_ufs *ufs) 1219{ 1220 ufs->hba = hba; 1221 ufs->opts = ufs->drv_data->opts; 1222 ufs->rx_sel_idx = PA_MAXDATALANES; 1223 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) 1224 ufs->rx_sel_idx = 0; 1225 hba->priv = (void *)ufs; 1226 hba->quirks = ufs->drv_data->quirks; 1227} 1228 1229#ifdef CONFIG_SCSI_UFS_CRYPTO 1230 1231/* 1232 * Support for Flash Memory Protector (FMP), which is the inline encryption 1233 * hardware on Exynos and Exynos-based SoCs. The interface to this hardware is 1234 * not compatible with the standard UFS crypto. It requires that encryption be 1235 * configured in the PRDT using a nonstandard extension. 1236 */ 1237 1238enum fmp_crypto_algo_mode { 1239 FMP_BYPASS_MODE = 0, 1240 FMP_ALGO_MODE_AES_CBC = 1, 1241 FMP_ALGO_MODE_AES_XTS = 2, 1242}; 1243enum fmp_crypto_key_length { 1244 FMP_KEYLEN_256BIT = 1, 1245}; 1246 1247/** 1248 * struct fmp_sg_entry - nonstandard format of PRDT entries when FMP is enabled 1249 * 1250 * @base: The standard PRDT entry, but with nonstandard bitfields in the high 1251 * bits of the 'size' field, i.e. the last 32-bit word. When these 1252 * nonstandard bitfields are zero, the data segment won't be encrypted or 1253 * decrypted. Otherwise they specify the algorithm and key length with 1254 * which the data segment will be encrypted or decrypted. 1255 * @file_iv: The initialization vector (IV) with all bytes reversed 1256 * @file_enckey: The first half of the AES-XTS key with all bytes reserved 1257 * @file_twkey: The second half of the AES-XTS key with all bytes reserved 1258 * @disk_iv: Unused 1259 * @reserved: Unused 1260 */ 1261struct fmp_sg_entry { 1262 struct ufshcd_sg_entry base; 1263 __be64 file_iv[2]; 1264 __be64 file_enckey[4]; 1265 __be64 file_twkey[4]; 1266 __be64 disk_iv[2]; 1267 __be64 reserved[2]; 1268}; 1269 1270#define SMC_CMD_FMP_SECURITY \ 1271 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1272 ARM_SMCCC_OWNER_SIP, 0x1810) 1273#define SMC_CMD_SMU \ 1274 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1275 ARM_SMCCC_OWNER_SIP, 0x1850) 1276#define SMC_CMD_FMP_SMU_RESUME \ 1277 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1278 ARM_SMCCC_OWNER_SIP, 0x1860) 1279#define SMU_EMBEDDED 0 1280#define SMU_INIT 0 1281#define CFG_DESCTYPE_3 3 1282 1283static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) 1284{ 1285 struct blk_crypto_profile *profile = &hba->crypto_profile; 1286 struct arm_smccc_res res; 1287 int err; 1288 1289 /* 1290 * Check for the standard crypto support bit, since it's available even 1291 * though the rest of the interface to FMP is nonstandard. 1292 * 1293 * This check should have the effect of preventing the driver from 1294 * trying to use FMP on old Exynos SoCs that don't have FMP. 1295 */ 1296 if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) & 1297 MASK_CRYPTO_SUPPORT)) 1298 return; 1299 1300 /* 1301 * The below sequence of SMC calls to enable FMP can be found in the 1302 * downstream driver source for gs101 and other Exynos-based SoCs. It 1303 * is the only way to enable FMP that works on SoCs such as gs101 that 1304 * don't make the FMP registers accessible to Linux. It probably works 1305 * on other Exynos-based SoCs too, and might even still be the only way 1306 * that works. But this hasn't been properly tested, and this code is 1307 * mutually exclusive with exynos_ufs_config_smu(). So for now only 1308 * enable FMP support on SoCs with EXYNOS_UFS_OPT_UFSPR_SECURE. 1309 */ 1310 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) 1311 return; 1312 1313 /* 1314 * This call (which sets DESCTYPE to 0x3 in the FMPSECURITY0 register) 1315 * is needed to make the hardware use the larger PRDT entry size. 1316 */ 1317 BUILD_BUG_ON(sizeof(struct fmp_sg_entry) != 128); 1318 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3, 1319 0, 0, 0, 0, &res); 1320 if (res.a0) { 1321 dev_warn(hba->dev, 1322 "SMC_CMD_FMP_SECURITY failed on init: %ld. Disabling FMP support.\n", 1323 res.a0); 1324 return; 1325 } 1326 ufshcd_set_sg_entry_size(hba, sizeof(struct fmp_sg_entry)); 1327 1328 /* 1329 * This is needed to initialize FMP. Without it, errors occur when 1330 * inline encryption is used. 1331 */ 1332 arm_smccc_smc(SMC_CMD_SMU, SMU_INIT, SMU_EMBEDDED, 0, 0, 0, 0, 0, &res); 1333 if (res.a0) { 1334 dev_err(hba->dev, 1335 "SMC_CMD_SMU(SMU_INIT) failed: %ld. Disabling FMP support.\n", 1336 res.a0); 1337 return; 1338 } 1339 1340 /* Advertise crypto capabilities to the block layer. */ 1341 err = devm_blk_crypto_profile_init(hba->dev, profile, 0); 1342 if (err) { 1343 /* Only ENOMEM should be possible here. */ 1344 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n", 1345 err); 1346 return; 1347 } 1348 profile->max_dun_bytes_supported = AES_BLOCK_SIZE; 1349 profile->key_types_supported = BLK_CRYPTO_KEY_TYPE_RAW; 1350 profile->dev = hba->dev; 1351 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] = 1352 DATA_UNIT_SIZE; 1353 1354 /* Advertise crypto support to ufshcd-core. */ 1355 hba->caps |= UFSHCD_CAP_CRYPTO; 1356 1357 /* Advertise crypto quirks to ufshcd-core. */ 1358 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE | 1359 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE | 1360 UFSHCD_QUIRK_KEYS_IN_PRDT; 1361 1362} 1363 1364static void exynos_ufs_fmp_resume(struct ufs_hba *hba) 1365{ 1366 struct arm_smccc_res res; 1367 1368 if (!(hba->caps & UFSHCD_CAP_CRYPTO)) 1369 return; 1370 1371 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3, 1372 0, 0, 0, 0, &res); 1373 if (res.a0) 1374 dev_err(hba->dev, 1375 "SMC_CMD_FMP_SECURITY failed on resume: %ld\n", res.a0); 1376 1377 arm_smccc_smc(SMC_CMD_FMP_SMU_RESUME, 0, SMU_EMBEDDED, 0, 0, 0, 0, 0, 1378 &res); 1379 if (res.a0) 1380 dev_err(hba->dev, 1381 "SMC_CMD_FMP_SMU_RESUME failed: %ld\n", res.a0); 1382} 1383 1384static inline __be64 fmp_key_word(const u8 *key, int j) 1385{ 1386 return cpu_to_be64(get_unaligned_le64( 1387 key + AES_KEYSIZE_256 - (j + 1) * sizeof(u64))); 1388} 1389 1390/* Fill the PRDT for a request according to the given encryption context. */ 1391static int exynos_ufs_fmp_fill_prdt(struct ufs_hba *hba, 1392 const struct bio_crypt_ctx *crypt_ctx, 1393 void *prdt, unsigned int num_segments) 1394{ 1395 struct fmp_sg_entry *fmp_prdt = prdt; 1396 const u8 *enckey = crypt_ctx->bc_key->bytes; 1397 const u8 *twkey = enckey + AES_KEYSIZE_256; 1398 u64 dun_lo = crypt_ctx->bc_dun[0]; 1399 u64 dun_hi = crypt_ctx->bc_dun[1]; 1400 unsigned int i; 1401 1402 /* If FMP wasn't enabled, we shouldn't get any encrypted requests. */ 1403 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO))) 1404 return -EIO; 1405 1406 /* Configure FMP on each segment of the request. */ 1407 for (i = 0; i < num_segments; i++) { 1408 struct fmp_sg_entry *prd = &fmp_prdt[i]; 1409 int j; 1410 1411 /* Each segment must be exactly one data unit. */ 1412 if (prd->base.size != cpu_to_le32(DATA_UNIT_SIZE - 1)) { 1413 dev_err(hba->dev, 1414 "data segment is misaligned for FMP\n"); 1415 return -EIO; 1416 } 1417 1418 /* Set the algorithm and key length. */ 1419 prd->base.size |= cpu_to_le32((FMP_ALGO_MODE_AES_XTS << 28) | 1420 (FMP_KEYLEN_256BIT << 26)); 1421 1422 /* Set the IV. */ 1423 prd->file_iv[0] = cpu_to_be64(dun_hi); 1424 prd->file_iv[1] = cpu_to_be64(dun_lo); 1425 1426 /* Set the key. */ 1427 for (j = 0; j < AES_KEYSIZE_256 / sizeof(u64); j++) { 1428 prd->file_enckey[j] = fmp_key_word(enckey, j); 1429 prd->file_twkey[j] = fmp_key_word(twkey, j); 1430 } 1431 1432 /* Increment the data unit number. */ 1433 dun_lo++; 1434 if (dun_lo == 0) 1435 dun_hi++; 1436 } 1437 return 0; 1438} 1439 1440#else /* CONFIG_SCSI_UFS_CRYPTO */ 1441 1442static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) 1443{ 1444} 1445 1446static void exynos_ufs_fmp_resume(struct ufs_hba *hba) 1447{ 1448} 1449 1450#define exynos_ufs_fmp_fill_prdt NULL 1451 1452#endif /* !CONFIG_SCSI_UFS_CRYPTO */ 1453 1454static int exynos_ufs_init(struct ufs_hba *hba) 1455{ 1456 struct device *dev = hba->dev; 1457 struct platform_device *pdev = to_platform_device(dev); 1458 struct exynos_ufs *ufs; 1459 int ret; 1460 1461 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1462 if (!ufs) 1463 return -ENOMEM; 1464 1465 /* exynos-specific hci */ 1466 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1467 if (IS_ERR(ufs->reg_hci)) { 1468 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1469 return PTR_ERR(ufs->reg_hci); 1470 } 1471 1472 /* unipro */ 1473 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); 1474 if (IS_ERR(ufs->reg_unipro)) { 1475 dev_err(dev, "cannot ioremap for unipro register\n"); 1476 return PTR_ERR(ufs->reg_unipro); 1477 } 1478 1479 /* ufs protector */ 1480 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); 1481 if (IS_ERR(ufs->reg_ufsp)) { 1482 dev_err(dev, "cannot ioremap for ufs protector register\n"); 1483 return PTR_ERR(ufs->reg_ufsp); 1484 } 1485 1486 ret = exynos_ufs_parse_dt(dev, ufs); 1487 if (ret) { 1488 dev_err(dev, "failed to get dt info.\n"); 1489 goto out; 1490 } 1491 1492 ufs->phy = devm_phy_get(dev, "ufs-phy"); 1493 if (IS_ERR(ufs->phy)) { 1494 ret = PTR_ERR(ufs->phy); 1495 dev_err(dev, "failed to get ufs-phy\n"); 1496 goto out; 1497 } 1498 1499 exynos_ufs_priv_init(hba, ufs); 1500 1501 exynos_ufs_fmp_init(hba, ufs); 1502 1503 if (ufs->drv_data->drv_init) { 1504 ret = ufs->drv_data->drv_init(ufs); 1505 if (ret) { 1506 dev_err(dev, "failed to init drv-data\n"); 1507 goto out; 1508 } 1509 } 1510 1511 ret = exynos_ufs_get_clk_info(ufs); 1512 if (ret) 1513 goto out; 1514 exynos_ufs_specify_phy_time_attr(ufs); 1515 1516 exynos_ufs_config_smu(ufs); 1517 1518 hba->host->dma_alignment = DATA_UNIT_SIZE - 1; 1519 return 0; 1520 1521out: 1522 hba->priv = NULL; 1523 return ret; 1524} 1525 1526static void exynos_ufs_exit(struct ufs_hba *hba) 1527{ 1528 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1529 1530 phy_power_off(ufs->phy); 1531 phy_exit(ufs->phy); 1532} 1533 1534static int exynos_ufs_host_reset(struct ufs_hba *hba) 1535{ 1536 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1537 unsigned long timeout = jiffies + msecs_to_jiffies(1); 1538 u32 val; 1539 int ret = 0; 1540 1541 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 1542 1543 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST); 1544 1545 do { 1546 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK)) 1547 goto out; 1548 } while (time_before(jiffies, timeout)); 1549 1550 dev_err(hba->dev, "timeout host sw-reset\n"); 1551 ret = -ETIMEDOUT; 1552 1553out: 1554 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 1555 return ret; 1556} 1557 1558static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) 1559{ 1560 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1561 1562 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); 1563 udelay(5); 1564 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT); 1565} 1566 1567static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) 1568{ 1569 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1570 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1571 1572 if (cmd == UIC_CMD_DME_HIBER_EXIT) { 1573 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1574 exynos_ufs_disable_auto_ctrl_hcc(ufs); 1575 exynos_ufs_ungate_clks(ufs); 1576 1577 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1578 static const unsigned int granularity_tbl[] = { 1579 1, 4, 8, 16, 32, 100 1580 }; 1581 int h8_time = attr->pa_hibern8time * 1582 granularity_tbl[attr->pa_granularity - 1]; 1583 unsigned long us; 1584 s64 delta; 1585 1586 do { 1587 delta = h8_time - ktime_us_delta(ktime_get(), 1588 ufs->entry_hibern8_t); 1589 if (delta <= 0) 1590 break; 1591 1592 us = min_t(s64, delta, USEC_PER_MSEC); 1593 if (us >= 10) 1594 usleep_range(us, us + 10); 1595 } while (1); 1596 } 1597 } 1598} 1599 1600static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) 1601{ 1602 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1603 1604 if (cmd == UIC_CMD_DME_HIBER_ENTER) { 1605 ufs->entry_hibern8_t = ktime_get(); 1606 exynos_ufs_gate_clks(ufs); 1607 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1608 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1609 } 1610} 1611 1612static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, 1613 enum ufs_notify_change_status status) 1614{ 1615 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1616 int ret = 0; 1617 1618 switch (status) { 1619 case PRE_CHANGE: 1620 /* 1621 * The maximum segment size must be set after scsi_host_alloc() 1622 * has been called and before LUN scanning starts 1623 * (ufshcd_async_scan()). Note: this callback may also be called 1624 * from other functions than ufshcd_init(). 1625 */ 1626 hba->host->max_segment_size = DATA_UNIT_SIZE; 1627 1628 if (ufs->drv_data->pre_hce_enable) { 1629 ret = ufs->drv_data->pre_hce_enable(ufs); 1630 if (ret) 1631 return ret; 1632 } 1633 1634 ret = exynos_ufs_host_reset(hba); 1635 if (ret) 1636 return ret; 1637 exynos_ufs_dev_hw_reset(hba); 1638 break; 1639 case POST_CHANGE: 1640 exynos_ufs_calc_pwm_clk_div(ufs); 1641 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) 1642 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1643 1644 if (ufs->drv_data->post_hce_enable) 1645 ret = ufs->drv_data->post_hce_enable(ufs); 1646 1647 break; 1648 } 1649 1650 return ret; 1651} 1652 1653static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, 1654 enum ufs_notify_change_status status) 1655{ 1656 int ret = 0; 1657 1658 switch (status) { 1659 case PRE_CHANGE: 1660 ret = exynos_ufs_pre_link(hba); 1661 break; 1662 case POST_CHANGE: 1663 ret = exynos_ufs_post_link(hba); 1664 break; 1665 } 1666 1667 return ret; 1668} 1669 1670static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, 1671 enum ufs_notify_change_status status, 1672 const struct ufs_pa_layer_attr *dev_max_params, 1673 struct ufs_pa_layer_attr *dev_req_params) 1674{ 1675 int ret = 0; 1676 1677 switch (status) { 1678 case PRE_CHANGE: 1679 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, 1680 dev_req_params); 1681 break; 1682 case POST_CHANGE: 1683 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); 1684 break; 1685 } 1686 1687 return ret; 1688} 1689 1690static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, 1691 enum uic_cmd_dme cmd, 1692 enum ufs_notify_change_status notify) 1693{ 1694 switch ((u8)notify) { 1695 case PRE_CHANGE: 1696 exynos_ufs_pre_hibern8(hba, cmd); 1697 break; 1698 case POST_CHANGE: 1699 exynos_ufs_post_hibern8(hba, cmd); 1700 break; 1701 } 1702} 1703 1704static int gs101_ufs_suspend(struct exynos_ufs *ufs) 1705{ 1706 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); 1707 return 0; 1708} 1709 1710static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 1711 enum ufs_notify_change_status status) 1712{ 1713 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1714 1715 if (status == PRE_CHANGE) 1716 return 0; 1717 1718 if (ufs->drv_data->suspend) 1719 ufs->drv_data->suspend(ufs); 1720 1721 if (!ufshcd_is_link_active(hba)) 1722 phy_power_off(ufs->phy); 1723 1724 return 0; 1725} 1726 1727static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 1728{ 1729 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1730 1731 if (!ufshcd_is_link_active(hba)) 1732 phy_power_on(ufs->phy); 1733 1734 exynos_ufs_config_smu(ufs); 1735 exynos_ufs_fmp_resume(hba); 1736 return 0; 1737} 1738 1739static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba, 1740 enum ufs_notify_change_status status) 1741{ 1742 if (status == POST_CHANGE) { 1743 ufshcd_set_link_active(hba); 1744 ufshcd_set_ufs_dev_active(hba); 1745 } 1746 1747 return 0; 1748} 1749 1750static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba) 1751{ 1752 u32 mbox; 1753 ktime_t start, stop; 1754 1755 start = ktime_get(); 1756 stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS)); 1757 1758 do { 1759 mbox = ufshcd_readl(hba, PH2VH_MBOX); 1760 /* TODO: Mailbox message protocols between the PH and VHs are 1761 * not implemented yet. This will be supported later 1762 */ 1763 if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY) 1764 return 0; 1765 1766 usleep_range(40, 50); 1767 } while (ktime_before(ktime_get(), stop)); 1768 1769 return -ETIME; 1770} 1771 1772static int exynosauto_ufs_vh_init(struct ufs_hba *hba) 1773{ 1774 struct device *dev = hba->dev; 1775 struct platform_device *pdev = to_platform_device(dev); 1776 struct exynos_ufs *ufs; 1777 int ret; 1778 1779 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1780 if (!ufs) 1781 return -ENOMEM; 1782 1783 /* exynos-specific hci */ 1784 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1785 if (IS_ERR(ufs->reg_hci)) { 1786 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1787 return PTR_ERR(ufs->reg_hci); 1788 } 1789 1790 ret = exynosauto_ufs_vh_wait_ph_ready(hba); 1791 if (ret) 1792 return ret; 1793 1794 ufs->drv_data = device_get_match_data(dev); 1795 if (!ufs->drv_data) 1796 return -ENODEV; 1797 1798 exynos_ufs_priv_init(hba, ufs); 1799 1800 return 0; 1801} 1802 1803static int fsd_ufs_pre_link(struct exynos_ufs *ufs) 1804{ 1805 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1806 struct ufs_hba *hba = ufs->hba; 1807 int i; 1808 1809 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 1810 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1811 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); 1812 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1813 1814 for_each_ufs_tx_lane(ufs, i) { 1815 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1816 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1817 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); 1818 } 1819 1820 for_each_ufs_rx_lane(ufs, i) { 1821 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1822 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1823 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); 1824 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); 1825 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); 1826 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); 1827 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); 1828 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); 1829 } 1830 1831 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1832 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); 1833 1834 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 1835 0x2e820183); 1836 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1837 1838 exynos_ufs_establish_connt(ufs); 1839 1840 return 0; 1841} 1842 1843static int fsd_ufs_post_link(struct exynos_ufs *ufs) 1844{ 1845 int i; 1846 struct ufs_hba *hba = ufs->hba; 1847 u32 hw_cap_min_tactivate; 1848 u32 peer_rx_min_actv_time_cap; 1849 u32 max_rx_hibern8_time_cap; 1850 1851 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), 1852 &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */ 1853 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 1854 &peer_rx_min_actv_time_cap); /* PA_TActivate */ 1855 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1856 &max_rx_hibern8_time_cap); /* PA_Hibern8Time */ 1857 1858 if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate) 1859 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1860 peer_rx_min_actv_time_cap + 1); 1861 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1); 1862 1863 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01); 1864 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA); 1865 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00); 1866 1867 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1868 1869 for_each_ufs_rx_lane(ufs, i) { 1870 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); 1871 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); 1872 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); 1873 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); 1874 } 1875 1876 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1877 1878 return 0; 1879} 1880 1881static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1882 struct ufs_pa_layer_attr *pwr) 1883{ 1884 struct ufs_hba *hba = ufs->hba; 1885 1886 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1); 1887 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1); 1888 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1889 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1890 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1891 1892 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1893 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1894 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1895 1896 return 0; 1897} 1898 1899static int fsd_ufs_suspend(struct exynos_ufs *ufs) 1900{ 1901 exynos_ufs_gate_clks(ufs); 1902 hci_writel(ufs, 0, HCI_GPIO_OUT); 1903 return 0; 1904} 1905 1906static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs) 1907{ 1908 return (16 * 1000 * 1000000UL / ufs->mclk_rate); 1909} 1910 1911static int gs101_ufs_pre_link(struct exynos_ufs *ufs) 1912{ 1913 struct ufs_hba *hba = ufs->hba; 1914 int i; 1915 u32 tx_line_reset_period, rx_line_reset_period; 1916 1917 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) 1918 / NSEC_PER_MSEC; 1919 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) 1920 / NSEC_PER_MSEC; 1921 1922 unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD); 1923 1924 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1925 1926 for_each_ufs_rx_lane(ufs, i) { 1927 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 1928 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1929 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 1930 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 1931 (rx_line_reset_period >> 16) & 0xFF); 1932 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 1933 (rx_line_reset_period >> 8) & 0xFF); 1934 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 1935 (rx_line_reset_period) & 0xFF); 1936 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); 1937 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 1938 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 1939 } 1940 1941 for_each_ufs_tx_lane(ufs, i) { 1942 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 1943 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1944 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 1945 0x02); 1946 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 1947 (tx_line_reset_period >> 16) & 0xFF); 1948 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 1949 (tx_line_reset_period >> 8) & 0xFF); 1950 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 1951 (tx_line_reset_period) & 0xFF); 1952 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1); 1953 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0); 1954 } 1955 1956 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1957 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1958 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0); 1959 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1); 1960 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1); 1961 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 1962 ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000); 1963 1964 return 0; 1965} 1966 1967static int gs101_ufs_post_link(struct exynos_ufs *ufs) 1968{ 1969 struct ufs_hba *hba = ufs->hba; 1970 1971 /* 1972 * Enable Write Line Unique. This field has to be 0x3 1973 * to support Write Line Unique transaction on gs101. 1974 */ 1975 hci_writel(ufs, WLU_EN | WLU_BURST_LEN(3), HCI_AXIDMA_RWDATA_BURST_LEN); 1976 1977 exynos_ufs_enable_dbg_mode(hba); 1978 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); 1979 exynos_ufs_disable_dbg_mode(hba); 1980 1981 return 0; 1982} 1983 1984static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1985 struct ufs_pa_layer_attr *pwr) 1986{ 1987 struct ufs_hba *hba = ufs->hba; 1988 1989 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1990 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1991 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1992 unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0); 1993 unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1); 1994 unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2); 1995 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1996 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1997 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1998 1999 return 0; 2000} 2001 2002static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = { 2003 .name = "exynos_ufs", 2004 .init = exynos_ufs_init, 2005 .exit = exynos_ufs_exit, 2006 .hce_enable_notify = exynos_ufs_hce_enable_notify, 2007 .link_startup_notify = exynos_ufs_link_startup_notify, 2008 .pwr_change_notify = exynos_ufs_pwr_change_notify, 2009 .setup_clocks = exynos_ufs_setup_clocks, 2010 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req, 2011 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req, 2012 .hibern8_notify = exynos_ufs_hibern8_notify, 2013 .suspend = exynos_ufs_suspend, 2014 .resume = exynos_ufs_resume, 2015 .fill_crypto_prdt = exynos_ufs_fmp_fill_prdt, 2016}; 2017 2018static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = { 2019 .name = "exynosauto_ufs_vh", 2020 .init = exynosauto_ufs_vh_init, 2021 .link_startup_notify = exynosauto_ufs_vh_link_startup_notify, 2022}; 2023 2024static int exynos_ufs_probe(struct platform_device *pdev) 2025{ 2026 int err; 2027 struct device *dev = &pdev->dev; 2028 const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops; 2029 const struct exynos_ufs_drv_data *drv_data = 2030 device_get_match_data(dev); 2031 2032 if (drv_data && drv_data->vops) 2033 vops = drv_data->vops; 2034 2035 err = ufshcd_pltfrm_init(pdev, vops); 2036 if (err) 2037 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); 2038 2039 return err; 2040} 2041 2042static void exynos_ufs_remove(struct platform_device *pdev) 2043{ 2044 ufshcd_pltfrm_remove(pdev); 2045} 2046 2047static struct exynos_ufs_uic_attr exynos7_uic_attr = { 2048 .tx_trailingclks = 0x10, 2049 .tx_dif_p_nsec = 3000000, /* unit: ns */ 2050 .tx_dif_n_nsec = 1000000, /* unit: ns */ 2051 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 2052 .tx_base_unit_nsec = 100000, /* unit: ns */ 2053 .tx_gran_unit_nsec = 4000, /* unit: ns */ 2054 .tx_sleep_cnt = 1000, /* unit: ns */ 2055 .tx_min_activatetime = 0xa, 2056 .rx_filler_enable = 0x2, 2057 .rx_dif_p_nsec = 1000000, /* unit: ns */ 2058 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 2059 .rx_base_unit_nsec = 100000, /* unit: ns */ 2060 .rx_gran_unit_nsec = 4000, /* unit: ns */ 2061 .rx_sleep_cnt = 1280, /* unit: ns */ 2062 .rx_stall_cnt = 320, /* unit: ns */ 2063 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 2064 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 2065 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 2066 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 2067 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 2068 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 2069 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 2070 .pa_dbg_opt_suite1_val = 0x30103, 2071 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 2072}; 2073 2074static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = { 2075 .uic_attr = &exynos7_uic_attr, 2076 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2077 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2078 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2079 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2080 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2081 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2082 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2083 .iocc_mask = UFS_EXYNOSAUTO_SHARABLE, 2084 .drv_init = exynosauto_ufs_drv_init, 2085 .post_hce_enable = exynosauto_ufs_post_hce_enable, 2086 .pre_link = exynosauto_ufs_pre_link, 2087 .pre_pwr_change = exynosauto_ufs_pre_pwr_change, 2088 .post_pwr_change = exynosauto_ufs_post_pwr_change, 2089}; 2090 2091static const struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = { 2092 .vops = &ufs_hba_exynosauto_vh_ops, 2093 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2094 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2095 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2096 UFSHCI_QUIRK_BROKEN_HCE | 2097 UFSHCD_QUIRK_BROKEN_UIC_CMD | 2098 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION | 2099 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2100 .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2101}; 2102 2103static const struct exynos_ufs_drv_data exynos_ufs_drvs = { 2104 .uic_attr = &exynos7_uic_attr, 2105 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2106 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2107 UFSHCI_QUIRK_BROKEN_HCE | 2108 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2109 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2110 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 2111 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2112 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 2113 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2114 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX | 2115 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB | 2116 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER, 2117 .pre_link = exynos7_ufs_pre_link, 2118 .post_link = exynos7_ufs_post_link, 2119 .pre_pwr_change = exynos7_ufs_pre_pwr_change, 2120 .post_pwr_change = exynos7_ufs_post_pwr_change, 2121}; 2122 2123static struct exynos_ufs_uic_attr gs101_uic_attr = { 2124 .tx_trailingclks = 0xff, 2125 .pa_dbg_opt_suite1_val = 0x90913C1C, 2126 .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1, 2127 .pa_dbg_opt_suite2_val = 0xE01C115F, 2128 .pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2, 2129}; 2130 2131static struct exynos_ufs_uic_attr fsd_uic_attr = { 2132 .tx_trailingclks = 0x10, 2133 .tx_dif_p_nsec = 3000000, /* unit: ns */ 2134 .tx_dif_n_nsec = 1000000, /* unit: ns */ 2135 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 2136 .tx_base_unit_nsec = 100000, /* unit: ns */ 2137 .tx_gran_unit_nsec = 4000, /* unit: ns */ 2138 .tx_sleep_cnt = 1000, /* unit: ns */ 2139 .tx_min_activatetime = 0xa, 2140 .rx_filler_enable = 0x2, 2141 .rx_dif_p_nsec = 1000000, /* unit: ns */ 2142 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 2143 .rx_base_unit_nsec = 100000, /* unit: ns */ 2144 .rx_gran_unit_nsec = 4000, /* unit: ns */ 2145 .rx_sleep_cnt = 1280, /* unit: ns */ 2146 .rx_stall_cnt = 320, /* unit: ns */ 2147 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 2148 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 2149 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 2150 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 2151 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 2152 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 2153 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 2154 .pa_dbg_opt_suite1_val = 0x2E820183, 2155 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 2156}; 2157 2158static const struct exynos_ufs_drv_data fsd_ufs_drvs = { 2159 .uic_attr = &fsd_uic_attr, 2160 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2161 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2162 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2163 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING | 2164 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR, 2165 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 2166 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2167 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2168 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2169 .pre_link = fsd_ufs_pre_link, 2170 .post_link = fsd_ufs_post_link, 2171 .pre_pwr_change = fsd_ufs_pre_pwr_change, 2172 .suspend = fsd_ufs_suspend, 2173}; 2174 2175static const struct exynos_ufs_drv_data gs101_ufs_drvs = { 2176 .uic_attr = &gs101_uic_attr, 2177 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2178 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2179 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2180 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2181 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 2182 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2183 .opts = EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2184 EXYNOS_UFS_OPT_UFSPR_SECURE | 2185 EXYNOS_UFS_OPT_TIMER_TICK_SELECT, 2186 .iocc_mask = UFS_GS101_SHARABLE, 2187 .drv_init = gs101_ufs_drv_init, 2188 .pre_link = gs101_ufs_pre_link, 2189 .post_link = gs101_ufs_post_link, 2190 .pre_pwr_change = gs101_ufs_pre_pwr_change, 2191 .suspend = gs101_ufs_suspend, 2192}; 2193 2194static const struct of_device_id exynos_ufs_of_match[] = { 2195 { .compatible = "google,gs101-ufs", 2196 .data = &gs101_ufs_drvs }, 2197 { .compatible = "samsung,exynos7-ufs", 2198 .data = &exynos_ufs_drvs }, 2199 { .compatible = "samsung,exynosautov9-ufs", 2200 .data = &exynosauto_ufs_drvs }, 2201 { .compatible = "samsung,exynosautov9-ufs-vh", 2202 .data = &exynosauto_ufs_vh_drvs }, 2203 { .compatible = "tesla,fsd-ufs", 2204 .data = &fsd_ufs_drvs }, 2205 {}, 2206}; 2207MODULE_DEVICE_TABLE(of, exynos_ufs_of_match); 2208 2209static const struct dev_pm_ops exynos_ufs_pm_ops = { 2210 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) 2211 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2212 .prepare = ufshcd_suspend_prepare, 2213 .complete = ufshcd_resume_complete, 2214}; 2215 2216static struct platform_driver exynos_ufs_pltform = { 2217 .probe = exynos_ufs_probe, 2218 .remove = exynos_ufs_remove, 2219 .driver = { 2220 .name = "exynos-ufshc", 2221 .pm = &exynos_ufs_pm_ops, 2222 .of_match_table = exynos_ufs_of_match, 2223 }, 2224}; 2225module_platform_driver(exynos_ufs_pltform); 2226 2227MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>"); 2228MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>"); 2229MODULE_DESCRIPTION("Exynos UFS HCI Driver"); 2230MODULE_LICENSE("GPL v2");
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