ufshcd-crypto.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2019 Google LLC
  4 */
  5
  6#include <ufs/ufshcd.h>
  7#include "ufshcd-crypto.h"
  8
  9/* Blk-crypto modes supported by UFS crypto */
 10static const struct ufs_crypto_alg_entry {
 11	enum ufs_crypto_alg ufs_alg;
 12	enum ufs_crypto_key_size ufs_key_size;
 13} ufs_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
 14	[BLK_ENCRYPTION_MODE_AES_256_XTS] = {
 15		.ufs_alg = UFS_CRYPTO_ALG_AES_XTS,
 16		.ufs_key_size = UFS_CRYPTO_KEY_SIZE_256,
 17	},
 18};
 19
 20static void ufshcd_program_key(struct ufs_hba *hba,
 21			       const union ufs_crypto_cfg_entry *cfg, int slot)
 22{
 23	int i;
 24	u32 slot_offset = hba->crypto_cfg_register + slot * sizeof(*cfg);
 25
 26	ufshcd_hold(hba);
 27
 28	/* Ensure that CFGE is cleared before programming the key */
 29	ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
 30	for (i = 0; i < 16; i++) {
 31		ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),
 32			      slot_offset + i * sizeof(cfg->reg_val[0]));
 33	}
 34	/* Write dword 17 */
 35	ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),
 36		      slot_offset + 17 * sizeof(cfg->reg_val[0]));
 37	/* Dword 16 must be written last */
 38	ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),
 39		      slot_offset + 16 * sizeof(cfg->reg_val[0]));
 40	ufshcd_release(hba);
 41}
 42
 43static int ufshcd_crypto_keyslot_program(struct blk_crypto_profile *profile,
 44					 const struct blk_crypto_key *key,
 45					 unsigned int slot)
 46{
 47	struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
 48	const union ufs_crypto_cap_entry *ccap_array = hba->crypto_cap_array;
 49	const struct ufs_crypto_alg_entry *alg =
 50			&ufs_crypto_algs[key->crypto_cfg.crypto_mode];
 51	u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
 52	int i;
 53	int cap_idx = -1;
 54	union ufs_crypto_cfg_entry cfg = {};
 55
 56	BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
 57	for (i = 0; i < hba->crypto_capabilities.num_crypto_cap; i++) {
 58		if (ccap_array[i].algorithm_id == alg->ufs_alg &&
 59		    ccap_array[i].key_size == alg->ufs_key_size &&
 60		    (ccap_array[i].sdus_mask & data_unit_mask)) {
 61			cap_idx = i;
 62			break;
 63		}
 64	}
 65
 66	if (WARN_ON(cap_idx < 0))
 67		return -EOPNOTSUPP;
 68
 69	cfg.data_unit_size = data_unit_mask;
 70	cfg.crypto_cap_idx = cap_idx;
 71	cfg.config_enable = UFS_CRYPTO_CONFIGURATION_ENABLE;
 72
 73	if (ccap_array[cap_idx].algorithm_id == UFS_CRYPTO_ALG_AES_XTS) {
 74		/* In XTS mode, the blk_crypto_key's size is already doubled */
 75		memcpy(cfg.crypto_key, key->bytes, key->size/2);
 76		memcpy(cfg.crypto_key + UFS_CRYPTO_KEY_MAX_SIZE/2,
 77		       key->bytes + key->size/2, key->size/2);
 78	} else {
 79		memcpy(cfg.crypto_key, key->bytes, key->size);
 80	}
 81
 82	ufshcd_program_key(hba, &cfg, slot);
 83
 84	memzero_explicit(&cfg, sizeof(cfg));
 85	return 0;
 86}
 87
 88static int ufshcd_crypto_keyslot_evict(struct blk_crypto_profile *profile,
 89				       const struct blk_crypto_key *key,
 90				       unsigned int slot)
 91{
 92	struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile);
 93	/*
 94	 * Clear the crypto cfg on the device. Clearing CFGE
 95	 * might not be sufficient, so just clear the entire cfg.
 96	 */
 97	union ufs_crypto_cfg_entry cfg = {};
 98
 99	ufshcd_program_key(hba, &cfg, slot);
100	return 0;
101}
102
103/*
104 * Reprogram the keyslots if needed, and return true if CRYPTO_GENERAL_ENABLE
105 * should be used in the host controller initialization sequence.
106 */
107bool ufshcd_crypto_enable(struct ufs_hba *hba)
108{
109	if (!(hba->caps & UFSHCD_CAP_CRYPTO))
110		return false;
111
112	/* Reset might clear all keys, so reprogram all the keys. */
113	blk_crypto_reprogram_all_keys(&hba->crypto_profile);
114
115	if (hba->quirks & UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE)
116		return false;
117
118	return true;
119}
120
121static const struct blk_crypto_ll_ops ufshcd_crypto_ops = {
122	.keyslot_program	= ufshcd_crypto_keyslot_program,
123	.keyslot_evict		= ufshcd_crypto_keyslot_evict,
124};
125
126static enum blk_crypto_mode_num
127ufshcd_find_blk_crypto_mode(union ufs_crypto_cap_entry cap)
128{
129	int i;
130
131	for (i = 0; i < ARRAY_SIZE(ufs_crypto_algs); i++) {
132		BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
133		if (ufs_crypto_algs[i].ufs_alg == cap.algorithm_id &&
134		    ufs_crypto_algs[i].ufs_key_size == cap.key_size) {
135			return i;
136		}
137	}
138	return BLK_ENCRYPTION_MODE_INVALID;
139}
140
141/**
142 * ufshcd_hba_init_crypto_capabilities - Read crypto capabilities, init crypto
143 *					 fields in hba
144 * @hba: Per adapter instance
145 *
146 * Return: 0 if crypto was initialized or is not supported, else a -errno value.
147 */
148int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba)
149{
150	int cap_idx;
151	int err = 0;
152	enum blk_crypto_mode_num blk_mode_num;
153
154	if (hba->quirks & UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE)
155		return 0;
156
157	/*
158	 * Don't use crypto if either the hardware doesn't advertise the
159	 * standard crypto capability bit *or* if the vendor specific driver
160	 * hasn't advertised that crypto is supported.
161	 */
162	if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) ||
163	    !(hba->caps & UFSHCD_CAP_CRYPTO))
164		goto out;
165
166	hba->crypto_capabilities.reg_val =
167			cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
168	hba->crypto_cfg_register =
169		(u32)hba->crypto_capabilities.config_array_ptr * 0x100;
170	hba->crypto_cap_array =
171		devm_kcalloc(hba->dev, hba->crypto_capabilities.num_crypto_cap,
172			     sizeof(hba->crypto_cap_array[0]), GFP_KERNEL);
173	if (!hba->crypto_cap_array) {
174		err = -ENOMEM;
175		goto out;
176	}
177
178	/* The actual number of configurations supported is (CFGC+1) */
179	err = devm_blk_crypto_profile_init(
180			hba->dev, &hba->crypto_profile,
181			hba->crypto_capabilities.config_count + 1);
182	if (err)
183		goto out;
184
185	hba->crypto_profile.ll_ops = ufshcd_crypto_ops;
186	/* UFS only supports 8 bytes for any DUN */
187	hba->crypto_profile.max_dun_bytes_supported = 8;
188	hba->crypto_profile.key_types_supported = BLK_CRYPTO_KEY_TYPE_RAW;
189	hba->crypto_profile.dev = hba->dev;
190
191	/*
192	 * Cache all the UFS crypto capabilities and advertise the supported
193	 * crypto modes and data unit sizes to the block layer.
194	 */
195	for (cap_idx = 0; cap_idx < hba->crypto_capabilities.num_crypto_cap;
196	     cap_idx++) {
197		hba->crypto_cap_array[cap_idx].reg_val =
198			cpu_to_le32(ufshcd_readl(hba,
199						 REG_UFS_CRYPTOCAP +
200						 cap_idx * sizeof(__le32)));
201		blk_mode_num = ufshcd_find_blk_crypto_mode(
202						hba->crypto_cap_array[cap_idx]);
203		if (blk_mode_num != BLK_ENCRYPTION_MODE_INVALID)
204			hba->crypto_profile.modes_supported[blk_mode_num] |=
205				hba->crypto_cap_array[cap_idx].sdus_mask * 512;
206	}
207
208	return 0;
209
210out:
211	/* Indicate that init failed by clearing UFSHCD_CAP_CRYPTO */
212	hba->caps &= ~UFSHCD_CAP_CRYPTO;
213	return err;
214}
215
216/**
217 * ufshcd_init_crypto - Initialize crypto hardware
218 * @hba: Per adapter instance
219 */
220void ufshcd_init_crypto(struct ufs_hba *hba)
221{
222	int slot;
223
224	if (!(hba->caps & UFSHCD_CAP_CRYPTO))
225		return;
226
227	/* Clear all keyslots. */
228	for (slot = 0; slot < hba->crypto_profile.num_slots; slot++)
229		hba->crypto_profile.ll_ops.keyslot_evict(&hba->crypto_profile,
230							 NULL, slot);
231}
232
233void ufshcd_crypto_register(struct ufs_hba *hba, struct request_queue *q)
234{
235	if (hba->caps & UFSHCD_CAP_CRYPTO)
236		blk_crypto_register(&hba->crypto_profile, q);
237}