sifive.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * SiFive UART driver
   4 * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com>
   5 * Copyright (C) 2018-2019 SiFive
   6 *
   7 * Based partially on:
   8 * - drivers/tty/serial/pxa.c
   9 * - drivers/tty/serial/amba-pl011.c
  10 * - drivers/tty/serial/uartlite.c
  11 * - drivers/tty/serial/omap-serial.c
  12 * - drivers/pwm/pwm-sifive.c
  13 *
  14 * See the following sources for further documentation:
  15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
  16 *   SiFive FE310-G000 v2p3
  17 * - The tree/master/src/main/scala/devices/uart directory of
  18 *   https://github.com/sifive/sifive-blocks/
  19 *
  20 * The SiFive UART design is not 8250-compatible.  The following common
  21 * features are not supported:
  22 * - Word lengths other than 8 bits
  23 * - Break handling
  24 * - Parity
  25 * - Flow control
  26 * - Modem signals (DSR, RI, etc.)
  27 * On the other hand, the design is free from the baggage of the 8250
  28 * programming model.
  29 */
  30
  31#include <linux/clk.h>
  32#include <linux/console.h>
  33#include <linux/delay.h>
  34#include <linux/init.h>
  35#include <linux/io.h>
  36#include <linux/irq.h>
  37#include <linux/module.h>
  38#include <linux/of.h>
  39#include <linux/of_irq.h>
  40#include <linux/platform_device.h>
  41#include <linux/serial_core.h>
  42#include <linux/serial_reg.h>
  43#include <linux/slab.h>
  44#include <linux/tty.h>
  45#include <linux/tty_flip.h>
  46
  47/*
  48 * Register offsets
  49 */
  50
  51/* TXDATA */
  52#define SIFIVE_SERIAL_TXDATA_OFFS		0x0
  53#define SIFIVE_SERIAL_TXDATA_FULL_SHIFT		31
  54#define SIFIVE_SERIAL_TXDATA_FULL_MASK		(1 << SIFIVE_SERIAL_TXDATA_FULL_SHIFT)
  55#define SIFIVE_SERIAL_TXDATA_DATA_SHIFT		0
  56#define SIFIVE_SERIAL_TXDATA_DATA_MASK		(0xff << SIFIVE_SERIAL_TXDATA_DATA_SHIFT)
  57
  58/* RXDATA */
  59#define SIFIVE_SERIAL_RXDATA_OFFS		0x4
  60#define SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT	31
  61#define SIFIVE_SERIAL_RXDATA_EMPTY_MASK		(1 << SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT)
  62#define SIFIVE_SERIAL_RXDATA_DATA_SHIFT		0
  63#define SIFIVE_SERIAL_RXDATA_DATA_MASK		(0xff << SIFIVE_SERIAL_RXDATA_DATA_SHIFT)
  64
  65/* TXCTRL */
  66#define SIFIVE_SERIAL_TXCTRL_OFFS		0x8
  67#define SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT	16
  68#define SIFIVE_SERIAL_TXCTRL_TXCNT_MASK		(0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
  69#define SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT	1
  70#define SIFIVE_SERIAL_TXCTRL_NSTOP_MASK		(1 << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT)
  71#define SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT		0
  72#define SIFIVE_SERIAL_TXCTRL_TXEN_MASK		(1 << SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT)
  73
  74/* RXCTRL */
  75#define SIFIVE_SERIAL_RXCTRL_OFFS		0xC
  76#define SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT	16
  77#define SIFIVE_SERIAL_RXCTRL_RXCNT_MASK		(0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
  78#define SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT		0
  79#define SIFIVE_SERIAL_RXCTRL_RXEN_MASK		(1 << SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT)
  80
  81/* IE */
  82#define SIFIVE_SERIAL_IE_OFFS			0x10
  83#define SIFIVE_SERIAL_IE_RXWM_SHIFT		1
  84#define SIFIVE_SERIAL_IE_RXWM_MASK		(1 << SIFIVE_SERIAL_IE_RXWM_SHIFT)
  85#define SIFIVE_SERIAL_IE_TXWM_SHIFT		0
  86#define SIFIVE_SERIAL_IE_TXWM_MASK		(1 << SIFIVE_SERIAL_IE_TXWM_SHIFT)
  87
  88/* IP */
  89#define SIFIVE_SERIAL_IP_OFFS			0x14
  90#define SIFIVE_SERIAL_IP_RXWM_SHIFT		1
  91#define SIFIVE_SERIAL_IP_RXWM_MASK		(1 << SIFIVE_SERIAL_IP_RXWM_SHIFT)
  92#define SIFIVE_SERIAL_IP_TXWM_SHIFT		0
  93#define SIFIVE_SERIAL_IP_TXWM_MASK		(1 << SIFIVE_SERIAL_IP_TXWM_SHIFT)
  94
  95/* DIV */
  96#define SIFIVE_SERIAL_DIV_OFFS			0x18
  97#define SIFIVE_SERIAL_DIV_DIV_SHIFT		0
  98#define SIFIVE_SERIAL_DIV_DIV_MASK		(0xffff << SIFIVE_SERIAL_IP_DIV_SHIFT)
  99
 100/*
 101 * Config macros
 102 */
 103
 104/*
 105 * SIFIVE_SERIAL_MAX_PORTS: maximum number of UARTs on a device that can
 106 *                          host a serial console
 107 */
 108#define SIFIVE_SERIAL_MAX_PORTS			8
 109
 110/*
 111 * SIFIVE_DEFAULT_BAUD_RATE: default baud rate that the driver should
 112 *                           configure itself to use
 113 */
 114#define SIFIVE_DEFAULT_BAUD_RATE		115200
 115
 116/* SIFIVE_SERIAL_NAME: our driver's name that we pass to the operating system */
 117#define SIFIVE_SERIAL_NAME			"sifive-serial"
 118
 119/* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
 120#define SIFIVE_TTY_PREFIX			"ttySIF"
 121
 122/* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
 123#define SIFIVE_TX_FIFO_DEPTH			8
 124
 125/* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
 126#define SIFIVE_RX_FIFO_DEPTH			8
 127
 128#if (SIFIVE_TX_FIFO_DEPTH != SIFIVE_RX_FIFO_DEPTH)
 129#error Driver does not support configurations with different TX, RX FIFO sizes
 130#endif
 131
 132/*
 133 *
 134 */
 135
 136/**
 137 * struct sifive_serial_port - driver-specific data extension to struct uart_port
 138 * @port: struct uart_port embedded in this struct
 139 * @dev: struct device *
 140 * @ier: shadowed copy of the interrupt enable register
 141 * @baud_rate: UART serial line rate (e.g., 115200 baud)
 142 * @clk: reference to this device's clock
 143 * @clk_notifier: clock rate change notifier for upstream clock changes
 144 * @console_line_ended: indicate that the console line is fully written
 145 *
 146 * Configuration data specific to this SiFive UART.
 147 */
 148struct sifive_serial_port {
 149	struct uart_port	port;
 150	struct device		*dev;
 151	unsigned char		ier;
 152	unsigned long		baud_rate;
 153	struct clk		*clk;
 154	struct notifier_block	clk_notifier;
 155	bool			console_line_ended;
 156};
 157
 158/*
 159 * Structure container-of macros
 160 */
 161
 162#define port_to_sifive_serial_port(p) (container_of((p), \
 163						    struct sifive_serial_port, \
 164						    port))
 165
 166#define notifier_to_sifive_serial_port(nb) (container_of((nb), \
 167							 struct sifive_serial_port, \
 168							 clk_notifier))
 169
 170/*
 171 * Forward declarations
 172 */
 173static void sifive_serial_stop_tx(struct uart_port *port);
 174
 175/*
 176 * Internal functions
 177 */
 178
 179/**
 180 * __ssp_early_writel() - write to a SiFive serial port register (early)
 181 * @port: pointer to a struct uart_port record
 182 * @offs: register address offset from the IP block base address
 183 * @v: value to write to the register
 184 *
 185 * Given a pointer @port to a struct uart_port record, write the value
 186 * @v to the IP block register address offset @offs.  This function is
 187 * intended for early console use.
 188 *
 189 * Context: Intended to be used only by the earlyconsole code.
 190 */
 191static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port)
 192{
 193	writel_relaxed(v, port->membase + offs);
 194}
 195
 196/**
 197 * __ssp_early_readl() - read from a SiFive serial port register (early)
 198 * @port: pointer to a struct uart_port record
 199 * @offs: register address offset from the IP block base address
 200 *
 201 * Given a pointer @port to a struct uart_port record, read the
 202 * contents of the IP block register located at offset @offs from the
 203 * IP block base and return it.  This function is intended for early
 204 * console use.
 205 *
 206 * Context: Intended to be called only by the earlyconsole code or by
 207 *          __ssp_readl() or __ssp_writel() (in this driver)
 208 *
 209 * Returns: the register value read from the UART.
 210 */
 211static u32 __ssp_early_readl(struct uart_port *port, u16 offs)
 212{
 213	return readl_relaxed(port->membase + offs);
 214}
 215
 216/**
 217 * __ssp_writel() - write to a SiFive serial port register
 218 * @v: value to write to the register
 219 * @offs: register address offset from the IP block base address
 220 * @ssp: pointer to a struct sifive_serial_port record
 221 *
 222 * Write the value @v to the IP block register located at offset @offs from the
 223 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
 224 *
 225 * Context: Any context.
 226 */
 227static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
 228{
 229	__ssp_early_writel(v, offs, &ssp->port);
 230}
 231
 232/**
 233 * __ssp_readl() - read from a SiFive serial port register
 234 * @ssp: pointer to a struct sifive_serial_port record
 235 * @offs: register address offset from the IP block base address
 236 *
 237 * Read the contents of the IP block register located at offset @offs from the
 238 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
 239 *
 240 * Context: Any context.
 241 *
 242 * Returns: the value of the UART register
 243 */
 244static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs)
 245{
 246	return __ssp_early_readl(&ssp->port, offs);
 247}
 248
 249/**
 250 * sifive_serial_is_txfifo_full() - is the TXFIFO full?
 251 * @ssp: pointer to a struct sifive_serial_port
 252 *
 253 * Read the transmit FIFO "full" bit, returning a non-zero value if the
 254 * TX FIFO is full, or zero if space remains.  Intended to be used to prevent
 255 * writes to the TX FIFO when it's full.
 256 *
 257 * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
 258 * is full, or 0 if space remains.
 259 */
 260static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp)
 261{
 262	return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) &
 263		SIFIVE_SERIAL_TXDATA_FULL_MASK;
 264}
 265
 266/**
 267 * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
 268 * @ssp: pointer to a struct sifive_serial_port
 269 * @ch: character to transmit
 270 *
 271 * Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the
 272 * struct sifive_serial_port * to transmit on.  Caller should first check to
 273 * ensure that the TXFIFO has space; see sifive_serial_is_txfifo_full().
 274 *
 275 * Context: Any context.
 276 */
 277static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch)
 278{
 279	__ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp);
 280}
 281
 282/**
 283 * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
 284 * @ssp: pointer to a struct sifive_serial_port
 285 *
 286 * Transfer up to a TX FIFO size's worth of characters from the Linux serial
 287 * transmit buffer to the SiFive UART TX FIFO.
 288 *
 289 * Context: Any context.  Expects @ssp->port.lock to be held by caller.
 290 */
 291static void __ssp_transmit_chars(struct sifive_serial_port *ssp)
 292{
 293	u8 ch;
 294
 295	uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH,
 296		true,
 297		__ssp_transmit_char(ssp, ch),
 298		({}));
 299}
 300
 301/**
 302 * __ssp_enable_txwm() - enable transmit watermark interrupts
 303 * @ssp: pointer to a struct sifive_serial_port
 304 *
 305 * Enable interrupt generation when the transmit FIFO watermark is reached
 306 * on the SiFive UART referred to by @ssp.
 307 */
 308static void __ssp_enable_txwm(struct sifive_serial_port *ssp)
 309{
 310	if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)
 311		return;
 312
 313	ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;
 314	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
 315}
 316
 317/**
 318 * __ssp_enable_rxwm() - enable receive watermark interrupts
 319 * @ssp: pointer to a struct sifive_serial_port
 320 *
 321 * Enable interrupt generation when the receive FIFO watermark is reached
 322 * on the SiFive UART referred to by @ssp.
 323 */
 324static void __ssp_enable_rxwm(struct sifive_serial_port *ssp)
 325{
 326	if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)
 327		return;
 328
 329	ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;
 330	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
 331}
 332
 333/**
 334 * __ssp_disable_txwm() - disable transmit watermark interrupts
 335 * @ssp: pointer to a struct sifive_serial_port
 336 *
 337 * Disable interrupt generation when the transmit FIFO watermark is reached
 338 * on the UART referred to by @ssp.
 339 */
 340static void __ssp_disable_txwm(struct sifive_serial_port *ssp)
 341{
 342	if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))
 343		return;
 344
 345	ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;
 346	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
 347}
 348
 349/**
 350 * __ssp_disable_rxwm() - disable receive watermark interrupts
 351 * @ssp: pointer to a struct sifive_serial_port
 352 *
 353 * Disable interrupt generation when the receive FIFO watermark is reached
 354 * on the UART referred to by @ssp.
 355 */
 356static void __ssp_disable_rxwm(struct sifive_serial_port *ssp)
 357{
 358	if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))
 359		return;
 360
 361	ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;
 362	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
 363}
 364
 365/**
 366 * __ssp_receive_char() - receive a byte from the UART
 367 * @ssp: pointer to a struct sifive_serial_port
 368 * @is_empty: char pointer to return whether the RX FIFO is empty
 369 *
 370 * Try to read a byte from the SiFive UART RX FIFO, referenced by
 371 * @ssp, and to return it.  Also returns the RX FIFO empty bit in
 372 * the char pointed to by @ch.  The caller must pass the byte back to the
 373 * Linux serial layer if needed.
 374 *
 375 * Returns: the byte read from the UART RX FIFO.
 376 */
 377static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty)
 378{
 379	u32 v;
 380	u8 ch;
 381
 382	v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
 383
 384	if (!is_empty)
 385		WARN_ON(1);
 386	else
 387		*is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >>
 388			SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT;
 389
 390	ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >>
 391		SIFIVE_SERIAL_RXDATA_DATA_SHIFT;
 392
 393	return ch;
 394}
 395
 396/**
 397 * __ssp_receive_chars() - receive multiple bytes from the UART
 398 * @ssp: pointer to a struct sifive_serial_port
 399 *
 400 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
 401 * to by @ssp and pass them up to the Linux serial layer.
 402 *
 403 * Context: Expects ssp->port.lock to be held by caller.
 404 */
 405static void __ssp_receive_chars(struct sifive_serial_port *ssp)
 406{
 407	char is_empty;
 408	int c;
 409	u8 ch;
 410
 411	for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
 412		ch = __ssp_receive_char(ssp, &is_empty);
 413		if (is_empty)
 414			break;
 415
 416		ssp->port.icount.rx++;
 417		if (!uart_prepare_sysrq_char(&ssp->port, ch))
 418			uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);
 419	}
 420
 421	tty_flip_buffer_push(&ssp->port.state->port);
 422}
 423
 424/**
 425 * __ssp_update_div() - calculate the divisor setting by the line rate
 426 * @ssp: pointer to a struct sifive_serial_port
 427 *
 428 * Calculate the appropriate value of the clock divisor for the UART
 429 * and target line rate referred to by @ssp and write it into the
 430 * hardware.
 431 */
 432static void __ssp_update_div(struct sifive_serial_port *ssp)
 433{
 434	u16 div;
 435
 436	div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;
 437
 438	__ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
 439}
 440
 441/**
 442 * __ssp_update_baud_rate() - set the UART "baud rate"
 443 * @ssp: pointer to a struct sifive_serial_port
 444 * @rate: new target bit rate
 445 *
 446 * Calculate the UART divisor value for the target bit rate @rate for the
 447 * SiFive UART described by @ssp and program it into the UART.  There may
 448 * be some error between the target bit rate and the actual bit rate implemented
 449 * by the UART due to clock ratio granularity.
 450 */
 451static void __ssp_update_baud_rate(struct sifive_serial_port *ssp,
 452				   unsigned int rate)
 453{
 454	if (ssp->baud_rate == rate)
 455		return;
 456
 457	ssp->baud_rate = rate;
 458	__ssp_update_div(ssp);
 459}
 460
 461/**
 462 * __ssp_set_stop_bits() - set the number of stop bits
 463 * @ssp: pointer to a struct sifive_serial_port
 464 * @nstop: 1 or 2 (stop bits)
 465 *
 466 * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
 467 */
 468static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop)
 469{
 470	u32 v;
 471
 472	if (nstop < 1 || nstop > 2) {
 473		WARN_ON(1);
 474		return;
 475	}
 476
 477	v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
 478	v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK;
 479	v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;
 480	__ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
 481}
 482
 483/**
 484 * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
 485 * @ssp: pointer to a struct sifive_serial_port
 486 *
 487 * Delay while the UART TX FIFO referred to by @ssp is marked as full.
 488 *
 489 * Context: Any context.
 490 */
 491static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp)
 492{
 493	while (sifive_serial_is_txfifo_full(ssp))
 494		udelay(1); /* XXX Could probably be more intelligent here */
 495}
 496
 497/*
 498 * Linux serial API functions
 499 */
 500
 501static void sifive_serial_stop_tx(struct uart_port *port)
 502{
 503	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 504
 505	__ssp_disable_txwm(ssp);
 506}
 507
 508static void sifive_serial_stop_rx(struct uart_port *port)
 509{
 510	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 511
 512	__ssp_disable_rxwm(ssp);
 513}
 514
 515static void sifive_serial_start_tx(struct uart_port *port)
 516{
 517	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 518
 519	__ssp_enable_txwm(ssp);
 520}
 521
 522static irqreturn_t sifive_serial_irq(int irq, void *dev_id)
 523{
 524	struct sifive_serial_port *ssp = dev_id;
 525	u32 ip;
 526
 527	uart_port_lock(&ssp->port);
 528
 529	ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS);
 530	if (!ip) {
 531		uart_port_unlock(&ssp->port);
 532		return IRQ_NONE;
 533	}
 534
 535	if (ip & SIFIVE_SERIAL_IP_RXWM_MASK)
 536		__ssp_receive_chars(ssp);
 537	if (ip & SIFIVE_SERIAL_IP_TXWM_MASK)
 538		__ssp_transmit_chars(ssp);
 539
 540	uart_unlock_and_check_sysrq(&ssp->port);
 541
 542	return IRQ_HANDLED;
 543}
 544
 545static unsigned int sifive_serial_tx_empty(struct uart_port *port)
 546{
 547	return TIOCSER_TEMT;
 548}
 549
 550static unsigned int sifive_serial_get_mctrl(struct uart_port *port)
 551{
 552	return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
 553}
 554
 555static void sifive_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 556{
 557	/* IP block does not support these signals */
 558}
 559
 560static void sifive_serial_break_ctl(struct uart_port *port, int break_state)
 561{
 562	/* IP block does not support sending a break */
 563}
 564
 565static int sifive_serial_startup(struct uart_port *port)
 566{
 567	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 568	unsigned long flags;
 569
 570	uart_port_lock_irqsave(&ssp->port, &flags);
 571	__ssp_enable_rxwm(ssp);
 572	uart_port_unlock_irqrestore(&ssp->port, flags);
 573
 574	return 0;
 575}
 576
 577static void sifive_serial_shutdown(struct uart_port *port)
 578{
 579	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 580	unsigned long flags;
 581
 582	uart_port_lock_irqsave(&ssp->port, &flags);
 583	__ssp_disable_rxwm(ssp);
 584	__ssp_disable_txwm(ssp);
 585	uart_port_unlock_irqrestore(&ssp->port, flags);
 586}
 587
 588/**
 589 * sifive_serial_clk_notifier() - clock post-rate-change notifier
 590 * @nb: pointer to the struct notifier_block, from the notifier code
 591 * @event: event mask from the notifier code
 592 * @data: pointer to the struct clk_notifier_data from the notifier code
 593 *
 594 * On the V0 SoC, the UART IP block is derived from the CPU clock source
 595 * after a synchronous divide-by-two divider, so any CPU clock rate change
 596 * requires the UART baud rate to be updated.  This presumably corrupts any
 597 * serial word currently being transmitted or received.  In order to avoid
 598 * corrupting the output data stream, we drain the transmit queue before
 599 * allowing the clock's rate to be changed.
 600 */
 601static int sifive_serial_clk_notifier(struct notifier_block *nb,
 602				      unsigned long event, void *data)
 603{
 604	struct clk_notifier_data *cnd = data;
 605	struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb);
 606
 607	if (event == PRE_RATE_CHANGE) {
 608		/*
 609		 * The TX watermark is always set to 1 by this driver, which
 610		 * means that the TX busy bit will lower when there are 0 bytes
 611		 * left in the TX queue -- in other words, when the TX FIFO is
 612		 * empty.
 613		 */
 614		__ssp_wait_for_xmitr(ssp);
 615		/*
 616		 * On the cycle the TX FIFO goes empty there is still a full
 617		 * UART frame left to be transmitted in the shift register.
 618		 * The UART provides no way for software to directly determine
 619		 * when that last frame has been transmitted, so we just sleep
 620		 * here instead.  As we're not tracking the number of stop bits
 621		 * they're just worst cased here.  The rest of the serial
 622		 * framing parameters aren't configurable by software.
 623		 */
 624		udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
 625	}
 626
 627	if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {
 628		ssp->port.uartclk = cnd->new_rate;
 629		__ssp_update_div(ssp);
 630	}
 631
 632	return NOTIFY_OK;
 633}
 634
 635static void sifive_serial_set_termios(struct uart_port *port,
 636				      struct ktermios *termios,
 637				      const struct ktermios *old)
 638{
 639	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 640	unsigned long flags;
 641	u32 v, old_v;
 642	int rate;
 643	char nstop;
 644
 645	if ((termios->c_cflag & CSIZE) != CS8) {
 646		dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
 647		termios->c_cflag &= ~CSIZE;
 648		termios->c_cflag |= CS8;
 649	}
 650	if (termios->c_iflag & (INPCK | PARMRK))
 651		dev_err_once(ssp->port.dev, "parity checking not supported\n");
 652	if (termios->c_iflag & BRKINT)
 653		dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
 654	termios->c_iflag &= ~(INPCK|PARMRK|BRKINT);
 655
 656	/* Set number of stop bits */
 657	nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
 658	__ssp_set_stop_bits(ssp, nstop);
 659
 660	/* Set line rate */
 661	rate = uart_get_baud_rate(port, termios, old, 0,
 662				  ssp->port.uartclk / 16);
 663	__ssp_update_baud_rate(ssp, rate);
 664
 665	uart_port_lock_irqsave(&ssp->port, &flags);
 666
 667	/* Update the per-port timeout */
 668	uart_update_timeout(port, termios->c_cflag, rate);
 669
 670	ssp->port.read_status_mask = 0;
 671
 672	/* Ignore all characters if CREAD is not set */
 673	v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
 674	old_v = v;
 675	if ((termios->c_cflag & CREAD) == 0)
 676		v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
 677	else
 678		v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
 679	if (v != old_v)
 680		__ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
 681
 682	uart_port_unlock_irqrestore(&ssp->port, flags);
 683}
 684
 685static void sifive_serial_release_port(struct uart_port *port)
 686{
 687}
 688
 689static int sifive_serial_request_port(struct uart_port *port)
 690{
 691	return 0;
 692}
 693
 694static void sifive_serial_config_port(struct uart_port *port, int flags)
 695{
 696	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 697
 698	ssp->port.type = PORT_SIFIVE_V0;
 699}
 700
 701static int sifive_serial_verify_port(struct uart_port *port,
 702				     struct serial_struct *ser)
 703{
 704	return -EINVAL;
 705}
 706
 707static const char *sifive_serial_type(struct uart_port *port)
 708{
 709	return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;
 710}
 711
 712#ifdef CONFIG_CONSOLE_POLL
 713static int sifive_serial_poll_get_char(struct uart_port *port)
 714{
 715	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 716	char is_empty, ch;
 717
 718	ch = __ssp_receive_char(ssp, &is_empty);
 719	if (is_empty)
 720		return NO_POLL_CHAR;
 721
 722	return ch;
 723}
 724
 725static void sifive_serial_poll_put_char(struct uart_port *port,
 726					unsigned char c)
 727{
 728	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 729
 730	__ssp_wait_for_xmitr(ssp);
 731	__ssp_transmit_char(ssp, c);
 732}
 733#endif /* CONFIG_CONSOLE_POLL */
 734
 735/*
 736 * Early console support
 737 */
 738
 739#ifdef CONFIG_SERIAL_EARLYCON
 740static void early_sifive_serial_putc(struct uart_port *port, unsigned char c)
 741{
 742	while (__ssp_early_readl(port, SIFIVE_SERIAL_TXDATA_OFFS) &
 743	       SIFIVE_SERIAL_TXDATA_FULL_MASK)
 744		cpu_relax();
 745
 746	__ssp_early_writel(c, SIFIVE_SERIAL_TXDATA_OFFS, port);
 747}
 748
 749static void early_sifive_serial_write(struct console *con, const char *s,
 750				      unsigned int n)
 751{
 752	struct earlycon_device *dev = con->data;
 753	struct uart_port *port = &dev->port;
 754
 755	uart_console_write(port, s, n, early_sifive_serial_putc);
 756}
 757
 758static int __init early_sifive_serial_setup(struct earlycon_device *dev,
 759					    const char *options)
 760{
 761	struct uart_port *port = &dev->port;
 762
 763	if (!port->membase)
 764		return -ENODEV;
 765
 766	dev->con->write = early_sifive_serial_write;
 767
 768	return 0;
 769}
 770
 771OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
 772OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart",
 773		    early_sifive_serial_setup);
 774#endif /* CONFIG_SERIAL_EARLYCON */
 775
 776/*
 777 * Linux console interface
 778 */
 779
 780#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
 781
 782static struct sifive_serial_port *sifive_serial_console_ports[SIFIVE_SERIAL_MAX_PORTS];
 783
 784static void sifive_serial_console_putchar(struct uart_port *port, unsigned char ch)
 785{
 786	struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
 787
 788	__ssp_wait_for_xmitr(ssp);
 789	__ssp_transmit_char(ssp, ch);
 790
 791	ssp->console_line_ended = (ch == '\n');
 792}
 793
 794static void sifive_serial_device_lock(struct console *co, unsigned long *flags)
 795{
 796	struct uart_port *up = &sifive_serial_console_ports[co->index]->port;
 797
 798	__uart_port_lock_irqsave(up, flags);
 799}
 800
 801static void sifive_serial_device_unlock(struct console *co, unsigned long flags)
 802{
 803	struct uart_port *up = &sifive_serial_console_ports[co->index]->port;
 804
 805	__uart_port_unlock_irqrestore(up, flags);
 806}
 807
 808static void sifive_serial_console_write_atomic(struct console *co,
 809					       struct nbcon_write_context *wctxt)
 810{
 811	struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
 812	struct uart_port *port = &ssp->port;
 813	unsigned int ier;
 814
 815	if (!ssp)
 816		return;
 817
 818	if (!nbcon_enter_unsafe(wctxt))
 819		return;
 820
 821	ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
 822	__ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
 823
 824	if (!ssp->console_line_ended)
 825		uart_console_write(port, "\n", 1, sifive_serial_console_putchar);
 826	uart_console_write(port, wctxt->outbuf, wctxt->len,
 827			   sifive_serial_console_putchar);
 828
 829	__ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
 830
 831	nbcon_exit_unsafe(wctxt);
 832}
 833
 834static void sifive_serial_console_write_thread(struct console *co,
 835					       struct nbcon_write_context *wctxt)
 836{
 837	struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
 838	struct uart_port *port = &ssp->port;
 839	unsigned int ier;
 840
 841	if (!ssp)
 842		return;
 843
 844	if (!nbcon_enter_unsafe(wctxt))
 845		return;
 846
 847	ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
 848	__ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
 849
 850	if (nbcon_exit_unsafe(wctxt)) {
 851		int len = READ_ONCE(wctxt->len);
 852		int i;
 853
 854		for (i = 0; i < len; i++) {
 855			if (!nbcon_enter_unsafe(wctxt))
 856				break;
 857
 858			uart_console_write(port, wctxt->outbuf + i, 1,
 859					   sifive_serial_console_putchar);
 860
 861			if (!nbcon_exit_unsafe(wctxt))
 862				break;
 863		}
 864	}
 865
 866	while (!nbcon_enter_unsafe(wctxt))
 867		nbcon_reacquire_nobuf(wctxt);
 868
 869	__ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
 870
 871	nbcon_exit_unsafe(wctxt);
 872}
 873
 874static int sifive_serial_console_setup(struct console *co, char *options)
 875{
 876	struct sifive_serial_port *ssp;
 877	int baud = SIFIVE_DEFAULT_BAUD_RATE;
 878	int bits = 8;
 879	int parity = 'n';
 880	int flow = 'n';
 881
 882	if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)
 883		return -ENODEV;
 884
 885	ssp = sifive_serial_console_ports[co->index];
 886	if (!ssp)
 887		return -ENODEV;
 888
 889	ssp->console_line_ended = true;
 890
 891	if (options)
 892		uart_parse_options(options, &baud, &parity, &bits, &flow);
 893
 894	return uart_set_options(&ssp->port, co, baud, parity, bits, flow);
 895}
 896
 897static struct uart_driver sifive_serial_uart_driver;
 898
 899static struct console sifive_serial_console = {
 900	.name		= SIFIVE_TTY_PREFIX,
 901	.write_atomic	= sifive_serial_console_write_atomic,
 902	.write_thread	= sifive_serial_console_write_thread,
 903	.device_lock	= sifive_serial_device_lock,
 904	.device_unlock	= sifive_serial_device_unlock,
 905	.device		= uart_console_device,
 906	.setup		= sifive_serial_console_setup,
 907	.flags		= CON_PRINTBUFFER | CON_NBCON,
 908	.index		= -1,
 909	.data		= &sifive_serial_uart_driver,
 910};
 911
 912static int __init sifive_console_init(void)
 913{
 914	register_console(&sifive_serial_console);
 915	return 0;
 916}
 917
 918console_initcall(sifive_console_init);
 919
 920static void __ssp_add_console_port(struct sifive_serial_port *ssp)
 921{
 922	sifive_serial_console_ports[ssp->port.line] = ssp;
 923}
 924
 925static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
 926{
 927	sifive_serial_console_ports[ssp->port.line] = NULL;
 928}
 929
 930#define SIFIVE_SERIAL_CONSOLE	(&sifive_serial_console)
 931
 932#else
 933
 934#define SIFIVE_SERIAL_CONSOLE	NULL
 935
 936static void __ssp_add_console_port(struct sifive_serial_port *ssp)
 937{}
 938static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
 939{}
 940
 941#endif
 942
 943static const struct uart_ops sifive_serial_uops = {
 944	.tx_empty	= sifive_serial_tx_empty,
 945	.set_mctrl	= sifive_serial_set_mctrl,
 946	.get_mctrl	= sifive_serial_get_mctrl,
 947	.stop_tx	= sifive_serial_stop_tx,
 948	.start_tx	= sifive_serial_start_tx,
 949	.stop_rx	= sifive_serial_stop_rx,
 950	.break_ctl	= sifive_serial_break_ctl,
 951	.startup	= sifive_serial_startup,
 952	.shutdown	= sifive_serial_shutdown,
 953	.set_termios	= sifive_serial_set_termios,
 954	.type		= sifive_serial_type,
 955	.release_port	= sifive_serial_release_port,
 956	.request_port	= sifive_serial_request_port,
 957	.config_port	= sifive_serial_config_port,
 958	.verify_port	= sifive_serial_verify_port,
 959#ifdef CONFIG_CONSOLE_POLL
 960	.poll_get_char	= sifive_serial_poll_get_char,
 961	.poll_put_char	= sifive_serial_poll_put_char,
 962#endif
 963};
 964
 965static struct uart_driver sifive_serial_uart_driver = {
 966	.owner		= THIS_MODULE,
 967	.driver_name	= SIFIVE_SERIAL_NAME,
 968	.dev_name	= SIFIVE_TTY_PREFIX,
 969	.nr		= SIFIVE_SERIAL_MAX_PORTS,
 970	.cons		= SIFIVE_SERIAL_CONSOLE,
 971};
 972
 973static int sifive_serial_probe(struct platform_device *pdev)
 974{
 975	struct sifive_serial_port *ssp;
 976	struct resource *mem;
 977	struct clk *clk;
 978	void __iomem *base;
 979	int irq, id, r;
 980
 981	irq = platform_get_irq(pdev, 0);
 982	if (irq < 0)
 983		return -EPROBE_DEFER;
 984
 985	base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
 986	if (IS_ERR(base))
 987		return PTR_ERR(base);
 988
 989	clk = devm_clk_get_enabled(&pdev->dev, NULL);
 990	if (IS_ERR(clk)) {
 991		dev_err(&pdev->dev, "unable to find controller clock\n");
 992		return PTR_ERR(clk);
 993	}
 994
 995	id = of_alias_get_id(pdev->dev.of_node, "serial");
 996	if (id < 0) {
 997		dev_err(&pdev->dev, "missing aliases entry\n");
 998		return id;
 999	}
1000
1001#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
1002	if (id > SIFIVE_SERIAL_MAX_PORTS) {
1003		dev_err(&pdev->dev, "too many UARTs (%d)\n", id);
1004		return -EINVAL;
1005	}
1006#endif
1007
1008	ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
1009	if (!ssp)
1010		return -ENOMEM;
1011
1012	ssp->port.dev = &pdev->dev;
1013	ssp->port.type = PORT_SIFIVE_V0;
1014	ssp->port.iotype = UPIO_MEM;
1015	ssp->port.irq = irq;
1016	ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;
1017	ssp->port.ops = &sifive_serial_uops;
1018	ssp->port.line = id;
1019	ssp->port.mapbase = mem->start;
1020	ssp->port.membase = base;
1021	ssp->dev = &pdev->dev;
1022	ssp->clk = clk;
1023	ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;
1024
1025	r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);
1026	if (r) {
1027		dev_err(&pdev->dev, "could not register clock notifier: %d\n",
1028			r);
1029		goto probe_out1;
1030	}
1031
1032	/* Set up clock divider */
1033	ssp->port.uartclk = clk_get_rate(ssp->clk);
1034	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
1035	__ssp_update_div(ssp);
1036
1037	platform_set_drvdata(pdev, ssp);
1038
1039	/* Enable transmits and set the watermark level to 1 */
1040	__ssp_writel((1 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) |
1041		     SIFIVE_SERIAL_TXCTRL_TXEN_MASK,
1042		     SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
1043
1044	/* Enable receives and set the watermark level to 0 */
1045	__ssp_writel((0 << SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT) |
1046		     SIFIVE_SERIAL_RXCTRL_RXEN_MASK,
1047		     SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
1048
1049	r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,
1050			dev_name(&pdev->dev), ssp);
1051	if (r) {
1052		dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);
1053		goto probe_out2;
1054	}
1055
1056	__ssp_add_console_port(ssp);
1057
1058	r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);
1059	if (r != 0) {
1060		dev_err(&pdev->dev, "could not add uart: %d\n", r);
1061		goto probe_out3;
1062	}
1063
1064	return 0;
1065
1066probe_out3:
1067	__ssp_remove_console_port(ssp);
1068	free_irq(ssp->port.irq, ssp);
1069probe_out2:
1070	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1071probe_out1:
1072	return r;
1073}
1074
1075static void sifive_serial_remove(struct platform_device *dev)
1076{
1077	struct sifive_serial_port *ssp = platform_get_drvdata(dev);
1078
1079	__ssp_remove_console_port(ssp);
1080	uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);
1081	free_irq(ssp->port.irq, ssp);
1082	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1083}
1084
1085static int sifive_serial_suspend(struct device *dev)
1086{
1087	struct sifive_serial_port *ssp = dev_get_drvdata(dev);
1088
1089	return uart_suspend_port(&sifive_serial_uart_driver, &ssp->port);
1090}
1091
1092static int sifive_serial_resume(struct device *dev)
1093{
1094	struct sifive_serial_port *ssp = dev_get_drvdata(dev);
1095
1096	return uart_resume_port(&sifive_serial_uart_driver, &ssp->port);
1097}
1098
1099static DEFINE_SIMPLE_DEV_PM_OPS(sifive_uart_pm_ops, sifive_serial_suspend,
1100				sifive_serial_resume);
1101
1102static const struct of_device_id sifive_serial_of_match[] = {
1103	{ .compatible = "sifive,fu540-c000-uart" },
1104	{ .compatible = "sifive,uart0" },
1105	{},
1106};
1107MODULE_DEVICE_TABLE(of, sifive_serial_of_match);
1108
1109static struct platform_driver sifive_serial_platform_driver = {
1110	.probe		= sifive_serial_probe,
1111	.remove		= sifive_serial_remove,
1112	.driver		= {
1113		.name	= SIFIVE_SERIAL_NAME,
1114		.pm = pm_sleep_ptr(&sifive_uart_pm_ops),
1115		.of_match_table = sifive_serial_of_match,
1116	},
1117};
1118
1119static int __init sifive_serial_init(void)
1120{
1121	int r;
1122
1123	r = uart_register_driver(&sifive_serial_uart_driver);
1124	if (r)
1125		goto init_out1;
1126
1127	r = platform_driver_register(&sifive_serial_platform_driver);
1128	if (r)
1129		goto init_out2;
1130
1131	return 0;
1132
1133init_out2:
1134	uart_unregister_driver(&sifive_serial_uart_driver);
1135init_out1:
1136	return r;
1137}
1138
1139static void __exit sifive_serial_exit(void)
1140{
1141	platform_driver_unregister(&sifive_serial_platform_driver);
1142	uart_unregister_driver(&sifive_serial_uart_driver);
1143}
1144
1145module_init(sifive_serial_init);
1146module_exit(sifive_serial_exit);
1147
1148MODULE_DESCRIPTION("SiFive UART serial driver");
1149MODULE_LICENSE("GPL");
1150MODULE_AUTHOR("Paul Walmsley <paul@pwsan.com>");