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sh-sci.c
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linux-6.19.14/drivers/tty/serial/sh-sci.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18#undef DEBUG 19 20#include <linux/bitops.h> 21#include <linux/clk.h> 22#include <linux/console.h> 23#include <linux/cpufreq.h> 24#include <linux/ctype.h> 25#include <linux/delay.h> 26#include <linux/dma-mapping.h> 27#include <linux/dmaengine.h> 28#include <linux/err.h> 29#include <linux/errno.h> 30#include <linux/init.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/ioport.h> 34#include <linux/ktime.h> 35#include <linux/major.h> 36#include <linux/minmax.h> 37#include <linux/mm.h> 38#include <linux/module.h> 39#include <linux/of.h> 40#include <linux/platform_device.h> 41#include <linux/pm_runtime.h> 42#include <linux/reset.h> 43#include <linux/scatterlist.h> 44#include <linux/serial.h> 45#include <linux/serial_core.h> 46#include <linux/serial_sci.h> 47#include <linux/sh_dma.h> 48#include <linux/slab.h> 49#include <linux/string.h> 50#include <linux/sysrq.h> 51#include <linux/timer.h> 52#include <linux/tty.h> 53#include <linux/tty_flip.h> 54 55#ifdef CONFIG_SUPERH 56#include <asm/platform_early.h> 57#include <asm/sh_bios.h> 58#endif 59 60#include "rsci.h" 61#include "serial_mctrl_gpio.h" 62#include "sh-sci-common.h" 63 64#define SCI_MAJOR 204 65#define SCI_MINOR_START 8 66 67/* 68 * SCI register subset common for all port types. 69 * Not all registers will exist on all parts. 70 */ 71enum { 72 SCSMR, /* Serial Mode Register */ 73 SCBRR, /* Bit Rate Register */ 74 SCSCR, /* Serial Control Register */ 75 SCxSR, /* Serial Status Register */ 76 SCFCR, /* FIFO Control Register */ 77 SCFDR, /* FIFO Data Count Register */ 78 SCxTDR, /* Transmit (FIFO) Data Register */ 79 SCxRDR, /* Receive (FIFO) Data Register */ 80 SCLSR, /* Line Status Register */ 81 SCTFDR, /* Transmit FIFO Data Count Register */ 82 SCRFDR, /* Receive FIFO Data Count Register */ 83 SCSPTR, /* Serial Port Register */ 84 HSSRR, /* Sampling Rate Register */ 85 SCPCR, /* Serial Port Control Register */ 86 SCPDR, /* Serial Port Data Register */ 87 SCDL, /* BRG Frequency Division Register */ 88 SCCKS, /* BRG Clock Select Register */ 89 HSRTRGR, /* Rx FIFO Data Count Trigger Register */ 90 HSTTRGR, /* Tx FIFO Data Count Trigger Register */ 91 SEMR, /* Serial extended mode register */ 92}; 93 94/* SCSMR (Serial Mode Register) */ 95#define SCSMR_C_A BIT(7) /* Communication Mode */ 96#define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */ 97#define SCSMR_ASYNC 0 /* - Asynchronous mode */ 98#define SCSMR_CHR BIT(6) /* 7-bit Character Length */ 99#define SCSMR_PE BIT(5) /* Parity Enable */ 100#define SCSMR_ODD BIT(4) /* Odd Parity */ 101#define SCSMR_STOP BIT(3) /* Stop Bit Length */ 102#define SCSMR_CKS 0x0003 /* Clock Select */ 103 104/* Serial Mode Register, SCIFA/SCIFB only bits */ 105#define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */ 106#define SCSMR_SRC_MASK 0x0700 /* Sampling Control */ 107#define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */ 108#define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */ 109#define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */ 110#define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */ 111#define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */ 112#define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */ 113#define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */ 114#define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */ 115 116/* Serial Control Register, SCI only bits */ 117#define SCSCR_TEIE BIT(2) /* Transmit End Interrupt Enable */ 118 119/* Serial Control Register, SCIFA/SCIFB only bits */ 120#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */ 121#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */ 122 123/* Serial Control Register, HSCIF-only bits */ 124#define HSSCR_TOT_SHIFT 14 125 126/* SCxSR (Serial Status Register) on SCI */ 127#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */ 128#define SCI_RDRF BIT(6) /* Receive Data Register Full */ 129#define SCI_ORER BIT(5) /* Overrun Error */ 130#define SCI_FER BIT(4) /* Framing Error */ 131#define SCI_PER BIT(3) /* Parity Error */ 132#define SCI_TEND BIT(2) /* Transmit End */ 133#define SCI_RESERVED 0x03 /* All reserved bits */ 134 135#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) 136 137#define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF)) 138#define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) 139#define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE)) 140#define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) 141 142/* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */ 143#define SCIF_ER BIT(7) /* Receive Error */ 144#define SCIF_TEND BIT(6) /* Transmission End */ 145#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */ 146#define SCIF_BRK BIT(4) /* Break Detect */ 147#define SCIF_FER BIT(3) /* Framing Error */ 148#define SCIF_PER BIT(2) /* Parity Error */ 149#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */ 150#define SCIF_DR BIT(0) /* Receive Data Ready */ 151/* SCIF only (optional) */ 152#define SCIF_PERC 0xf000 /* Number of Parity Errors */ 153#define SCIF_FERC 0x0f00 /* Number of Framing Errors */ 154/*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */ 155#define SCIFA_ORER BIT(9) /* Overrun Error */ 156 157#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER) 158 159#define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF)) 160#define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER)) 161#define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE)) 162#define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) 163 164/* SCFCR (FIFO Control Register) */ 165#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */ 166#define SCFCR_RTRG0 BIT(6) 167#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */ 168#define SCFCR_TTRG0 BIT(4) 169#define SCFCR_MCE BIT(3) /* Modem Control Enable */ 170#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ 171#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ 172#define SCFCR_LOOP BIT(0) /* Loopback Test */ 173 174/* SCLSR (Line Status Register) on (H)SCIF */ 175#define SCLSR_TO BIT(2) /* Timeout */ 176#define SCLSR_ORER BIT(0) /* Overrun Error */ 177 178/* SCSPTR (Serial Port Register), optional */ 179#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */ 180#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */ 181#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */ 182#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */ 183#define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */ 184#define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */ 185#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */ 186#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */ 187 188/* HSSRR HSCIF */ 189#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */ 190#define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */ 191 192#define HSCIF_SRHP_SHIFT 8 193#define HSCIF_SRHP_MASK 0x0f00 194 195/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */ 196#define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */ 197#define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */ 198#define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */ 199#define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */ 200#define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */ 201 202/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */ 203#define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */ 204#define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */ 205#define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */ 206#define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */ 207#define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */ 208 209/* 210 * BRG Clock Select Register (Some SCIF and HSCIF) 211 * The Baud Rate Generator for external clock can provide a clock source for 212 * the sampling clock. It outputs either its frequency divided clock, or the 213 * (undivided) (H)SCK external clock. 214 */ 215#define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */ 216#define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ 217 218#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 219#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF) 220#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 221#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 222#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 223#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 224 225#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) 226 227#define SCxSR_RDxF_CLEAR(port) \ 228 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR) 229#define SCxSR_ERROR_CLEAR(port) \ 230 (to_sci_port(port)->params->error_clear) 231#define SCxSR_TDxE_CLEAR(port) \ 232 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR) 233#define SCxSR_BREAK_CLEAR(port) \ 234 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR) 235 236#define SCIx_IRQ_IS_MUXED(port) \ 237 ((port)->irqs[SCIx_ERI_IRQ] == \ 238 (port)->irqs[SCIx_RXI_IRQ]) || \ 239 ((port)->irqs[SCIx_ERI_IRQ] && \ 240 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 241 242#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 243 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 244 SCI_SR(19) | SCI_SR(27) 245 246/* Iterate over all supported sampling rates, from high to low */ 247#define for_each_sr(_sr, _port) \ 248 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 249 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 250 251#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 252 253#define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port)) 254 255static struct sci_port sci_ports[SCI_NPORTS]; 256static unsigned long sci_ports_in_use; 257static struct uart_driver sci_uart_driver; 258static bool sci_uart_earlycon; 259static bool sci_uart_earlycon_dev_probing; 260 261static const struct sci_port_params_bits sci_sci_port_params_bits = { 262 .rxtx_enable = SCSCR_RE | SCSCR_TE, 263 .te_clear = SCSCR_TE | SCSCR_TEIE, 264 .poll_sent_bits = SCI_TDRE | SCI_TEND 265}; 266 267static const struct sci_port_params_bits sci_scif_port_params_bits = { 268 .rxtx_enable = SCSCR_RE | SCSCR_TE, 269 .te_clear = SCSCR_TE | SCSCR_TEIE, 270 .poll_sent_bits = SCIF_TDFE | SCIF_TEND 271}; 272 273static const struct sci_common_regs sci_common_regs = { 274 .status = SCxSR, 275 .control = SCSCR, 276}; 277 278struct sci_suspend_regs { 279 u16 scdl; 280 u16 sccks; 281 u16 scsmr; 282 u16 scscr; 283 u16 scfcr; 284 u16 scsptr; 285 u16 hssrr; 286 u16 scpcr; 287 u16 scpdr; 288 u8 scbrr; 289 u8 semr; 290}; 291 292static size_t sci_suspend_regs_size(void) 293{ 294 return sizeof(struct sci_suspend_regs); 295} 296 297static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 298 /* 299 * Common SCI definitions, dependent on the port's regshift 300 * value. 301 */ 302 [SCIx_SCI_REGTYPE] = { 303 .regs = { 304 [SCSMR] = { 0x00, 8 }, 305 [SCBRR] = { 0x01, 8 }, 306 [SCSCR] = { 0x02, 8 }, 307 [SCxTDR] = { 0x03, 8 }, 308 [SCxSR] = { 0x04, 8 }, 309 [SCxRDR] = { 0x05, 8 }, 310 }, 311 .fifosize = 1, 312 .overrun_reg = SCxSR, 313 .overrun_mask = SCI_ORER, 314 .sampling_rate_mask = SCI_SR(32), 315 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 316 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 317 .param_bits = &sci_sci_port_params_bits, 318 .common_regs = &sci_common_regs, 319 }, 320 321 /* 322 * Common definitions for legacy IrDA ports. 323 */ 324 [SCIx_IRDA_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 1, 336 .overrun_reg = SCxSR, 337 .overrun_mask = SCI_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 340 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 341 .param_bits = &sci_scif_port_params_bits, 342 .common_regs = &sci_common_regs, 343 }, 344 345 /* 346 * Common SCIFA definitions. 347 */ 348 [SCIx_SCIFA_REGTYPE] = { 349 .regs = { 350 [SCSMR] = { 0x00, 16 }, 351 [SCBRR] = { 0x04, 8 }, 352 [SCSCR] = { 0x08, 16 }, 353 [SCxTDR] = { 0x20, 8 }, 354 [SCxSR] = { 0x14, 16 }, 355 [SCxRDR] = { 0x24, 8 }, 356 [SCFCR] = { 0x18, 16 }, 357 [SCFDR] = { 0x1c, 16 }, 358 [SCPCR] = { 0x30, 16 }, 359 [SCPDR] = { 0x34, 16 }, 360 }, 361 .fifosize = 64, 362 .overrun_reg = SCxSR, 363 .overrun_mask = SCIFA_ORER, 364 .sampling_rate_mask = SCI_SR_SCIFAB, 365 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 366 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 367 .param_bits = &sci_scif_port_params_bits, 368 .common_regs = &sci_common_regs, 369 }, 370 371 /* 372 * Common SCIFB definitions. 373 */ 374 [SCIx_SCIFB_REGTYPE] = { 375 .regs = { 376 [SCSMR] = { 0x00, 16 }, 377 [SCBRR] = { 0x04, 8 }, 378 [SCSCR] = { 0x08, 16 }, 379 [SCxTDR] = { 0x40, 8 }, 380 [SCxSR] = { 0x14, 16 }, 381 [SCxRDR] = { 0x60, 8 }, 382 [SCFCR] = { 0x18, 16 }, 383 [SCTFDR] = { 0x38, 16 }, 384 [SCRFDR] = { 0x3c, 16 }, 385 [SCPCR] = { 0x30, 16 }, 386 [SCPDR] = { 0x34, 16 }, 387 }, 388 .fifosize = 256, 389 .overrun_reg = SCxSR, 390 .overrun_mask = SCIFA_ORER, 391 .sampling_rate_mask = SCI_SR_SCIFAB, 392 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 393 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 394 .param_bits = &sci_scif_port_params_bits, 395 .common_regs = &sci_common_regs, 396 }, 397 398 /* 399 * Common SH-2(A) SCIF definitions for ports with FIFO data 400 * count registers. 401 */ 402 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 403 .regs = { 404 [SCSMR] = { 0x00, 16 }, 405 [SCBRR] = { 0x04, 8 }, 406 [SCSCR] = { 0x08, 16 }, 407 [SCxTDR] = { 0x0c, 8 }, 408 [SCxSR] = { 0x10, 16 }, 409 [SCxRDR] = { 0x14, 8 }, 410 [SCFCR] = { 0x18, 16 }, 411 [SCFDR] = { 0x1c, 16 }, 412 [SCSPTR] = { 0x20, 16 }, 413 [SCLSR] = { 0x24, 16 }, 414 }, 415 .fifosize = 16, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR(32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 .param_bits = &sci_scif_port_params_bits, 422 .common_regs = &sci_common_regs, 423 }, 424 425 /* 426 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1. 427 * It looks like a normal SCIF with FIFO data, but with a 428 * compressed address space. Also, the break out of interrupts 429 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 430 */ 431 [SCIx_RZ_SCIFA_REGTYPE] = { 432 .regs = { 433 [SCSMR] = { 0x00, 16 }, 434 [SCBRR] = { 0x02, 8 }, 435 [SCSCR] = { 0x04, 16 }, 436 [SCxTDR] = { 0x06, 8 }, 437 [SCxSR] = { 0x08, 16 }, 438 [SCxRDR] = { 0x0A, 8 }, 439 [SCFCR] = { 0x0C, 16 }, 440 [SCFDR] = { 0x0E, 16 }, 441 [SCSPTR] = { 0x10, 16 }, 442 [SCLSR] = { 0x12, 16 }, 443 [SEMR] = { 0x14, 8 }, 444 }, 445 .fifosize = 16, 446 .overrun_reg = SCLSR, 447 .overrun_mask = SCLSR_ORER, 448 .sampling_rate_mask = SCI_SR(32), 449 .error_mask = SCIF_DEFAULT_ERROR_MASK, 450 .error_clear = SCIF_ERROR_CLEAR, 451 .param_bits = &sci_scif_port_params_bits, 452 .common_regs = &sci_common_regs, 453 }, 454 455 /* 456 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC 457 * with below differences, 458 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, 459 * TEI-DRI, RXI-EDGE and TXI-EDGE. 460 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. 461 * - SCFCR register does not have SCFCR_MCE bit. 462 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. 463 */ 464 [SCIx_RZV2H_SCIF_REGTYPE] = { 465 .regs = { 466 [SCSMR] = { 0x00, 16 }, 467 [SCBRR] = { 0x02, 8 }, 468 [SCSCR] = { 0x04, 16 }, 469 [SCxTDR] = { 0x06, 8 }, 470 [SCxSR] = { 0x08, 16 }, 471 [SCxRDR] = { 0x0a, 8 }, 472 [SCFCR] = { 0x0c, 16 }, 473 [SCFDR] = { 0x0e, 16 }, 474 [SCSPTR] = { 0x10, 16 }, 475 [SCLSR] = { 0x12, 16 }, 476 [SEMR] = { 0x14, 8 }, 477 }, 478 .fifosize = 16, 479 .overrun_reg = SCLSR, 480 .overrun_mask = SCLSR_ORER, 481 .sampling_rate_mask = SCI_SR(32), 482 .error_mask = SCIF_DEFAULT_ERROR_MASK, 483 .error_clear = SCIF_ERROR_CLEAR, 484 .param_bits = &sci_scif_port_params_bits, 485 .common_regs = &sci_common_regs, 486 }, 487 488 /* 489 * Common SH-3 SCIF definitions. 490 */ 491 [SCIx_SH3_SCIF_REGTYPE] = { 492 .regs = { 493 [SCSMR] = { 0x00, 8 }, 494 [SCBRR] = { 0x02, 8 }, 495 [SCSCR] = { 0x04, 8 }, 496 [SCxTDR] = { 0x06, 8 }, 497 [SCxSR] = { 0x08, 16 }, 498 [SCxRDR] = { 0x0a, 8 }, 499 [SCFCR] = { 0x0c, 8 }, 500 [SCFDR] = { 0x0e, 16 }, 501 }, 502 .fifosize = 16, 503 .overrun_reg = SCLSR, 504 .overrun_mask = SCLSR_ORER, 505 .sampling_rate_mask = SCI_SR(32), 506 .error_mask = SCIF_DEFAULT_ERROR_MASK, 507 .error_clear = SCIF_ERROR_CLEAR, 508 .param_bits = &sci_scif_port_params_bits, 509 .common_regs = &sci_common_regs, 510 }, 511 512 /* 513 * Common SH-4(A) SCIF(B) definitions. 514 */ 515 [SCIx_SH4_SCIF_REGTYPE] = { 516 .regs = { 517 [SCSMR] = { 0x00, 16 }, 518 [SCBRR] = { 0x04, 8 }, 519 [SCSCR] = { 0x08, 16 }, 520 [SCxTDR] = { 0x0c, 8 }, 521 [SCxSR] = { 0x10, 16 }, 522 [SCxRDR] = { 0x14, 8 }, 523 [SCFCR] = { 0x18, 16 }, 524 [SCFDR] = { 0x1c, 16 }, 525 [SCSPTR] = { 0x20, 16 }, 526 [SCLSR] = { 0x24, 16 }, 527 }, 528 .fifosize = 16, 529 .overrun_reg = SCLSR, 530 .overrun_mask = SCLSR_ORER, 531 .sampling_rate_mask = SCI_SR(32), 532 .error_mask = SCIF_DEFAULT_ERROR_MASK, 533 .error_clear = SCIF_ERROR_CLEAR, 534 .param_bits = &sci_scif_port_params_bits, 535 .common_regs = &sci_common_regs, 536 }, 537 538 /* 539 * Common SCIF definitions for ports with a Baud Rate Generator for 540 * External Clock (BRG). 541 */ 542 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 543 .regs = { 544 [SCSMR] = { 0x00, 16 }, 545 [SCBRR] = { 0x04, 8 }, 546 [SCSCR] = { 0x08, 16 }, 547 [SCxTDR] = { 0x0c, 8 }, 548 [SCxSR] = { 0x10, 16 }, 549 [SCxRDR] = { 0x14, 8 }, 550 [SCFCR] = { 0x18, 16 }, 551 [SCFDR] = { 0x1c, 16 }, 552 [SCSPTR] = { 0x20, 16 }, 553 [SCLSR] = { 0x24, 16 }, 554 [SCDL] = { 0x30, 16 }, 555 [SCCKS] = { 0x34, 16 }, 556 }, 557 .fifosize = 16, 558 .overrun_reg = SCLSR, 559 .overrun_mask = SCLSR_ORER, 560 .sampling_rate_mask = SCI_SR(32), 561 .error_mask = SCIF_DEFAULT_ERROR_MASK, 562 .error_clear = SCIF_ERROR_CLEAR, 563 .param_bits = &sci_scif_port_params_bits, 564 .common_regs = &sci_common_regs, 565 }, 566 567 /* 568 * Common HSCIF definitions. 569 */ 570 [SCIx_HSCIF_REGTYPE] = { 571 .regs = { 572 [SCSMR] = { 0x00, 16 }, 573 [SCBRR] = { 0x04, 8 }, 574 [SCSCR] = { 0x08, 16 }, 575 [SCxTDR] = { 0x0c, 8 }, 576 [SCxSR] = { 0x10, 16 }, 577 [SCxRDR] = { 0x14, 8 }, 578 [SCFCR] = { 0x18, 16 }, 579 [SCFDR] = { 0x1c, 16 }, 580 [SCSPTR] = { 0x20, 16 }, 581 [SCLSR] = { 0x24, 16 }, 582 [HSSRR] = { 0x40, 16 }, 583 [SCDL] = { 0x30, 16 }, 584 [SCCKS] = { 0x34, 16 }, 585 [HSRTRGR] = { 0x54, 16 }, 586 [HSTTRGR] = { 0x58, 16 }, 587 }, 588 .fifosize = 128, 589 .overrun_reg = SCLSR, 590 .overrun_mask = SCLSR_ORER, 591 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 592 .error_mask = SCIF_DEFAULT_ERROR_MASK, 593 .error_clear = SCIF_ERROR_CLEAR, 594 .param_bits = &sci_scif_port_params_bits, 595 .common_regs = &sci_common_regs, 596 }, 597 598 /* 599 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 600 * register. 601 */ 602 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 603 .regs = { 604 [SCSMR] = { 0x00, 16 }, 605 [SCBRR] = { 0x04, 8 }, 606 [SCSCR] = { 0x08, 16 }, 607 [SCxTDR] = { 0x0c, 8 }, 608 [SCxSR] = { 0x10, 16 }, 609 [SCxRDR] = { 0x14, 8 }, 610 [SCFCR] = { 0x18, 16 }, 611 [SCFDR] = { 0x1c, 16 }, 612 [SCLSR] = { 0x24, 16 }, 613 }, 614 .fifosize = 16, 615 .overrun_reg = SCLSR, 616 .overrun_mask = SCLSR_ORER, 617 .sampling_rate_mask = SCI_SR(32), 618 .error_mask = SCIF_DEFAULT_ERROR_MASK, 619 .error_clear = SCIF_ERROR_CLEAR, 620 .param_bits = &sci_scif_port_params_bits, 621 .common_regs = &sci_common_regs, 622 }, 623 624 /* 625 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 626 * count registers. 627 */ 628 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 629 .regs = { 630 [SCSMR] = { 0x00, 16 }, 631 [SCBRR] = { 0x04, 8 }, 632 [SCSCR] = { 0x08, 16 }, 633 [SCxTDR] = { 0x0c, 8 }, 634 [SCxSR] = { 0x10, 16 }, 635 [SCxRDR] = { 0x14, 8 }, 636 [SCFCR] = { 0x18, 16 }, 637 [SCFDR] = { 0x1c, 16 }, 638 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 639 [SCRFDR] = { 0x20, 16 }, 640 [SCSPTR] = { 0x24, 16 }, 641 [SCLSR] = { 0x28, 16 }, 642 }, 643 .fifosize = 16, 644 .overrun_reg = SCLSR, 645 .overrun_mask = SCLSR_ORER, 646 .sampling_rate_mask = SCI_SR(32), 647 .error_mask = SCIF_DEFAULT_ERROR_MASK, 648 .error_clear = SCIF_ERROR_CLEAR, 649 .param_bits = &sci_scif_port_params_bits, 650 .common_regs = &sci_common_regs, 651 }, 652 653 /* 654 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 655 * registers. 656 */ 657 [SCIx_SH7705_SCIF_REGTYPE] = { 658 .regs = { 659 [SCSMR] = { 0x00, 16 }, 660 [SCBRR] = { 0x04, 8 }, 661 [SCSCR] = { 0x08, 16 }, 662 [SCxTDR] = { 0x20, 8 }, 663 [SCxSR] = { 0x14, 16 }, 664 [SCxRDR] = { 0x24, 8 }, 665 [SCFCR] = { 0x18, 16 }, 666 [SCFDR] = { 0x1c, 16 }, 667 }, 668 .fifosize = 64, 669 .overrun_reg = SCxSR, 670 .overrun_mask = SCIFA_ORER, 671 .sampling_rate_mask = SCI_SR(16), 672 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 673 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 674 .param_bits = &sci_scif_port_params_bits, 675 .common_regs = &sci_common_regs, 676 }, 677}; 678 679#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 680 681/* 682 * The "offset" here is rather misleading, in that it refers to an enum 683 * value relative to the port mapping rather than the fixed offset 684 * itself, which needs to be manually retrieved from the platform's 685 * register map for the given port. 686 */ 687static unsigned int sci_serial_in(struct uart_port *p, int offset) 688{ 689 const struct plat_sci_reg *reg = sci_getreg(p, offset); 690 691 if (reg->size == 8) 692 return ioread8(p->membase + (reg->offset << p->regshift)); 693 else if (reg->size == 16) 694 return ioread16(p->membase + (reg->offset << p->regshift)); 695 else 696 WARN(1, "Invalid register access\n"); 697 698 return 0; 699} 700 701static void sci_serial_out(struct uart_port *p, int offset, int value) 702{ 703 const struct plat_sci_reg *reg = sci_getreg(p, offset); 704 705 if (reg->size == 8) 706 iowrite8(value, p->membase + (reg->offset << p->regshift)); 707 else if (reg->size == 16) 708 iowrite16(value, p->membase + (reg->offset << p->regshift)); 709 else 710 WARN(1, "Invalid register access\n"); 711} 712 713void sci_port_enable(struct sci_port *sci_port) 714{ 715 unsigned int i; 716 717 if (!sci_port->port.dev) 718 return; 719 720 pm_runtime_get_sync(sci_port->port.dev); 721 722 for (i = 0; i < SCI_NUM_CLKS; i++) { 723 clk_prepare_enable(sci_port->clks[i]); 724 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 725 } 726 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 727} 728EXPORT_SYMBOL_NS_GPL(sci_port_enable, "SH_SCI"); 729 730void sci_port_disable(struct sci_port *sci_port) 731{ 732 unsigned int i; 733 734 if (!sci_port->port.dev) 735 return; 736 737 for (i = SCI_NUM_CLKS; i-- > 0; ) 738 clk_disable_unprepare(sci_port->clks[i]); 739 740 pm_runtime_put_sync(sci_port->port.dev); 741} 742EXPORT_SYMBOL_NS_GPL(sci_port_disable, "SH_SCI"); 743 744static inline unsigned long port_rx_irq_mask(struct uart_port *port) 745{ 746 /* 747 * Not all ports (such as SCIFA) will support REIE. Rather than 748 * special-casing the port type, we check the port initialization 749 * IRQ enable mask to see whether the IRQ is desired at all. If 750 * it's unset, it's logically inferred that there's no point in 751 * testing for it. 752 */ 753 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 754} 755 756static void sci_start_tx(struct uart_port *port) 757{ 758 struct sci_port *s = to_sci_port(port); 759 unsigned short ctrl; 760 761#ifdef CONFIG_SERIAL_SH_SCI_DMA 762 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 763 u16 new, scr = sci_serial_in(port, SCSCR); 764 if (s->chan_tx) 765 new = scr | SCSCR_TDRQE; 766 else 767 new = scr & ~SCSCR_TDRQE; 768 if (new != scr) 769 sci_serial_out(port, SCSCR, new); 770 } 771 772 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && 773 dma_submit_error(s->cookie_tx)) { 774 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) 775 /* Switch irq from SCIF to DMA */ 776 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 777 778 s->cookie_tx = 0; 779 schedule_work(&s->work_tx); 780 } 781#endif 782 783 if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE || 784 s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 785 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 786 ctrl = sci_serial_in(port, SCSCR); 787 788 /* 789 * For SCI, TE (transmit enable) must be set after setting TIE 790 * (transmit interrupt enable) or in the same instruction to start 791 * the transmit process. 792 */ 793 if (s->type == PORT_SCI) 794 ctrl |= SCSCR_TE; 795 796 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); 797 } 798} 799 800static void sci_stop_tx(struct uart_port *port) 801{ 802 struct sci_port *s = to_sci_port(port); 803 unsigned short ctrl; 804 805 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 806 ctrl = sci_serial_in(port, SCSCR); 807 808 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 809 ctrl &= ~SCSCR_TDRQE; 810 811 ctrl &= ~SCSCR_TIE; 812 813 sci_serial_out(port, SCSCR, ctrl); 814 815#ifdef CONFIG_SERIAL_SH_SCI_DMA 816 if (s->chan_tx && 817 !dma_submit_error(s->cookie_tx)) { 818 dmaengine_terminate_async(s->chan_tx); 819 s->cookie_tx = -EINVAL; 820 } 821#endif 822} 823 824static void sci_start_rx(struct uart_port *port) 825{ 826 struct sci_port *s = to_sci_port(port); 827 unsigned short ctrl; 828 829 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); 830 831 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 832 ctrl &= ~SCSCR_RDRQE; 833 834 sci_serial_out(port, SCSCR, ctrl); 835} 836 837static void sci_stop_rx(struct uart_port *port) 838{ 839 struct sci_port *s = to_sci_port(port); 840 unsigned short ctrl; 841 842 ctrl = sci_serial_in(port, SCSCR); 843 844 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 845 ctrl &= ~SCSCR_RDRQE; 846 847 ctrl &= ~port_rx_irq_mask(port); 848 849 sci_serial_out(port, SCSCR, ctrl); 850} 851 852static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 853{ 854 struct sci_port *s = to_sci_port(port); 855 856 if (s->type == PORT_SCI) { 857 /* Just store the mask */ 858 sci_serial_out(port, SCxSR, mask); 859 } else if (s->params->overrun_mask == SCIFA_ORER) { 860 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 861 /* Only clear the status bits we want to clear */ 862 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); 863 } else { 864 /* Store the mask, clear parity/framing errors */ 865 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 866 } 867} 868 869#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 870 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 871 872#ifdef CONFIG_CONSOLE_POLL 873static int sci_poll_get_char(struct uart_port *port) 874{ 875 unsigned short status; 876 struct sci_port *s = to_sci_port(port); 877 int c; 878 879 do { 880 status = sci_serial_in(port, SCxSR); 881 if (status & SCxSR_ERRORS(port)) { 882 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 883 continue; 884 } 885 break; 886 } while (1); 887 888 if (!(status & SCxSR_RDxF(port))) 889 return NO_POLL_CHAR; 890 891 c = sci_serial_in(port, SCxRDR); 892 893 /* Dummy read */ 894 sci_serial_in(port, SCxSR); 895 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 896 897 return c; 898} 899#endif 900 901static void sci_poll_put_char(struct uart_port *port, unsigned char c) 902{ 903 struct sci_port *s = to_sci_port(port); 904 const struct sci_common_regs *regs = s->params->common_regs; 905 unsigned int status; 906 907 do { 908 status = s->ops->read_reg(port, regs->status); 909 } while (!(status & SCxSR_TDxE(port))); 910 911 sci_serial_out(port, SCxTDR, c); 912 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 913} 914#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 915 CONFIG_SERIAL_SH_SCI_EARLYCON */ 916 917static void sci_init_pins(struct uart_port *port, unsigned int cflag) 918{ 919 struct sci_port *s = to_sci_port(port); 920 921 /* 922 * Use port-specific handler if provided. 923 */ 924 if (s->cfg->ops && s->cfg->ops->init_pins) { 925 s->cfg->ops->init_pins(port, cflag); 926 return; 927 } 928 929 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 930 u16 data = sci_serial_in(port, SCPDR); 931 u16 ctrl = sci_serial_in(port, SCPCR); 932 933 /* Enable RXD and TXD pin functions */ 934 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 935 if (s->has_rtscts) { 936 /* RTS# is output, active low, unless autorts */ 937 if (!(port->mctrl & TIOCM_RTS)) { 938 ctrl |= SCPCR_RTSC; 939 data |= SCPDR_RTSD; 940 } else if (!s->autorts) { 941 ctrl |= SCPCR_RTSC; 942 data &= ~SCPDR_RTSD; 943 } else { 944 /* Enable RTS# pin function */ 945 ctrl &= ~SCPCR_RTSC; 946 } 947 /* Enable CTS# pin function */ 948 ctrl &= ~SCPCR_CTSC; 949 } 950 sci_serial_out(port, SCPDR, data); 951 sci_serial_out(port, SCPCR, ctrl); 952 } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) { 953 u16 status = sci_serial_in(port, SCSPTR); 954 955 /* RTS# is always output; and active low, unless autorts */ 956 status |= SCSPTR_RTSIO; 957 if (!(port->mctrl & TIOCM_RTS)) 958 status |= SCSPTR_RTSDT; 959 else if (!s->autorts) 960 status &= ~SCSPTR_RTSDT; 961 /* CTS# and SCK are inputs */ 962 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 963 sci_serial_out(port, SCSPTR, status); 964 } 965} 966 967static int sci_txfill(struct uart_port *port) 968{ 969 struct sci_port *s = to_sci_port(port); 970 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 971 const struct plat_sci_reg *reg; 972 973 reg = sci_getreg(port, SCTFDR); 974 if (reg->size) 975 return sci_serial_in(port, SCTFDR) & fifo_mask; 976 977 reg = sci_getreg(port, SCFDR); 978 if (reg->size) 979 return sci_serial_in(port, SCFDR) >> 8; 980 981 return !(sci_serial_in(port, SCxSR) & SCI_TDRE); 982} 983 984static int sci_txroom(struct uart_port *port) 985{ 986 return port->fifosize - sci_txfill(port); 987} 988 989static int sci_rxfill(struct uart_port *port) 990{ 991 struct sci_port *s = to_sci_port(port); 992 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 993 const struct plat_sci_reg *reg; 994 995 reg = sci_getreg(port, SCRFDR); 996 if (reg->size) 997 return sci_serial_in(port, SCRFDR) & fifo_mask; 998 999 reg = sci_getreg(port, SCFDR); 1000 if (reg->size) 1001 return sci_serial_in(port, SCFDR) & fifo_mask; 1002 1003 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 1004} 1005 1006/* ********************************************************************** * 1007 * the interrupt related routines * 1008 * ********************************************************************** */ 1009 1010static void sci_transmit_chars(struct uart_port *port) 1011{ 1012 struct tty_port *tport = &port->state->port; 1013 unsigned int stopped = uart_tx_stopped(port); 1014 struct sci_port *s = to_sci_port(port); 1015 unsigned short status; 1016 unsigned short ctrl; 1017 int count; 1018 1019 status = sci_serial_in(port, SCxSR); 1020 if (!(status & SCxSR_TDxE(port))) { 1021 ctrl = sci_serial_in(port, SCSCR); 1022 if (kfifo_is_empty(&tport->xmit_fifo)) 1023 ctrl &= ~SCSCR_TIE; 1024 else 1025 ctrl |= SCSCR_TIE; 1026 sci_serial_out(port, SCSCR, ctrl); 1027 return; 1028 } 1029 1030 count = sci_txroom(port); 1031 1032 do { 1033 unsigned char c; 1034 1035 if (port->x_char) { 1036 c = port->x_char; 1037 port->x_char = 0; 1038 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 1039 if (s->type == PORT_SCI && 1040 kfifo_is_empty(&tport->xmit_fifo)) { 1041 ctrl = sci_serial_in(port, SCSCR); 1042 ctrl &= ~SCSCR_TE; 1043 sci_serial_out(port, SCSCR, ctrl); 1044 return; 1045 } 1046 break; 1047 } 1048 1049 sci_serial_out(port, SCxTDR, c); 1050 s->tx_occurred = true; 1051 1052 port->icount.tx++; 1053 } while (--count > 0); 1054 1055 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 1056 1057 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1058 uart_write_wakeup(port); 1059 if (kfifo_is_empty(&tport->xmit_fifo)) { 1060 if (s->type == PORT_SCI) { 1061 ctrl = sci_serial_in(port, SCSCR); 1062 ctrl &= ~SCSCR_TIE; 1063 ctrl |= SCSCR_TEIE; 1064 sci_serial_out(port, SCSCR, ctrl); 1065 } 1066 1067 sci_stop_tx(port); 1068 } 1069} 1070 1071static void sci_receive_chars(struct uart_port *port) 1072{ 1073 struct tty_port *tport = &port->state->port; 1074 struct sci_port *s = to_sci_port(port); 1075 int i, count, copied = 0; 1076 unsigned short status; 1077 unsigned char flag; 1078 1079 status = sci_serial_in(port, SCxSR); 1080 if (!(status & SCxSR_RDxF(port))) 1081 return; 1082 1083 while (1) { 1084 /* Don't copy more bytes than there is room for in the buffer */ 1085 count = tty_buffer_request_room(tport, sci_rxfill(port)); 1086 1087 /* If for any reason we can't copy more data, we're done! */ 1088 if (count == 0) 1089 break; 1090 1091 if (s->type == PORT_SCI) { 1092 char c = sci_serial_in(port, SCxRDR); 1093 if (uart_handle_sysrq_char(port, c)) 1094 count = 0; 1095 else 1096 tty_insert_flip_char(tport, c, TTY_NORMAL); 1097 } else { 1098 for (i = 0; i < count; i++) { 1099 char c; 1100 1101 if (s->type == PORT_SCIF || 1102 s->type == PORT_HSCIF) { 1103 status = sci_serial_in(port, SCxSR); 1104 c = sci_serial_in(port, SCxRDR); 1105 } else { 1106 c = sci_serial_in(port, SCxRDR); 1107 status = sci_serial_in(port, SCxSR); 1108 } 1109 if (uart_handle_sysrq_char(port, c)) { 1110 count--; i--; 1111 continue; 1112 } 1113 1114 /* Store data and status */ 1115 if (status & SCxSR_FER(port)) { 1116 flag = TTY_FRAME; 1117 port->icount.frame++; 1118 } else if (status & SCxSR_PER(port)) { 1119 flag = TTY_PARITY; 1120 port->icount.parity++; 1121 } else 1122 flag = TTY_NORMAL; 1123 1124 tty_insert_flip_char(tport, c, flag); 1125 } 1126 } 1127 1128 sci_serial_in(port, SCxSR); /* dummy read */ 1129 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1130 1131 copied += count; 1132 port->icount.rx += count; 1133 } 1134 1135 if (copied) { 1136 /* Tell the rest of the system the news. New characters! */ 1137 tty_flip_buffer_push(tport); 1138 } else { 1139 /* TTY buffers full; read from RX reg to prevent lockup */ 1140 sci_serial_in(port, SCxRDR); 1141 sci_serial_in(port, SCxSR); /* dummy read */ 1142 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1143 } 1144} 1145 1146static int sci_handle_errors(struct uart_port *port) 1147{ 1148 int copied = 0; 1149 struct sci_port *s = to_sci_port(port); 1150 const struct sci_common_regs *regs = s->params->common_regs; 1151 unsigned int status = s->ops->read_reg(port, regs->status); 1152 struct tty_port *tport = &port->state->port; 1153 1154 /* Handle overruns */ 1155 if (status & s->params->overrun_mask) { 1156 port->icount.overrun++; 1157 1158 /* overrun error */ 1159 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 1160 copied++; 1161 } 1162 1163 if (status & SCxSR_FER(port)) { 1164 /* frame error */ 1165 port->icount.frame++; 1166 1167 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 1168 copied++; 1169 } 1170 1171 if (status & SCxSR_PER(port)) { 1172 /* parity error */ 1173 port->icount.parity++; 1174 1175 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 1176 copied++; 1177 } 1178 1179 if (copied) 1180 tty_flip_buffer_push(tport); 1181 1182 return copied; 1183} 1184 1185static int sci_handle_fifo_overrun(struct uart_port *port) 1186{ 1187 struct tty_port *tport = &port->state->port; 1188 struct sci_port *s = to_sci_port(port); 1189 const struct plat_sci_reg *reg; 1190 int copied = 0; 1191 u32 status; 1192 1193 if (s->type != SCI_PORT_RSCI) { 1194 reg = sci_getreg(port, s->params->overrun_reg); 1195 if (!reg->size) 1196 return 0; 1197 } 1198 1199 status = s->ops->read_reg(port, s->params->overrun_reg); 1200 if (status & s->params->overrun_mask) { 1201 if (s->type == SCI_PORT_RSCI) { 1202 /* 1203 * All of the CFCLR_*C clearing bits match the corresponding 1204 * CSR_*status bits. So, reuse the overrun mask for clearing. 1205 */ 1206 s->ops->clear_SCxSR(port, s->params->overrun_mask); 1207 } else { 1208 status &= ~s->params->overrun_mask; 1209 s->ops->write_reg(port, s->params->overrun_reg, status); 1210 } 1211 1212 port->icount.overrun++; 1213 1214 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1215 tty_flip_buffer_push(tport); 1216 copied++; 1217 } 1218 1219 return copied; 1220} 1221 1222static int sci_handle_breaks(struct uart_port *port) 1223{ 1224 int copied = 0; 1225 unsigned short status = sci_serial_in(port, SCxSR); 1226 struct tty_port *tport = &port->state->port; 1227 1228 if (uart_handle_break(port)) 1229 return 0; 1230 1231 if (status & SCxSR_BRK(port)) { 1232 port->icount.brk++; 1233 1234 /* Notify of BREAK */ 1235 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1236 copied++; 1237 } 1238 1239 if (copied) 1240 tty_flip_buffer_push(tport); 1241 1242 copied += sci_handle_fifo_overrun(port); 1243 1244 return copied; 1245} 1246 1247static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1248{ 1249 struct sci_port *s = to_sci_port(port); 1250 unsigned int bits; 1251 1252 if (rx_trig >= port->fifosize) 1253 rx_trig = port->fifosize - 1; 1254 if (rx_trig < 1) 1255 rx_trig = 1; 1256 1257 /* HSCIF can be set to an arbitrary level. */ 1258 if (sci_getreg(port, HSRTRGR)->size) { 1259 sci_serial_out(port, HSRTRGR, rx_trig); 1260 return rx_trig; 1261 } 1262 1263 switch (s->type) { 1264 case PORT_SCIF: 1265 if (rx_trig < 4) { 1266 bits = 0; 1267 rx_trig = 1; 1268 } else if (rx_trig < 8) { 1269 bits = SCFCR_RTRG0; 1270 rx_trig = 4; 1271 } else if (rx_trig < 14) { 1272 bits = SCFCR_RTRG1; 1273 rx_trig = 8; 1274 } else { 1275 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1276 rx_trig = 14; 1277 } 1278 break; 1279 case PORT_SCIFA: 1280 case PORT_SCIFB: 1281 if (rx_trig < 16) { 1282 bits = 0; 1283 rx_trig = 1; 1284 } else if (rx_trig < 32) { 1285 bits = SCFCR_RTRG0; 1286 rx_trig = 16; 1287 } else if (rx_trig < 48) { 1288 bits = SCFCR_RTRG1; 1289 rx_trig = 32; 1290 } else { 1291 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1292 rx_trig = 48; 1293 } 1294 break; 1295 default: 1296 WARN(1, "unknown FIFO configuration"); 1297 return 1; 1298 } 1299 1300 sci_serial_out(port, SCFCR, 1301 (sci_serial_in(port, SCFCR) & 1302 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1303 1304 return rx_trig; 1305} 1306 1307static int scif_rtrg_enabled(struct uart_port *port) 1308{ 1309 if (sci_getreg(port, HSRTRGR)->size) 1310 return sci_serial_in(port, HSRTRGR) != 0; 1311 else 1312 return (sci_serial_in(port, SCFCR) & 1313 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1314} 1315 1316static void rx_fifo_timer_fn(struct timer_list *t) 1317{ 1318 struct sci_port *s = timer_container_of(s, t, rx_fifo_timer); 1319 struct uart_port *port = &s->port; 1320 1321 dev_dbg(port->dev, "Rx timed out\n"); 1322 s->ops->set_rtrg(port, 1); 1323} 1324 1325static ssize_t rx_fifo_trigger_show(struct device *dev, 1326 struct device_attribute *attr, char *buf) 1327{ 1328 struct uart_port *port = dev_get_drvdata(dev); 1329 struct sci_port *sci = to_sci_port(port); 1330 1331 return sprintf(buf, "%d\n", sci->rx_trigger); 1332} 1333 1334static ssize_t rx_fifo_trigger_store(struct device *dev, 1335 struct device_attribute *attr, 1336 const char *buf, size_t count) 1337{ 1338 struct uart_port *port = dev_get_drvdata(dev); 1339 struct sci_port *sci = to_sci_port(port); 1340 int ret; 1341 long r; 1342 1343 ret = kstrtol(buf, 0, &r); 1344 if (ret) 1345 return ret; 1346 1347 sci->rx_trigger = sci->ops->set_rtrg(port, r); 1348 if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB) 1349 sci->ops->set_rtrg(port, 1); 1350 1351 return count; 1352} 1353 1354static DEVICE_ATTR_RW(rx_fifo_trigger); 1355 1356static ssize_t rx_fifo_timeout_show(struct device *dev, 1357 struct device_attribute *attr, 1358 char *buf) 1359{ 1360 struct uart_port *port = dev_get_drvdata(dev); 1361 struct sci_port *sci = to_sci_port(port); 1362 int v; 1363 1364 if (sci->type == PORT_HSCIF) 1365 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1366 else 1367 v = sci->rx_fifo_timeout; 1368 1369 return sprintf(buf, "%d\n", v); 1370} 1371 1372static ssize_t rx_fifo_timeout_store(struct device *dev, 1373 struct device_attribute *attr, 1374 const char *buf, 1375 size_t count) 1376{ 1377 struct uart_port *port = dev_get_drvdata(dev); 1378 struct sci_port *sci = to_sci_port(port); 1379 int ret; 1380 long r; 1381 1382 ret = kstrtol(buf, 0, &r); 1383 if (ret) 1384 return ret; 1385 1386 if (sci->type == PORT_HSCIF) { 1387 if (r < 0 || r > 3) 1388 return -EINVAL; 1389 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1390 } else { 1391 sci->rx_fifo_timeout = r; 1392 sci->ops->set_rtrg(port, 1); 1393 if (r > 0) 1394 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1395 } 1396 1397 return count; 1398} 1399 1400static DEVICE_ATTR_RW(rx_fifo_timeout); 1401 1402 1403#ifdef CONFIG_SERIAL_SH_SCI_DMA 1404static void sci_dma_tx_complete(void *arg) 1405{ 1406 struct sci_port *s = arg; 1407 struct uart_port *port = &s->port; 1408 struct tty_port *tport = &port->state->port; 1409 unsigned long flags; 1410 1411 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1412 1413 uart_port_lock_irqsave(port, &flags); 1414 1415 uart_xmit_advance(port, s->tx_dma_len); 1416 1417 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1418 uart_write_wakeup(port); 1419 1420 s->tx_occurred = true; 1421 1422 if (!kfifo_is_empty(&tport->xmit_fifo)) { 1423 s->cookie_tx = 0; 1424 schedule_work(&s->work_tx); 1425 } else { 1426 s->cookie_tx = -EINVAL; 1427 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1428 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1429 u16 ctrl = sci_serial_in(port, SCSCR); 1430 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1431 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1432 /* Switch irq from DMA to SCIF */ 1433 dmaengine_pause(s->chan_tx_saved); 1434 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1435 } 1436 } 1437 } 1438 1439 uart_port_unlock_irqrestore(port, flags); 1440} 1441 1442/* Locking: called with port lock held */ 1443static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1444{ 1445 struct uart_port *port = &s->port; 1446 struct tty_port *tport = &port->state->port; 1447 int copied; 1448 1449 copied = tty_insert_flip_string(tport, buf, count); 1450 if (copied < count) 1451 port->icount.buf_overrun++; 1452 1453 port->icount.rx += copied; 1454 1455 return copied; 1456} 1457 1458static int sci_dma_rx_find_active(struct sci_port *s) 1459{ 1460 unsigned int i; 1461 1462 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1463 if (s->active_rx == s->cookie_rx[i]) 1464 return i; 1465 1466 return -1; 1467} 1468 1469/* Must only be called with uart_port_lock taken */ 1470static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1471{ 1472 unsigned int i; 1473 1474 s->chan_rx = NULL; 1475 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1476 s->cookie_rx[i] = -EINVAL; 1477 s->active_rx = 0; 1478} 1479 1480static void sci_dma_rx_release(struct sci_port *s) 1481{ 1482 struct dma_chan *chan = s->chan_rx_saved; 1483 struct uart_port *port = &s->port; 1484 unsigned long flags; 1485 1486 uart_port_lock_irqsave(port, &flags); 1487 s->chan_rx_saved = NULL; 1488 sci_dma_rx_chan_invalidate(s); 1489 uart_port_unlock_irqrestore(port, flags); 1490 1491 dmaengine_terminate_sync(chan); 1492 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1493 sg_dma_address(&s->sg_rx[0])); 1494 dma_release_channel(chan); 1495} 1496 1497static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1498{ 1499 long sec = usec / 1000000; 1500 long nsec = (usec % 1000000) * 1000; 1501 ktime_t t = ktime_set(sec, nsec); 1502 1503 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1504} 1505 1506static void sci_dma_rx_reenable_irq(struct sci_port *s) 1507{ 1508 struct uart_port *port = &s->port; 1509 u16 scr; 1510 1511 /* Direct new serial port interrupts back to CPU */ 1512 scr = sci_serial_in(port, SCSCR); 1513 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1514 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1515 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1516 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) 1517 s->ops->set_rtrg(port, s->rx_trigger); 1518 else 1519 scr &= ~SCSCR_RDRQE; 1520 } 1521 sci_serial_out(port, SCSCR, scr | SCSCR_RIE); 1522} 1523 1524static void sci_dma_rx_complete(void *arg) 1525{ 1526 struct sci_port *s = arg; 1527 struct dma_chan *chan = s->chan_rx; 1528 struct uart_port *port = &s->port; 1529 struct dma_async_tx_descriptor *desc; 1530 unsigned long flags; 1531 int active, count = 0; 1532 1533 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1534 s->active_rx); 1535 1536 hrtimer_cancel(&s->rx_timer); 1537 1538 uart_port_lock_irqsave(port, &flags); 1539 1540 active = sci_dma_rx_find_active(s); 1541 if (active >= 0) 1542 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1543 1544 if (count) 1545 tty_flip_buffer_push(&port->state->port); 1546 1547 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1548 DMA_DEV_TO_MEM, 1549 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1550 if (!desc) 1551 goto fail; 1552 1553 desc->callback = sci_dma_rx_complete; 1554 desc->callback_param = s; 1555 s->cookie_rx[active] = dmaengine_submit(desc); 1556 if (dma_submit_error(s->cookie_rx[active])) 1557 goto fail; 1558 1559 s->active_rx = s->cookie_rx[!active]; 1560 1561 dma_async_issue_pending(chan); 1562 1563 uart_port_unlock_irqrestore(port, flags); 1564 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1565 __func__, s->cookie_rx[active], active, s->active_rx); 1566 1567 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1568 1569 return; 1570 1571fail: 1572 /* Switch to PIO */ 1573 dmaengine_terminate_async(chan); 1574 sci_dma_rx_chan_invalidate(s); 1575 sci_dma_rx_reenable_irq(s); 1576 uart_port_unlock_irqrestore(port, flags); 1577 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1578} 1579 1580static void sci_dma_tx_release(struct sci_port *s) 1581{ 1582 struct dma_chan *chan = s->chan_tx_saved; 1583 1584 cancel_work_sync(&s->work_tx); 1585 s->chan_tx_saved = s->chan_tx = NULL; 1586 s->cookie_tx = -EINVAL; 1587 dmaengine_terminate_sync(chan); 1588 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1589 DMA_TO_DEVICE); 1590 dma_release_channel(chan); 1591} 1592 1593static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1594{ 1595 struct dma_chan *chan = s->chan_rx; 1596 struct uart_port *port = &s->port; 1597 unsigned long flags; 1598 int i; 1599 1600 for (i = 0; i < 2; i++) { 1601 struct scatterlist *sg = &s->sg_rx[i]; 1602 struct dma_async_tx_descriptor *desc; 1603 1604 desc = dmaengine_prep_slave_sg(chan, 1605 sg, 1, DMA_DEV_TO_MEM, 1606 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1607 if (!desc) 1608 goto fail; 1609 1610 desc->callback = sci_dma_rx_complete; 1611 desc->callback_param = s; 1612 s->cookie_rx[i] = dmaengine_submit(desc); 1613 if (dma_submit_error(s->cookie_rx[i])) 1614 goto fail; 1615 1616 } 1617 1618 s->active_rx = s->cookie_rx[0]; 1619 1620 dma_async_issue_pending(chan); 1621 return 0; 1622 1623fail: 1624 /* Switch to PIO */ 1625 if (!port_lock_held) 1626 uart_port_lock_irqsave(port, &flags); 1627 if (i) 1628 dmaengine_terminate_async(chan); 1629 sci_dma_rx_chan_invalidate(s); 1630 sci_start_rx(port); 1631 if (!port_lock_held) 1632 uart_port_unlock_irqrestore(port, flags); 1633 return -EAGAIN; 1634} 1635 1636static void sci_dma_tx_work_fn(struct work_struct *work) 1637{ 1638 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1639 struct dma_async_tx_descriptor *desc; 1640 struct dma_chan *chan = s->chan_tx; 1641 struct uart_port *port = &s->port; 1642 struct tty_port *tport = &port->state->port; 1643 unsigned long flags; 1644 unsigned int tail; 1645 dma_addr_t buf; 1646 1647 /* 1648 * DMA is idle now. 1649 * Port xmit buffer is already mapped, and it is one page... Just adjust 1650 * offsets and lengths. Since it is a circular buffer, we have to 1651 * transmit till the end, and then the rest. Take the port lock to get a 1652 * consistent xmit buffer state. 1653 */ 1654 uart_port_lock_irq(port); 1655 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, 1656 UART_XMIT_SIZE); 1657 buf = s->tx_dma_addr + tail; 1658 if (!s->tx_dma_len) { 1659 /* Transmit buffer has been flushed */ 1660 uart_port_unlock_irq(port); 1661 return; 1662 } 1663 1664 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1665 DMA_MEM_TO_DEV, 1666 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1667 if (!desc) { 1668 uart_port_unlock_irq(port); 1669 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1670 goto switch_to_pio; 1671 } 1672 1673 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1674 DMA_TO_DEVICE); 1675 1676 desc->callback = sci_dma_tx_complete; 1677 desc->callback_param = s; 1678 s->cookie_tx = dmaengine_submit(desc); 1679 if (dma_submit_error(s->cookie_tx)) { 1680 uart_port_unlock_irq(port); 1681 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1682 goto switch_to_pio; 1683 } 1684 1685 uart_port_unlock_irq(port); 1686 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", 1687 __func__, tport->xmit_buf, tail, s->cookie_tx); 1688 1689 dma_async_issue_pending(chan); 1690 return; 1691 1692switch_to_pio: 1693 uart_port_lock_irqsave(port, &flags); 1694 s->chan_tx = NULL; 1695 sci_start_tx(port); 1696 uart_port_unlock_irqrestore(port, flags); 1697 return; 1698} 1699 1700static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1701{ 1702 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1703 struct dma_chan *chan = s->chan_rx; 1704 struct uart_port *port = &s->port; 1705 struct dma_tx_state state; 1706 enum dma_status status; 1707 unsigned long flags; 1708 unsigned int read; 1709 int active, count; 1710 1711 dev_dbg(port->dev, "DMA Rx timed out\n"); 1712 1713 uart_port_lock_irqsave(port, &flags); 1714 1715 active = sci_dma_rx_find_active(s); 1716 if (active < 0) { 1717 uart_port_unlock_irqrestore(port, flags); 1718 return HRTIMER_NORESTART; 1719 } 1720 1721 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1722 if (status == DMA_COMPLETE) { 1723 uart_port_unlock_irqrestore(port, flags); 1724 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1725 s->active_rx, active); 1726 1727 /* Let packet complete handler take care of the packet */ 1728 return HRTIMER_NORESTART; 1729 } 1730 1731 dmaengine_pause(chan); 1732 1733 /* 1734 * sometimes DMA transfer doesn't stop even if it is stopped and 1735 * data keeps on coming until transaction is complete so check 1736 * for DMA_COMPLETE again 1737 * Let packet complete handler take care of the packet 1738 */ 1739 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1740 if (status == DMA_COMPLETE) { 1741 uart_port_unlock_irqrestore(port, flags); 1742 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1743 return HRTIMER_NORESTART; 1744 } 1745 1746 /* Handle incomplete DMA receive */ 1747 dmaengine_terminate_async(s->chan_rx); 1748 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1749 1750 if (read) { 1751 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1752 if (count) 1753 tty_flip_buffer_push(&port->state->port); 1754 } 1755 1756 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1757 s->regtype == SCIx_RZ_SCIFA_REGTYPE) 1758 sci_dma_rx_submit(s, true); 1759 1760 sci_dma_rx_reenable_irq(s); 1761 1762 uart_port_unlock_irqrestore(port, flags); 1763 1764 return HRTIMER_NORESTART; 1765} 1766 1767static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1768 enum dma_transfer_direction dir) 1769{ 1770 struct dma_chan *chan; 1771 struct dma_slave_config cfg; 1772 int ret; 1773 1774 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1775 if (IS_ERR(chan)) { 1776 dev_dbg(port->dev, "dma_request_chan failed\n"); 1777 return NULL; 1778 } 1779 1780 memset(&cfg, 0, sizeof(cfg)); 1781 cfg.direction = dir; 1782 cfg.dst_addr = port->mapbase + 1783 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1784 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1785 cfg.src_addr = port->mapbase + 1786 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1787 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1788 1789 ret = dmaengine_slave_config(chan, &cfg); 1790 if (ret) { 1791 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1792 dma_release_channel(chan); 1793 return NULL; 1794 } 1795 1796 return chan; 1797} 1798 1799static void sci_request_dma(struct uart_port *port) 1800{ 1801 struct sci_port *s = to_sci_port(port); 1802 struct tty_port *tport = &port->state->port; 1803 struct dma_chan *chan; 1804 1805 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1806 1807 /* 1808 * DMA on console may interfere with Kernel log messages which use 1809 * plain putchar(). So, simply don't use it with a console. 1810 */ 1811 if (uart_console(port)) 1812 return; 1813 1814 if (!port->dev->of_node) 1815 return; 1816 1817 s->cookie_tx = -EINVAL; 1818 1819 /* 1820 * Don't request a dma channel if no channel was specified 1821 * in the device tree. 1822 */ 1823 if (!of_property_present(port->dev->of_node, "dmas")) 1824 return; 1825 1826 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1827 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1828 if (chan) { 1829 /* UART circular tx buffer is an aligned page. */ 1830 s->tx_dma_addr = dma_map_single(chan->device->dev, 1831 tport->xmit_buf, 1832 UART_XMIT_SIZE, 1833 DMA_TO_DEVICE); 1834 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1835 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1836 dma_release_channel(chan); 1837 } else { 1838 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1839 __func__, UART_XMIT_SIZE, 1840 tport->xmit_buf, &s->tx_dma_addr); 1841 1842 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1843 s->chan_tx_saved = s->chan_tx = chan; 1844 } 1845 } 1846 1847 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1848 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1849 if (chan) { 1850 unsigned int i; 1851 dma_addr_t dma; 1852 void *buf; 1853 1854 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1855 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1856 &dma, GFP_KERNEL); 1857 if (!buf) { 1858 dev_warn(port->dev, 1859 "Failed to allocate Rx dma buffer, using PIO\n"); 1860 dma_release_channel(chan); 1861 return; 1862 } 1863 1864 for (i = 0; i < 2; i++) { 1865 struct scatterlist *sg = &s->sg_rx[i]; 1866 1867 sg_init_table(sg, 1); 1868 s->rx_buf[i] = buf; 1869 sg_dma_address(sg) = dma; 1870 sg_dma_len(sg) = s->buf_len_rx; 1871 1872 buf += s->buf_len_rx; 1873 dma += s->buf_len_rx; 1874 } 1875 1876 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1877 1878 s->chan_rx_saved = s->chan_rx = chan; 1879 1880 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1881 s->regtype == SCIx_RZ_SCIFA_REGTYPE) 1882 sci_dma_rx_submit(s, false); 1883 } 1884} 1885 1886static void sci_free_dma(struct uart_port *port) 1887{ 1888 struct sci_port *s = to_sci_port(port); 1889 1890 if (s->chan_tx_saved) 1891 sci_dma_tx_release(s); 1892 if (s->chan_rx_saved) 1893 sci_dma_rx_release(s); 1894} 1895 1896static void sci_flush_buffer(struct uart_port *port) 1897{ 1898 struct sci_port *s = to_sci_port(port); 1899 1900 /* 1901 * In uart_flush_buffer(), the xmit circular buffer has just been 1902 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1903 * pending transfers 1904 */ 1905 s->tx_dma_len = 0; 1906 if (s->chan_tx) { 1907 dmaengine_terminate_async(s->chan_tx); 1908 s->cookie_tx = -EINVAL; 1909 } 1910} 1911 1912static void sci_dma_check_tx_occurred(struct sci_port *s) 1913{ 1914 struct dma_tx_state state; 1915 enum dma_status status; 1916 1917 if (!s->chan_tx || s->cookie_tx <= 0) 1918 return; 1919 1920 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state); 1921 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS) 1922 s->tx_occurred = true; 1923} 1924#else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1925static inline void sci_request_dma(struct uart_port *port) 1926{ 1927} 1928 1929static inline void sci_free_dma(struct uart_port *port) 1930{ 1931} 1932 1933static void sci_dma_check_tx_occurred(struct sci_port *s) 1934{ 1935} 1936 1937#define sci_flush_buffer NULL 1938#endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1939 1940static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1941{ 1942 struct uart_port *port = ptr; 1943 struct sci_port *s = to_sci_port(port); 1944 1945#ifdef CONFIG_SERIAL_SH_SCI_DMA 1946 if (s->chan_rx) { 1947 u16 scr = sci_serial_in(port, SCSCR); 1948 u16 ssr = sci_serial_in(port, SCxSR); 1949 1950 /* Disable future Rx interrupts */ 1951 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1952 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1953 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1954 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1955 s->ops->set_rtrg(port, 1); 1956 scr |= SCSCR_RIE; 1957 } else { 1958 scr |= SCSCR_RDRQE; 1959 } 1960 } else { 1961 if (sci_dma_rx_submit(s, false) < 0) 1962 goto handle_pio; 1963 1964 scr &= ~SCSCR_RIE; 1965 } 1966 sci_serial_out(port, SCSCR, scr); 1967 /* Clear current interrupt */ 1968 sci_serial_out(port, SCxSR, 1969 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1970 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1971 jiffies, s->rx_timeout); 1972 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1973 1974 return IRQ_HANDLED; 1975 } 1976 1977handle_pio: 1978#endif 1979 1980 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1981 if (!s->ops->rtrg_enabled(port)) 1982 s->ops->set_rtrg(port, s->rx_trigger); 1983 1984 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1985 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1986 } 1987 1988 /* I think sci_receive_chars has to be called irrespective 1989 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1990 * to be disabled? 1991 */ 1992 s->ops->receive_chars(port); 1993 1994 return IRQ_HANDLED; 1995} 1996 1997static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1998{ 1999 struct uart_port *port = ptr; 2000 unsigned long flags; 2001 struct sci_port *s = to_sci_port(port); 2002 2003 uart_port_lock_irqsave(port, &flags); 2004 s->ops->transmit_chars(port); 2005 uart_port_unlock_irqrestore(port, flags); 2006 2007 return IRQ_HANDLED; 2008} 2009 2010static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 2011{ 2012 struct uart_port *port = ptr; 2013 struct sci_port *s = to_sci_port(port); 2014 const struct sci_common_regs *regs = s->params->common_regs; 2015 unsigned long flags; 2016 u32 ctrl; 2017 2018 if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI) 2019 return sci_tx_interrupt(irq, ptr); 2020 2021 uart_port_lock_irqsave(port, &flags); 2022 ctrl = s->ops->read_reg(port, regs->control) & 2023 ~(s->params->param_bits->te_clear); 2024 s->ops->write_reg(port, regs->control, ctrl); 2025 uart_port_unlock_irqrestore(port, flags); 2026 2027 return IRQ_HANDLED; 2028} 2029 2030static irqreturn_t sci_br_interrupt(int irq, void *ptr) 2031{ 2032 struct uart_port *port = ptr; 2033 struct sci_port *s = to_sci_port(port); 2034 2035 /* Handle BREAKs */ 2036 sci_handle_breaks(port); 2037 2038 /* drop invalid character received before break was detected */ 2039 sci_serial_in(port, SCxRDR); 2040 2041 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 2042 2043 return IRQ_HANDLED; 2044} 2045 2046static irqreturn_t sci_er_interrupt(int irq, void *ptr) 2047{ 2048 struct uart_port *port = ptr; 2049 struct sci_port *s = to_sci_port(port); 2050 2051 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 2052 /* Break and Error interrupts are muxed */ 2053 unsigned short ssr_status = sci_serial_in(port, SCxSR); 2054 2055 /* Break Interrupt */ 2056 if (ssr_status & SCxSR_BRK(port)) 2057 sci_br_interrupt(irq, ptr); 2058 2059 /* Break only? */ 2060 if (!(ssr_status & SCxSR_ERRORS(port))) 2061 return IRQ_HANDLED; 2062 } 2063 2064 /* Handle errors */ 2065 if (s->type == PORT_SCI) { 2066 if (sci_handle_errors(port)) { 2067 /* discard character in rx buffer */ 2068 sci_serial_in(port, SCxSR); 2069 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 2070 } 2071 } else { 2072 sci_handle_fifo_overrun(port); 2073 if (!s->chan_rx) 2074 s->ops->receive_chars(port); 2075 } 2076 2077 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 2078 2079 /* Kick the transmission */ 2080 if (!s->chan_tx) 2081 sci_tx_interrupt(irq, ptr); 2082 2083 return IRQ_HANDLED; 2084} 2085 2086static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 2087{ 2088 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 2089 struct uart_port *port = ptr; 2090 struct sci_port *s = to_sci_port(port); 2091 irqreturn_t ret = IRQ_NONE; 2092 2093 ssr_status = sci_serial_in(port, SCxSR); 2094 scr_status = sci_serial_in(port, SCSCR); 2095 if (s->params->overrun_reg == SCxSR) 2096 orer_status = ssr_status; 2097 else if (sci_getreg(port, s->params->overrun_reg)->size) 2098 orer_status = sci_serial_in(port, s->params->overrun_reg); 2099 2100 err_enabled = scr_status & port_rx_irq_mask(port); 2101 2102 /* Tx Interrupt */ 2103 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 2104 !s->chan_tx) 2105 ret = sci_tx_interrupt(irq, ptr); 2106 2107 /* 2108 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 2109 * DR flags 2110 */ 2111 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 2112 (scr_status & SCSCR_RIE)) 2113 ret = sci_rx_interrupt(irq, ptr); 2114 2115 /* Error Interrupt */ 2116 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 2117 ret = sci_er_interrupt(irq, ptr); 2118 2119 /* Break Interrupt */ 2120 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 2121 (ssr_status & SCxSR_BRK(port)) && err_enabled) 2122 ret = sci_br_interrupt(irq, ptr); 2123 2124 /* Overrun Interrupt */ 2125 if (orer_status & s->params->overrun_mask) { 2126 sci_handle_fifo_overrun(port); 2127 ret = IRQ_HANDLED; 2128 } 2129 2130 return ret; 2131} 2132 2133static const struct sci_irq_desc { 2134 const char *desc; 2135 irq_handler_t handler; 2136} sci_irq_desc[] = { 2137 /* 2138 * Split out handlers, the default case. 2139 */ 2140 [SCIx_ERI_IRQ] = { 2141 .desc = "rx err", 2142 .handler = sci_er_interrupt, 2143 }, 2144 2145 [SCIx_RXI_IRQ] = { 2146 .desc = "rx full", 2147 .handler = sci_rx_interrupt, 2148 }, 2149 2150 [SCIx_TXI_IRQ] = { 2151 .desc = "tx empty", 2152 .handler = sci_tx_interrupt, 2153 }, 2154 2155 [SCIx_BRI_IRQ] = { 2156 .desc = "break", 2157 .handler = sci_br_interrupt, 2158 }, 2159 2160 [SCIx_DRI_IRQ] = { 2161 .desc = "rx ready", 2162 .handler = sci_rx_interrupt, 2163 }, 2164 2165 [SCIx_TEI_IRQ] = { 2166 .desc = "tx end", 2167 .handler = sci_tx_end_interrupt, 2168 }, 2169 2170 /* 2171 * Special muxed handler. 2172 */ 2173 [SCIx_MUX_IRQ] = { 2174 .desc = "mux", 2175 .handler = sci_mpxed_interrupt, 2176 }, 2177}; 2178 2179static int sci_request_irq(struct sci_port *port) 2180{ 2181 struct uart_port *up = &port->port; 2182 int i, j, w, ret = 0; 2183 2184 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 2185 const struct sci_irq_desc *desc; 2186 int irq; 2187 2188 /* Check if already registered (muxed) */ 2189 for (w = 0; w < i; w++) 2190 if (port->irqs[w] == port->irqs[i]) 2191 w = i + 1; 2192 if (w > i) 2193 continue; 2194 2195 if (SCIx_IRQ_IS_MUXED(port)) { 2196 i = SCIx_MUX_IRQ; 2197 irq = up->irq; 2198 } else { 2199 irq = port->irqs[i]; 2200 2201 /* 2202 * Certain port types won't support all of the 2203 * available interrupt sources. 2204 */ 2205 if (unlikely(irq < 0)) 2206 continue; 2207 } 2208 2209 desc = sci_irq_desc + i; 2210 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 2211 dev_name(up->dev), desc->desc); 2212 if (!port->irqstr[j]) { 2213 ret = -ENOMEM; 2214 goto out_nomem; 2215 } 2216 2217 ret = request_irq(irq, desc->handler, up->irqflags, 2218 port->irqstr[j], port); 2219 if (unlikely(ret)) { 2220 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 2221 goto out_noirq; 2222 } 2223 } 2224 2225 return 0; 2226 2227out_noirq: 2228 while (--i >= 0) 2229 free_irq(port->irqs[i], port); 2230 2231out_nomem: 2232 while (--j >= 0) 2233 kfree(port->irqstr[j]); 2234 2235 return ret; 2236} 2237 2238static void sci_free_irq(struct sci_port *port) 2239{ 2240 int i, j; 2241 2242 /* 2243 * Intentionally in reverse order so we iterate over the muxed 2244 * IRQ first. 2245 */ 2246 for (i = 0; i < SCIx_NR_IRQS; i++) { 2247 int irq = port->irqs[i]; 2248 2249 /* 2250 * Certain port types won't support all of the available 2251 * interrupt sources. 2252 */ 2253 if (unlikely(irq < 0)) 2254 continue; 2255 2256 /* Check if already freed (irq was muxed) */ 2257 for (j = 0; j < i; j++) 2258 if (port->irqs[j] == irq) 2259 j = i + 1; 2260 if (j > i) 2261 continue; 2262 2263 free_irq(port->irqs[i], port); 2264 kfree(port->irqstr[i]); 2265 2266 if (SCIx_IRQ_IS_MUXED(port)) { 2267 /* If there's only one IRQ, we're done. */ 2268 return; 2269 } 2270 } 2271} 2272 2273static unsigned int sci_tx_empty(struct uart_port *port) 2274{ 2275 unsigned short status = sci_serial_in(port, SCxSR); 2276 unsigned short in_tx_fifo = sci_txfill(port); 2277 struct sci_port *s = to_sci_port(port); 2278 2279 sci_dma_check_tx_occurred(s); 2280 2281 if (!s->tx_occurred) 2282 return TIOCSER_TEMT; 2283 2284 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2285} 2286 2287static void sci_set_rts(struct uart_port *port, bool state) 2288{ 2289 struct sci_port *s = to_sci_port(port); 2290 2291 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 2292 u16 data = sci_serial_in(port, SCPDR); 2293 2294 /* Active low */ 2295 if (state) 2296 data &= ~SCPDR_RTSD; 2297 else 2298 data |= SCPDR_RTSD; 2299 sci_serial_out(port, SCPDR, data); 2300 2301 /* RTS# is output */ 2302 sci_serial_out(port, SCPCR, 2303 sci_serial_in(port, SCPCR) | SCPCR_RTSC); 2304 } else if (sci_getreg(port, SCSPTR)->size) { 2305 u16 ctrl = sci_serial_in(port, SCSPTR); 2306 2307 /* Active low */ 2308 if (state) 2309 ctrl &= ~SCSPTR_RTSDT; 2310 else 2311 ctrl |= SCSPTR_RTSDT; 2312 sci_serial_out(port, SCSPTR, ctrl); 2313 } 2314} 2315 2316static bool sci_get_cts(struct uart_port *port) 2317{ 2318 struct sci_port *s = to_sci_port(port); 2319 2320 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 2321 /* Active low */ 2322 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); 2323 } else if (sci_getreg(port, SCSPTR)->size) { 2324 /* Active low */ 2325 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT); 2326 } 2327 2328 return true; 2329} 2330 2331/* 2332 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2333 * CTS/RTS is supported in hardware by at least one port and controlled 2334 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2335 * handled via the ->init_pins() op, which is a bit of a one-way street, 2336 * lacking any ability to defer pin control -- this will later be 2337 * converted over to the GPIO framework). 2338 * 2339 * Other modes (such as loopback) are supported generically on certain 2340 * port types, but not others. For these it's sufficient to test for the 2341 * existence of the support register and simply ignore the port type. 2342 */ 2343static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2344{ 2345 struct sci_port *s = to_sci_port(port); 2346 2347 if (mctrl & TIOCM_LOOP) { 2348 const struct plat_sci_reg *reg; 2349 2350 /* 2351 * Standard loopback mode for SCFCR ports. 2352 */ 2353 reg = sci_getreg(port, SCFCR); 2354 if (reg->size) 2355 sci_serial_out(port, SCFCR, 2356 sci_serial_in(port, SCFCR) | SCFCR_LOOP); 2357 } 2358 2359 mctrl_gpio_set(s->gpios, mctrl); 2360 2361 if (!s->has_rtscts) 2362 return; 2363 2364 if (!(mctrl & TIOCM_RTS)) { 2365 /* Disable Auto RTS */ 2366 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2367 sci_serial_out(port, SCFCR, 2368 sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2369 2370 /* Clear RTS */ 2371 sci_set_rts(port, 0); 2372 } else if (s->autorts) { 2373 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 2374 /* Enable RTS# pin function */ 2375 sci_serial_out(port, SCPCR, 2376 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); 2377 } 2378 2379 /* Enable Auto RTS */ 2380 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2381 sci_serial_out(port, SCFCR, 2382 sci_serial_in(port, SCFCR) | SCFCR_MCE); 2383 } else { 2384 /* Set RTS */ 2385 sci_set_rts(port, 1); 2386 } 2387} 2388 2389static unsigned int sci_get_mctrl(struct uart_port *port) 2390{ 2391 struct sci_port *s = to_sci_port(port); 2392 struct mctrl_gpios *gpios = s->gpios; 2393 unsigned int mctrl = 0; 2394 2395 mctrl_gpio_get(gpios, &mctrl); 2396 2397 /* 2398 * CTS/RTS is handled in hardware when supported, while nothing 2399 * else is wired up. 2400 */ 2401 if (s->autorts) { 2402 if (sci_get_cts(port)) 2403 mctrl |= TIOCM_CTS; 2404 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2405 mctrl |= TIOCM_CTS; 2406 } 2407 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2408 mctrl |= TIOCM_DSR; 2409 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2410 mctrl |= TIOCM_CAR; 2411 2412 return mctrl; 2413} 2414 2415static void sci_enable_ms(struct uart_port *port) 2416{ 2417 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2418} 2419 2420static void sci_break_ctl(struct uart_port *port, int break_state) 2421{ 2422 unsigned short scscr, scsptr; 2423 unsigned long flags; 2424 2425 /* check whether the port has SCSPTR */ 2426 if (!sci_getreg(port, SCSPTR)->size) { 2427 /* 2428 * Not supported by hardware. Most parts couple break and rx 2429 * interrupts together, with break detection always enabled. 2430 */ 2431 return; 2432 } 2433 2434 uart_port_lock_irqsave(port, &flags); 2435 scsptr = sci_serial_in(port, SCSPTR); 2436 scscr = sci_serial_in(port, SCSCR); 2437 2438 if (break_state == -1) { 2439 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2440 scscr &= ~SCSCR_TE; 2441 } else { 2442 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2443 scscr |= SCSCR_TE; 2444 } 2445 2446 sci_serial_out(port, SCSPTR, scsptr); 2447 sci_serial_out(port, SCSCR, scscr); 2448 uart_port_unlock_irqrestore(port, flags); 2449} 2450 2451static void sci_shutdown_complete(struct uart_port *port) 2452{ 2453 struct sci_port *s = to_sci_port(port); 2454 u16 scr; 2455 2456 scr = sci_serial_in(port, SCSCR); 2457 sci_serial_out(port, SCSCR, 2458 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2459} 2460 2461int sci_startup(struct uart_port *port) 2462{ 2463 struct sci_port *s = to_sci_port(port); 2464 int ret; 2465 2466 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2467 2468 s->tx_occurred = false; 2469 sci_request_dma(port); 2470 2471 ret = sci_request_irq(s); 2472 if (unlikely(ret < 0)) { 2473 sci_free_dma(port); 2474 return ret; 2475 } 2476 2477 return 0; 2478} 2479EXPORT_SYMBOL_NS_GPL(sci_startup, "SH_SCI"); 2480 2481void sci_shutdown(struct uart_port *port) 2482{ 2483 struct sci_port *s = to_sci_port(port); 2484 unsigned long flags; 2485 2486 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2487 2488 s->autorts = false; 2489 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios); 2490 2491 uart_port_lock_irqsave(port, &flags); 2492 s->port.ops->stop_rx(port); 2493 s->port.ops->stop_tx(port); 2494 s->ops->shutdown_complete(port); 2495 uart_port_unlock_irqrestore(port, flags); 2496 2497#ifdef CONFIG_SERIAL_SH_SCI_DMA 2498 if (s->chan_rx_saved) { 2499 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2500 port->line); 2501 hrtimer_cancel(&s->rx_timer); 2502 } 2503#endif 2504 2505 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2506 timer_delete_sync(&s->rx_fifo_timer); 2507 sci_free_irq(s); 2508 sci_free_dma(port); 2509} 2510EXPORT_SYMBOL_NS_GPL(sci_shutdown, "SH_SCI"); 2511 2512static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2513 unsigned int *srr) 2514{ 2515 unsigned long freq = s->clk_rates[SCI_SCK]; 2516 int err, min_err = INT_MAX; 2517 unsigned int sr; 2518 2519 if (s->type != PORT_HSCIF) 2520 freq *= 2; 2521 2522 for_each_sr(sr, s) { 2523 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2524 if (abs(err) >= abs(min_err)) 2525 continue; 2526 2527 min_err = err; 2528 *srr = sr - 1; 2529 2530 if (!err) 2531 break; 2532 } 2533 2534 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2535 *srr + 1); 2536 return min_err; 2537} 2538 2539static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2540 unsigned long freq, unsigned int *dlr, 2541 unsigned int *srr) 2542{ 2543 int err, min_err = INT_MAX; 2544 unsigned int sr, dl; 2545 2546 if (s->type != PORT_HSCIF) 2547 freq *= 2; 2548 2549 for_each_sr(sr, s) { 2550 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2551 dl = clamp(dl, 1U, 65535U); 2552 2553 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2554 if (abs(err) >= abs(min_err)) 2555 continue; 2556 2557 min_err = err; 2558 *dlr = dl; 2559 *srr = sr - 1; 2560 2561 if (!err) 2562 break; 2563 } 2564 2565 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2566 min_err, *dlr, *srr + 1); 2567 return min_err; 2568} 2569 2570/* calculate sample rate, BRR, and clock select */ 2571static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2572 unsigned int *brr, unsigned int *srr, 2573 unsigned int *cks) 2574{ 2575 unsigned long freq = s->clk_rates[SCI_FCK]; 2576 unsigned int sr, br, prediv, scrate, c; 2577 int err, min_err = INT_MAX; 2578 2579 if (s->type != PORT_HSCIF) 2580 freq *= 2; 2581 2582 /* 2583 * Find the combination of sample rate and clock select with the 2584 * smallest deviation from the desired baud rate. 2585 * Prefer high sample rates to maximise the receive margin. 2586 * 2587 * M: Receive margin (%) 2588 * N: Ratio of bit rate to clock (N = sampling rate) 2589 * D: Clock duty (D = 0 to 1.0) 2590 * L: Frame length (L = 9 to 12) 2591 * F: Absolute value of clock frequency deviation 2592 * 2593 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2594 * (|D - 0.5| / N * (1 + F))| 2595 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2596 */ 2597 for_each_sr(sr, s) { 2598 for (c = 0; c <= 3; c++) { 2599 /* integerized formulas from HSCIF documentation */ 2600 prediv = sr << (2 * c + 1); 2601 2602 /* 2603 * We need to calculate: 2604 * 2605 * br = freq / (prediv * bps) clamped to [1..256] 2606 * err = freq / (br * prediv) - bps 2607 * 2608 * Watch out for overflow when calculating the desired 2609 * sampling clock rate! 2610 */ 2611 if (bps > UINT_MAX / prediv) 2612 break; 2613 2614 scrate = prediv * bps; 2615 br = DIV_ROUND_CLOSEST(freq, scrate); 2616 br = clamp(br, 1U, 256U); 2617 2618 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2619 if (abs(err) >= abs(min_err)) 2620 continue; 2621 2622 min_err = err; 2623 *brr = br - 1; 2624 *srr = sr - 1; 2625 *cks = c; 2626 2627 if (!err) 2628 goto found; 2629 } 2630 } 2631 2632found: 2633 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2634 min_err, *brr, *srr + 1, *cks); 2635 return min_err; 2636} 2637 2638static void sci_reset(struct uart_port *port) 2639{ 2640 const struct plat_sci_reg *reg; 2641 unsigned int status; 2642 struct sci_port *s = to_sci_port(port); 2643 2644 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2645 2646 reg = sci_getreg(port, SCFCR); 2647 if (reg->size) 2648 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2649 2650 s->ops->clear_SCxSR(port, 2651 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2652 SCxSR_BREAK_CLEAR(port)); 2653 if (sci_getreg(port, SCLSR)->size) { 2654 status = sci_serial_in(port, SCLSR); 2655 status &= ~(SCLSR_TO | SCLSR_ORER); 2656 sci_serial_out(port, SCLSR, status); 2657 } 2658 2659 if (s->rx_trigger > 1) { 2660 if (s->rx_fifo_timeout) { 2661 s->ops->set_rtrg(port, 1); 2662 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2663 } else { 2664 if (s->type == PORT_SCIFA || 2665 s->type == PORT_SCIFB) 2666 s->ops->set_rtrg(port, 1); 2667 else 2668 s->ops->set_rtrg(port, s->rx_trigger); 2669 } 2670 } 2671} 2672 2673static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2674 const struct ktermios *old) 2675{ 2676 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2677 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2678 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2679 struct sci_port *s = to_sci_port(port); 2680 const struct plat_sci_reg *reg; 2681 int min_err = INT_MAX, err; 2682 unsigned long max_freq = 0; 2683 int best_clk = -1; 2684 unsigned long flags; 2685 2686 if ((termios->c_cflag & CSIZE) == CS7) { 2687 smr_val |= SCSMR_CHR; 2688 } else { 2689 termios->c_cflag &= ~CSIZE; 2690 termios->c_cflag |= CS8; 2691 } 2692 if (termios->c_cflag & PARENB) 2693 smr_val |= SCSMR_PE; 2694 if (termios->c_cflag & PARODD) 2695 smr_val |= SCSMR_PE | SCSMR_ODD; 2696 if (termios->c_cflag & CSTOPB) 2697 smr_val |= SCSMR_STOP; 2698 2699 /* 2700 * earlyprintk comes here early on with port->uartclk set to zero. 2701 * the clock framework is not up and running at this point so here 2702 * we assume that 115200 is the maximum baud rate. please note that 2703 * the baud rate is not programmed during earlyprintk - it is assumed 2704 * that the previous boot loader has enabled required clocks and 2705 * setup the baud rate generator hardware for us already. 2706 */ 2707 if (!port->uartclk) { 2708 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2709 goto done; 2710 } 2711 2712 for (i = 0; i < SCI_NUM_CLKS; i++) 2713 max_freq = max(max_freq, s->clk_rates[i]); 2714 2715 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2716 if (!baud) 2717 goto done; 2718 2719 /* 2720 * There can be multiple sources for the sampling clock. Find the one 2721 * that gives us the smallest deviation from the desired baud rate. 2722 */ 2723 2724 /* Optional Undivided External Clock */ 2725 if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA && 2726 s->type != PORT_SCIFB) { 2727 err = sci_sck_calc(s, baud, &srr1); 2728 if (abs(err) < abs(min_err)) { 2729 best_clk = SCI_SCK; 2730 scr_val = SCSCR_CKE1; 2731 sccks = SCCKS_CKS; 2732 min_err = err; 2733 srr = srr1; 2734 if (!err) 2735 goto done; 2736 } 2737 } 2738 2739 /* Optional BRG Frequency Divided External Clock */ 2740 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2741 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2742 &srr1); 2743 if (abs(err) < abs(min_err)) { 2744 best_clk = SCI_SCIF_CLK; 2745 scr_val = SCSCR_CKE1; 2746 sccks = 0; 2747 min_err = err; 2748 dl = dl1; 2749 srr = srr1; 2750 if (!err) 2751 goto done; 2752 } 2753 } 2754 2755 /* Optional BRG Frequency Divided Internal Clock */ 2756 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2757 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2758 &srr1); 2759 if (abs(err) < abs(min_err)) { 2760 best_clk = SCI_BRG_INT; 2761 scr_val = SCSCR_CKE1; 2762 sccks = SCCKS_XIN; 2763 min_err = err; 2764 dl = dl1; 2765 srr = srr1; 2766 if (!min_err) 2767 goto done; 2768 } 2769 } 2770 2771 /* Divided Functional Clock using standard Bit Rate Register */ 2772 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2773 if (abs(err) < abs(min_err)) { 2774 best_clk = SCI_FCK; 2775 scr_val = 0; 2776 min_err = err; 2777 brr = brr1; 2778 srr = srr1; 2779 cks = cks1; 2780 } 2781 2782done: 2783 if (best_clk >= 0) 2784 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2785 s->clks[best_clk], baud, min_err); 2786 2787 sci_port_enable(s); 2788 2789 /* 2790 * Program the optional External Baud Rate Generator (BRG) first. 2791 * It controls the mux to select (H)SCK or frequency divided clock. 2792 */ 2793 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2794 sci_serial_out(port, SCDL, dl); 2795 sci_serial_out(port, SCCKS, sccks); 2796 } 2797 2798 uart_port_lock_irqsave(port, &flags); 2799 2800 sci_reset(port); 2801 2802 uart_update_timeout(port, termios->c_cflag, baud); 2803 2804 /* byte size and parity */ 2805 bits = tty_get_frame_size(termios->c_cflag); 2806 2807 if (sci_getreg(port, SEMR)->size) 2808 sci_serial_out(port, SEMR, 0); 2809 2810 if (best_clk >= 0) { 2811 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 2812 switch (srr + 1) { 2813 case 5: smr_val |= SCSMR_SRC_5; break; 2814 case 7: smr_val |= SCSMR_SRC_7; break; 2815 case 11: smr_val |= SCSMR_SRC_11; break; 2816 case 13: smr_val |= SCSMR_SRC_13; break; 2817 case 16: smr_val |= SCSMR_SRC_16; break; 2818 case 17: smr_val |= SCSMR_SRC_17; break; 2819 case 19: smr_val |= SCSMR_SRC_19; break; 2820 case 27: smr_val |= SCSMR_SRC_27; break; 2821 } 2822 smr_val |= cks; 2823 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2824 sci_serial_out(port, SCSMR, smr_val); 2825 sci_serial_out(port, SCBRR, brr); 2826 if (sci_getreg(port, HSSRR)->size) { 2827 unsigned int hssrr = srr | HSCIF_SRE; 2828 /* Calculate deviation from intended rate at the 2829 * center of the last stop bit in sampling clocks. 2830 */ 2831 int last_stop = bits * 2 - 1; 2832 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2833 (int)(srr + 1), 2834 2 * (int)baud); 2835 2836 if (abs(deviation) >= 2) { 2837 /* At least two sampling clocks off at the 2838 * last stop bit; we can increase the error 2839 * margin by shifting the sampling point. 2840 */ 2841 int shift = clamp(deviation / 2, -8, 7); 2842 2843 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2844 HSCIF_SRHP_MASK; 2845 hssrr |= HSCIF_SRDE; 2846 } 2847 sci_serial_out(port, HSSRR, hssrr); 2848 } 2849 2850 /* Wait one bit interval */ 2851 udelay((1000000 + (baud - 1)) / baud); 2852 } else { 2853 /* Don't touch the bit rate configuration */ 2854 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2855 smr_val |= sci_serial_in(port, SCSMR) & 2856 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2857 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2858 sci_serial_out(port, SCSMR, smr_val); 2859 } 2860 2861 sci_init_pins(port, termios->c_cflag); 2862 2863 port->status &= ~UPSTAT_AUTOCTS; 2864 s->autorts = false; 2865 reg = sci_getreg(port, SCFCR); 2866 if (reg->size) { 2867 unsigned short ctrl = sci_serial_in(port, SCFCR); 2868 2869 if ((port->flags & UPF_HARD_FLOW) && 2870 (termios->c_cflag & CRTSCTS)) { 2871 /* There is no CTS interrupt to restart the hardware */ 2872 port->status |= UPSTAT_AUTOCTS; 2873 /* MCE is enabled when RTS is raised */ 2874 s->autorts = true; 2875 } 2876 2877 /* 2878 * As we've done a sci_reset() above, ensure we don't 2879 * interfere with the FIFOs while toggling MCE. As the 2880 * reset values could still be set, simply mask them out. 2881 */ 2882 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2883 2884 sci_serial_out(port, SCFCR, ctrl); 2885 } 2886 if (port->flags & UPF_HARD_FLOW) { 2887 /* Refresh (Auto) RTS */ 2888 sci_set_mctrl(port, port->mctrl); 2889 } 2890 2891 /* 2892 * For SCI, TE (transmit enable) must be set after setting TIE 2893 * (transmit interrupt enable) or in the same instruction to 2894 * start the transmitting process. So skip setting TE here for SCI. 2895 */ 2896 if (s->type != PORT_SCI) 2897 scr_val |= SCSCR_TE; 2898 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2899 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2900 if ((srr + 1 == 5) && 2901 (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) { 2902 /* 2903 * In asynchronous mode, when the sampling rate is 1/5, first 2904 * received data may become invalid on some SCIFA and SCIFB. 2905 * To avoid this problem wait more than 1 serial data time (1 2906 * bit time x serial data number) after setting SCSCR.RE = 1. 2907 */ 2908 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2909 } 2910 2911 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2912 s->rx_frame = (10000 * bits) / (baud / 100); 2913#ifdef CONFIG_SERIAL_SH_SCI_DMA 2914 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2915#endif 2916 2917 if ((termios->c_cflag & CREAD) != 0) 2918 sci_start_rx(port); 2919 2920 uart_port_unlock_irqrestore(port, flags); 2921 2922 sci_port_disable(s); 2923 2924 if (UART_ENABLE_MS(port, termios->c_cflag)) 2925 sci_enable_ms(port); 2926} 2927 2928void sci_pm(struct uart_port *port, unsigned int state, 2929 unsigned int oldstate) 2930{ 2931 struct sci_port *sci_port = to_sci_port(port); 2932 2933 switch (state) { 2934 case UART_PM_STATE_OFF: 2935 sci_port_disable(sci_port); 2936 break; 2937 default: 2938 sci_port_enable(sci_port); 2939 break; 2940 } 2941} 2942EXPORT_SYMBOL_NS_GPL(sci_pm, "SH_SCI"); 2943 2944static const char *sci_type(struct uart_port *port) 2945{ 2946 struct sci_port *s = to_sci_port(port); 2947 2948 switch (s->type) { 2949 case PORT_IRDA: 2950 return "irda"; 2951 case PORT_SCI: 2952 return "sci"; 2953 case PORT_SCIF: 2954 return "scif"; 2955 case PORT_SCIFA: 2956 return "scifa"; 2957 case PORT_SCIFB: 2958 return "scifb"; 2959 case PORT_HSCIF: 2960 return "hscif"; 2961 } 2962 2963 return NULL; 2964} 2965 2966static int sci_remap_port(struct uart_port *port) 2967{ 2968 struct sci_port *sport = to_sci_port(port); 2969 2970 /* 2971 * Nothing to do if there's already an established membase. 2972 */ 2973 if (port->membase) 2974 return 0; 2975 2976 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2977 port->membase = ioremap(port->mapbase, sport->reg_size); 2978 if (unlikely(!port->membase)) { 2979 dev_err(port->dev, "can't remap port#%d\n", port->line); 2980 return -ENXIO; 2981 } 2982 } else { 2983 /* 2984 * For the simple (and majority of) cases where we don't 2985 * need to do any remapping, just cast the cookie 2986 * directly. 2987 */ 2988 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2989 } 2990 2991 return 0; 2992} 2993 2994void sci_release_port(struct uart_port *port) 2995{ 2996 struct sci_port *sport = to_sci_port(port); 2997 2998 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2999 iounmap(port->membase); 3000 port->membase = NULL; 3001 } 3002 3003 release_mem_region(port->mapbase, sport->reg_size); 3004} 3005EXPORT_SYMBOL_NS_GPL(sci_release_port, "SH_SCI"); 3006 3007int sci_request_port(struct uart_port *port) 3008{ 3009 struct resource *res; 3010 struct sci_port *sport = to_sci_port(port); 3011 int ret; 3012 3013 res = request_mem_region(port->mapbase, sport->reg_size, 3014 dev_name(port->dev)); 3015 if (unlikely(res == NULL)) { 3016 dev_err(port->dev, "request_mem_region failed."); 3017 return -EBUSY; 3018 } 3019 3020 ret = sci_remap_port(port); 3021 if (unlikely(ret != 0)) { 3022 release_resource(res); 3023 return ret; 3024 } 3025 3026 return 0; 3027} 3028EXPORT_SYMBOL_NS_GPL(sci_request_port, "SH_SCI"); 3029 3030void sci_config_port(struct uart_port *port, int flags) 3031{ 3032 if (flags & UART_CONFIG_TYPE) { 3033 struct sci_port *sport = to_sci_port(port); 3034 port->type = SCI_PUBLIC_PORT_ID(sport->type); 3035 sci_request_port(port); 3036 } 3037} 3038EXPORT_SYMBOL_NS_GPL(sci_config_port, "SH_SCI"); 3039 3040int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 3041{ 3042 if (ser->baud_base < 2400) 3043 /* No paper tape reader for Mitch.. */ 3044 return -EINVAL; 3045 3046 return 0; 3047} 3048EXPORT_SYMBOL_NS_GPL(sci_verify_port, "SH_SCI"); 3049 3050static void sci_prepare_console_write(struct uart_port *port, u32 ctrl) 3051{ 3052 struct sci_port *s = to_sci_port(port); 3053 u32 ctrl_temp = 3054 s->params->param_bits->rxtx_enable | 3055 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3056 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) | 3057 s->hscif_tot; 3058 sci_serial_out(port, SCSCR, ctrl_temp); 3059} 3060 3061static void sci_console_save(struct uart_port *port) 3062{ 3063 struct sci_port *s = to_sci_port(port); 3064 struct sci_suspend_regs *regs = s->suspend_regs; 3065 3066 if (sci_getreg(port, SCDL)->size) 3067 regs->scdl = sci_serial_in(port, SCDL); 3068 if (sci_getreg(port, SCCKS)->size) 3069 regs->sccks = sci_serial_in(port, SCCKS); 3070 if (sci_getreg(port, SCSMR)->size) 3071 regs->scsmr = sci_serial_in(port, SCSMR); 3072 if (sci_getreg(port, SCSCR)->size) 3073 regs->scscr = sci_serial_in(port, SCSCR); 3074 if (sci_getreg(port, SCFCR)->size) 3075 regs->scfcr = sci_serial_in(port, SCFCR); 3076 if (sci_getreg(port, SCSPTR)->size) 3077 regs->scsptr = sci_serial_in(port, SCSPTR); 3078 if (sci_getreg(port, SCBRR)->size) 3079 regs->scbrr = sci_serial_in(port, SCBRR); 3080 if (sci_getreg(port, HSSRR)->size) 3081 regs->hssrr = sci_serial_in(port, HSSRR); 3082 if (sci_getreg(port, SCPCR)->size) 3083 regs->scpcr = sci_serial_in(port, SCPCR); 3084 if (sci_getreg(port, SCPDR)->size) 3085 regs->scpdr = sci_serial_in(port, SCPDR); 3086 if (sci_getreg(port, SEMR)->size) 3087 regs->semr = sci_serial_in(port, SEMR); 3088} 3089 3090static void sci_console_restore(struct uart_port *port) 3091{ 3092 struct sci_port *s = to_sci_port(port); 3093 struct sci_suspend_regs *regs = s->suspend_regs; 3094 3095 if (sci_getreg(port, SCDL)->size) 3096 sci_serial_out(port, SCDL, regs->scdl); 3097 if (sci_getreg(port, SCCKS)->size) 3098 sci_serial_out(port, SCCKS, regs->sccks); 3099 if (sci_getreg(port, SCSMR)->size) 3100 sci_serial_out(port, SCSMR, regs->scsmr); 3101 if (sci_getreg(port, SCSCR)->size) 3102 sci_serial_out(port, SCSCR, regs->scscr); 3103 if (sci_getreg(port, SCFCR)->size) 3104 sci_serial_out(port, SCFCR, regs->scfcr); 3105 if (sci_getreg(port, SCSPTR)->size) 3106 sci_serial_out(port, SCSPTR, regs->scsptr); 3107 if (sci_getreg(port, SCBRR)->size) 3108 sci_serial_out(port, SCBRR, regs->scbrr); 3109 if (sci_getreg(port, HSSRR)->size) 3110 sci_serial_out(port, HSSRR, regs->hssrr); 3111 if (sci_getreg(port, SCPCR)->size) 3112 sci_serial_out(port, SCPCR, regs->scpcr); 3113 if (sci_getreg(port, SCPDR)->size) 3114 sci_serial_out(port, SCPDR, regs->scpdr); 3115 if (sci_getreg(port, SEMR)->size) 3116 sci_serial_out(port, SEMR, regs->semr); 3117} 3118 3119static const struct uart_ops sci_uart_ops = { 3120 .tx_empty = sci_tx_empty, 3121 .set_mctrl = sci_set_mctrl, 3122 .get_mctrl = sci_get_mctrl, 3123 .start_tx = sci_start_tx, 3124 .stop_tx = sci_stop_tx, 3125 .stop_rx = sci_stop_rx, 3126 .enable_ms = sci_enable_ms, 3127 .break_ctl = sci_break_ctl, 3128 .startup = sci_startup, 3129 .shutdown = sci_shutdown, 3130 .flush_buffer = sci_flush_buffer, 3131 .set_termios = sci_set_termios, 3132 .pm = sci_pm, 3133 .type = sci_type, 3134 .release_port = sci_release_port, 3135 .request_port = sci_request_port, 3136 .config_port = sci_config_port, 3137 .verify_port = sci_verify_port, 3138#ifdef CONFIG_CONSOLE_POLL 3139 .poll_get_char = sci_poll_get_char, 3140 .poll_put_char = sci_poll_put_char, 3141#endif 3142}; 3143 3144static const struct sci_port_ops sci_port_ops = { 3145 .read_reg = sci_serial_in, 3146 .write_reg = sci_serial_out, 3147 .clear_SCxSR = sci_clear_SCxSR, 3148 .transmit_chars = sci_transmit_chars, 3149 .receive_chars = sci_receive_chars, 3150#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3151 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3152 .poll_put_char = sci_poll_put_char, 3153#endif 3154 .set_rtrg = scif_set_rtrg, 3155 .rtrg_enabled = scif_rtrg_enabled, 3156 .shutdown_complete = sci_shutdown_complete, 3157 .prepare_console_write = sci_prepare_console_write, 3158 .console_save = sci_console_save, 3159 .console_restore = sci_console_restore, 3160 .suspend_regs_size = sci_suspend_regs_size, 3161}; 3162 3163static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 3164{ 3165 const char *clk_names[] = { 3166 [SCI_FCK] = "fck", 3167 [SCI_SCK] = "sck", 3168 [SCI_BRG_INT] = "brg_int", 3169 [SCI_SCIF_CLK] = "scif_clk", 3170 }; 3171 struct clk *clk; 3172 unsigned int i; 3173 3174 if (sci_port->type == PORT_HSCIF) { 3175 clk_names[SCI_SCK] = "hsck"; 3176 } else if (sci_port->type == SCI_PORT_RSCI) { 3177 clk_names[SCI_FCK] = "operation"; 3178 clk_names[SCI_BRG_INT] = "bus"; 3179 } 3180 3181 for (i = 0; i < SCI_NUM_CLKS; i++) { 3182 const char *name = clk_names[i]; 3183 3184 clk = devm_clk_get_optional(dev, name); 3185 if (IS_ERR(clk)) 3186 return PTR_ERR(clk); 3187 3188 if (!clk && sci_port->type == SCI_PORT_RSCI && 3189 (i == SCI_FCK || i == SCI_BRG_INT)) { 3190 return dev_err_probe(dev, -ENODEV, 3191 "failed to get %s\n", 3192 name); 3193 } 3194 3195 if (!clk && i == SCI_FCK) { 3196 /* 3197 * Not all SH platforms declare a clock lookup entry 3198 * for SCI devices, in which case we need to get the 3199 * global "peripheral_clk" clock. 3200 */ 3201 clk = devm_clk_get(dev, "peripheral_clk"); 3202 if (IS_ERR(clk)) 3203 return dev_err_probe(dev, PTR_ERR(clk), 3204 "failed to get %s\n", 3205 name); 3206 } 3207 3208 if (!clk) 3209 dev_dbg(dev, "failed to get %s\n", name); 3210 else 3211 dev_dbg(dev, "clk %s is %pC rate %lu\n", name, 3212 clk, clk_get_rate(clk)); 3213 sci_port->clks[i] = clk; 3214 } 3215 return 0; 3216} 3217 3218static const struct sci_port_params * 3219sci_probe_regmap(const struct plat_sci_port *cfg, struct sci_port *sci_port) 3220{ 3221 unsigned int regtype; 3222 3223 sci_port->ops = &sci_port_ops; 3224 sci_port->port.ops = &sci_uart_ops; 3225 3226 if (cfg->regtype != SCIx_PROBE_REGTYPE) 3227 return &sci_port_params[cfg->regtype]; 3228 3229 switch (cfg->type) { 3230 case PORT_SCI: 3231 regtype = SCIx_SCI_REGTYPE; 3232 break; 3233 case PORT_IRDA: 3234 regtype = SCIx_IRDA_REGTYPE; 3235 break; 3236 case PORT_SCIFA: 3237 regtype = SCIx_SCIFA_REGTYPE; 3238 break; 3239 case PORT_SCIFB: 3240 regtype = SCIx_SCIFB_REGTYPE; 3241 break; 3242 case PORT_SCIF: 3243 /* 3244 * The SH-4 is a bit of a misnomer here, although that's 3245 * where this particular port layout originated. This 3246 * configuration (or some slight variation thereof) 3247 * remains the dominant model for all SCIFs. 3248 */ 3249 regtype = SCIx_SH4_SCIF_REGTYPE; 3250 break; 3251 case PORT_HSCIF: 3252 regtype = SCIx_HSCIF_REGTYPE; 3253 break; 3254 default: 3255 pr_err("Can't probe register map for given port\n"); 3256 return NULL; 3257 } 3258 3259 return &sci_port_params[regtype]; 3260} 3261 3262static int sci_init_single(struct platform_device *dev, 3263 struct sci_port *sci_port, unsigned int index, 3264 const struct plat_sci_port *p, bool early) 3265{ 3266 struct uart_port *port = &sci_port->port; 3267 const struct resource *res; 3268 unsigned int i; 3269 int ret; 3270 3271 sci_port->cfg = p; 3272 3273 sci_port->type = p->type; 3274 sci_port->regtype = p->regtype; 3275 3276 port->iotype = UPIO_MEM; 3277 port->line = index; 3278 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 3279 3280 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 3281 if (res == NULL) 3282 return -ENOMEM; 3283 3284 port->mapbase = res->start; 3285 sci_port->reg_size = resource_size(res); 3286 3287 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 3288 if (i) 3289 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 3290 else 3291 sci_port->irqs[i] = platform_get_irq(dev, i); 3292 } 3293 3294 /* 3295 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so 3296 * shuffle the interrupts. 3297 */ 3298 if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI) 3299 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 3300 3301 /* The SCI generates several interrupts. They can be muxed together or 3302 * connected to different interrupt lines. In the muxed case only one 3303 * interrupt resource is specified as there is only one interrupt ID. 3304 * In the non-muxed case, up to 6 interrupt signals might be generated 3305 * from the SCI, however those signals might have their own individual 3306 * interrupt ID numbers, or muxed together with another interrupt. 3307 */ 3308 if (sci_port->irqs[0] < 0) 3309 return -ENXIO; 3310 3311 if (sci_port->irqs[1] < 0) 3312 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 3313 sci_port->irqs[i] = sci_port->irqs[0]; 3314 3315 switch (p->type) { 3316 case PORT_SCIFB: 3317 sci_port->rx_trigger = 48; 3318 break; 3319 case PORT_HSCIF: 3320 sci_port->rx_trigger = 64; 3321 break; 3322 case PORT_SCIFA: 3323 sci_port->rx_trigger = 32; 3324 break; 3325 case PORT_SCIF: 3326 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 3327 /* RX triggering not implemented for this IP */ 3328 sci_port->rx_trigger = 1; 3329 else 3330 sci_port->rx_trigger = 8; 3331 break; 3332 case SCI_PORT_RSCI: 3333 sci_port->rx_trigger = 15; 3334 break; 3335 default: 3336 sci_port->rx_trigger = 1; 3337 break; 3338 } 3339 3340 sci_port->rx_fifo_timeout = 0; 3341 sci_port->hscif_tot = 0; 3342 3343 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 3344 * match the SoC datasheet, this should be investigated. Let platform 3345 * data override the sampling rate for now. 3346 */ 3347 sci_port->sampling_rate_mask = p->sampling_rate 3348 ? SCI_SR(p->sampling_rate) 3349 : sci_port->params->sampling_rate_mask; 3350 3351 if (!early) { 3352 ret = sci_init_clocks(sci_port, &dev->dev); 3353 if (ret < 0) 3354 return ret; 3355 } 3356 3357 port->type = SCI_PUBLIC_PORT_ID(p->type); 3358 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3359 port->fifosize = sci_port->params->fifosize; 3360 3361 if (p->type == PORT_SCI && !dev->dev.of_node) { 3362 if (sci_port->reg_size >= 0x20) 3363 port->regshift = 2; 3364 else 3365 port->regshift = 1; 3366 } 3367 3368 /* 3369 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3370 * for the multi-IRQ ports, which is where we are primarily 3371 * concerned with the shutdown path synchronization. 3372 * 3373 * For the muxed case there's nothing more to do. 3374 */ 3375 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3376 port->irqflags = 0; 3377 3378 return 0; 3379} 3380 3381#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3382 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3383static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3384{ 3385 to_sci_port(port)->ops->poll_put_char(port, ch); 3386} 3387 3388/* 3389 * Print a string to the serial port trying not to disturb 3390 * any possible real use of the port... 3391 */ 3392static void serial_console_write(struct console *co, const char *s, 3393 unsigned count) 3394{ 3395 struct sci_port *sci_port = &sci_ports[co->index]; 3396 struct uart_port *port = &sci_port->port; 3397 const struct sci_common_regs *regs = sci_port->params->common_regs; 3398 unsigned int bits; 3399 u32 ctrl; 3400 unsigned long flags; 3401 int locked = 1; 3402 3403 if (port->sysrq) 3404 locked = 0; 3405 else if (oops_in_progress) 3406 locked = uart_port_trylock_irqsave(port, &flags); 3407 else 3408 uart_port_lock_irqsave(port, &flags); 3409 3410 /* first save SCSCR then disable interrupts, keep clock source */ 3411 3412 ctrl = sci_port->ops->read_reg(port, regs->control); 3413 sci_port->ops->prepare_console_write(port, ctrl); 3414 3415 uart_console_write(port, s, count, serial_console_putchar); 3416 3417 /* wait until fifo is empty and last bit has been transmitted */ 3418 3419 bits = sci_port->params->param_bits->poll_sent_bits; 3420 3421 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits) 3422 cpu_relax(); 3423 3424 /* restore the SCSCR */ 3425 sci_port->ops->write_reg(port, regs->control, ctrl); 3426 3427 if (locked) 3428 uart_port_unlock_irqrestore(port, flags); 3429} 3430 3431static int serial_console_setup(struct console *co, char *options) 3432{ 3433 struct sci_port *sci_port; 3434 struct uart_port *port; 3435 int baud = 115200; 3436 int bits = 8; 3437 int parity = 'n'; 3438 int flow = 'n'; 3439 int ret; 3440 3441 /* 3442 * Refuse to handle any bogus ports. 3443 */ 3444 if (co->index < 0 || co->index >= SCI_NPORTS) 3445 return -ENODEV; 3446 3447 sci_port = &sci_ports[co->index]; 3448 port = &sci_port->port; 3449 3450 /* 3451 * Refuse to handle uninitialized ports. 3452 */ 3453 if (!port->ops) 3454 return -ENODEV; 3455 3456 ret = sci_remap_port(port); 3457 if (unlikely(ret != 0)) 3458 return ret; 3459 3460 if (options) 3461 uart_parse_options(options, &baud, &parity, &bits, &flow); 3462 3463 return uart_set_options(port, co, baud, parity, bits, flow); 3464} 3465 3466static struct console serial_console = { 3467 .name = "ttySC", 3468 .device = uart_console_device, 3469 .write = serial_console_write, 3470 .setup = serial_console_setup, 3471 .flags = CON_PRINTBUFFER, 3472 .index = -1, 3473 .data = &sci_uart_driver, 3474}; 3475 3476#ifdef CONFIG_SUPERH 3477static char early_serial_buf[32]; 3478 3479static int early_serial_console_setup(struct console *co, char *options) 3480{ 3481 /* 3482 * This early console is always registered using the earlyprintk= 3483 * parameter, which does not call add_preferred_console(). Thus 3484 * @options is always NULL and the options for this early console 3485 * are passed using a custom buffer. 3486 */ 3487 WARN_ON(options); 3488 3489 return serial_console_setup(co, early_serial_buf); 3490} 3491 3492static struct console early_serial_console = { 3493 .name = "early_ttySC", 3494 .write = serial_console_write, 3495 .setup = early_serial_console_setup, 3496 .flags = CON_PRINTBUFFER, 3497 .index = -1, 3498}; 3499 3500static int sci_probe_earlyprintk(struct platform_device *pdev) 3501{ 3502 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3503 struct sci_port *sp = &sci_ports[pdev->id]; 3504 3505 if (early_serial_console.data) 3506 return -EEXIST; 3507 3508 early_serial_console.index = pdev->id; 3509 3510 sp->params = sci_probe_regmap(cfg, sp); 3511 if (!sp->params) 3512 return -ENODEV; 3513 3514 sci_init_single(pdev, sp, pdev->id, cfg, true); 3515 3516 if (!strstr(early_serial_buf, "keep")) 3517 early_serial_console.flags |= CON_BOOT; 3518 3519 register_console(&early_serial_console); 3520 return 0; 3521} 3522#endif 3523 3524#define SCI_CONSOLE (&serial_console) 3525 3526#else 3527static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3528{ 3529 return -EINVAL; 3530} 3531 3532#define SCI_CONSOLE NULL 3533 3534#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3535 3536static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3537 3538static DEFINE_MUTEX(sci_uart_registration_lock); 3539static struct uart_driver sci_uart_driver = { 3540 .owner = THIS_MODULE, 3541 .driver_name = "sci", 3542 .dev_name = "ttySC", 3543 .major = SCI_MAJOR, 3544 .minor = SCI_MINOR_START, 3545 .nr = SCI_NPORTS, 3546 .cons = SCI_CONSOLE, 3547}; 3548 3549static void sci_remove(struct platform_device *dev) 3550{ 3551 struct sci_port *s = platform_get_drvdata(dev); 3552 unsigned int type = s->type; /* uart_remove_... clears it */ 3553 3554 sci_ports_in_use &= ~BIT(s->port.line); 3555 uart_remove_one_port(&sci_uart_driver, &s->port); 3556 3557 if (s->port.fifosize > 1) 3558 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3559 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF || 3560 type == SCI_PORT_RSCI) 3561 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3562} 3563 3564static const struct sci_of_data of_sci_scif_sh2 = { 3565 .type = PORT_SCIF, 3566 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 3567 .ops = &sci_port_ops, 3568 .uart_ops = &sci_uart_ops, 3569 .params = &sci_port_params[SCIx_SH2_SCIF_FIFODATA_REGTYPE], 3570}; 3571 3572static const struct sci_of_data of_sci_scif_rz_scifa = { 3573 .type = PORT_SCIF, 3574 .regtype = SCIx_RZ_SCIFA_REGTYPE, 3575 .ops = &sci_port_ops, 3576 .uart_ops = &sci_uart_ops, 3577 .params = &sci_port_params[SCIx_RZ_SCIFA_REGTYPE], 3578}; 3579 3580static const struct sci_of_data of_sci_scif_rzv2h = { 3581 .type = PORT_SCIF, 3582 .regtype = SCIx_RZV2H_SCIF_REGTYPE, 3583 .ops = &sci_port_ops, 3584 .uart_ops = &sci_uart_ops, 3585 .params = &sci_port_params[SCIx_RZV2H_SCIF_REGTYPE], 3586}; 3587 3588static const struct sci_of_data of_sci_rcar_scif = { 3589 .type = PORT_SCIF, 3590 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 3591 .ops = &sci_port_ops, 3592 .uart_ops = &sci_uart_ops, 3593 .params = &sci_port_params[SCIx_SH4_SCIF_BRG_REGTYPE], 3594}; 3595 3596static const struct sci_of_data of_sci_scif_sh4 = { 3597 .type = PORT_SCIF, 3598 .regtype = SCIx_SH4_SCIF_REGTYPE, 3599 .ops = &sci_port_ops, 3600 .uart_ops = &sci_uart_ops, 3601 .params = &sci_port_params[SCIx_SH4_SCIF_REGTYPE], 3602}; 3603 3604static const struct sci_of_data of_sci_scifa = { 3605 .type = PORT_SCIFA, 3606 .regtype = SCIx_SCIFA_REGTYPE, 3607 .ops = &sci_port_ops, 3608 .uart_ops = &sci_uart_ops, 3609 .params = &sci_port_params[SCIx_SCIFA_REGTYPE], 3610}; 3611 3612static const struct sci_of_data of_sci_scifb = { 3613 .type = PORT_SCIFB, 3614 .regtype = SCIx_SCIFB_REGTYPE, 3615 .ops = &sci_port_ops, 3616 .uart_ops = &sci_uart_ops, 3617 .params = &sci_port_params[SCIx_SCIFB_REGTYPE], 3618}; 3619 3620static const struct sci_of_data of_sci_hscif = { 3621 .type = PORT_HSCIF, 3622 .regtype = SCIx_HSCIF_REGTYPE, 3623 .ops = &sci_port_ops, 3624 .uart_ops = &sci_uart_ops, 3625 .params = &sci_port_params[SCIx_HSCIF_REGTYPE], 3626}; 3627 3628static const struct sci_of_data of_sci_sci = { 3629 .type = PORT_SCI, 3630 .regtype = SCIx_SCI_REGTYPE, 3631 .ops = &sci_port_ops, 3632 .uart_ops = &sci_uart_ops, 3633 .params = &sci_port_params[SCIx_SCI_REGTYPE], 3634}; 3635 3636static const struct of_device_id of_sci_match[] __maybe_unused = { 3637 /* SoC-specific types */ 3638 { 3639 .compatible = "renesas,scif-r7s72100", 3640 .data = &of_sci_scif_sh2, 3641 }, 3642 { 3643 .compatible = "renesas,scif-r7s9210", 3644 .data = &of_sci_scif_rz_scifa, 3645 }, 3646 { 3647 .compatible = "renesas,scif-r9a07g044", 3648 .data = &of_sci_scif_rz_scifa, 3649 }, 3650 { 3651 .compatible = "renesas,scif-r9a09g057", 3652 .data = &of_sci_scif_rzv2h, 3653 }, 3654#ifdef CONFIG_SERIAL_RSCI 3655 { 3656 .compatible = "renesas,r9a09g077-rsci", 3657 .data = &of_sci_rsci_data, 3658 }, 3659#endif /* CONFIG_SERIAL_RSCI */ 3660 /* Family-specific types */ 3661 { 3662 .compatible = "renesas,rcar-gen1-scif", 3663 .data = &of_sci_rcar_scif, 3664 }, { 3665 .compatible = "renesas,rcar-gen2-scif", 3666 .data = &of_sci_rcar_scif, 3667 }, { 3668 .compatible = "renesas,rcar-gen3-scif", 3669 .data = &of_sci_rcar_scif 3670 }, { 3671 .compatible = "renesas,rcar-gen4-scif", 3672 .data = &of_sci_rcar_scif 3673 }, { 3674 .compatible = "renesas,rcar-gen5-scif", 3675 .data = &of_sci_rcar_scif 3676 }, 3677 /* Generic types */ 3678 { 3679 .compatible = "renesas,scif", 3680 .data = &of_sci_scif_sh4, 3681 }, { 3682 .compatible = "renesas,scifa", 3683 .data = &of_sci_scifa, 3684 }, { 3685 .compatible = "renesas,scifb", 3686 .data = &of_sci_scifb, 3687 }, { 3688 .compatible = "renesas,hscif", 3689 .data = &of_sci_hscif, 3690 }, { 3691 .compatible = "renesas,sci", 3692 .data = &of_sci_sci, 3693 }, { 3694 /* Terminator */ 3695 }, 3696}; 3697MODULE_DEVICE_TABLE(of, of_sci_match); 3698 3699static void sci_reset_control_assert(void *data) 3700{ 3701 reset_control_assert(data); 3702} 3703 3704static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3705 unsigned int *dev_id) 3706{ 3707 struct device_node *np = pdev->dev.of_node; 3708 struct reset_control *rstc; 3709 struct plat_sci_port *p; 3710 struct sci_port *sp; 3711 const struct sci_of_data *data; 3712 int id, ret; 3713 3714 if (!IS_ENABLED(CONFIG_OF) || !np) 3715 return ERR_PTR(-EINVAL); 3716 3717 data = of_device_get_match_data(&pdev->dev); 3718 3719 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3720 if (IS_ERR(rstc)) 3721 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3722 "failed to get reset ctrl\n")); 3723 3724 ret = reset_control_deassert(rstc); 3725 if (ret) { 3726 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3727 return ERR_PTR(ret); 3728 } 3729 3730 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3731 if (ret) { 3732 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3733 ret); 3734 return ERR_PTR(ret); 3735 } 3736 3737 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3738 if (!p) 3739 return ERR_PTR(-ENOMEM); 3740 3741 /* Get the line number from the aliases node. */ 3742 id = of_alias_get_id(np, "serial"); 3743 if (id < 0 && ~sci_ports_in_use) 3744 id = ffz(sci_ports_in_use); 3745 if (id < 0) { 3746 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3747 return ERR_PTR(-EINVAL); 3748 } 3749 if (id >= ARRAY_SIZE(sci_ports)) { 3750 dev_err(&pdev->dev, "serial%d out of range\n", id); 3751 return ERR_PTR(-EINVAL); 3752 } 3753 3754 sp = &sci_ports[id]; 3755 sp->rstc = rstc; 3756 *dev_id = id; 3757 3758 p->type = data->type; 3759 p->regtype = data->regtype; 3760 3761 sp->ops = data->ops; 3762 sp->port.ops = data->uart_ops; 3763 sp->params = data->params; 3764 3765 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3766 3767 return p; 3768} 3769 3770static int sci_probe_single(struct platform_device *dev, 3771 unsigned int index, 3772 struct plat_sci_port *p, 3773 struct sci_port *sciport, 3774 struct resource *sci_res) 3775{ 3776 int ret; 3777 3778 /* Sanity check */ 3779 if (unlikely(index >= SCI_NPORTS)) { 3780 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3781 index+1, SCI_NPORTS); 3782 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3783 return -EINVAL; 3784 } 3785 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3786 if (sci_ports_in_use & BIT(index)) 3787 return -EBUSY; 3788 3789 mutex_lock(&sci_uart_registration_lock); 3790 if (!sci_uart_driver.state) { 3791 ret = uart_register_driver(&sci_uart_driver); 3792 if (ret) { 3793 mutex_unlock(&sci_uart_registration_lock); 3794 return ret; 3795 } 3796 } 3797 mutex_unlock(&sci_uart_registration_lock); 3798 3799 ret = sci_init_single(dev, sciport, index, p, false); 3800 if (ret) 3801 return ret; 3802 3803 sciport->port.dev = &dev->dev; 3804 ret = devm_pm_runtime_enable(&dev->dev); 3805 if (ret) 3806 return ret; 3807 3808 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3809 if (IS_ERR(sciport->gpios)) 3810 return PTR_ERR(sciport->gpios); 3811 3812 if (sciport->has_rtscts) { 3813 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3814 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3815 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3816 return -EINVAL; 3817 } 3818 sciport->port.flags |= UPF_HARD_FLOW; 3819 } 3820 3821 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { 3822 /* 3823 * In case: 3824 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and 3825 * - it now maps to an alias other than zero and 3826 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is 3827 * available in bootargs) 3828 * 3829 * we need to avoid disabling clocks and PM domains through the runtime 3830 * PM APIs called in __device_attach(). For this, increment the runtime 3831 * PM reference counter (the clocks and PM domains were already enabled 3832 * by the bootloader). Otherwise the earlycon may access the HW when it 3833 * has no clocks enabled leading to failures (infinite loop in 3834 * sci_poll_put_char()). 3835 */ 3836 pm_runtime_get_noresume(&dev->dev); 3837 3838 /* 3839 * Skip cleanup the sci_port[0] in early_console_exit(), this 3840 * port is the same as the earlycon one. 3841 */ 3842 sci_uart_earlycon_dev_probing = true; 3843 } 3844 3845 return uart_add_one_port(&sci_uart_driver, &sciport->port); 3846} 3847 3848static int sci_probe(struct platform_device *dev) 3849{ 3850 struct plat_sci_port *p; 3851 struct resource *res; 3852 struct sci_port *sp; 3853 unsigned int dev_id; 3854 int ret; 3855 3856 /* 3857 * If we've come here via earlyprintk initialization, head off to 3858 * the special early probe. We don't have sufficient device state 3859 * to make it beyond this yet. 3860 */ 3861#ifdef CONFIG_SUPERH 3862 if (is_sh_early_platform_device(dev)) 3863 return sci_probe_earlyprintk(dev); 3864#endif 3865 3866 if (dev->dev.of_node) { 3867 p = sci_parse_dt(dev, &dev_id); 3868 if (IS_ERR(p)) 3869 return PTR_ERR(p); 3870 sp = &sci_ports[dev_id]; 3871 } else { 3872 p = dev->dev.platform_data; 3873 if (p == NULL) { 3874 dev_err(&dev->dev, "no platform data supplied\n"); 3875 return -EINVAL; 3876 } 3877 3878 dev_id = dev->id; 3879 sp = &sci_ports[dev_id]; 3880 sp->params = sci_probe_regmap(p, sp); 3881 if (!sp->params) 3882 return -ENODEV; 3883 } 3884 3885 sp->suspend_regs = devm_kzalloc(&dev->dev, 3886 sp->ops->suspend_regs_size(), 3887 GFP_KERNEL); 3888 if (!sp->suspend_regs) 3889 return -ENOMEM; 3890 3891 /* 3892 * In case: 3893 * - the probed port alias is zero (as the one used by earlycon), and 3894 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in 3895 * bootargs) 3896 * 3897 * defer the probe of this serial. This is a debug scenario and the user 3898 * must be aware of it. 3899 * 3900 * Except when the probed port is the same as the earlycon port. 3901 */ 3902 3903 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 3904 if (!res) 3905 return -ENODEV; 3906 3907 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) 3908 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n"); 3909 3910 platform_set_drvdata(dev, sp); 3911 3912 ret = sci_probe_single(dev, dev_id, p, sp, res); 3913 if (ret) 3914 return ret; 3915 3916 if (sp->port.fifosize > 1) { 3917 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3918 if (ret) 3919 return ret; 3920 } 3921 if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB || 3922 sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) { 3923 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3924 if (ret) { 3925 if (sp->port.fifosize > 1) { 3926 device_remove_file(&dev->dev, 3927 &dev_attr_rx_fifo_trigger); 3928 } 3929 return ret; 3930 } 3931 } 3932 3933#ifdef CONFIG_SH_STANDARD_BIOS 3934 sh_bios_gdb_detach(); 3935#endif 3936 3937 sci_ports_in_use |= BIT(dev_id); 3938 return 0; 3939} 3940 3941static int sci_suspend(struct device *dev) 3942{ 3943 struct sci_port *sport = dev_get_drvdata(dev); 3944 3945 if (sport) { 3946 uart_suspend_port(&sci_uart_driver, &sport->port); 3947 3948 if (!console_suspend_enabled && uart_console(&sport->port)) { 3949 if (sport->ops->console_save) 3950 sport->ops->console_save(&sport->port); 3951 } 3952 else 3953 return reset_control_assert(sport->rstc); 3954 } 3955 3956 return 0; 3957} 3958 3959static int sci_resume(struct device *dev) 3960{ 3961 struct sci_port *sport = dev_get_drvdata(dev); 3962 3963 if (sport) { 3964 if (!console_suspend_enabled && uart_console(&sport->port)) { 3965 if (sport->ops->console_restore) 3966 sport->ops->console_restore(&sport->port); 3967 } else { 3968 int ret = reset_control_deassert(sport->rstc); 3969 3970 if (ret) 3971 return ret; 3972 } 3973 3974 uart_resume_port(&sci_uart_driver, &sport->port); 3975 } 3976 3977 return 0; 3978} 3979 3980static DEFINE_SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3981 3982static struct platform_driver sci_driver = { 3983 .probe = sci_probe, 3984 .remove = sci_remove, 3985 .driver = { 3986 .name = "sh-sci", 3987 .pm = pm_sleep_ptr(&sci_dev_pm_ops), 3988 .of_match_table = of_match_ptr(of_sci_match), 3989 }, 3990}; 3991 3992static int __init sci_init(void) 3993{ 3994 pr_info("%s\n", banner); 3995 3996 return platform_driver_register(&sci_driver); 3997} 3998 3999static void __exit sci_exit(void) 4000{ 4001 platform_driver_unregister(&sci_driver); 4002 4003 if (sci_uart_driver.state) 4004 uart_unregister_driver(&sci_uart_driver); 4005} 4006 4007#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 4008sh_early_platform_init_buffer("earlyprintk", &sci_driver, 4009 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 4010#endif 4011#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 4012static struct plat_sci_port port_cfg; 4013 4014static int early_console_exit(struct console *co) 4015{ 4016 struct sci_port *sci_port = &sci_ports[0]; 4017 4018 /* 4019 * Clean the slot used by earlycon. A new SCI device might 4020 * map to this slot. 4021 */ 4022 if (!sci_uart_earlycon_dev_probing) { 4023 memset(sci_port, 0, sizeof(*sci_port)); 4024 sci_uart_earlycon = false; 4025 } 4026 4027 return 0; 4028} 4029 4030int __init scix_early_console_setup(struct earlycon_device *device, 4031 const struct sci_of_data *data) 4032{ 4033 const struct sci_common_regs *regs; 4034 4035 if (!device->port.membase) 4036 return -ENODEV; 4037 4038 device->port.type = SCI_PUBLIC_PORT_ID(data->type); 4039 4040 sci_ports[0].port = device->port; 4041 sci_ports[0].type = data->type; 4042 sci_ports[0].regtype = data->regtype; 4043 4044 port_cfg.type = data->type; 4045 port_cfg.regtype = data->regtype; 4046 4047 sci_ports[0].cfg = &port_cfg; 4048 sci_ports[0].params = data->params; 4049 sci_ports[0].ops = data->ops; 4050 sci_ports[0].port.ops = data->uart_ops; 4051 sci_uart_earlycon = true; 4052 regs = sci_ports[0].params->common_regs; 4053 4054 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control); 4055 sci_ports[0].ops->write_reg(&sci_ports[0].port, 4056 regs->control, 4057 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr); 4058 4059 device->con->write = serial_console_write; 4060 device->con->exit = early_console_exit; 4061 4062 return 0; 4063} 4064static int __init sci_early_console_setup(struct earlycon_device *device, 4065 const char *opt) 4066{ 4067 return scix_early_console_setup(device, &of_sci_sci); 4068} 4069static int __init scif_early_console_setup(struct earlycon_device *device, 4070 const char *opt) 4071{ 4072 return scix_early_console_setup(device, &of_sci_scif_sh4); 4073} 4074static int __init rzscifa_early_console_setup(struct earlycon_device *device, 4075 const char *opt) 4076{ 4077 return scix_early_console_setup(device, &of_sci_scif_rz_scifa); 4078} 4079 4080static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, 4081 const char *opt) 4082{ 4083 return scix_early_console_setup(device, &of_sci_scif_rzv2h); 4084} 4085 4086static int __init scifa_early_console_setup(struct earlycon_device *device, 4087 const char *opt) 4088{ 4089 return scix_early_console_setup(device, &of_sci_scifa); 4090} 4091static int __init scifb_early_console_setup(struct earlycon_device *device, 4092 const char *opt) 4093{ 4094 return scix_early_console_setup(device, &of_sci_scifb); 4095} 4096static int __init hscif_early_console_setup(struct earlycon_device *device, 4097 const char *opt) 4098{ 4099 return scix_early_console_setup(device, &of_sci_hscif); 4100} 4101 4102OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 4103OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 4104OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 4105OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 4106OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup); 4107OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 4108OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 4109OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 4110#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 4111 4112module_init(sci_init); 4113module_exit(sci_exit); 4114 4115MODULE_LICENSE("GPL"); 4116MODULE_ALIAS("platform:sh-sci"); 4117MODULE_AUTHOR("Paul Mundt"); 4118MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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